1 //===---------------------- RetireControlUnit.cpp ---------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 ///
10 /// This file simulates the hardware responsible for retiring instructions.
11 ///
12 //===----------------------------------------------------------------------===//
13 
14 #include "llvm/MCA/HardwareUnits/RetireControlUnit.h"
15 #include "llvm/Support/Debug.h"
16 
17 #define DEBUG_TYPE "llvm-mca"
18 
19 namespace llvm {
20 namespace mca {
21 
22 RetireControlUnit::RetireControlUnit(const MCSchedModel &SM)
23     : NextAvailableSlotIdx(0), CurrentInstructionSlotIdx(0),
24       NumROBEntries(SM.MicroOpBufferSize),
25       AvailableEntries(SM.MicroOpBufferSize), MaxRetirePerCycle(0) {
26   // Check if the scheduling model provides extra information about the machine
27   // processor. If so, then use that information to set the reorder buffer size
28   // and the maximum number of instructions retired per cycle.
29   if (SM.hasExtraProcessorInfo()) {
30     const MCExtraProcessorInfo &EPI = SM.getExtraProcessorInfo();
31     if (EPI.ReorderBufferSize)
32       AvailableEntries = EPI.ReorderBufferSize;
33     MaxRetirePerCycle = EPI.MaxRetirePerCycle;
34   }
35   NumROBEntries = AvailableEntries;
36   bool IsOutOfOrder = SM.MicroOpBufferSize;
37   if (!IsOutOfOrder && !NumROBEntries)
38     return;
39   assert(NumROBEntries && "Invalid reorder buffer size!");
40   Queue.resize(2 * NumROBEntries);
41 }
42 
43 // Reserves a number of slots, and returns a new token.
44 unsigned RetireControlUnit::dispatch(const InstRef &IR) {
45   if (!NumROBEntries)
46     return UnhandledTokenID;
47 
48   const Instruction &Inst = *IR.getInstruction();
49   unsigned Entries = normalizeQuantity(Inst.getNumMicroOps());
50   assert((AvailableEntries >= Entries) && "Reorder Buffer unavailable!");
51 
52   unsigned TokenID = NextAvailableSlotIdx;
53   Queue[NextAvailableSlotIdx] = {IR, Entries, false};
54   NextAvailableSlotIdx += std::max(1U, Entries);
55   NextAvailableSlotIdx %= Queue.size();
56   assert(TokenID < UnhandledTokenID && "Invalid token ID");
57 
58   AvailableEntries -= Entries;
59   return TokenID;
60 }
61 
62 const RetireControlUnit::RUToken &RetireControlUnit::getCurrentToken() const {
63   const RetireControlUnit::RUToken &Current = Queue[CurrentInstructionSlotIdx];
64 #ifndef NDEBUG
65   const Instruction *Inst = Current.IR.getInstruction();
66   assert(Inst && "Invalid RUToken in the RCU queue.");
67 #endif
68   return Current;
69 }
70 
71 unsigned RetireControlUnit::computeNextSlotIdx() const {
72   const RetireControlUnit::RUToken &Current = getCurrentToken();
73   unsigned NextSlotIdx = CurrentInstructionSlotIdx + std::max(1U, Current.NumSlots);
74   return NextSlotIdx % Queue.size();
75 }
76 
77 const RetireControlUnit::RUToken &RetireControlUnit::peekNextToken() const {
78   return Queue[computeNextSlotIdx()];
79 }
80 
81 void RetireControlUnit::consumeCurrentToken() {
82   RetireControlUnit::RUToken &Current = Queue[CurrentInstructionSlotIdx];
83   Current.IR.getInstruction()->retire();
84 
85   // Update the slot index to be the next item in the circular queue.
86   CurrentInstructionSlotIdx += std::max(1U, Current.NumSlots);
87   CurrentInstructionSlotIdx %= Queue.size();
88   AvailableEntries += Current.NumSlots;
89   Current = { InstRef(), 0U, false };
90 }
91 
92 void RetireControlUnit::onInstructionExecuted(unsigned TokenID) {
93   assert(Queue.size() > TokenID);
94   assert(Queue[TokenID].IR.getInstruction() && "Instruction was not dispatched!");
95   assert(Queue[TokenID].Executed == false && "Instruction already executed!");
96   Queue[TokenID].Executed = true;
97 }
98 
99 #ifndef NDEBUG
100 void RetireControlUnit::dump() const {
101   dbgs() << "Retire Unit: { Total ROB Entries =" << NumROBEntries
102          << ", Available ROB entries=" << AvailableEntries << " }\n";
103 }
104 #endif
105 
106 } // namespace mca
107 } // namespace llvm
108