1 //===---------------------- RetireControlUnit.cpp ---------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 ///
10 /// This file simulates the hardware responsible for retiring instructions.
11 ///
12 //===----------------------------------------------------------------------===//
13 
14 #include "llvm/MCA/HardwareUnits/RetireControlUnit.h"
15 #include "llvm/Support/Debug.h"
16 
17 #define DEBUG_TYPE "llvm-mca"
18 
19 namespace llvm {
20 namespace mca {
21 
22 RetireControlUnit::RetireControlUnit(const MCSchedModel &SM)
23     : NextAvailableSlotIdx(0), CurrentInstructionSlotIdx(0),
24       AvailableEntries(SM.isOutOfOrder() ? SM.MicroOpBufferSize : 0),
25       MaxRetirePerCycle(0) {
26   // Check if the scheduling model provides extra information about the machine
27   // processor. If so, then use that information to set the reorder buffer size
28   // and the maximum number of instructions retired per cycle.
29   if (SM.hasExtraProcessorInfo()) {
30     const MCExtraProcessorInfo &EPI = SM.getExtraProcessorInfo();
31     if (EPI.ReorderBufferSize)
32       AvailableEntries = EPI.ReorderBufferSize;
33     MaxRetirePerCycle = EPI.MaxRetirePerCycle;
34   }
35   NumROBEntries = AvailableEntries;
36   if (!SM.isOutOfOrder() && !NumROBEntries)
37     return;
38   assert(NumROBEntries && "Invalid reorder buffer size!");
39   Queue.resize(2 * NumROBEntries);
40 }
41 
42 // Reserves a number of slots, and returns a new token.
43 unsigned RetireControlUnit::dispatch(const InstRef &IR) {
44   if (!NumROBEntries)
45     return UnhandledTokenID;
46 
47   const Instruction &Inst = *IR.getInstruction();
48   unsigned Entries = normalizeQuantity(Inst.getNumMicroOps());
49   assert((AvailableEntries >= Entries) && "Reorder Buffer unavailable!");
50 
51   unsigned TokenID = NextAvailableSlotIdx;
52   Queue[NextAvailableSlotIdx] = {IR, Entries, false};
53   NextAvailableSlotIdx += std::max(1U, Entries);
54   NextAvailableSlotIdx %= Queue.size();
55   assert(TokenID < UnhandledTokenID && "Invalid token ID");
56 
57   AvailableEntries -= Entries;
58   return TokenID;
59 }
60 
61 const RetireControlUnit::RUToken &RetireControlUnit::getCurrentToken() const {
62   const RetireControlUnit::RUToken &Current = Queue[CurrentInstructionSlotIdx];
63 #ifndef NDEBUG
64   const Instruction *Inst = Current.IR.getInstruction();
65   assert(Inst && "Invalid RUToken in the RCU queue.");
66 #endif
67   return Current;
68 }
69 
70 unsigned RetireControlUnit::computeNextSlotIdx() const {
71   const RetireControlUnit::RUToken &Current = getCurrentToken();
72   unsigned NextSlotIdx = CurrentInstructionSlotIdx + std::max(1U, Current.NumSlots);
73   return NextSlotIdx % Queue.size();
74 }
75 
76 const RetireControlUnit::RUToken &RetireControlUnit::peekNextToken() const {
77   return Queue[computeNextSlotIdx()];
78 }
79 
80 void RetireControlUnit::consumeCurrentToken() {
81   RetireControlUnit::RUToken &Current = Queue[CurrentInstructionSlotIdx];
82   Current.IR.getInstruction()->retire();
83 
84   // Update the slot index to be the next item in the circular queue.
85   CurrentInstructionSlotIdx += std::max(1U, Current.NumSlots);
86   CurrentInstructionSlotIdx %= Queue.size();
87   AvailableEntries += Current.NumSlots;
88   Current = { InstRef(), 0U, false };
89 }
90 
91 void RetireControlUnit::onInstructionExecuted(unsigned TokenID) {
92   assert(Queue.size() > TokenID);
93   assert(Queue[TokenID].IR.getInstruction() && "Instruction was not dispatched!");
94   assert(Queue[TokenID].Executed == false && "Instruction already executed!");
95   Queue[TokenID].Executed = true;
96 }
97 
98 #ifndef NDEBUG
99 void RetireControlUnit::dump() const {
100   dbgs() << "Retire Unit: { Total ROB Entries =" << NumROBEntries
101          << ", Available ROB entries=" << AvailableEntries << " }\n";
102 }
103 #endif
104 
105 } // namespace mca
106 } // namespace llvm
107