1 //===---------------------------- Context.cpp -------------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 /// \file 9 /// 10 /// This file defines a class for holding ownership of various simulated 11 /// hardware units. A Context also provides a utility routine for constructing 12 /// a default out-of-order pipeline with fetch, dispatch, execute, and retire 13 /// stages. 14 /// 15 //===----------------------------------------------------------------------===// 16 17 #include "llvm/MCA/Context.h" 18 #include "llvm/MCA/HardwareUnits/RegisterFile.h" 19 #include "llvm/MCA/HardwareUnits/RetireControlUnit.h" 20 #include "llvm/MCA/HardwareUnits/Scheduler.h" 21 #include "llvm/MCA/Stages/DispatchStage.h" 22 #include "llvm/MCA/Stages/EntryStage.h" 23 #include "llvm/MCA/Stages/ExecuteStage.h" 24 #include "llvm/MCA/Stages/InOrderIssueStage.h" 25 #include "llvm/MCA/Stages/MicroOpQueueStage.h" 26 #include "llvm/MCA/Stages/RetireStage.h" 27 28 namespace llvm { 29 namespace mca { 30 31 std::unique_ptr<Pipeline> 32 Context::createDefaultPipeline(const PipelineOptions &Opts, SourceMgr &SrcMgr) { 33 const MCSchedModel &SM = STI.getSchedModel(); 34 35 if (!SM.isOutOfOrder()) 36 return createInOrderPipeline(Opts, SrcMgr); 37 38 // Create the hardware units defining the backend. 39 auto RCU = std::make_unique<RetireControlUnit>(SM); 40 auto PRF = std::make_unique<RegisterFile>(SM, MRI, Opts.RegisterFileSize); 41 auto LSU = std::make_unique<LSUnit>(SM, Opts.LoadQueueSize, 42 Opts.StoreQueueSize, Opts.AssumeNoAlias); 43 auto HWS = std::make_unique<Scheduler>(SM, *LSU); 44 45 // Create the pipeline stages. 46 auto Fetch = std::make_unique<EntryStage>(SrcMgr); 47 auto Dispatch = std::make_unique<DispatchStage>(STI, MRI, Opts.DispatchWidth, 48 *RCU, *PRF); 49 auto Execute = 50 std::make_unique<ExecuteStage>(*HWS, Opts.EnableBottleneckAnalysis); 51 auto Retire = std::make_unique<RetireStage>(*RCU, *PRF, *LSU); 52 53 // Pass the ownership of all the hardware units to this Context. 54 addHardwareUnit(std::move(RCU)); 55 addHardwareUnit(std::move(PRF)); 56 addHardwareUnit(std::move(LSU)); 57 addHardwareUnit(std::move(HWS)); 58 59 // Build the pipeline. 60 auto StagePipeline = std::make_unique<Pipeline>(); 61 StagePipeline->appendStage(std::move(Fetch)); 62 if (Opts.MicroOpQueueSize) 63 StagePipeline->appendStage(std::make_unique<MicroOpQueueStage>( 64 Opts.MicroOpQueueSize, Opts.DecodersThroughput)); 65 StagePipeline->appendStage(std::move(Dispatch)); 66 StagePipeline->appendStage(std::move(Execute)); 67 StagePipeline->appendStage(std::move(Retire)); 68 return StagePipeline; 69 } 70 71 std::unique_ptr<Pipeline> 72 Context::createInOrderPipeline(const PipelineOptions &Opts, SourceMgr &SrcMgr) { 73 const MCSchedModel &SM = STI.getSchedModel(); 74 auto RCU = std::make_unique<RetireControlUnit>(SM); 75 auto PRF = std::make_unique<RegisterFile>(SM, MRI, Opts.RegisterFileSize); 76 auto LSU = std::make_unique<LSUnit>(SM, Opts.LoadQueueSize, 77 Opts.StoreQueueSize, Opts.AssumeNoAlias); 78 79 auto Entry = std::make_unique<EntryStage>(SrcMgr); 80 auto InOrderIssue = std::make_unique<InOrderIssueStage>(*RCU, *PRF, SM, STI); 81 auto Retire = std::make_unique<RetireStage>(*RCU, *PRF, *LSU); 82 83 auto StagePipeline = std::make_unique<Pipeline>(); 84 StagePipeline->appendStage(std::move(Entry)); 85 StagePipeline->appendStage(std::move(InOrderIssue)); 86 StagePipeline->appendStage(std::move(Retire)); 87 88 addHardwareUnit(std::move(RCU)); 89 addHardwareUnit(std::move(PRF)); 90 addHardwareUnit(std::move(LSU)); 91 92 return StagePipeline; 93 } 94 95 } // namespace mca 96 } // namespace llvm 97