1 //===-- AutoUpgrade.cpp - Implement auto-upgrade helper functions ---------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements the auto-upgrade helper functions. 11 // This is where deprecated IR intrinsics and other IR features are updated to 12 // current specifications. 13 // 14 //===----------------------------------------------------------------------===// 15 16 #include "llvm/IR/AutoUpgrade.h" 17 #include "llvm/ADT/StringSwitch.h" 18 #include "llvm/IR/CFG.h" 19 #include "llvm/IR/CallSite.h" 20 #include "llvm/IR/Constants.h" 21 #include "llvm/IR/DIBuilder.h" 22 #include "llvm/IR/DebugInfo.h" 23 #include "llvm/IR/DiagnosticInfo.h" 24 #include "llvm/IR/Function.h" 25 #include "llvm/IR/IRBuilder.h" 26 #include "llvm/IR/Instruction.h" 27 #include "llvm/IR/IntrinsicInst.h" 28 #include "llvm/IR/LLVMContext.h" 29 #include "llvm/IR/Module.h" 30 #include "llvm/Support/ErrorHandling.h" 31 #include "llvm/Support/Regex.h" 32 #include <cstring> 33 using namespace llvm; 34 35 static void rename(GlobalValue *GV) { GV->setName(GV->getName() + ".old"); } 36 37 // Upgrade the declarations of the SSE4.1 ptest intrinsics whose arguments have 38 // changed their type from v4f32 to v2i64. 39 static bool UpgradePTESTIntrinsic(Function* F, Intrinsic::ID IID, 40 Function *&NewFn) { 41 // Check whether this is an old version of the function, which received 42 // v4f32 arguments. 43 Type *Arg0Type = F->getFunctionType()->getParamType(0); 44 if (Arg0Type != VectorType::get(Type::getFloatTy(F->getContext()), 4)) 45 return false; 46 47 // Yes, it's old, replace it with new version. 48 rename(F); 49 NewFn = Intrinsic::getDeclaration(F->getParent(), IID); 50 return true; 51 } 52 53 // Upgrade the declarations of intrinsic functions whose 8-bit immediate mask 54 // arguments have changed their type from i32 to i8. 55 static bool UpgradeX86IntrinsicsWith8BitMask(Function *F, Intrinsic::ID IID, 56 Function *&NewFn) { 57 // Check that the last argument is an i32. 58 Type *LastArgType = F->getFunctionType()->getParamType( 59 F->getFunctionType()->getNumParams() - 1); 60 if (!LastArgType->isIntegerTy(32)) 61 return false; 62 63 // Move this function aside and map down. 64 rename(F); 65 NewFn = Intrinsic::getDeclaration(F->getParent(), IID); 66 return true; 67 } 68 69 static bool ShouldUpgradeX86Intrinsic(Function *F, StringRef Name) { 70 // All of the intrinsics matches below should be marked with which llvm 71 // version started autoupgrading them. At some point in the future we would 72 // like to use this information to remove upgrade code for some older 73 // intrinsics. It is currently undecided how we will determine that future 74 // point. 75 if (Name.startswith("sse2.pcmpeq.") || // Added in 3.1 76 Name.startswith("sse2.pcmpgt.") || // Added in 3.1 77 Name.startswith("avx2.pcmpeq.") || // Added in 3.1 78 Name.startswith("avx2.pcmpgt.") || // Added in 3.1 79 Name.startswith("avx512.mask.pcmpeq.") || // Added in 3.9 80 Name.startswith("avx512.mask.pcmpgt.") || // Added in 3.9 81 Name == "sse.add.ss" || // Added in 4.0 82 Name == "sse2.add.sd" || // Added in 4.0 83 Name == "sse.sub.ss" || // Added in 4.0 84 Name == "sse2.sub.sd" || // Added in 4.0 85 Name == "sse.mul.ss" || // Added in 4.0 86 Name == "sse2.mul.sd" || // Added in 4.0 87 Name == "sse.div.ss" || // Added in 4.0 88 Name == "sse2.div.sd" || // Added in 4.0 89 Name == "sse41.pmaxsb" || // Added in 3.9 90 Name == "sse2.pmaxs.w" || // Added in 3.9 91 Name == "sse41.pmaxsd" || // Added in 3.9 92 Name == "sse2.pmaxu.b" || // Added in 3.9 93 Name == "sse41.pmaxuw" || // Added in 3.9 94 Name == "sse41.pmaxud" || // Added in 3.9 95 Name == "sse41.pminsb" || // Added in 3.9 96 Name == "sse2.pmins.w" || // Added in 3.9 97 Name == "sse41.pminsd" || // Added in 3.9 98 Name == "sse2.pminu.b" || // Added in 3.9 99 Name == "sse41.pminuw" || // Added in 3.9 100 Name == "sse41.pminud" || // Added in 3.9 101 Name.startswith("avx512.mask.pshuf.b.") || // Added in 4.0 102 Name.startswith("avx2.pmax") || // Added in 3.9 103 Name.startswith("avx2.pmin") || // Added in 3.9 104 Name.startswith("avx512.mask.pmax") || // Added in 4.0 105 Name.startswith("avx512.mask.pmin") || // Added in 4.0 106 Name.startswith("avx2.vbroadcast") || // Added in 3.8 107 Name.startswith("avx2.pbroadcast") || // Added in 3.8 108 Name.startswith("avx.vpermil.") || // Added in 3.1 109 Name.startswith("sse2.pshuf") || // Added in 3.9 110 Name.startswith("avx512.pbroadcast") || // Added in 3.9 111 Name.startswith("avx512.mask.broadcast.s") || // Added in 3.9 112 Name.startswith("avx512.mask.movddup") || // Added in 3.9 113 Name.startswith("avx512.mask.movshdup") || // Added in 3.9 114 Name.startswith("avx512.mask.movsldup") || // Added in 3.9 115 Name.startswith("avx512.mask.pshuf.d.") || // Added in 3.9 116 Name.startswith("avx512.mask.pshufl.w.") || // Added in 3.9 117 Name.startswith("avx512.mask.pshufh.w.") || // Added in 3.9 118 Name.startswith("avx512.mask.shuf.p") || // Added in 4.0 119 Name.startswith("avx512.mask.vpermil.p") || // Added in 3.9 120 Name.startswith("avx512.mask.perm.df.") || // Added in 3.9 121 Name.startswith("avx512.mask.perm.di.") || // Added in 3.9 122 Name.startswith("avx512.mask.punpckl") || // Added in 3.9 123 Name.startswith("avx512.mask.punpckh") || // Added in 3.9 124 Name.startswith("avx512.mask.unpckl.") || // Added in 3.9 125 Name.startswith("avx512.mask.unpckh.") || // Added in 3.9 126 Name.startswith("avx512.mask.pand.") || // Added in 3.9 127 Name.startswith("avx512.mask.pandn.") || // Added in 3.9 128 Name.startswith("avx512.mask.por.") || // Added in 3.9 129 Name.startswith("avx512.mask.pxor.") || // Added in 3.9 130 Name.startswith("avx512.mask.and.") || // Added in 3.9 131 Name.startswith("avx512.mask.andn.") || // Added in 3.9 132 Name.startswith("avx512.mask.or.") || // Added in 3.9 133 Name.startswith("avx512.mask.xor.") || // Added in 3.9 134 Name.startswith("avx512.mask.padd.") || // Added in 4.0 135 Name.startswith("avx512.mask.psub.") || // Added in 4.0 136 Name.startswith("avx512.mask.pmull.") || // Added in 4.0 137 Name.startswith("avx512.mask.cvtdq2pd.") || // Added in 4.0 138 Name.startswith("avx512.mask.cvtudq2pd.") || // Added in 4.0 139 Name.startswith("avx512.mask.pmul.dq.") || // Added in 4.0 140 Name.startswith("avx512.mask.pmulu.dq.") || // Added in 4.0 141 Name.startswith("avx512.mask.packsswb.") || // Added in 5.0 142 Name.startswith("avx512.mask.packssdw.") || // Added in 5.0 143 Name.startswith("avx512.mask.packuswb.") || // Added in 5.0 144 Name.startswith("avx512.mask.packusdw.") || // Added in 5.0 145 Name == "avx512.mask.add.pd.128" || // Added in 4.0 146 Name == "avx512.mask.add.pd.256" || // Added in 4.0 147 Name == "avx512.mask.add.ps.128" || // Added in 4.0 148 Name == "avx512.mask.add.ps.256" || // Added in 4.0 149 Name == "avx512.mask.div.pd.128" || // Added in 4.0 150 Name == "avx512.mask.div.pd.256" || // Added in 4.0 151 Name == "avx512.mask.div.ps.128" || // Added in 4.0 152 Name == "avx512.mask.div.ps.256" || // Added in 4.0 153 Name == "avx512.mask.mul.pd.128" || // Added in 4.0 154 Name == "avx512.mask.mul.pd.256" || // Added in 4.0 155 Name == "avx512.mask.mul.ps.128" || // Added in 4.0 156 Name == "avx512.mask.mul.ps.256" || // Added in 4.0 157 Name == "avx512.mask.sub.pd.128" || // Added in 4.0 158 Name == "avx512.mask.sub.pd.256" || // Added in 4.0 159 Name == "avx512.mask.sub.ps.128" || // Added in 4.0 160 Name == "avx512.mask.sub.ps.256" || // Added in 4.0 161 Name == "avx512.mask.max.pd.128" || // Added in 5.0 162 Name == "avx512.mask.max.pd.256" || // Added in 5.0 163 Name == "avx512.mask.max.ps.128" || // Added in 5.0 164 Name == "avx512.mask.max.ps.256" || // Added in 5.0 165 Name == "avx512.mask.min.pd.128" || // Added in 5.0 166 Name == "avx512.mask.min.pd.256" || // Added in 5.0 167 Name == "avx512.mask.min.ps.128" || // Added in 5.0 168 Name == "avx512.mask.min.ps.256" || // Added in 5.0 169 Name.startswith("avx512.mask.vpermilvar.") || // Added in 4.0 170 Name.startswith("avx512.mask.psll.d") || // Added in 4.0 171 Name.startswith("avx512.mask.psll.q") || // Added in 4.0 172 Name.startswith("avx512.mask.psll.w") || // Added in 4.0 173 Name.startswith("avx512.mask.psra.d") || // Added in 4.0 174 Name.startswith("avx512.mask.psra.q") || // Added in 4.0 175 Name.startswith("avx512.mask.psra.w") || // Added in 4.0 176 Name.startswith("avx512.mask.psrl.d") || // Added in 4.0 177 Name.startswith("avx512.mask.psrl.q") || // Added in 4.0 178 Name.startswith("avx512.mask.psrl.w") || // Added in 4.0 179 Name.startswith("avx512.mask.pslli") || // Added in 4.0 180 Name.startswith("avx512.mask.psrai") || // Added in 4.0 181 Name.startswith("avx512.mask.psrli") || // Added in 4.0 182 Name.startswith("avx512.mask.psllv") || // Added in 4.0 183 Name.startswith("avx512.mask.psrav") || // Added in 4.0 184 Name.startswith("avx512.mask.psrlv") || // Added in 4.0 185 Name.startswith("sse41.pmovsx") || // Added in 3.8 186 Name.startswith("sse41.pmovzx") || // Added in 3.9 187 Name.startswith("avx2.pmovsx") || // Added in 3.9 188 Name.startswith("avx2.pmovzx") || // Added in 3.9 189 Name.startswith("avx512.mask.pmovsx") || // Added in 4.0 190 Name.startswith("avx512.mask.pmovzx") || // Added in 4.0 191 Name.startswith("avx512.mask.lzcnt.") || // Added in 5.0 192 Name == "sse2.cvtdq2pd" || // Added in 3.9 193 Name == "sse2.cvtps2pd" || // Added in 3.9 194 Name == "avx.cvtdq2.pd.256" || // Added in 3.9 195 Name == "avx.cvt.ps2.pd.256" || // Added in 3.9 196 Name.startswith("avx.vinsertf128.") || // Added in 3.7 197 Name == "avx2.vinserti128" || // Added in 3.7 198 Name.startswith("avx512.mask.insert") || // Added in 4.0 199 Name.startswith("avx.vextractf128.") || // Added in 3.7 200 Name == "avx2.vextracti128" || // Added in 3.7 201 Name.startswith("avx512.mask.vextract") || // Added in 4.0 202 Name.startswith("sse4a.movnt.") || // Added in 3.9 203 Name.startswith("avx.movnt.") || // Added in 3.2 204 Name.startswith("avx512.storent.") || // Added in 3.9 205 Name == "sse2.storel.dq" || // Added in 3.9 206 Name.startswith("sse.storeu.") || // Added in 3.9 207 Name.startswith("sse2.storeu.") || // Added in 3.9 208 Name.startswith("avx.storeu.") || // Added in 3.9 209 Name.startswith("avx512.mask.storeu.") || // Added in 3.9 210 Name.startswith("avx512.mask.store.p") || // Added in 3.9 211 Name.startswith("avx512.mask.store.b.") || // Added in 3.9 212 Name.startswith("avx512.mask.store.w.") || // Added in 3.9 213 Name.startswith("avx512.mask.store.d.") || // Added in 3.9 214 Name.startswith("avx512.mask.store.q.") || // Added in 3.9 215 Name.startswith("avx512.mask.loadu.") || // Added in 3.9 216 Name.startswith("avx512.mask.load.") || // Added in 3.9 217 Name == "sse42.crc32.64.8" || // Added in 3.4 218 Name.startswith("avx.vbroadcast.s") || // Added in 3.5 219 Name.startswith("avx512.mask.palignr.") || // Added in 3.9 220 Name.startswith("avx512.mask.valign.") || // Added in 4.0 221 Name.startswith("sse2.psll.dq") || // Added in 3.7 222 Name.startswith("sse2.psrl.dq") || // Added in 3.7 223 Name.startswith("avx2.psll.dq") || // Added in 3.7 224 Name.startswith("avx2.psrl.dq") || // Added in 3.7 225 Name.startswith("avx512.psll.dq") || // Added in 3.9 226 Name.startswith("avx512.psrl.dq") || // Added in 3.9 227 Name == "sse41.pblendw" || // Added in 3.7 228 Name.startswith("sse41.blendp") || // Added in 3.7 229 Name.startswith("avx.blend.p") || // Added in 3.7 230 Name == "avx2.pblendw" || // Added in 3.7 231 Name.startswith("avx2.pblendd.") || // Added in 3.7 232 Name.startswith("avx.vbroadcastf128") || // Added in 4.0 233 Name == "avx2.vbroadcasti128" || // Added in 3.7 234 Name == "xop.vpcmov" || // Added in 3.8 235 Name == "xop.vpcmov.256" || // Added in 5.0 236 Name.startswith("avx512.mask.move.s") || // Added in 4.0 237 (Name.startswith("xop.vpcom") && // Added in 3.2 238 F->arg_size() == 2)) 239 return true; 240 241 return false; 242 } 243 244 static bool UpgradeX86IntrinsicFunction(Function *F, StringRef Name, 245 Function *&NewFn) { 246 // Only handle intrinsics that start with "x86.". 247 if (!Name.startswith("x86.")) 248 return false; 249 // Remove "x86." prefix. 250 Name = Name.substr(4); 251 252 if (ShouldUpgradeX86Intrinsic(F, Name)) { 253 NewFn = nullptr; 254 return true; 255 } 256 257 // SSE4.1 ptest functions may have an old signature. 258 if (Name.startswith("sse41.ptest")) { // Added in 3.2 259 if (Name.substr(11) == "c") 260 return UpgradePTESTIntrinsic(F, Intrinsic::x86_sse41_ptestc, NewFn); 261 if (Name.substr(11) == "z") 262 return UpgradePTESTIntrinsic(F, Intrinsic::x86_sse41_ptestz, NewFn); 263 if (Name.substr(11) == "nzc") 264 return UpgradePTESTIntrinsic(F, Intrinsic::x86_sse41_ptestnzc, NewFn); 265 } 266 // Several blend and other instructions with masks used the wrong number of 267 // bits. 268 if (Name == "sse41.insertps") // Added in 3.6 269 return UpgradeX86IntrinsicsWith8BitMask(F, Intrinsic::x86_sse41_insertps, 270 NewFn); 271 if (Name == "sse41.dppd") // Added in 3.6 272 return UpgradeX86IntrinsicsWith8BitMask(F, Intrinsic::x86_sse41_dppd, 273 NewFn); 274 if (Name == "sse41.dpps") // Added in 3.6 275 return UpgradeX86IntrinsicsWith8BitMask(F, Intrinsic::x86_sse41_dpps, 276 NewFn); 277 if (Name == "sse41.mpsadbw") // Added in 3.6 278 return UpgradeX86IntrinsicsWith8BitMask(F, Intrinsic::x86_sse41_mpsadbw, 279 NewFn); 280 if (Name == "avx.dp.ps.256") // Added in 3.6 281 return UpgradeX86IntrinsicsWith8BitMask(F, Intrinsic::x86_avx_dp_ps_256, 282 NewFn); 283 if (Name == "avx2.mpsadbw") // Added in 3.6 284 return UpgradeX86IntrinsicsWith8BitMask(F, Intrinsic::x86_avx2_mpsadbw, 285 NewFn); 286 287 // frcz.ss/sd may need to have an argument dropped. Added in 3.2 288 if (Name.startswith("xop.vfrcz.ss") && F->arg_size() == 2) { 289 rename(F); 290 NewFn = Intrinsic::getDeclaration(F->getParent(), 291 Intrinsic::x86_xop_vfrcz_ss); 292 return true; 293 } 294 if (Name.startswith("xop.vfrcz.sd") && F->arg_size() == 2) { 295 rename(F); 296 NewFn = Intrinsic::getDeclaration(F->getParent(), 297 Intrinsic::x86_xop_vfrcz_sd); 298 return true; 299 } 300 // Upgrade any XOP PERMIL2 index operand still using a float/double vector. 301 if (Name.startswith("xop.vpermil2")) { // Added in 3.9 302 auto Idx = F->getFunctionType()->getParamType(2); 303 if (Idx->isFPOrFPVectorTy()) { 304 rename(F); 305 unsigned IdxSize = Idx->getPrimitiveSizeInBits(); 306 unsigned EltSize = Idx->getScalarSizeInBits(); 307 Intrinsic::ID Permil2ID; 308 if (EltSize == 64 && IdxSize == 128) 309 Permil2ID = Intrinsic::x86_xop_vpermil2pd; 310 else if (EltSize == 32 && IdxSize == 128) 311 Permil2ID = Intrinsic::x86_xop_vpermil2ps; 312 else if (EltSize == 64 && IdxSize == 256) 313 Permil2ID = Intrinsic::x86_xop_vpermil2pd_256; 314 else 315 Permil2ID = Intrinsic::x86_xop_vpermil2ps_256; 316 NewFn = Intrinsic::getDeclaration(F->getParent(), Permil2ID); 317 return true; 318 } 319 } 320 321 return false; 322 } 323 324 static bool UpgradeIntrinsicFunction1(Function *F, Function *&NewFn) { 325 assert(F && "Illegal to upgrade a non-existent Function."); 326 327 // Quickly eliminate it, if it's not a candidate. 328 StringRef Name = F->getName(); 329 if (Name.size() <= 8 || !Name.startswith("llvm.")) 330 return false; 331 Name = Name.substr(5); // Strip off "llvm." 332 333 switch (Name[0]) { 334 default: break; 335 case 'a': { 336 if (Name.startswith("arm.rbit") || Name.startswith("aarch64.rbit")) { 337 NewFn = Intrinsic::getDeclaration(F->getParent(), Intrinsic::bitreverse, 338 F->arg_begin()->getType()); 339 return true; 340 } 341 if (Name.startswith("arm.neon.vclz")) { 342 Type* args[2] = { 343 F->arg_begin()->getType(), 344 Type::getInt1Ty(F->getContext()) 345 }; 346 // Can't use Intrinsic::getDeclaration here as it adds a ".i1" to 347 // the end of the name. Change name from llvm.arm.neon.vclz.* to 348 // llvm.ctlz.* 349 FunctionType* fType = FunctionType::get(F->getReturnType(), args, false); 350 NewFn = Function::Create(fType, F->getLinkage(), 351 "llvm.ctlz." + Name.substr(14), F->getParent()); 352 return true; 353 } 354 if (Name.startswith("arm.neon.vcnt")) { 355 NewFn = Intrinsic::getDeclaration(F->getParent(), Intrinsic::ctpop, 356 F->arg_begin()->getType()); 357 return true; 358 } 359 Regex vldRegex("^arm\\.neon\\.vld([1234]|[234]lane)\\.v[a-z0-9]*$"); 360 if (vldRegex.match(Name)) { 361 auto fArgs = F->getFunctionType()->params(); 362 SmallVector<Type *, 4> Tys(fArgs.begin(), fArgs.end()); 363 // Can't use Intrinsic::getDeclaration here as the return types might 364 // then only be structurally equal. 365 FunctionType* fType = FunctionType::get(F->getReturnType(), Tys, false); 366 NewFn = Function::Create(fType, F->getLinkage(), 367 "llvm." + Name + ".p0i8", F->getParent()); 368 return true; 369 } 370 Regex vstRegex("^arm\\.neon\\.vst([1234]|[234]lane)\\.v[a-z0-9]*$"); 371 if (vstRegex.match(Name)) { 372 static const Intrinsic::ID StoreInts[] = {Intrinsic::arm_neon_vst1, 373 Intrinsic::arm_neon_vst2, 374 Intrinsic::arm_neon_vst3, 375 Intrinsic::arm_neon_vst4}; 376 377 static const Intrinsic::ID StoreLaneInts[] = { 378 Intrinsic::arm_neon_vst2lane, Intrinsic::arm_neon_vst3lane, 379 Intrinsic::arm_neon_vst4lane 380 }; 381 382 auto fArgs = F->getFunctionType()->params(); 383 Type *Tys[] = {fArgs[0], fArgs[1]}; 384 if (Name.find("lane") == StringRef::npos) 385 NewFn = Intrinsic::getDeclaration(F->getParent(), 386 StoreInts[fArgs.size() - 3], Tys); 387 else 388 NewFn = Intrinsic::getDeclaration(F->getParent(), 389 StoreLaneInts[fArgs.size() - 5], Tys); 390 return true; 391 } 392 if (Name == "aarch64.thread.pointer" || Name == "arm.thread.pointer") { 393 NewFn = Intrinsic::getDeclaration(F->getParent(), Intrinsic::thread_pointer); 394 return true; 395 } 396 break; 397 } 398 399 case 'c': { 400 if (Name.startswith("ctlz.") && F->arg_size() == 1) { 401 rename(F); 402 NewFn = Intrinsic::getDeclaration(F->getParent(), Intrinsic::ctlz, 403 F->arg_begin()->getType()); 404 return true; 405 } 406 if (Name.startswith("cttz.") && F->arg_size() == 1) { 407 rename(F); 408 NewFn = Intrinsic::getDeclaration(F->getParent(), Intrinsic::cttz, 409 F->arg_begin()->getType()); 410 return true; 411 } 412 break; 413 } 414 case 'i': { 415 if (Name.startswith("invariant.start")) { 416 auto Args = F->getFunctionType()->params(); 417 Type* ObjectPtr[1] = {Args[1]}; 418 if (F->getName() != 419 Intrinsic::getName(Intrinsic::invariant_start, ObjectPtr)) { 420 rename(F); 421 NewFn = Intrinsic::getDeclaration( 422 F->getParent(), Intrinsic::invariant_start, ObjectPtr); 423 return true; 424 } 425 } 426 if (Name.startswith("invariant.end")) { 427 auto Args = F->getFunctionType()->params(); 428 Type* ObjectPtr[1] = {Args[2]}; 429 if (F->getName() != 430 Intrinsic::getName(Intrinsic::invariant_end, ObjectPtr)) { 431 rename(F); 432 NewFn = Intrinsic::getDeclaration(F->getParent(), 433 Intrinsic::invariant_end, ObjectPtr); 434 return true; 435 } 436 } 437 break; 438 } 439 case 'm': { 440 if (Name.startswith("masked.load.")) { 441 Type *Tys[] = { F->getReturnType(), F->arg_begin()->getType() }; 442 if (F->getName() != Intrinsic::getName(Intrinsic::masked_load, Tys)) { 443 rename(F); 444 NewFn = Intrinsic::getDeclaration(F->getParent(), 445 Intrinsic::masked_load, 446 Tys); 447 return true; 448 } 449 } 450 if (Name.startswith("masked.store.")) { 451 auto Args = F->getFunctionType()->params(); 452 Type *Tys[] = { Args[0], Args[1] }; 453 if (F->getName() != Intrinsic::getName(Intrinsic::masked_store, Tys)) { 454 rename(F); 455 NewFn = Intrinsic::getDeclaration(F->getParent(), 456 Intrinsic::masked_store, 457 Tys); 458 return true; 459 } 460 } 461 break; 462 } 463 case 'n': { 464 if (Name.startswith("nvvm.")) { 465 Name = Name.substr(5); 466 467 // The following nvvm intrinsics correspond exactly to an LLVM intrinsic. 468 Intrinsic::ID IID = StringSwitch<Intrinsic::ID>(Name) 469 .Cases("brev32", "brev64", Intrinsic::bitreverse) 470 .Case("clz.i", Intrinsic::ctlz) 471 .Case("popc.i", Intrinsic::ctpop) 472 .Default(Intrinsic::not_intrinsic); 473 if (IID != Intrinsic::not_intrinsic && F->arg_size() == 1) { 474 NewFn = Intrinsic::getDeclaration(F->getParent(), IID, 475 {F->getReturnType()}); 476 return true; 477 } 478 479 // The following nvvm intrinsics correspond exactly to an LLVM idiom, but 480 // not to an intrinsic alone. We expand them in UpgradeIntrinsicCall. 481 // 482 // TODO: We could add lohi.i2d. 483 bool Expand = StringSwitch<bool>(Name) 484 .Cases("abs.i", "abs.ll", true) 485 .Cases("clz.ll", "popc.ll", "h2f", true) 486 .Cases("max.i", "max.ll", "max.ui", "max.ull", true) 487 .Cases("min.i", "min.ll", "min.ui", "min.ull", true) 488 .Default(false); 489 if (Expand) { 490 NewFn = nullptr; 491 return true; 492 } 493 } 494 } 495 case 'o': 496 // We only need to change the name to match the mangling including the 497 // address space. 498 if (F->arg_size() == 2 && Name.startswith("objectsize.")) { 499 Type *Tys[2] = { F->getReturnType(), F->arg_begin()->getType() }; 500 if (F->getName() != Intrinsic::getName(Intrinsic::objectsize, Tys)) { 501 rename(F); 502 NewFn = Intrinsic::getDeclaration(F->getParent(), 503 Intrinsic::objectsize, Tys); 504 return true; 505 } 506 } 507 break; 508 509 case 's': 510 if (Name == "stackprotectorcheck") { 511 NewFn = nullptr; 512 return true; 513 } 514 break; 515 516 case 'x': 517 if (UpgradeX86IntrinsicFunction(F, Name, NewFn)) 518 return true; 519 } 520 // Remangle our intrinsic since we upgrade the mangling 521 auto Result = llvm::Intrinsic::remangleIntrinsicFunction(F); 522 if (Result != None) { 523 NewFn = Result.getValue(); 524 return true; 525 } 526 527 // This may not belong here. This function is effectively being overloaded 528 // to both detect an intrinsic which needs upgrading, and to provide the 529 // upgraded form of the intrinsic. We should perhaps have two separate 530 // functions for this. 531 return false; 532 } 533 534 bool llvm::UpgradeIntrinsicFunction(Function *F, Function *&NewFn) { 535 NewFn = nullptr; 536 bool Upgraded = UpgradeIntrinsicFunction1(F, NewFn); 537 assert(F != NewFn && "Intrinsic function upgraded to the same function"); 538 539 // Upgrade intrinsic attributes. This does not change the function. 540 if (NewFn) 541 F = NewFn; 542 if (Intrinsic::ID id = F->getIntrinsicID()) 543 F->setAttributes(Intrinsic::getAttributes(F->getContext(), id)); 544 return Upgraded; 545 } 546 547 bool llvm::UpgradeGlobalVariable(GlobalVariable *GV) { 548 // Nothing to do yet. 549 return false; 550 } 551 552 // Handles upgrading SSE2/AVX2/AVX512BW PSLLDQ intrinsics by converting them 553 // to byte shuffles. 554 static Value *UpgradeX86PSLLDQIntrinsics(IRBuilder<> &Builder, 555 Value *Op, unsigned Shift) { 556 Type *ResultTy = Op->getType(); 557 unsigned NumElts = ResultTy->getVectorNumElements() * 8; 558 559 // Bitcast from a 64-bit element type to a byte element type. 560 Type *VecTy = VectorType::get(Builder.getInt8Ty(), NumElts); 561 Op = Builder.CreateBitCast(Op, VecTy, "cast"); 562 563 // We'll be shuffling in zeroes. 564 Value *Res = Constant::getNullValue(VecTy); 565 566 // If shift is less than 16, emit a shuffle to move the bytes. Otherwise, 567 // we'll just return the zero vector. 568 if (Shift < 16) { 569 uint32_t Idxs[64]; 570 // 256/512-bit version is split into 2/4 16-byte lanes. 571 for (unsigned l = 0; l != NumElts; l += 16) 572 for (unsigned i = 0; i != 16; ++i) { 573 unsigned Idx = NumElts + i - Shift; 574 if (Idx < NumElts) 575 Idx -= NumElts - 16; // end of lane, switch operand. 576 Idxs[l + i] = Idx + l; 577 } 578 579 Res = Builder.CreateShuffleVector(Res, Op, makeArrayRef(Idxs, NumElts)); 580 } 581 582 // Bitcast back to a 64-bit element type. 583 return Builder.CreateBitCast(Res, ResultTy, "cast"); 584 } 585 586 // Handles upgrading SSE2/AVX2/AVX512BW PSRLDQ intrinsics by converting them 587 // to byte shuffles. 588 static Value *UpgradeX86PSRLDQIntrinsics(IRBuilder<> &Builder, Value *Op, 589 unsigned Shift) { 590 Type *ResultTy = Op->getType(); 591 unsigned NumElts = ResultTy->getVectorNumElements() * 8; 592 593 // Bitcast from a 64-bit element type to a byte element type. 594 Type *VecTy = VectorType::get(Builder.getInt8Ty(), NumElts); 595 Op = Builder.CreateBitCast(Op, VecTy, "cast"); 596 597 // We'll be shuffling in zeroes. 598 Value *Res = Constant::getNullValue(VecTy); 599 600 // If shift is less than 16, emit a shuffle to move the bytes. Otherwise, 601 // we'll just return the zero vector. 602 if (Shift < 16) { 603 uint32_t Idxs[64]; 604 // 256/512-bit version is split into 2/4 16-byte lanes. 605 for (unsigned l = 0; l != NumElts; l += 16) 606 for (unsigned i = 0; i != 16; ++i) { 607 unsigned Idx = i + Shift; 608 if (Idx >= 16) 609 Idx += NumElts - 16; // end of lane, switch operand. 610 Idxs[l + i] = Idx + l; 611 } 612 613 Res = Builder.CreateShuffleVector(Op, Res, makeArrayRef(Idxs, NumElts)); 614 } 615 616 // Bitcast back to a 64-bit element type. 617 return Builder.CreateBitCast(Res, ResultTy, "cast"); 618 } 619 620 static Value *getX86MaskVec(IRBuilder<> &Builder, Value *Mask, 621 unsigned NumElts) { 622 llvm::VectorType *MaskTy = llvm::VectorType::get(Builder.getInt1Ty(), 623 cast<IntegerType>(Mask->getType())->getBitWidth()); 624 Mask = Builder.CreateBitCast(Mask, MaskTy); 625 626 // If we have less than 8 elements, then the starting mask was an i8 and 627 // we need to extract down to the right number of elements. 628 if (NumElts < 8) { 629 uint32_t Indices[4]; 630 for (unsigned i = 0; i != NumElts; ++i) 631 Indices[i] = i; 632 Mask = Builder.CreateShuffleVector(Mask, Mask, 633 makeArrayRef(Indices, NumElts), 634 "extract"); 635 } 636 637 return Mask; 638 } 639 640 static Value *EmitX86Select(IRBuilder<> &Builder, Value *Mask, 641 Value *Op0, Value *Op1) { 642 // If the mask is all ones just emit the align operation. 643 if (const auto *C = dyn_cast<Constant>(Mask)) 644 if (C->isAllOnesValue()) 645 return Op0; 646 647 Mask = getX86MaskVec(Builder, Mask, Op0->getType()->getVectorNumElements()); 648 return Builder.CreateSelect(Mask, Op0, Op1); 649 } 650 651 // Handle autoupgrade for masked PALIGNR and VALIGND/Q intrinsics. 652 // PALIGNR handles large immediates by shifting while VALIGN masks the immediate 653 // so we need to handle both cases. VALIGN also doesn't have 128-bit lanes. 654 static Value *UpgradeX86ALIGNIntrinsics(IRBuilder<> &Builder, Value *Op0, 655 Value *Op1, Value *Shift, 656 Value *Passthru, Value *Mask, 657 bool IsVALIGN) { 658 unsigned ShiftVal = cast<llvm::ConstantInt>(Shift)->getZExtValue(); 659 660 unsigned NumElts = Op0->getType()->getVectorNumElements(); 661 assert((IsVALIGN || NumElts % 16 == 0) && "Illegal NumElts for PALIGNR!"); 662 assert((!IsVALIGN || NumElts <= 16) && "NumElts too large for VALIGN!"); 663 assert(isPowerOf2_32(NumElts) && "NumElts not a power of 2!"); 664 665 // Mask the immediate for VALIGN. 666 if (IsVALIGN) 667 ShiftVal &= (NumElts - 1); 668 669 // If palignr is shifting the pair of vectors more than the size of two 670 // lanes, emit zero. 671 if (ShiftVal >= 32) 672 return llvm::Constant::getNullValue(Op0->getType()); 673 674 // If palignr is shifting the pair of input vectors more than one lane, 675 // but less than two lanes, convert to shifting in zeroes. 676 if (ShiftVal > 16) { 677 ShiftVal -= 16; 678 Op1 = Op0; 679 Op0 = llvm::Constant::getNullValue(Op0->getType()); 680 } 681 682 uint32_t Indices[64]; 683 // 256-bit palignr operates on 128-bit lanes so we need to handle that 684 for (unsigned l = 0; l < NumElts; l += 16) { 685 for (unsigned i = 0; i != 16; ++i) { 686 unsigned Idx = ShiftVal + i; 687 if (!IsVALIGN && Idx >= 16) // Disable wrap for VALIGN. 688 Idx += NumElts - 16; // End of lane, switch operand. 689 Indices[l + i] = Idx + l; 690 } 691 } 692 693 Value *Align = Builder.CreateShuffleVector(Op1, Op0, 694 makeArrayRef(Indices, NumElts), 695 "palignr"); 696 697 return EmitX86Select(Builder, Mask, Align, Passthru); 698 } 699 700 static Value *UpgradeMaskedStore(IRBuilder<> &Builder, 701 Value *Ptr, Value *Data, Value *Mask, 702 bool Aligned) { 703 // Cast the pointer to the right type. 704 Ptr = Builder.CreateBitCast(Ptr, 705 llvm::PointerType::getUnqual(Data->getType())); 706 unsigned Align = 707 Aligned ? cast<VectorType>(Data->getType())->getBitWidth() / 8 : 1; 708 709 // If the mask is all ones just emit a regular store. 710 if (const auto *C = dyn_cast<Constant>(Mask)) 711 if (C->isAllOnesValue()) 712 return Builder.CreateAlignedStore(Data, Ptr, Align); 713 714 // Convert the mask from an integer type to a vector of i1. 715 unsigned NumElts = Data->getType()->getVectorNumElements(); 716 Mask = getX86MaskVec(Builder, Mask, NumElts); 717 return Builder.CreateMaskedStore(Data, Ptr, Align, Mask); 718 } 719 720 static Value *UpgradeMaskedLoad(IRBuilder<> &Builder, 721 Value *Ptr, Value *Passthru, Value *Mask, 722 bool Aligned) { 723 // Cast the pointer to the right type. 724 Ptr = Builder.CreateBitCast(Ptr, 725 llvm::PointerType::getUnqual(Passthru->getType())); 726 unsigned Align = 727 Aligned ? cast<VectorType>(Passthru->getType())->getBitWidth() / 8 : 1; 728 729 // If the mask is all ones just emit a regular store. 730 if (const auto *C = dyn_cast<Constant>(Mask)) 731 if (C->isAllOnesValue()) 732 return Builder.CreateAlignedLoad(Ptr, Align); 733 734 // Convert the mask from an integer type to a vector of i1. 735 unsigned NumElts = Passthru->getType()->getVectorNumElements(); 736 Mask = getX86MaskVec(Builder, Mask, NumElts); 737 return Builder.CreateMaskedLoad(Ptr, Align, Mask, Passthru); 738 } 739 740 static Value *upgradeIntMinMax(IRBuilder<> &Builder, CallInst &CI, 741 ICmpInst::Predicate Pred) { 742 Value *Op0 = CI.getArgOperand(0); 743 Value *Op1 = CI.getArgOperand(1); 744 Value *Cmp = Builder.CreateICmp(Pred, Op0, Op1); 745 Value *Res = Builder.CreateSelect(Cmp, Op0, Op1); 746 747 if (CI.getNumArgOperands() == 4) 748 Res = EmitX86Select(Builder, CI.getArgOperand(3), Res, CI.getArgOperand(2)); 749 750 return Res; 751 } 752 753 static Value *upgradeMaskedCompare(IRBuilder<> &Builder, CallInst &CI, 754 ICmpInst::Predicate Pred) { 755 Value *Op0 = CI.getArgOperand(0); 756 unsigned NumElts = Op0->getType()->getVectorNumElements(); 757 Value *Cmp = Builder.CreateICmp(Pred, Op0, CI.getArgOperand(1)); 758 759 Value *Mask = CI.getArgOperand(2); 760 const auto *C = dyn_cast<Constant>(Mask); 761 if (!C || !C->isAllOnesValue()) 762 Cmp = Builder.CreateAnd(Cmp, getX86MaskVec(Builder, Mask, NumElts)); 763 764 if (NumElts < 8) { 765 uint32_t Indices[8]; 766 for (unsigned i = 0; i != NumElts; ++i) 767 Indices[i] = i; 768 for (unsigned i = NumElts; i != 8; ++i) 769 Indices[i] = NumElts + i % NumElts; 770 Cmp = Builder.CreateShuffleVector(Cmp, 771 Constant::getNullValue(Cmp->getType()), 772 Indices); 773 } 774 return Builder.CreateBitCast(Cmp, IntegerType::get(CI.getContext(), 775 std::max(NumElts, 8U))); 776 } 777 778 // Replace a masked intrinsic with an older unmasked intrinsic. 779 static Value *UpgradeX86MaskedShift(IRBuilder<> &Builder, CallInst &CI, 780 Intrinsic::ID IID) { 781 Function *F = CI.getCalledFunction(); 782 Function *Intrin = Intrinsic::getDeclaration(F->getParent(), IID); 783 Value *Rep = Builder.CreateCall(Intrin, 784 { CI.getArgOperand(0), CI.getArgOperand(1) }); 785 return EmitX86Select(Builder, CI.getArgOperand(3), Rep, CI.getArgOperand(2)); 786 } 787 788 static Value* upgradeMaskedMove(IRBuilder<> &Builder, CallInst &CI) { 789 Value* A = CI.getArgOperand(0); 790 Value* B = CI.getArgOperand(1); 791 Value* Src = CI.getArgOperand(2); 792 Value* Mask = CI.getArgOperand(3); 793 794 Value* AndNode = Builder.CreateAnd(Mask, APInt(8, 1)); 795 Value* Cmp = Builder.CreateIsNotNull(AndNode); 796 Value* Extract1 = Builder.CreateExtractElement(B, (uint64_t)0); 797 Value* Extract2 = Builder.CreateExtractElement(Src, (uint64_t)0); 798 Value* Select = Builder.CreateSelect(Cmp, Extract1, Extract2); 799 return Builder.CreateInsertElement(A, Select, (uint64_t)0); 800 } 801 802 /// Upgrade a call to an old intrinsic. All argument and return casting must be 803 /// provided to seamlessly integrate with existing context. 804 void llvm::UpgradeIntrinsicCall(CallInst *CI, Function *NewFn) { 805 Function *F = CI->getCalledFunction(); 806 LLVMContext &C = CI->getContext(); 807 IRBuilder<> Builder(C); 808 Builder.SetInsertPoint(CI->getParent(), CI->getIterator()); 809 810 assert(F && "Intrinsic call is not direct?"); 811 812 if (!NewFn) { 813 // Get the Function's name. 814 StringRef Name = F->getName(); 815 816 assert(Name.startswith("llvm.") && "Intrinsic doesn't start with 'llvm.'"); 817 Name = Name.substr(5); 818 819 bool IsX86 = Name.startswith("x86."); 820 if (IsX86) 821 Name = Name.substr(4); 822 bool IsNVVM = Name.startswith("nvvm."); 823 if (IsNVVM) 824 Name = Name.substr(5); 825 826 if (IsX86 && Name.startswith("sse4a.movnt.")) { 827 Module *M = F->getParent(); 828 SmallVector<Metadata *, 1> Elts; 829 Elts.push_back( 830 ConstantAsMetadata::get(ConstantInt::get(Type::getInt32Ty(C), 1))); 831 MDNode *Node = MDNode::get(C, Elts); 832 833 Value *Arg0 = CI->getArgOperand(0); 834 Value *Arg1 = CI->getArgOperand(1); 835 836 // Nontemporal (unaligned) store of the 0'th element of the float/double 837 // vector. 838 Type *SrcEltTy = cast<VectorType>(Arg1->getType())->getElementType(); 839 PointerType *EltPtrTy = PointerType::getUnqual(SrcEltTy); 840 Value *Addr = Builder.CreateBitCast(Arg0, EltPtrTy, "cast"); 841 Value *Extract = 842 Builder.CreateExtractElement(Arg1, (uint64_t)0, "extractelement"); 843 844 StoreInst *SI = Builder.CreateAlignedStore(Extract, Addr, 1); 845 SI->setMetadata(M->getMDKindID("nontemporal"), Node); 846 847 // Remove intrinsic. 848 CI->eraseFromParent(); 849 return; 850 } 851 852 if (IsX86 && (Name.startswith("avx.movnt.") || 853 Name.startswith("avx512.storent."))) { 854 Module *M = F->getParent(); 855 SmallVector<Metadata *, 1> Elts; 856 Elts.push_back( 857 ConstantAsMetadata::get(ConstantInt::get(Type::getInt32Ty(C), 1))); 858 MDNode *Node = MDNode::get(C, Elts); 859 860 Value *Arg0 = CI->getArgOperand(0); 861 Value *Arg1 = CI->getArgOperand(1); 862 863 // Convert the type of the pointer to a pointer to the stored type. 864 Value *BC = Builder.CreateBitCast(Arg0, 865 PointerType::getUnqual(Arg1->getType()), 866 "cast"); 867 VectorType *VTy = cast<VectorType>(Arg1->getType()); 868 StoreInst *SI = Builder.CreateAlignedStore(Arg1, BC, 869 VTy->getBitWidth() / 8); 870 SI->setMetadata(M->getMDKindID("nontemporal"), Node); 871 872 // Remove intrinsic. 873 CI->eraseFromParent(); 874 return; 875 } 876 877 if (IsX86 && Name == "sse2.storel.dq") { 878 Value *Arg0 = CI->getArgOperand(0); 879 Value *Arg1 = CI->getArgOperand(1); 880 881 Type *NewVecTy = VectorType::get(Type::getInt64Ty(C), 2); 882 Value *BC0 = Builder.CreateBitCast(Arg1, NewVecTy, "cast"); 883 Value *Elt = Builder.CreateExtractElement(BC0, (uint64_t)0); 884 Value *BC = Builder.CreateBitCast(Arg0, 885 PointerType::getUnqual(Elt->getType()), 886 "cast"); 887 Builder.CreateAlignedStore(Elt, BC, 1); 888 889 // Remove intrinsic. 890 CI->eraseFromParent(); 891 return; 892 } 893 894 if (IsX86 && (Name.startswith("sse.storeu.") || 895 Name.startswith("sse2.storeu.") || 896 Name.startswith("avx.storeu."))) { 897 Value *Arg0 = CI->getArgOperand(0); 898 Value *Arg1 = CI->getArgOperand(1); 899 900 Arg0 = Builder.CreateBitCast(Arg0, 901 PointerType::getUnqual(Arg1->getType()), 902 "cast"); 903 Builder.CreateAlignedStore(Arg1, Arg0, 1); 904 905 // Remove intrinsic. 906 CI->eraseFromParent(); 907 return; 908 } 909 910 if (IsX86 && (Name.startswith("avx512.mask.store"))) { 911 // "avx512.mask.storeu." or "avx512.mask.store." 912 bool Aligned = Name[17] != 'u'; // "avx512.mask.storeu". 913 UpgradeMaskedStore(Builder, CI->getArgOperand(0), CI->getArgOperand(1), 914 CI->getArgOperand(2), Aligned); 915 916 // Remove intrinsic. 917 CI->eraseFromParent(); 918 return; 919 } 920 921 Value *Rep; 922 // Upgrade packed integer vector compare intrinsics to compare instructions. 923 if (IsX86 && (Name.startswith("sse2.pcmp") || 924 Name.startswith("avx2.pcmp"))) { 925 // "sse2.pcpmpeq." "sse2.pcmpgt." "avx2.pcmpeq." or "avx2.pcmpgt." 926 bool CmpEq = Name[9] == 'e'; 927 Rep = Builder.CreateICmp(CmpEq ? ICmpInst::ICMP_EQ : ICmpInst::ICMP_SGT, 928 CI->getArgOperand(0), CI->getArgOperand(1)); 929 Rep = Builder.CreateSExt(Rep, CI->getType(), ""); 930 } else if (IsX86 && (Name == "sse.add.ss" || Name == "sse2.add.sd")) { 931 Type *I32Ty = Type::getInt32Ty(C); 932 Value *Elt0 = Builder.CreateExtractElement(CI->getArgOperand(0), 933 ConstantInt::get(I32Ty, 0)); 934 Value *Elt1 = Builder.CreateExtractElement(CI->getArgOperand(1), 935 ConstantInt::get(I32Ty, 0)); 936 Rep = Builder.CreateInsertElement(CI->getArgOperand(0), 937 Builder.CreateFAdd(Elt0, Elt1), 938 ConstantInt::get(I32Ty, 0)); 939 } else if (IsX86 && (Name == "sse.sub.ss" || Name == "sse2.sub.sd")) { 940 Type *I32Ty = Type::getInt32Ty(C); 941 Value *Elt0 = Builder.CreateExtractElement(CI->getArgOperand(0), 942 ConstantInt::get(I32Ty, 0)); 943 Value *Elt1 = Builder.CreateExtractElement(CI->getArgOperand(1), 944 ConstantInt::get(I32Ty, 0)); 945 Rep = Builder.CreateInsertElement(CI->getArgOperand(0), 946 Builder.CreateFSub(Elt0, Elt1), 947 ConstantInt::get(I32Ty, 0)); 948 } else if (IsX86 && (Name == "sse.mul.ss" || Name == "sse2.mul.sd")) { 949 Type *I32Ty = Type::getInt32Ty(C); 950 Value *Elt0 = Builder.CreateExtractElement(CI->getArgOperand(0), 951 ConstantInt::get(I32Ty, 0)); 952 Value *Elt1 = Builder.CreateExtractElement(CI->getArgOperand(1), 953 ConstantInt::get(I32Ty, 0)); 954 Rep = Builder.CreateInsertElement(CI->getArgOperand(0), 955 Builder.CreateFMul(Elt0, Elt1), 956 ConstantInt::get(I32Ty, 0)); 957 } else if (IsX86 && (Name == "sse.div.ss" || Name == "sse2.div.sd")) { 958 Type *I32Ty = Type::getInt32Ty(C); 959 Value *Elt0 = Builder.CreateExtractElement(CI->getArgOperand(0), 960 ConstantInt::get(I32Ty, 0)); 961 Value *Elt1 = Builder.CreateExtractElement(CI->getArgOperand(1), 962 ConstantInt::get(I32Ty, 0)); 963 Rep = Builder.CreateInsertElement(CI->getArgOperand(0), 964 Builder.CreateFDiv(Elt0, Elt1), 965 ConstantInt::get(I32Ty, 0)); 966 } else if (IsX86 && Name.startswith("avx512.mask.pcmp")) { 967 // "avx512.mask.pcmpeq." or "avx512.mask.pcmpgt." 968 bool CmpEq = Name[16] == 'e'; 969 Rep = upgradeMaskedCompare(Builder, *CI, 970 CmpEq ? ICmpInst::ICMP_EQ 971 : ICmpInst::ICMP_SGT); 972 } else if (IsX86 && (Name == "sse41.pmaxsb" || 973 Name == "sse2.pmaxs.w" || 974 Name == "sse41.pmaxsd" || 975 Name.startswith("avx2.pmaxs") || 976 Name.startswith("avx512.mask.pmaxs"))) { 977 Rep = upgradeIntMinMax(Builder, *CI, ICmpInst::ICMP_SGT); 978 } else if (IsX86 && (Name == "sse2.pmaxu.b" || 979 Name == "sse41.pmaxuw" || 980 Name == "sse41.pmaxud" || 981 Name.startswith("avx2.pmaxu") || 982 Name.startswith("avx512.mask.pmaxu"))) { 983 Rep = upgradeIntMinMax(Builder, *CI, ICmpInst::ICMP_UGT); 984 } else if (IsX86 && (Name == "sse41.pminsb" || 985 Name == "sse2.pmins.w" || 986 Name == "sse41.pminsd" || 987 Name.startswith("avx2.pmins") || 988 Name.startswith("avx512.mask.pmins"))) { 989 Rep = upgradeIntMinMax(Builder, *CI, ICmpInst::ICMP_SLT); 990 } else if (IsX86 && (Name == "sse2.pminu.b" || 991 Name == "sse41.pminuw" || 992 Name == "sse41.pminud" || 993 Name.startswith("avx2.pminu") || 994 Name.startswith("avx512.mask.pminu"))) { 995 Rep = upgradeIntMinMax(Builder, *CI, ICmpInst::ICMP_ULT); 996 } else if (IsX86 && (Name == "sse2.cvtdq2pd" || 997 Name == "sse2.cvtps2pd" || 998 Name == "avx.cvtdq2.pd.256" || 999 Name == "avx.cvt.ps2.pd.256" || 1000 Name.startswith("avx512.mask.cvtdq2pd.") || 1001 Name.startswith("avx512.mask.cvtudq2pd."))) { 1002 // Lossless i32/float to double conversion. 1003 // Extract the bottom elements if necessary and convert to double vector. 1004 Value *Src = CI->getArgOperand(0); 1005 VectorType *SrcTy = cast<VectorType>(Src->getType()); 1006 VectorType *DstTy = cast<VectorType>(CI->getType()); 1007 Rep = CI->getArgOperand(0); 1008 1009 unsigned NumDstElts = DstTy->getNumElements(); 1010 if (NumDstElts < SrcTy->getNumElements()) { 1011 assert(NumDstElts == 2 && "Unexpected vector size"); 1012 uint32_t ShuffleMask[2] = { 0, 1 }; 1013 Rep = Builder.CreateShuffleVector(Rep, UndefValue::get(SrcTy), 1014 ShuffleMask); 1015 } 1016 1017 bool SInt2Double = (StringRef::npos != Name.find("cvtdq2")); 1018 bool UInt2Double = (StringRef::npos != Name.find("cvtudq2")); 1019 if (SInt2Double) 1020 Rep = Builder.CreateSIToFP(Rep, DstTy, "cvtdq2pd"); 1021 else if (UInt2Double) 1022 Rep = Builder.CreateUIToFP(Rep, DstTy, "cvtudq2pd"); 1023 else 1024 Rep = Builder.CreateFPExt(Rep, DstTy, "cvtps2pd"); 1025 1026 if (CI->getNumArgOperands() == 3) 1027 Rep = EmitX86Select(Builder, CI->getArgOperand(2), Rep, 1028 CI->getArgOperand(1)); 1029 } else if (IsX86 && (Name.startswith("avx512.mask.loadu."))) { 1030 Rep = UpgradeMaskedLoad(Builder, CI->getArgOperand(0), 1031 CI->getArgOperand(1), CI->getArgOperand(2), 1032 /*Aligned*/false); 1033 } else if (IsX86 && (Name.startswith("avx512.mask.load."))) { 1034 Rep = UpgradeMaskedLoad(Builder, CI->getArgOperand(0), 1035 CI->getArgOperand(1),CI->getArgOperand(2), 1036 /*Aligned*/true); 1037 } else if (IsX86 && Name.startswith("xop.vpcom")) { 1038 Intrinsic::ID intID; 1039 if (Name.endswith("ub")) 1040 intID = Intrinsic::x86_xop_vpcomub; 1041 else if (Name.endswith("uw")) 1042 intID = Intrinsic::x86_xop_vpcomuw; 1043 else if (Name.endswith("ud")) 1044 intID = Intrinsic::x86_xop_vpcomud; 1045 else if (Name.endswith("uq")) 1046 intID = Intrinsic::x86_xop_vpcomuq; 1047 else if (Name.endswith("b")) 1048 intID = Intrinsic::x86_xop_vpcomb; 1049 else if (Name.endswith("w")) 1050 intID = Intrinsic::x86_xop_vpcomw; 1051 else if (Name.endswith("d")) 1052 intID = Intrinsic::x86_xop_vpcomd; 1053 else if (Name.endswith("q")) 1054 intID = Intrinsic::x86_xop_vpcomq; 1055 else 1056 llvm_unreachable("Unknown suffix"); 1057 1058 Name = Name.substr(9); // strip off "xop.vpcom" 1059 unsigned Imm; 1060 if (Name.startswith("lt")) 1061 Imm = 0; 1062 else if (Name.startswith("le")) 1063 Imm = 1; 1064 else if (Name.startswith("gt")) 1065 Imm = 2; 1066 else if (Name.startswith("ge")) 1067 Imm = 3; 1068 else if (Name.startswith("eq")) 1069 Imm = 4; 1070 else if (Name.startswith("ne")) 1071 Imm = 5; 1072 else if (Name.startswith("false")) 1073 Imm = 6; 1074 else if (Name.startswith("true")) 1075 Imm = 7; 1076 else 1077 llvm_unreachable("Unknown condition"); 1078 1079 Function *VPCOM = Intrinsic::getDeclaration(F->getParent(), intID); 1080 Rep = 1081 Builder.CreateCall(VPCOM, {CI->getArgOperand(0), CI->getArgOperand(1), 1082 Builder.getInt8(Imm)}); 1083 } else if (IsX86 && Name.startswith("xop.vpcmov")) { 1084 Value *Sel = CI->getArgOperand(2); 1085 Value *NotSel = Builder.CreateNot(Sel); 1086 Value *Sel0 = Builder.CreateAnd(CI->getArgOperand(0), Sel); 1087 Value *Sel1 = Builder.CreateAnd(CI->getArgOperand(1), NotSel); 1088 Rep = Builder.CreateOr(Sel0, Sel1); 1089 } else if (IsX86 && Name == "sse42.crc32.64.8") { 1090 Function *CRC32 = Intrinsic::getDeclaration(F->getParent(), 1091 Intrinsic::x86_sse42_crc32_32_8); 1092 Value *Trunc0 = Builder.CreateTrunc(CI->getArgOperand(0), Type::getInt32Ty(C)); 1093 Rep = Builder.CreateCall(CRC32, {Trunc0, CI->getArgOperand(1)}); 1094 Rep = Builder.CreateZExt(Rep, CI->getType(), ""); 1095 } else if (IsX86 && Name.startswith("avx.vbroadcast.s")) { 1096 // Replace broadcasts with a series of insertelements. 1097 Type *VecTy = CI->getType(); 1098 Type *EltTy = VecTy->getVectorElementType(); 1099 unsigned EltNum = VecTy->getVectorNumElements(); 1100 Value *Cast = Builder.CreateBitCast(CI->getArgOperand(0), 1101 EltTy->getPointerTo()); 1102 Value *Load = Builder.CreateLoad(EltTy, Cast); 1103 Type *I32Ty = Type::getInt32Ty(C); 1104 Rep = UndefValue::get(VecTy); 1105 for (unsigned I = 0; I < EltNum; ++I) 1106 Rep = Builder.CreateInsertElement(Rep, Load, 1107 ConstantInt::get(I32Ty, I)); 1108 } else if (IsX86 && (Name.startswith("sse41.pmovsx") || 1109 Name.startswith("sse41.pmovzx") || 1110 Name.startswith("avx2.pmovsx") || 1111 Name.startswith("avx2.pmovzx") || 1112 Name.startswith("avx512.mask.pmovsx") || 1113 Name.startswith("avx512.mask.pmovzx"))) { 1114 VectorType *SrcTy = cast<VectorType>(CI->getArgOperand(0)->getType()); 1115 VectorType *DstTy = cast<VectorType>(CI->getType()); 1116 unsigned NumDstElts = DstTy->getNumElements(); 1117 1118 // Extract a subvector of the first NumDstElts lanes and sign/zero extend. 1119 SmallVector<uint32_t, 8> ShuffleMask(NumDstElts); 1120 for (unsigned i = 0; i != NumDstElts; ++i) 1121 ShuffleMask[i] = i; 1122 1123 Value *SV = Builder.CreateShuffleVector( 1124 CI->getArgOperand(0), UndefValue::get(SrcTy), ShuffleMask); 1125 1126 bool DoSext = (StringRef::npos != Name.find("pmovsx")); 1127 Rep = DoSext ? Builder.CreateSExt(SV, DstTy) 1128 : Builder.CreateZExt(SV, DstTy); 1129 // If there are 3 arguments, it's a masked intrinsic so we need a select. 1130 if (CI->getNumArgOperands() == 3) 1131 Rep = EmitX86Select(Builder, CI->getArgOperand(2), Rep, 1132 CI->getArgOperand(1)); 1133 } else if (IsX86 && (Name.startswith("avx.vbroadcastf128") || 1134 Name == "avx2.vbroadcasti128")) { 1135 // Replace vbroadcastf128/vbroadcasti128 with a vector load+shuffle. 1136 Type *EltTy = CI->getType()->getVectorElementType(); 1137 unsigned NumSrcElts = 128 / EltTy->getPrimitiveSizeInBits(); 1138 Type *VT = VectorType::get(EltTy, NumSrcElts); 1139 Value *Op = Builder.CreatePointerCast(CI->getArgOperand(0), 1140 PointerType::getUnqual(VT)); 1141 Value *Load = Builder.CreateAlignedLoad(Op, 1); 1142 if (NumSrcElts == 2) 1143 Rep = Builder.CreateShuffleVector(Load, UndefValue::get(Load->getType()), 1144 { 0, 1, 0, 1 }); 1145 else 1146 Rep = Builder.CreateShuffleVector(Load, UndefValue::get(Load->getType()), 1147 { 0, 1, 2, 3, 0, 1, 2, 3 }); 1148 } else if (IsX86 && (Name.startswith("avx2.pbroadcast") || 1149 Name.startswith("avx2.vbroadcast") || 1150 Name.startswith("avx512.pbroadcast") || 1151 Name.startswith("avx512.mask.broadcast.s"))) { 1152 // Replace vp?broadcasts with a vector shuffle. 1153 Value *Op = CI->getArgOperand(0); 1154 unsigned NumElts = CI->getType()->getVectorNumElements(); 1155 Type *MaskTy = VectorType::get(Type::getInt32Ty(C), NumElts); 1156 Rep = Builder.CreateShuffleVector(Op, UndefValue::get(Op->getType()), 1157 Constant::getNullValue(MaskTy)); 1158 1159 if (CI->getNumArgOperands() == 3) 1160 Rep = EmitX86Select(Builder, CI->getArgOperand(2), Rep, 1161 CI->getArgOperand(1)); 1162 } else if (IsX86 && Name.startswith("avx512.mask.palignr.")) { 1163 Rep = UpgradeX86ALIGNIntrinsics(Builder, CI->getArgOperand(0), 1164 CI->getArgOperand(1), 1165 CI->getArgOperand(2), 1166 CI->getArgOperand(3), 1167 CI->getArgOperand(4), 1168 false); 1169 } else if (IsX86 && Name.startswith("avx512.mask.valign.")) { 1170 Rep = UpgradeX86ALIGNIntrinsics(Builder, CI->getArgOperand(0), 1171 CI->getArgOperand(1), 1172 CI->getArgOperand(2), 1173 CI->getArgOperand(3), 1174 CI->getArgOperand(4), 1175 true); 1176 } else if (IsX86 && (Name == "sse2.psll.dq" || 1177 Name == "avx2.psll.dq")) { 1178 // 128/256-bit shift left specified in bits. 1179 unsigned Shift = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue(); 1180 Rep = UpgradeX86PSLLDQIntrinsics(Builder, CI->getArgOperand(0), 1181 Shift / 8); // Shift is in bits. 1182 } else if (IsX86 && (Name == "sse2.psrl.dq" || 1183 Name == "avx2.psrl.dq")) { 1184 // 128/256-bit shift right specified in bits. 1185 unsigned Shift = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue(); 1186 Rep = UpgradeX86PSRLDQIntrinsics(Builder, CI->getArgOperand(0), 1187 Shift / 8); // Shift is in bits. 1188 } else if (IsX86 && (Name == "sse2.psll.dq.bs" || 1189 Name == "avx2.psll.dq.bs" || 1190 Name == "avx512.psll.dq.512")) { 1191 // 128/256/512-bit shift left specified in bytes. 1192 unsigned Shift = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue(); 1193 Rep = UpgradeX86PSLLDQIntrinsics(Builder, CI->getArgOperand(0), Shift); 1194 } else if (IsX86 && (Name == "sse2.psrl.dq.bs" || 1195 Name == "avx2.psrl.dq.bs" || 1196 Name == "avx512.psrl.dq.512")) { 1197 // 128/256/512-bit shift right specified in bytes. 1198 unsigned Shift = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue(); 1199 Rep = UpgradeX86PSRLDQIntrinsics(Builder, CI->getArgOperand(0), Shift); 1200 } else if (IsX86 && (Name == "sse41.pblendw" || 1201 Name.startswith("sse41.blendp") || 1202 Name.startswith("avx.blend.p") || 1203 Name == "avx2.pblendw" || 1204 Name.startswith("avx2.pblendd."))) { 1205 Value *Op0 = CI->getArgOperand(0); 1206 Value *Op1 = CI->getArgOperand(1); 1207 unsigned Imm = cast <ConstantInt>(CI->getArgOperand(2))->getZExtValue(); 1208 VectorType *VecTy = cast<VectorType>(CI->getType()); 1209 unsigned NumElts = VecTy->getNumElements(); 1210 1211 SmallVector<uint32_t, 16> Idxs(NumElts); 1212 for (unsigned i = 0; i != NumElts; ++i) 1213 Idxs[i] = ((Imm >> (i%8)) & 1) ? i + NumElts : i; 1214 1215 Rep = Builder.CreateShuffleVector(Op0, Op1, Idxs); 1216 } else if (IsX86 && (Name.startswith("avx.vinsertf128.") || 1217 Name == "avx2.vinserti128" || 1218 Name.startswith("avx512.mask.insert"))) { 1219 Value *Op0 = CI->getArgOperand(0); 1220 Value *Op1 = CI->getArgOperand(1); 1221 unsigned Imm = cast<ConstantInt>(CI->getArgOperand(2))->getZExtValue(); 1222 unsigned DstNumElts = CI->getType()->getVectorNumElements(); 1223 unsigned SrcNumElts = Op1->getType()->getVectorNumElements(); 1224 unsigned Scale = DstNumElts / SrcNumElts; 1225 1226 // Mask off the high bits of the immediate value; hardware ignores those. 1227 Imm = Imm % Scale; 1228 1229 // Extend the second operand into a vector the size of the destination. 1230 Value *UndefV = UndefValue::get(Op1->getType()); 1231 SmallVector<uint32_t, 8> Idxs(DstNumElts); 1232 for (unsigned i = 0; i != SrcNumElts; ++i) 1233 Idxs[i] = i; 1234 for (unsigned i = SrcNumElts; i != DstNumElts; ++i) 1235 Idxs[i] = SrcNumElts; 1236 Rep = Builder.CreateShuffleVector(Op1, UndefV, Idxs); 1237 1238 // Insert the second operand into the first operand. 1239 1240 // Note that there is no guarantee that instruction lowering will actually 1241 // produce a vinsertf128 instruction for the created shuffles. In 1242 // particular, the 0 immediate case involves no lane changes, so it can 1243 // be handled as a blend. 1244 1245 // Example of shuffle mask for 32-bit elements: 1246 // Imm = 1 <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11> 1247 // Imm = 0 <i32 8, i32 9, i32 10, i32 11, i32 4, i32 5, i32 6, i32 7 > 1248 1249 // First fill with identify mask. 1250 for (unsigned i = 0; i != DstNumElts; ++i) 1251 Idxs[i] = i; 1252 // Then replace the elements where we need to insert. 1253 for (unsigned i = 0; i != SrcNumElts; ++i) 1254 Idxs[i + Imm * SrcNumElts] = i + DstNumElts; 1255 Rep = Builder.CreateShuffleVector(Op0, Rep, Idxs); 1256 1257 // If the intrinsic has a mask operand, handle that. 1258 if (CI->getNumArgOperands() == 5) 1259 Rep = EmitX86Select(Builder, CI->getArgOperand(4), Rep, 1260 CI->getArgOperand(3)); 1261 } else if (IsX86 && (Name.startswith("avx.vextractf128.") || 1262 Name == "avx2.vextracti128" || 1263 Name.startswith("avx512.mask.vextract"))) { 1264 Value *Op0 = CI->getArgOperand(0); 1265 unsigned Imm = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue(); 1266 unsigned DstNumElts = CI->getType()->getVectorNumElements(); 1267 unsigned SrcNumElts = Op0->getType()->getVectorNumElements(); 1268 unsigned Scale = SrcNumElts / DstNumElts; 1269 1270 // Mask off the high bits of the immediate value; hardware ignores those. 1271 Imm = Imm % Scale; 1272 1273 // Get indexes for the subvector of the input vector. 1274 SmallVector<uint32_t, 8> Idxs(DstNumElts); 1275 for (unsigned i = 0; i != DstNumElts; ++i) { 1276 Idxs[i] = i + (Imm * DstNumElts); 1277 } 1278 Rep = Builder.CreateShuffleVector(Op0, Op0, Idxs); 1279 1280 // If the intrinsic has a mask operand, handle that. 1281 if (CI->getNumArgOperands() == 4) 1282 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1283 CI->getArgOperand(2)); 1284 } else if (!IsX86 && Name == "stackprotectorcheck") { 1285 Rep = nullptr; 1286 } else if (IsX86 && (Name.startswith("avx512.mask.perm.df.") || 1287 Name.startswith("avx512.mask.perm.di."))) { 1288 Value *Op0 = CI->getArgOperand(0); 1289 unsigned Imm = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue(); 1290 VectorType *VecTy = cast<VectorType>(CI->getType()); 1291 unsigned NumElts = VecTy->getNumElements(); 1292 1293 SmallVector<uint32_t, 8> Idxs(NumElts); 1294 for (unsigned i = 0; i != NumElts; ++i) 1295 Idxs[i] = (i & ~0x3) + ((Imm >> (2 * (i & 0x3))) & 3); 1296 1297 Rep = Builder.CreateShuffleVector(Op0, Op0, Idxs); 1298 1299 if (CI->getNumArgOperands() == 4) 1300 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1301 CI->getArgOperand(2)); 1302 } else if (IsX86 && (Name.startswith("avx.vpermil.") || 1303 Name == "sse2.pshuf.d" || 1304 Name.startswith("avx512.mask.vpermil.p") || 1305 Name.startswith("avx512.mask.pshuf.d."))) { 1306 Value *Op0 = CI->getArgOperand(0); 1307 unsigned Imm = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue(); 1308 VectorType *VecTy = cast<VectorType>(CI->getType()); 1309 unsigned NumElts = VecTy->getNumElements(); 1310 // Calculate the size of each index in the immediate. 1311 unsigned IdxSize = 64 / VecTy->getScalarSizeInBits(); 1312 unsigned IdxMask = ((1 << IdxSize) - 1); 1313 1314 SmallVector<uint32_t, 8> Idxs(NumElts); 1315 // Lookup the bits for this element, wrapping around the immediate every 1316 // 8-bits. Elements are grouped into sets of 2 or 4 elements so we need 1317 // to offset by the first index of each group. 1318 for (unsigned i = 0; i != NumElts; ++i) 1319 Idxs[i] = ((Imm >> ((i * IdxSize) % 8)) & IdxMask) | (i & ~IdxMask); 1320 1321 Rep = Builder.CreateShuffleVector(Op0, Op0, Idxs); 1322 1323 if (CI->getNumArgOperands() == 4) 1324 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1325 CI->getArgOperand(2)); 1326 } else if (IsX86 && (Name == "sse2.pshufl.w" || 1327 Name.startswith("avx512.mask.pshufl.w."))) { 1328 Value *Op0 = CI->getArgOperand(0); 1329 unsigned Imm = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue(); 1330 unsigned NumElts = CI->getType()->getVectorNumElements(); 1331 1332 SmallVector<uint32_t, 16> Idxs(NumElts); 1333 for (unsigned l = 0; l != NumElts; l += 8) { 1334 for (unsigned i = 0; i != 4; ++i) 1335 Idxs[i + l] = ((Imm >> (2 * i)) & 0x3) + l; 1336 for (unsigned i = 4; i != 8; ++i) 1337 Idxs[i + l] = i + l; 1338 } 1339 1340 Rep = Builder.CreateShuffleVector(Op0, Op0, Idxs); 1341 1342 if (CI->getNumArgOperands() == 4) 1343 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1344 CI->getArgOperand(2)); 1345 } else if (IsX86 && (Name == "sse2.pshufh.w" || 1346 Name.startswith("avx512.mask.pshufh.w."))) { 1347 Value *Op0 = CI->getArgOperand(0); 1348 unsigned Imm = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue(); 1349 unsigned NumElts = CI->getType()->getVectorNumElements(); 1350 1351 SmallVector<uint32_t, 16> Idxs(NumElts); 1352 for (unsigned l = 0; l != NumElts; l += 8) { 1353 for (unsigned i = 0; i != 4; ++i) 1354 Idxs[i + l] = i + l; 1355 for (unsigned i = 0; i != 4; ++i) 1356 Idxs[i + l + 4] = ((Imm >> (2 * i)) & 0x3) + 4 + l; 1357 } 1358 1359 Rep = Builder.CreateShuffleVector(Op0, Op0, Idxs); 1360 1361 if (CI->getNumArgOperands() == 4) 1362 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1363 CI->getArgOperand(2)); 1364 } else if (IsX86 && Name.startswith("avx512.mask.shuf.p")) { 1365 Value *Op0 = CI->getArgOperand(0); 1366 Value *Op1 = CI->getArgOperand(1); 1367 unsigned Imm = cast<ConstantInt>(CI->getArgOperand(2))->getZExtValue(); 1368 unsigned NumElts = CI->getType()->getVectorNumElements(); 1369 1370 unsigned NumLaneElts = 128/CI->getType()->getScalarSizeInBits(); 1371 unsigned HalfLaneElts = NumLaneElts / 2; 1372 1373 SmallVector<uint32_t, 16> Idxs(NumElts); 1374 for (unsigned i = 0; i != NumElts; ++i) { 1375 // Base index is the starting element of the lane. 1376 Idxs[i] = i - (i % NumLaneElts); 1377 // If we are half way through the lane switch to the other source. 1378 if ((i % NumLaneElts) >= HalfLaneElts) 1379 Idxs[i] += NumElts; 1380 // Now select the specific element. By adding HalfLaneElts bits from 1381 // the immediate. Wrapping around the immediate every 8-bits. 1382 Idxs[i] += (Imm >> ((i * HalfLaneElts) % 8)) & ((1 << HalfLaneElts) - 1); 1383 } 1384 1385 Rep = Builder.CreateShuffleVector(Op0, Op1, Idxs); 1386 1387 Rep = EmitX86Select(Builder, CI->getArgOperand(4), Rep, 1388 CI->getArgOperand(3)); 1389 } else if (IsX86 && (Name.startswith("avx512.mask.movddup") || 1390 Name.startswith("avx512.mask.movshdup") || 1391 Name.startswith("avx512.mask.movsldup"))) { 1392 Value *Op0 = CI->getArgOperand(0); 1393 unsigned NumElts = CI->getType()->getVectorNumElements(); 1394 unsigned NumLaneElts = 128/CI->getType()->getScalarSizeInBits(); 1395 1396 unsigned Offset = 0; 1397 if (Name.startswith("avx512.mask.movshdup.")) 1398 Offset = 1; 1399 1400 SmallVector<uint32_t, 16> Idxs(NumElts); 1401 for (unsigned l = 0; l != NumElts; l += NumLaneElts) 1402 for (unsigned i = 0; i != NumLaneElts; i += 2) { 1403 Idxs[i + l + 0] = i + l + Offset; 1404 Idxs[i + l + 1] = i + l + Offset; 1405 } 1406 1407 Rep = Builder.CreateShuffleVector(Op0, Op0, Idxs); 1408 1409 Rep = EmitX86Select(Builder, CI->getArgOperand(2), Rep, 1410 CI->getArgOperand(1)); 1411 } else if (IsX86 && (Name.startswith("avx512.mask.punpckl") || 1412 Name.startswith("avx512.mask.unpckl."))) { 1413 Value *Op0 = CI->getArgOperand(0); 1414 Value *Op1 = CI->getArgOperand(1); 1415 int NumElts = CI->getType()->getVectorNumElements(); 1416 int NumLaneElts = 128/CI->getType()->getScalarSizeInBits(); 1417 1418 SmallVector<uint32_t, 64> Idxs(NumElts); 1419 for (int l = 0; l != NumElts; l += NumLaneElts) 1420 for (int i = 0; i != NumLaneElts; ++i) 1421 Idxs[i + l] = l + (i / 2) + NumElts * (i % 2); 1422 1423 Rep = Builder.CreateShuffleVector(Op0, Op1, Idxs); 1424 1425 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1426 CI->getArgOperand(2)); 1427 } else if (IsX86 && (Name.startswith("avx512.mask.punpckh") || 1428 Name.startswith("avx512.mask.unpckh."))) { 1429 Value *Op0 = CI->getArgOperand(0); 1430 Value *Op1 = CI->getArgOperand(1); 1431 int NumElts = CI->getType()->getVectorNumElements(); 1432 int NumLaneElts = 128/CI->getType()->getScalarSizeInBits(); 1433 1434 SmallVector<uint32_t, 64> Idxs(NumElts); 1435 for (int l = 0; l != NumElts; l += NumLaneElts) 1436 for (int i = 0; i != NumLaneElts; ++i) 1437 Idxs[i + l] = (NumLaneElts / 2) + l + (i / 2) + NumElts * (i % 2); 1438 1439 Rep = Builder.CreateShuffleVector(Op0, Op1, Idxs); 1440 1441 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1442 CI->getArgOperand(2)); 1443 } else if (IsX86 && Name.startswith("avx512.mask.pand.")) { 1444 Rep = Builder.CreateAnd(CI->getArgOperand(0), CI->getArgOperand(1)); 1445 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1446 CI->getArgOperand(2)); 1447 } else if (IsX86 && Name.startswith("avx512.mask.pandn.")) { 1448 Rep = Builder.CreateAnd(Builder.CreateNot(CI->getArgOperand(0)), 1449 CI->getArgOperand(1)); 1450 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1451 CI->getArgOperand(2)); 1452 } else if (IsX86 && Name.startswith("avx512.mask.por.")) { 1453 Rep = Builder.CreateOr(CI->getArgOperand(0), CI->getArgOperand(1)); 1454 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1455 CI->getArgOperand(2)); 1456 } else if (IsX86 && Name.startswith("avx512.mask.pxor.")) { 1457 Rep = Builder.CreateXor(CI->getArgOperand(0), CI->getArgOperand(1)); 1458 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1459 CI->getArgOperand(2)); 1460 } else if (IsX86 && Name.startswith("avx512.mask.and.")) { 1461 VectorType *FTy = cast<VectorType>(CI->getType()); 1462 VectorType *ITy = VectorType::getInteger(FTy); 1463 Rep = Builder.CreateAnd(Builder.CreateBitCast(CI->getArgOperand(0), ITy), 1464 Builder.CreateBitCast(CI->getArgOperand(1), ITy)); 1465 Rep = Builder.CreateBitCast(Rep, FTy); 1466 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1467 CI->getArgOperand(2)); 1468 } else if (IsX86 && Name.startswith("avx512.mask.andn.")) { 1469 VectorType *FTy = cast<VectorType>(CI->getType()); 1470 VectorType *ITy = VectorType::getInteger(FTy); 1471 Rep = Builder.CreateNot(Builder.CreateBitCast(CI->getArgOperand(0), ITy)); 1472 Rep = Builder.CreateAnd(Rep, 1473 Builder.CreateBitCast(CI->getArgOperand(1), ITy)); 1474 Rep = Builder.CreateBitCast(Rep, FTy); 1475 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1476 CI->getArgOperand(2)); 1477 } else if (IsX86 && Name.startswith("avx512.mask.or.")) { 1478 VectorType *FTy = cast<VectorType>(CI->getType()); 1479 VectorType *ITy = VectorType::getInteger(FTy); 1480 Rep = Builder.CreateOr(Builder.CreateBitCast(CI->getArgOperand(0), ITy), 1481 Builder.CreateBitCast(CI->getArgOperand(1), ITy)); 1482 Rep = Builder.CreateBitCast(Rep, FTy); 1483 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1484 CI->getArgOperand(2)); 1485 } else if (IsX86 && Name.startswith("avx512.mask.xor.")) { 1486 VectorType *FTy = cast<VectorType>(CI->getType()); 1487 VectorType *ITy = VectorType::getInteger(FTy); 1488 Rep = Builder.CreateXor(Builder.CreateBitCast(CI->getArgOperand(0), ITy), 1489 Builder.CreateBitCast(CI->getArgOperand(1), ITy)); 1490 Rep = Builder.CreateBitCast(Rep, FTy); 1491 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1492 CI->getArgOperand(2)); 1493 } else if (IsX86 && Name.startswith("avx512.mask.padd.")) { 1494 Rep = Builder.CreateAdd(CI->getArgOperand(0), CI->getArgOperand(1)); 1495 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1496 CI->getArgOperand(2)); 1497 } else if (IsX86 && Name.startswith("avx512.mask.psub.")) { 1498 Rep = Builder.CreateSub(CI->getArgOperand(0), CI->getArgOperand(1)); 1499 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1500 CI->getArgOperand(2)); 1501 } else if (IsX86 && Name.startswith("avx512.mask.pmull.")) { 1502 Rep = Builder.CreateMul(CI->getArgOperand(0), CI->getArgOperand(1)); 1503 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1504 CI->getArgOperand(2)); 1505 } else if (IsX86 && (Name.startswith("avx512.mask.add.p"))) { 1506 Rep = Builder.CreateFAdd(CI->getArgOperand(0), CI->getArgOperand(1)); 1507 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1508 CI->getArgOperand(2)); 1509 } else if (IsX86 && Name.startswith("avx512.mask.div.p")) { 1510 Rep = Builder.CreateFDiv(CI->getArgOperand(0), CI->getArgOperand(1)); 1511 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1512 CI->getArgOperand(2)); 1513 } else if (IsX86 && Name.startswith("avx512.mask.mul.p")) { 1514 Rep = Builder.CreateFMul(CI->getArgOperand(0), CI->getArgOperand(1)); 1515 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1516 CI->getArgOperand(2)); 1517 } else if (IsX86 && Name.startswith("avx512.mask.sub.p")) { 1518 Rep = Builder.CreateFSub(CI->getArgOperand(0), CI->getArgOperand(1)); 1519 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1520 CI->getArgOperand(2)); 1521 } else if (IsX86 && Name.startswith("avx512.mask.lzcnt.")) { 1522 Rep = Builder.CreateCall(Intrinsic::getDeclaration(F->getParent(), 1523 Intrinsic::ctlz, 1524 CI->getType()), 1525 { CI->getArgOperand(0), Builder.getInt1(false) }); 1526 Rep = EmitX86Select(Builder, CI->getArgOperand(2), Rep, 1527 CI->getArgOperand(1)); 1528 } else if (IsX86 && (Name.startswith("avx512.mask.max.p") || 1529 Name.startswith("avx512.mask.min.p"))) { 1530 bool IsMin = Name[13] == 'i'; 1531 VectorType *VecTy = cast<VectorType>(CI->getType()); 1532 unsigned VecWidth = VecTy->getPrimitiveSizeInBits(); 1533 unsigned EltWidth = VecTy->getScalarSizeInBits(); 1534 Intrinsic::ID IID; 1535 if (!IsMin && VecWidth == 128 && EltWidth == 32) 1536 IID = Intrinsic::x86_sse_max_ps; 1537 else if (!IsMin && VecWidth == 128 && EltWidth == 64) 1538 IID = Intrinsic::x86_sse2_max_pd; 1539 else if (!IsMin && VecWidth == 256 && EltWidth == 32) 1540 IID = Intrinsic::x86_avx_max_ps_256; 1541 else if (!IsMin && VecWidth == 256 && EltWidth == 64) 1542 IID = Intrinsic::x86_avx_max_pd_256; 1543 else if (IsMin && VecWidth == 128 && EltWidth == 32) 1544 IID = Intrinsic::x86_sse_min_ps; 1545 else if (IsMin && VecWidth == 128 && EltWidth == 64) 1546 IID = Intrinsic::x86_sse2_min_pd; 1547 else if (IsMin && VecWidth == 256 && EltWidth == 32) 1548 IID = Intrinsic::x86_avx_min_ps_256; 1549 else if (IsMin && VecWidth == 256 && EltWidth == 64) 1550 IID = Intrinsic::x86_avx_min_pd_256; 1551 else 1552 llvm_unreachable("Unexpected intrinsic"); 1553 1554 Rep = Builder.CreateCall(Intrinsic::getDeclaration(F->getParent(), IID), 1555 { CI->getArgOperand(0), CI->getArgOperand(1) }); 1556 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1557 CI->getArgOperand(2)); 1558 } else if (IsX86 && Name.startswith("avx512.mask.pshuf.b.")) { 1559 VectorType *VecTy = cast<VectorType>(CI->getType()); 1560 Intrinsic::ID IID; 1561 if (VecTy->getPrimitiveSizeInBits() == 128) 1562 IID = Intrinsic::x86_ssse3_pshuf_b_128; 1563 else if (VecTy->getPrimitiveSizeInBits() == 256) 1564 IID = Intrinsic::x86_avx2_pshuf_b; 1565 else if (VecTy->getPrimitiveSizeInBits() == 512) 1566 IID = Intrinsic::x86_avx512_pshuf_b_512; 1567 else 1568 llvm_unreachable("Unexpected intrinsic"); 1569 1570 Rep = Builder.CreateCall(Intrinsic::getDeclaration(F->getParent(), IID), 1571 { CI->getArgOperand(0), CI->getArgOperand(1) }); 1572 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1573 CI->getArgOperand(2)); 1574 } else if (IsX86 && (Name.startswith("avx512.mask.pmul.dq.") || 1575 Name.startswith("avx512.mask.pmulu.dq."))) { 1576 bool IsUnsigned = Name[16] == 'u'; 1577 VectorType *VecTy = cast<VectorType>(CI->getType()); 1578 Intrinsic::ID IID; 1579 if (!IsUnsigned && VecTy->getPrimitiveSizeInBits() == 128) 1580 IID = Intrinsic::x86_sse41_pmuldq; 1581 else if (!IsUnsigned && VecTy->getPrimitiveSizeInBits() == 256) 1582 IID = Intrinsic::x86_avx2_pmul_dq; 1583 else if (!IsUnsigned && VecTy->getPrimitiveSizeInBits() == 512) 1584 IID = Intrinsic::x86_avx512_pmul_dq_512; 1585 else if (IsUnsigned && VecTy->getPrimitiveSizeInBits() == 128) 1586 IID = Intrinsic::x86_sse2_pmulu_dq; 1587 else if (IsUnsigned && VecTy->getPrimitiveSizeInBits() == 256) 1588 IID = Intrinsic::x86_avx2_pmulu_dq; 1589 else if (IsUnsigned && VecTy->getPrimitiveSizeInBits() == 512) 1590 IID = Intrinsic::x86_avx512_pmulu_dq_512; 1591 else 1592 llvm_unreachable("Unexpected intrinsic"); 1593 1594 Rep = Builder.CreateCall(Intrinsic::getDeclaration(F->getParent(), IID), 1595 { CI->getArgOperand(0), CI->getArgOperand(1) }); 1596 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1597 CI->getArgOperand(2)); 1598 } else if (IsX86 && Name.startswith("avx512.mask.pack")) { 1599 bool IsUnsigned = Name[16] == 'u'; 1600 bool IsDW = Name[18] == 'd'; 1601 VectorType *VecTy = cast<VectorType>(CI->getType()); 1602 Intrinsic::ID IID; 1603 if (!IsUnsigned && !IsDW && VecTy->getPrimitiveSizeInBits() == 128) 1604 IID = Intrinsic::x86_sse2_packsswb_128; 1605 else if (!IsUnsigned && !IsDW && VecTy->getPrimitiveSizeInBits() == 256) 1606 IID = Intrinsic::x86_avx2_packsswb; 1607 else if (!IsUnsigned && !IsDW && VecTy->getPrimitiveSizeInBits() == 512) 1608 IID = Intrinsic::x86_avx512_packsswb_512; 1609 else if (!IsUnsigned && IsDW && VecTy->getPrimitiveSizeInBits() == 128) 1610 IID = Intrinsic::x86_sse2_packssdw_128; 1611 else if (!IsUnsigned && IsDW && VecTy->getPrimitiveSizeInBits() == 256) 1612 IID = Intrinsic::x86_avx2_packssdw; 1613 else if (!IsUnsigned && IsDW && VecTy->getPrimitiveSizeInBits() == 512) 1614 IID = Intrinsic::x86_avx512_packssdw_512; 1615 else if (IsUnsigned && !IsDW && VecTy->getPrimitiveSizeInBits() == 128) 1616 IID = Intrinsic::x86_sse2_packuswb_128; 1617 else if (IsUnsigned && !IsDW && VecTy->getPrimitiveSizeInBits() == 256) 1618 IID = Intrinsic::x86_avx2_packuswb; 1619 else if (IsUnsigned && !IsDW && VecTy->getPrimitiveSizeInBits() == 512) 1620 IID = Intrinsic::x86_avx512_packuswb_512; 1621 else if (IsUnsigned && IsDW && VecTy->getPrimitiveSizeInBits() == 128) 1622 IID = Intrinsic::x86_sse41_packusdw; 1623 else if (IsUnsigned && IsDW && VecTy->getPrimitiveSizeInBits() == 256) 1624 IID = Intrinsic::x86_avx2_packusdw; 1625 else if (IsUnsigned && IsDW && VecTy->getPrimitiveSizeInBits() == 512) 1626 IID = Intrinsic::x86_avx512_packusdw_512; 1627 else 1628 llvm_unreachable("Unexpected intrinsic"); 1629 1630 Rep = Builder.CreateCall(Intrinsic::getDeclaration(F->getParent(), IID), 1631 { CI->getArgOperand(0), CI->getArgOperand(1) }); 1632 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1633 CI->getArgOperand(2)); 1634 } else if (IsX86 && Name.startswith("avx512.mask.psll")) { 1635 bool IsImmediate = Name[16] == 'i' || 1636 (Name.size() > 18 && Name[18] == 'i'); 1637 bool IsVariable = Name[16] == 'v'; 1638 char Size = Name[16] == '.' ? Name[17] : 1639 Name[17] == '.' ? Name[18] : 1640 Name[18] == '.' ? Name[19] : 1641 Name[20]; 1642 1643 Intrinsic::ID IID; 1644 if (IsVariable && Name[17] != '.') { 1645 if (Size == 'd' && Name[17] == '2') // avx512.mask.psllv2.di 1646 IID = Intrinsic::x86_avx2_psllv_q; 1647 else if (Size == 'd' && Name[17] == '4') // avx512.mask.psllv4.di 1648 IID = Intrinsic::x86_avx2_psllv_q_256; 1649 else if (Size == 's' && Name[17] == '4') // avx512.mask.psllv4.si 1650 IID = Intrinsic::x86_avx2_psllv_d; 1651 else if (Size == 's' && Name[17] == '8') // avx512.mask.psllv8.si 1652 IID = Intrinsic::x86_avx2_psllv_d_256; 1653 else if (Size == 'h' && Name[17] == '8') // avx512.mask.psllv8.hi 1654 IID = Intrinsic::x86_avx512_psllv_w_128; 1655 else if (Size == 'h' && Name[17] == '1') // avx512.mask.psllv16.hi 1656 IID = Intrinsic::x86_avx512_psllv_w_256; 1657 else if (Name[17] == '3' && Name[18] == '2') // avx512.mask.psllv32hi 1658 IID = Intrinsic::x86_avx512_psllv_w_512; 1659 else 1660 llvm_unreachable("Unexpected size"); 1661 } else if (Name.endswith(".128")) { 1662 if (Size == 'd') // avx512.mask.psll.d.128, avx512.mask.psll.di.128 1663 IID = IsImmediate ? Intrinsic::x86_sse2_pslli_d 1664 : Intrinsic::x86_sse2_psll_d; 1665 else if (Size == 'q') // avx512.mask.psll.q.128, avx512.mask.psll.qi.128 1666 IID = IsImmediate ? Intrinsic::x86_sse2_pslli_q 1667 : Intrinsic::x86_sse2_psll_q; 1668 else if (Size == 'w') // avx512.mask.psll.w.128, avx512.mask.psll.wi.128 1669 IID = IsImmediate ? Intrinsic::x86_sse2_pslli_w 1670 : Intrinsic::x86_sse2_psll_w; 1671 else 1672 llvm_unreachable("Unexpected size"); 1673 } else if (Name.endswith(".256")) { 1674 if (Size == 'd') // avx512.mask.psll.d.256, avx512.mask.psll.di.256 1675 IID = IsImmediate ? Intrinsic::x86_avx2_pslli_d 1676 : Intrinsic::x86_avx2_psll_d; 1677 else if (Size == 'q') // avx512.mask.psll.q.256, avx512.mask.psll.qi.256 1678 IID = IsImmediate ? Intrinsic::x86_avx2_pslli_q 1679 : Intrinsic::x86_avx2_psll_q; 1680 else if (Size == 'w') // avx512.mask.psll.w.256, avx512.mask.psll.wi.256 1681 IID = IsImmediate ? Intrinsic::x86_avx2_pslli_w 1682 : Intrinsic::x86_avx2_psll_w; 1683 else 1684 llvm_unreachable("Unexpected size"); 1685 } else { 1686 if (Size == 'd') // psll.di.512, pslli.d, psll.d, psllv.d.512 1687 IID = IsImmediate ? Intrinsic::x86_avx512_pslli_d_512 : 1688 IsVariable ? Intrinsic::x86_avx512_psllv_d_512 : 1689 Intrinsic::x86_avx512_psll_d_512; 1690 else if (Size == 'q') // psll.qi.512, pslli.q, psll.q, psllv.q.512 1691 IID = IsImmediate ? Intrinsic::x86_avx512_pslli_q_512 : 1692 IsVariable ? Intrinsic::x86_avx512_psllv_q_512 : 1693 Intrinsic::x86_avx512_psll_q_512; 1694 else if (Size == 'w') // psll.wi.512, pslli.w, psll.w 1695 IID = IsImmediate ? Intrinsic::x86_avx512_pslli_w_512 1696 : Intrinsic::x86_avx512_psll_w_512; 1697 else 1698 llvm_unreachable("Unexpected size"); 1699 } 1700 1701 Rep = UpgradeX86MaskedShift(Builder, *CI, IID); 1702 } else if (IsX86 && Name.startswith("avx512.mask.psrl")) { 1703 bool IsImmediate = Name[16] == 'i' || 1704 (Name.size() > 18 && Name[18] == 'i'); 1705 bool IsVariable = Name[16] == 'v'; 1706 char Size = Name[16] == '.' ? Name[17] : 1707 Name[17] == '.' ? Name[18] : 1708 Name[18] == '.' ? Name[19] : 1709 Name[20]; 1710 1711 Intrinsic::ID IID; 1712 if (IsVariable && Name[17] != '.') { 1713 if (Size == 'd' && Name[17] == '2') // avx512.mask.psrlv2.di 1714 IID = Intrinsic::x86_avx2_psrlv_q; 1715 else if (Size == 'd' && Name[17] == '4') // avx512.mask.psrlv4.di 1716 IID = Intrinsic::x86_avx2_psrlv_q_256; 1717 else if (Size == 's' && Name[17] == '4') // avx512.mask.psrlv4.si 1718 IID = Intrinsic::x86_avx2_psrlv_d; 1719 else if (Size == 's' && Name[17] == '8') // avx512.mask.psrlv8.si 1720 IID = Intrinsic::x86_avx2_psrlv_d_256; 1721 else if (Size == 'h' && Name[17] == '8') // avx512.mask.psrlv8.hi 1722 IID = Intrinsic::x86_avx512_psrlv_w_128; 1723 else if (Size == 'h' && Name[17] == '1') // avx512.mask.psrlv16.hi 1724 IID = Intrinsic::x86_avx512_psrlv_w_256; 1725 else if (Name[17] == '3' && Name[18] == '2') // avx512.mask.psrlv32hi 1726 IID = Intrinsic::x86_avx512_psrlv_w_512; 1727 else 1728 llvm_unreachable("Unexpected size"); 1729 } else if (Name.endswith(".128")) { 1730 if (Size == 'd') // avx512.mask.psrl.d.128, avx512.mask.psrl.di.128 1731 IID = IsImmediate ? Intrinsic::x86_sse2_psrli_d 1732 : Intrinsic::x86_sse2_psrl_d; 1733 else if (Size == 'q') // avx512.mask.psrl.q.128, avx512.mask.psrl.qi.128 1734 IID = IsImmediate ? Intrinsic::x86_sse2_psrli_q 1735 : Intrinsic::x86_sse2_psrl_q; 1736 else if (Size == 'w') // avx512.mask.psrl.w.128, avx512.mask.psrl.wi.128 1737 IID = IsImmediate ? Intrinsic::x86_sse2_psrli_w 1738 : Intrinsic::x86_sse2_psrl_w; 1739 else 1740 llvm_unreachable("Unexpected size"); 1741 } else if (Name.endswith(".256")) { 1742 if (Size == 'd') // avx512.mask.psrl.d.256, avx512.mask.psrl.di.256 1743 IID = IsImmediate ? Intrinsic::x86_avx2_psrli_d 1744 : Intrinsic::x86_avx2_psrl_d; 1745 else if (Size == 'q') // avx512.mask.psrl.q.256, avx512.mask.psrl.qi.256 1746 IID = IsImmediate ? Intrinsic::x86_avx2_psrli_q 1747 : Intrinsic::x86_avx2_psrl_q; 1748 else if (Size == 'w') // avx512.mask.psrl.w.256, avx512.mask.psrl.wi.256 1749 IID = IsImmediate ? Intrinsic::x86_avx2_psrli_w 1750 : Intrinsic::x86_avx2_psrl_w; 1751 else 1752 llvm_unreachable("Unexpected size"); 1753 } else { 1754 if (Size == 'd') // psrl.di.512, psrli.d, psrl.d, psrl.d.512 1755 IID = IsImmediate ? Intrinsic::x86_avx512_psrli_d_512 : 1756 IsVariable ? Intrinsic::x86_avx512_psrlv_d_512 : 1757 Intrinsic::x86_avx512_psrl_d_512; 1758 else if (Size == 'q') // psrl.qi.512, psrli.q, psrl.q, psrl.q.512 1759 IID = IsImmediate ? Intrinsic::x86_avx512_psrli_q_512 : 1760 IsVariable ? Intrinsic::x86_avx512_psrlv_q_512 : 1761 Intrinsic::x86_avx512_psrl_q_512; 1762 else if (Size == 'w') // psrl.wi.512, psrli.w, psrl.w) 1763 IID = IsImmediate ? Intrinsic::x86_avx512_psrli_w_512 1764 : Intrinsic::x86_avx512_psrl_w_512; 1765 else 1766 llvm_unreachable("Unexpected size"); 1767 } 1768 1769 Rep = UpgradeX86MaskedShift(Builder, *CI, IID); 1770 } else if (IsX86 && Name.startswith("avx512.mask.psra")) { 1771 bool IsImmediate = Name[16] == 'i' || 1772 (Name.size() > 18 && Name[18] == 'i'); 1773 bool IsVariable = Name[16] == 'v'; 1774 char Size = Name[16] == '.' ? Name[17] : 1775 Name[17] == '.' ? Name[18] : 1776 Name[18] == '.' ? Name[19] : 1777 Name[20]; 1778 1779 Intrinsic::ID IID; 1780 if (IsVariable && Name[17] != '.') { 1781 if (Size == 's' && Name[17] == '4') // avx512.mask.psrav4.si 1782 IID = Intrinsic::x86_avx2_psrav_d; 1783 else if (Size == 's' && Name[17] == '8') // avx512.mask.psrav8.si 1784 IID = Intrinsic::x86_avx2_psrav_d_256; 1785 else if (Size == 'h' && Name[17] == '8') // avx512.mask.psrav8.hi 1786 IID = Intrinsic::x86_avx512_psrav_w_128; 1787 else if (Size == 'h' && Name[17] == '1') // avx512.mask.psrav16.hi 1788 IID = Intrinsic::x86_avx512_psrav_w_256; 1789 else if (Name[17] == '3' && Name[18] == '2') // avx512.mask.psrav32hi 1790 IID = Intrinsic::x86_avx512_psrav_w_512; 1791 else 1792 llvm_unreachable("Unexpected size"); 1793 } else if (Name.endswith(".128")) { 1794 if (Size == 'd') // avx512.mask.psra.d.128, avx512.mask.psra.di.128 1795 IID = IsImmediate ? Intrinsic::x86_sse2_psrai_d 1796 : Intrinsic::x86_sse2_psra_d; 1797 else if (Size == 'q') // avx512.mask.psra.q.128, avx512.mask.psra.qi.128 1798 IID = IsImmediate ? Intrinsic::x86_avx512_psrai_q_128 : 1799 IsVariable ? Intrinsic::x86_avx512_psrav_q_128 : 1800 Intrinsic::x86_avx512_psra_q_128; 1801 else if (Size == 'w') // avx512.mask.psra.w.128, avx512.mask.psra.wi.128 1802 IID = IsImmediate ? Intrinsic::x86_sse2_psrai_w 1803 : Intrinsic::x86_sse2_psra_w; 1804 else 1805 llvm_unreachable("Unexpected size"); 1806 } else if (Name.endswith(".256")) { 1807 if (Size == 'd') // avx512.mask.psra.d.256, avx512.mask.psra.di.256 1808 IID = IsImmediate ? Intrinsic::x86_avx2_psrai_d 1809 : Intrinsic::x86_avx2_psra_d; 1810 else if (Size == 'q') // avx512.mask.psra.q.256, avx512.mask.psra.qi.256 1811 IID = IsImmediate ? Intrinsic::x86_avx512_psrai_q_256 : 1812 IsVariable ? Intrinsic::x86_avx512_psrav_q_256 : 1813 Intrinsic::x86_avx512_psra_q_256; 1814 else if (Size == 'w') // avx512.mask.psra.w.256, avx512.mask.psra.wi.256 1815 IID = IsImmediate ? Intrinsic::x86_avx2_psrai_w 1816 : Intrinsic::x86_avx2_psra_w; 1817 else 1818 llvm_unreachable("Unexpected size"); 1819 } else { 1820 if (Size == 'd') // psra.di.512, psrai.d, psra.d, psrav.d.512 1821 IID = IsImmediate ? Intrinsic::x86_avx512_psrai_d_512 : 1822 IsVariable ? Intrinsic::x86_avx512_psrav_d_512 : 1823 Intrinsic::x86_avx512_psra_d_512; 1824 else if (Size == 'q') // psra.qi.512, psrai.q, psra.q 1825 IID = IsImmediate ? Intrinsic::x86_avx512_psrai_q_512 : 1826 IsVariable ? Intrinsic::x86_avx512_psrav_q_512 : 1827 Intrinsic::x86_avx512_psra_q_512; 1828 else if (Size == 'w') // psra.wi.512, psrai.w, psra.w 1829 IID = IsImmediate ? Intrinsic::x86_avx512_psrai_w_512 1830 : Intrinsic::x86_avx512_psra_w_512; 1831 else 1832 llvm_unreachable("Unexpected size"); 1833 } 1834 1835 Rep = UpgradeX86MaskedShift(Builder, *CI, IID); 1836 } else if (IsX86 && Name.startswith("avx512.mask.move.s")) { 1837 Rep = upgradeMaskedMove(Builder, *CI); 1838 } else if (IsX86 && Name.startswith("avx512.mask.vpermilvar.")) { 1839 Intrinsic::ID IID; 1840 if (Name.endswith("ps.128")) 1841 IID = Intrinsic::x86_avx_vpermilvar_ps; 1842 else if (Name.endswith("pd.128")) 1843 IID = Intrinsic::x86_avx_vpermilvar_pd; 1844 else if (Name.endswith("ps.256")) 1845 IID = Intrinsic::x86_avx_vpermilvar_ps_256; 1846 else if (Name.endswith("pd.256")) 1847 IID = Intrinsic::x86_avx_vpermilvar_pd_256; 1848 else if (Name.endswith("ps.512")) 1849 IID = Intrinsic::x86_avx512_vpermilvar_ps_512; 1850 else if (Name.endswith("pd.512")) 1851 IID = Intrinsic::x86_avx512_vpermilvar_pd_512; 1852 else 1853 llvm_unreachable("Unexpected vpermilvar intrinsic"); 1854 1855 Function *Intrin = Intrinsic::getDeclaration(F->getParent(), IID); 1856 Rep = Builder.CreateCall(Intrin, 1857 { CI->getArgOperand(0), CI->getArgOperand(1) }); 1858 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1859 CI->getArgOperand(2)); 1860 } else if (IsNVVM && (Name == "abs.i" || Name == "abs.ll")) { 1861 Value *Arg = CI->getArgOperand(0); 1862 Value *Neg = Builder.CreateNeg(Arg, "neg"); 1863 Value *Cmp = Builder.CreateICmpSGE( 1864 Arg, llvm::Constant::getNullValue(Arg->getType()), "abs.cond"); 1865 Rep = Builder.CreateSelect(Cmp, Arg, Neg, "abs"); 1866 } else if (IsNVVM && (Name == "max.i" || Name == "max.ll" || 1867 Name == "max.ui" || Name == "max.ull")) { 1868 Value *Arg0 = CI->getArgOperand(0); 1869 Value *Arg1 = CI->getArgOperand(1); 1870 Value *Cmp = Name.endswith(".ui") || Name.endswith(".ull") 1871 ? Builder.CreateICmpUGE(Arg0, Arg1, "max.cond") 1872 : Builder.CreateICmpSGE(Arg0, Arg1, "max.cond"); 1873 Rep = Builder.CreateSelect(Cmp, Arg0, Arg1, "max"); 1874 } else if (IsNVVM && (Name == "min.i" || Name == "min.ll" || 1875 Name == "min.ui" || Name == "min.ull")) { 1876 Value *Arg0 = CI->getArgOperand(0); 1877 Value *Arg1 = CI->getArgOperand(1); 1878 Value *Cmp = Name.endswith(".ui") || Name.endswith(".ull") 1879 ? Builder.CreateICmpULE(Arg0, Arg1, "min.cond") 1880 : Builder.CreateICmpSLE(Arg0, Arg1, "min.cond"); 1881 Rep = Builder.CreateSelect(Cmp, Arg0, Arg1, "min"); 1882 } else if (IsNVVM && Name == "clz.ll") { 1883 // llvm.nvvm.clz.ll returns an i32, but llvm.ctlz.i64 and returns an i64. 1884 Value *Arg = CI->getArgOperand(0); 1885 Value *Ctlz = Builder.CreateCall( 1886 Intrinsic::getDeclaration(F->getParent(), Intrinsic::ctlz, 1887 {Arg->getType()}), 1888 {Arg, Builder.getFalse()}, "ctlz"); 1889 Rep = Builder.CreateTrunc(Ctlz, Builder.getInt32Ty(), "ctlz.trunc"); 1890 } else if (IsNVVM && Name == "popc.ll") { 1891 // llvm.nvvm.popc.ll returns an i32, but llvm.ctpop.i64 and returns an 1892 // i64. 1893 Value *Arg = CI->getArgOperand(0); 1894 Value *Popc = Builder.CreateCall( 1895 Intrinsic::getDeclaration(F->getParent(), Intrinsic::ctpop, 1896 {Arg->getType()}), 1897 Arg, "ctpop"); 1898 Rep = Builder.CreateTrunc(Popc, Builder.getInt32Ty(), "ctpop.trunc"); 1899 } else if (IsNVVM && Name == "h2f") { 1900 Rep = Builder.CreateCall(Intrinsic::getDeclaration( 1901 F->getParent(), Intrinsic::convert_from_fp16, 1902 {Builder.getFloatTy()}), 1903 CI->getArgOperand(0), "h2f"); 1904 } else { 1905 llvm_unreachable("Unknown function for CallInst upgrade."); 1906 } 1907 1908 if (Rep) 1909 CI->replaceAllUsesWith(Rep); 1910 CI->eraseFromParent(); 1911 return; 1912 } 1913 1914 CallInst *NewCall = nullptr; 1915 switch (NewFn->getIntrinsicID()) { 1916 default: { 1917 // Handle generic mangling change, but nothing else 1918 assert( 1919 (CI->getCalledFunction()->getName() != NewFn->getName()) && 1920 "Unknown function for CallInst upgrade and isn't just a name change"); 1921 CI->setCalledFunction(NewFn); 1922 return; 1923 } 1924 1925 case Intrinsic::arm_neon_vld1: 1926 case Intrinsic::arm_neon_vld2: 1927 case Intrinsic::arm_neon_vld3: 1928 case Intrinsic::arm_neon_vld4: 1929 case Intrinsic::arm_neon_vld2lane: 1930 case Intrinsic::arm_neon_vld3lane: 1931 case Intrinsic::arm_neon_vld4lane: 1932 case Intrinsic::arm_neon_vst1: 1933 case Intrinsic::arm_neon_vst2: 1934 case Intrinsic::arm_neon_vst3: 1935 case Intrinsic::arm_neon_vst4: 1936 case Intrinsic::arm_neon_vst2lane: 1937 case Intrinsic::arm_neon_vst3lane: 1938 case Intrinsic::arm_neon_vst4lane: { 1939 SmallVector<Value *, 4> Args(CI->arg_operands().begin(), 1940 CI->arg_operands().end()); 1941 NewCall = Builder.CreateCall(NewFn, Args); 1942 break; 1943 } 1944 1945 case Intrinsic::bitreverse: 1946 NewCall = Builder.CreateCall(NewFn, {CI->getArgOperand(0)}); 1947 break; 1948 1949 case Intrinsic::ctlz: 1950 case Intrinsic::cttz: 1951 assert(CI->getNumArgOperands() == 1 && 1952 "Mismatch between function args and call args"); 1953 NewCall = 1954 Builder.CreateCall(NewFn, {CI->getArgOperand(0), Builder.getFalse()}); 1955 break; 1956 1957 case Intrinsic::objectsize: 1958 NewCall = 1959 Builder.CreateCall(NewFn, {CI->getArgOperand(0), CI->getArgOperand(1)}); 1960 break; 1961 1962 case Intrinsic::ctpop: 1963 NewCall = Builder.CreateCall(NewFn, {CI->getArgOperand(0)}); 1964 break; 1965 1966 case Intrinsic::convert_from_fp16: 1967 NewCall = Builder.CreateCall(NewFn, {CI->getArgOperand(0)}); 1968 break; 1969 1970 case Intrinsic::x86_xop_vfrcz_ss: 1971 case Intrinsic::x86_xop_vfrcz_sd: 1972 NewCall = Builder.CreateCall(NewFn, {CI->getArgOperand(1)}); 1973 break; 1974 1975 case Intrinsic::x86_xop_vpermil2pd: 1976 case Intrinsic::x86_xop_vpermil2ps: 1977 case Intrinsic::x86_xop_vpermil2pd_256: 1978 case Intrinsic::x86_xop_vpermil2ps_256: { 1979 SmallVector<Value *, 4> Args(CI->arg_operands().begin(), 1980 CI->arg_operands().end()); 1981 VectorType *FltIdxTy = cast<VectorType>(Args[2]->getType()); 1982 VectorType *IntIdxTy = VectorType::getInteger(FltIdxTy); 1983 Args[2] = Builder.CreateBitCast(Args[2], IntIdxTy); 1984 NewCall = Builder.CreateCall(NewFn, Args); 1985 break; 1986 } 1987 1988 case Intrinsic::x86_sse41_ptestc: 1989 case Intrinsic::x86_sse41_ptestz: 1990 case Intrinsic::x86_sse41_ptestnzc: { 1991 // The arguments for these intrinsics used to be v4f32, and changed 1992 // to v2i64. This is purely a nop, since those are bitwise intrinsics. 1993 // So, the only thing required is a bitcast for both arguments. 1994 // First, check the arguments have the old type. 1995 Value *Arg0 = CI->getArgOperand(0); 1996 if (Arg0->getType() != VectorType::get(Type::getFloatTy(C), 4)) 1997 return; 1998 1999 // Old intrinsic, add bitcasts 2000 Value *Arg1 = CI->getArgOperand(1); 2001 2002 Type *NewVecTy = VectorType::get(Type::getInt64Ty(C), 2); 2003 2004 Value *BC0 = Builder.CreateBitCast(Arg0, NewVecTy, "cast"); 2005 Value *BC1 = Builder.CreateBitCast(Arg1, NewVecTy, "cast"); 2006 2007 NewCall = Builder.CreateCall(NewFn, {BC0, BC1}); 2008 break; 2009 } 2010 2011 case Intrinsic::x86_sse41_insertps: 2012 case Intrinsic::x86_sse41_dppd: 2013 case Intrinsic::x86_sse41_dpps: 2014 case Intrinsic::x86_sse41_mpsadbw: 2015 case Intrinsic::x86_avx_dp_ps_256: 2016 case Intrinsic::x86_avx2_mpsadbw: { 2017 // Need to truncate the last argument from i32 to i8 -- this argument models 2018 // an inherently 8-bit immediate operand to these x86 instructions. 2019 SmallVector<Value *, 4> Args(CI->arg_operands().begin(), 2020 CI->arg_operands().end()); 2021 2022 // Replace the last argument with a trunc. 2023 Args.back() = Builder.CreateTrunc(Args.back(), Type::getInt8Ty(C), "trunc"); 2024 NewCall = Builder.CreateCall(NewFn, Args); 2025 break; 2026 } 2027 2028 case Intrinsic::thread_pointer: { 2029 NewCall = Builder.CreateCall(NewFn, {}); 2030 break; 2031 } 2032 2033 case Intrinsic::invariant_start: 2034 case Intrinsic::invariant_end: 2035 case Intrinsic::masked_load: 2036 case Intrinsic::masked_store: { 2037 SmallVector<Value *, 4> Args(CI->arg_operands().begin(), 2038 CI->arg_operands().end()); 2039 NewCall = Builder.CreateCall(NewFn, Args); 2040 break; 2041 } 2042 } 2043 assert(NewCall && "Should have either set this variable or returned through " 2044 "the default case"); 2045 std::string Name = CI->getName(); 2046 if (!Name.empty()) { 2047 CI->setName(Name + ".old"); 2048 NewCall->setName(Name); 2049 } 2050 CI->replaceAllUsesWith(NewCall); 2051 CI->eraseFromParent(); 2052 } 2053 2054 void llvm::UpgradeCallsToIntrinsic(Function *F) { 2055 assert(F && "Illegal attempt to upgrade a non-existent intrinsic."); 2056 2057 // Check if this function should be upgraded and get the replacement function 2058 // if there is one. 2059 Function *NewFn; 2060 if (UpgradeIntrinsicFunction(F, NewFn)) { 2061 // Replace all users of the old function with the new function or new 2062 // instructions. This is not a range loop because the call is deleted. 2063 for (auto UI = F->user_begin(), UE = F->user_end(); UI != UE; ) 2064 if (CallInst *CI = dyn_cast<CallInst>(*UI++)) 2065 UpgradeIntrinsicCall(CI, NewFn); 2066 2067 // Remove old function, no longer used, from the module. 2068 F->eraseFromParent(); 2069 } 2070 } 2071 2072 MDNode *llvm::UpgradeTBAANode(MDNode &MD) { 2073 // Check if the tag uses struct-path aware TBAA format. 2074 if (isa<MDNode>(MD.getOperand(0)) && MD.getNumOperands() >= 3) 2075 return &MD; 2076 2077 auto &Context = MD.getContext(); 2078 if (MD.getNumOperands() == 3) { 2079 Metadata *Elts[] = {MD.getOperand(0), MD.getOperand(1)}; 2080 MDNode *ScalarType = MDNode::get(Context, Elts); 2081 // Create a MDNode <ScalarType, ScalarType, offset 0, const> 2082 Metadata *Elts2[] = {ScalarType, ScalarType, 2083 ConstantAsMetadata::get( 2084 Constant::getNullValue(Type::getInt64Ty(Context))), 2085 MD.getOperand(2)}; 2086 return MDNode::get(Context, Elts2); 2087 } 2088 // Create a MDNode <MD, MD, offset 0> 2089 Metadata *Elts[] = {&MD, &MD, ConstantAsMetadata::get(Constant::getNullValue( 2090 Type::getInt64Ty(Context)))}; 2091 return MDNode::get(Context, Elts); 2092 } 2093 2094 Instruction *llvm::UpgradeBitCastInst(unsigned Opc, Value *V, Type *DestTy, 2095 Instruction *&Temp) { 2096 if (Opc != Instruction::BitCast) 2097 return nullptr; 2098 2099 Temp = nullptr; 2100 Type *SrcTy = V->getType(); 2101 if (SrcTy->isPtrOrPtrVectorTy() && DestTy->isPtrOrPtrVectorTy() && 2102 SrcTy->getPointerAddressSpace() != DestTy->getPointerAddressSpace()) { 2103 LLVMContext &Context = V->getContext(); 2104 2105 // We have no information about target data layout, so we assume that 2106 // the maximum pointer size is 64bit. 2107 Type *MidTy = Type::getInt64Ty(Context); 2108 Temp = CastInst::Create(Instruction::PtrToInt, V, MidTy); 2109 2110 return CastInst::Create(Instruction::IntToPtr, Temp, DestTy); 2111 } 2112 2113 return nullptr; 2114 } 2115 2116 Value *llvm::UpgradeBitCastExpr(unsigned Opc, Constant *C, Type *DestTy) { 2117 if (Opc != Instruction::BitCast) 2118 return nullptr; 2119 2120 Type *SrcTy = C->getType(); 2121 if (SrcTy->isPtrOrPtrVectorTy() && DestTy->isPtrOrPtrVectorTy() && 2122 SrcTy->getPointerAddressSpace() != DestTy->getPointerAddressSpace()) { 2123 LLVMContext &Context = C->getContext(); 2124 2125 // We have no information about target data layout, so we assume that 2126 // the maximum pointer size is 64bit. 2127 Type *MidTy = Type::getInt64Ty(Context); 2128 2129 return ConstantExpr::getIntToPtr(ConstantExpr::getPtrToInt(C, MidTy), 2130 DestTy); 2131 } 2132 2133 return nullptr; 2134 } 2135 2136 /// Check the debug info version number, if it is out-dated, drop the debug 2137 /// info. Return true if module is modified. 2138 bool llvm::UpgradeDebugInfo(Module &M) { 2139 unsigned Version = getDebugMetadataVersionFromModule(M); 2140 if (Version == DEBUG_METADATA_VERSION) 2141 return false; 2142 2143 bool RetCode = StripDebugInfo(M); 2144 if (RetCode) { 2145 DiagnosticInfoDebugMetadataVersion DiagVersion(M, Version); 2146 M.getContext().diagnose(DiagVersion); 2147 } 2148 return RetCode; 2149 } 2150 2151 bool llvm::UpgradeModuleFlags(Module &M) { 2152 const NamedMDNode *ModFlags = M.getModuleFlagsMetadata(); 2153 if (!ModFlags) 2154 return false; 2155 2156 bool HasObjCFlag = false, HasClassProperties = false; 2157 for (unsigned I = 0, E = ModFlags->getNumOperands(); I != E; ++I) { 2158 MDNode *Op = ModFlags->getOperand(I); 2159 if (Op->getNumOperands() < 2) 2160 continue; 2161 MDString *ID = dyn_cast_or_null<MDString>(Op->getOperand(1)); 2162 if (!ID) 2163 continue; 2164 if (ID->getString() == "Objective-C Image Info Version") 2165 HasObjCFlag = true; 2166 if (ID->getString() == "Objective-C Class Properties") 2167 HasClassProperties = true; 2168 } 2169 // "Objective-C Class Properties" is recently added for Objective-C. We 2170 // upgrade ObjC bitcodes to contain a "Objective-C Class Properties" module 2171 // flag of value 0, so we can correclty downgrade this flag when trying to 2172 // link an ObjC bitcode without this module flag with an ObjC bitcode with 2173 // this module flag. 2174 if (HasObjCFlag && !HasClassProperties) { 2175 M.addModuleFlag(llvm::Module::Override, "Objective-C Class Properties", 2176 (uint32_t)0); 2177 return true; 2178 } 2179 return false; 2180 } 2181 2182 static bool isOldLoopArgument(Metadata *MD) { 2183 auto *T = dyn_cast_or_null<MDTuple>(MD); 2184 if (!T) 2185 return false; 2186 if (T->getNumOperands() < 1) 2187 return false; 2188 auto *S = dyn_cast_or_null<MDString>(T->getOperand(0)); 2189 if (!S) 2190 return false; 2191 return S->getString().startswith("llvm.vectorizer."); 2192 } 2193 2194 static MDString *upgradeLoopTag(LLVMContext &C, StringRef OldTag) { 2195 StringRef OldPrefix = "llvm.vectorizer."; 2196 assert(OldTag.startswith(OldPrefix) && "Expected old prefix"); 2197 2198 if (OldTag == "llvm.vectorizer.unroll") 2199 return MDString::get(C, "llvm.loop.interleave.count"); 2200 2201 return MDString::get( 2202 C, (Twine("llvm.loop.vectorize.") + OldTag.drop_front(OldPrefix.size())) 2203 .str()); 2204 } 2205 2206 static Metadata *upgradeLoopArgument(Metadata *MD) { 2207 auto *T = dyn_cast_or_null<MDTuple>(MD); 2208 if (!T) 2209 return MD; 2210 if (T->getNumOperands() < 1) 2211 return MD; 2212 auto *OldTag = dyn_cast_or_null<MDString>(T->getOperand(0)); 2213 if (!OldTag) 2214 return MD; 2215 if (!OldTag->getString().startswith("llvm.vectorizer.")) 2216 return MD; 2217 2218 // This has an old tag. Upgrade it. 2219 SmallVector<Metadata *, 8> Ops; 2220 Ops.reserve(T->getNumOperands()); 2221 Ops.push_back(upgradeLoopTag(T->getContext(), OldTag->getString())); 2222 for (unsigned I = 1, E = T->getNumOperands(); I != E; ++I) 2223 Ops.push_back(T->getOperand(I)); 2224 2225 return MDTuple::get(T->getContext(), Ops); 2226 } 2227 2228 MDNode *llvm::upgradeInstructionLoopAttachment(MDNode &N) { 2229 auto *T = dyn_cast<MDTuple>(&N); 2230 if (!T) 2231 return &N; 2232 2233 if (none_of(T->operands(), isOldLoopArgument)) 2234 return &N; 2235 2236 SmallVector<Metadata *, 8> Ops; 2237 Ops.reserve(T->getNumOperands()); 2238 for (Metadata *MD : T->operands()) 2239 Ops.push_back(upgradeLoopArgument(MD)); 2240 2241 return MDTuple::get(T->getContext(), Ops); 2242 } 2243