1 //===-- AutoUpgrade.cpp - Implement auto-upgrade helper functions ---------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements the auto-upgrade helper functions. 11 // This is where deprecated IR intrinsics and other IR features are updated to 12 // current specifications. 13 // 14 //===----------------------------------------------------------------------===// 15 16 #include "llvm/IR/AutoUpgrade.h" 17 #include "llvm/ADT/StringSwitch.h" 18 #include "llvm/IR/CFG.h" 19 #include "llvm/IR/CallSite.h" 20 #include "llvm/IR/Constants.h" 21 #include "llvm/IR/DIBuilder.h" 22 #include "llvm/IR/DebugInfo.h" 23 #include "llvm/IR/DiagnosticInfo.h" 24 #include "llvm/IR/Function.h" 25 #include "llvm/IR/IRBuilder.h" 26 #include "llvm/IR/Instruction.h" 27 #include "llvm/IR/IntrinsicInst.h" 28 #include "llvm/IR/LLVMContext.h" 29 #include "llvm/IR/Module.h" 30 #include "llvm/Support/ErrorHandling.h" 31 #include "llvm/Support/Regex.h" 32 #include <cstring> 33 using namespace llvm; 34 35 static void rename(GlobalValue *GV) { GV->setName(GV->getName() + ".old"); } 36 37 // Upgrade the declarations of the SSE4.1 ptest intrinsics whose arguments have 38 // changed their type from v4f32 to v2i64. 39 static bool UpgradePTESTIntrinsic(Function* F, Intrinsic::ID IID, 40 Function *&NewFn) { 41 // Check whether this is an old version of the function, which received 42 // v4f32 arguments. 43 Type *Arg0Type = F->getFunctionType()->getParamType(0); 44 if (Arg0Type != VectorType::get(Type::getFloatTy(F->getContext()), 4)) 45 return false; 46 47 // Yes, it's old, replace it with new version. 48 rename(F); 49 NewFn = Intrinsic::getDeclaration(F->getParent(), IID); 50 return true; 51 } 52 53 // Upgrade the declarations of intrinsic functions whose 8-bit immediate mask 54 // arguments have changed their type from i32 to i8. 55 static bool UpgradeX86IntrinsicsWith8BitMask(Function *F, Intrinsic::ID IID, 56 Function *&NewFn) { 57 // Check that the last argument is an i32. 58 Type *LastArgType = F->getFunctionType()->getParamType( 59 F->getFunctionType()->getNumParams() - 1); 60 if (!LastArgType->isIntegerTy(32)) 61 return false; 62 63 // Move this function aside and map down. 64 rename(F); 65 NewFn = Intrinsic::getDeclaration(F->getParent(), IID); 66 return true; 67 } 68 69 static bool ShouldUpgradeX86Intrinsic(Function *F, StringRef Name) { 70 // All of the intrinsics matches below should be marked with which llvm 71 // version started autoupgrading them. At some point in the future we would 72 // like to use this information to remove upgrade code for some older 73 // intrinsics. It is currently undecided how we will determine that future 74 // point. 75 if (Name.startswith("sse2.pcmpeq.") || // Added in 3.1 76 Name.startswith("sse2.pcmpgt.") || // Added in 3.1 77 Name.startswith("avx2.pcmpeq.") || // Added in 3.1 78 Name.startswith("avx2.pcmpgt.") || // Added in 3.1 79 Name.startswith("avx512.mask.pcmpeq.") || // Added in 3.9 80 Name.startswith("avx512.mask.pcmpgt.") || // Added in 3.9 81 Name == "sse.add.ss" || // Added in 4.0 82 Name == "sse2.add.sd" || // Added in 4.0 83 Name == "sse.sub.ss" || // Added in 4.0 84 Name == "sse2.sub.sd" || // Added in 4.0 85 Name == "sse.mul.ss" || // Added in 4.0 86 Name == "sse2.mul.sd" || // Added in 4.0 87 Name == "sse.div.ss" || // Added in 4.0 88 Name == "sse2.div.sd" || // Added in 4.0 89 Name == "sse41.pmaxsb" || // Added in 3.9 90 Name == "sse2.pmaxs.w" || // Added in 3.9 91 Name == "sse41.pmaxsd" || // Added in 3.9 92 Name == "sse2.pmaxu.b" || // Added in 3.9 93 Name == "sse41.pmaxuw" || // Added in 3.9 94 Name == "sse41.pmaxud" || // Added in 3.9 95 Name == "sse41.pminsb" || // Added in 3.9 96 Name == "sse2.pmins.w" || // Added in 3.9 97 Name == "sse41.pminsd" || // Added in 3.9 98 Name == "sse2.pminu.b" || // Added in 3.9 99 Name == "sse41.pminuw" || // Added in 3.9 100 Name == "sse41.pminud" || // Added in 3.9 101 Name.startswith("avx512.mask.pshuf.b.") || // Added in 4.0 102 Name.startswith("avx2.pmax") || // Added in 3.9 103 Name.startswith("avx2.pmin") || // Added in 3.9 104 Name.startswith("avx512.mask.pmax") || // Added in 4.0 105 Name.startswith("avx512.mask.pmin") || // Added in 4.0 106 Name.startswith("avx2.vbroadcast") || // Added in 3.8 107 Name.startswith("avx2.pbroadcast") || // Added in 3.8 108 Name.startswith("avx.vpermil.") || // Added in 3.1 109 Name.startswith("sse2.pshuf") || // Added in 3.9 110 Name.startswith("avx512.pbroadcast") || // Added in 3.9 111 Name.startswith("avx512.mask.broadcast.s") || // Added in 3.9 112 Name.startswith("avx512.mask.movddup") || // Added in 3.9 113 Name.startswith("avx512.mask.movshdup") || // Added in 3.9 114 Name.startswith("avx512.mask.movsldup") || // Added in 3.9 115 Name.startswith("avx512.mask.pshuf.d.") || // Added in 3.9 116 Name.startswith("avx512.mask.pshufl.w.") || // Added in 3.9 117 Name.startswith("avx512.mask.pshufh.w.") || // Added in 3.9 118 Name.startswith("avx512.mask.shuf.p") || // Added in 4.0 119 Name.startswith("avx512.mask.vpermil.p") || // Added in 3.9 120 Name.startswith("avx512.mask.perm.df.") || // Added in 3.9 121 Name.startswith("avx512.mask.perm.di.") || // Added in 3.9 122 Name.startswith("avx512.mask.punpckl") || // Added in 3.9 123 Name.startswith("avx512.mask.punpckh") || // Added in 3.9 124 Name.startswith("avx512.mask.unpckl.") || // Added in 3.9 125 Name.startswith("avx512.mask.unpckh.") || // Added in 3.9 126 Name.startswith("avx512.mask.pand.") || // Added in 3.9 127 Name.startswith("avx512.mask.pandn.") || // Added in 3.9 128 Name.startswith("avx512.mask.por.") || // Added in 3.9 129 Name.startswith("avx512.mask.pxor.") || // Added in 3.9 130 Name.startswith("avx512.mask.and.") || // Added in 3.9 131 Name.startswith("avx512.mask.andn.") || // Added in 3.9 132 Name.startswith("avx512.mask.or.") || // Added in 3.9 133 Name.startswith("avx512.mask.xor.") || // Added in 3.9 134 Name.startswith("avx512.mask.padd.") || // Added in 4.0 135 Name.startswith("avx512.mask.psub.") || // Added in 4.0 136 Name.startswith("avx512.mask.pmull.") || // Added in 4.0 137 Name.startswith("avx512.mask.cvtdq2pd.") || // Added in 4.0 138 Name.startswith("avx512.mask.cvtudq2pd.") || // Added in 4.0 139 Name.startswith("avx512.mask.pmul.dq.") || // Added in 4.0 140 Name.startswith("avx512.mask.pmulu.dq.") || // Added in 4.0 141 Name.startswith("avx512.mask.packsswb.") || // Added in 5.0 142 Name.startswith("avx512.mask.packssdw.") || // Added in 5.0 143 Name.startswith("avx512.mask.packuswb.") || // Added in 5.0 144 Name.startswith("avx512.mask.packusdw.") || // Added in 5.0 145 Name.startswith("avx512.mask.cmp.b") || // Added in 5.0 146 Name.startswith("avx512.mask.cmp.d") || // Added in 5.0 147 Name.startswith("avx512.mask.cmp.q") || // Added in 5.0 148 Name.startswith("avx512.mask.cmp.w") || // Added in 5.0 149 Name.startswith("avx512.mask.ucmp.") || // Added in 5.0 150 Name == "avx512.mask.add.pd.128" || // Added in 4.0 151 Name == "avx512.mask.add.pd.256" || // Added in 4.0 152 Name == "avx512.mask.add.ps.128" || // Added in 4.0 153 Name == "avx512.mask.add.ps.256" || // Added in 4.0 154 Name == "avx512.mask.div.pd.128" || // Added in 4.0 155 Name == "avx512.mask.div.pd.256" || // Added in 4.0 156 Name == "avx512.mask.div.ps.128" || // Added in 4.0 157 Name == "avx512.mask.div.ps.256" || // Added in 4.0 158 Name == "avx512.mask.mul.pd.128" || // Added in 4.0 159 Name == "avx512.mask.mul.pd.256" || // Added in 4.0 160 Name == "avx512.mask.mul.ps.128" || // Added in 4.0 161 Name == "avx512.mask.mul.ps.256" || // Added in 4.0 162 Name == "avx512.mask.sub.pd.128" || // Added in 4.0 163 Name == "avx512.mask.sub.pd.256" || // Added in 4.0 164 Name == "avx512.mask.sub.ps.128" || // Added in 4.0 165 Name == "avx512.mask.sub.ps.256" || // Added in 4.0 166 Name == "avx512.mask.max.pd.128" || // Added in 5.0 167 Name == "avx512.mask.max.pd.256" || // Added in 5.0 168 Name == "avx512.mask.max.ps.128" || // Added in 5.0 169 Name == "avx512.mask.max.ps.256" || // Added in 5.0 170 Name == "avx512.mask.min.pd.128" || // Added in 5.0 171 Name == "avx512.mask.min.pd.256" || // Added in 5.0 172 Name == "avx512.mask.min.ps.128" || // Added in 5.0 173 Name == "avx512.mask.min.ps.256" || // Added in 5.0 174 Name.startswith("avx512.mask.vpermilvar.") || // Added in 4.0 175 Name.startswith("avx512.mask.psll.d") || // Added in 4.0 176 Name.startswith("avx512.mask.psll.q") || // Added in 4.0 177 Name.startswith("avx512.mask.psll.w") || // Added in 4.0 178 Name.startswith("avx512.mask.psra.d") || // Added in 4.0 179 Name.startswith("avx512.mask.psra.q") || // Added in 4.0 180 Name.startswith("avx512.mask.psra.w") || // Added in 4.0 181 Name.startswith("avx512.mask.psrl.d") || // Added in 4.0 182 Name.startswith("avx512.mask.psrl.q") || // Added in 4.0 183 Name.startswith("avx512.mask.psrl.w") || // Added in 4.0 184 Name.startswith("avx512.mask.pslli") || // Added in 4.0 185 Name.startswith("avx512.mask.psrai") || // Added in 4.0 186 Name.startswith("avx512.mask.psrli") || // Added in 4.0 187 Name.startswith("avx512.mask.psllv") || // Added in 4.0 188 Name.startswith("avx512.mask.psrav") || // Added in 4.0 189 Name.startswith("avx512.mask.psrlv") || // Added in 4.0 190 Name.startswith("sse41.pmovsx") || // Added in 3.8 191 Name.startswith("sse41.pmovzx") || // Added in 3.9 192 Name.startswith("avx2.pmovsx") || // Added in 3.9 193 Name.startswith("avx2.pmovzx") || // Added in 3.9 194 Name.startswith("avx512.mask.pmovsx") || // Added in 4.0 195 Name.startswith("avx512.mask.pmovzx") || // Added in 4.0 196 Name.startswith("avx512.mask.lzcnt.") || // Added in 5.0 197 Name == "sse2.cvtdq2pd" || // Added in 3.9 198 Name == "sse2.cvtps2pd" || // Added in 3.9 199 Name == "avx.cvtdq2.pd.256" || // Added in 3.9 200 Name == "avx.cvt.ps2.pd.256" || // Added in 3.9 201 Name.startswith("avx.vinsertf128.") || // Added in 3.7 202 Name == "avx2.vinserti128" || // Added in 3.7 203 Name.startswith("avx512.mask.insert") || // Added in 4.0 204 Name.startswith("avx.vextractf128.") || // Added in 3.7 205 Name == "avx2.vextracti128" || // Added in 3.7 206 Name.startswith("avx512.mask.vextract") || // Added in 4.0 207 Name.startswith("sse4a.movnt.") || // Added in 3.9 208 Name.startswith("avx.movnt.") || // Added in 3.2 209 Name.startswith("avx512.storent.") || // Added in 3.9 210 Name == "sse41.movntdqa" || // Added in 5.0 211 Name == "avx2.movntdqa" || // Added in 5.0 212 Name == "avx512.movntdqa" || // Added in 5.0 213 Name == "sse2.storel.dq" || // Added in 3.9 214 Name.startswith("sse.storeu.") || // Added in 3.9 215 Name.startswith("sse2.storeu.") || // Added in 3.9 216 Name.startswith("avx.storeu.") || // Added in 3.9 217 Name.startswith("avx512.mask.storeu.") || // Added in 3.9 218 Name.startswith("avx512.mask.store.p") || // Added in 3.9 219 Name.startswith("avx512.mask.store.b.") || // Added in 3.9 220 Name.startswith("avx512.mask.store.w.") || // Added in 3.9 221 Name.startswith("avx512.mask.store.d.") || // Added in 3.9 222 Name.startswith("avx512.mask.store.q.") || // Added in 3.9 223 Name.startswith("avx512.mask.loadu.") || // Added in 3.9 224 Name.startswith("avx512.mask.load.") || // Added in 3.9 225 Name == "sse42.crc32.64.8" || // Added in 3.4 226 Name.startswith("avx.vbroadcast.s") || // Added in 3.5 227 Name.startswith("avx512.mask.palignr.") || // Added in 3.9 228 Name.startswith("avx512.mask.valign.") || // Added in 4.0 229 Name.startswith("sse2.psll.dq") || // Added in 3.7 230 Name.startswith("sse2.psrl.dq") || // Added in 3.7 231 Name.startswith("avx2.psll.dq") || // Added in 3.7 232 Name.startswith("avx2.psrl.dq") || // Added in 3.7 233 Name.startswith("avx512.psll.dq") || // Added in 3.9 234 Name.startswith("avx512.psrl.dq") || // Added in 3.9 235 Name == "sse41.pblendw" || // Added in 3.7 236 Name.startswith("sse41.blendp") || // Added in 3.7 237 Name.startswith("avx.blend.p") || // Added in 3.7 238 Name == "avx2.pblendw" || // Added in 3.7 239 Name.startswith("avx2.pblendd.") || // Added in 3.7 240 Name.startswith("avx.vbroadcastf128") || // Added in 4.0 241 Name == "avx2.vbroadcasti128" || // Added in 3.7 242 Name.startswith("avx512.mask.broadcastf32x4.") || // Added in 6.0 243 Name.startswith("avx512.mask.broadcastf64x2.") || // Added in 6.0 244 Name.startswith("avx512.mask.broadcasti32x4.") || // Added in 6.0 245 Name.startswith("avx512.mask.broadcasti64x2.") || // Added in 6.0 246 Name == "avx512.mask.broadcastf32x8.512" || // Added in 6.0 247 Name == "avx512.mask.broadcasti32x8.512" || // Added in 6.0 248 Name == "avx512.mask.broadcastf64x4.512" || // Added in 6.0 249 Name == "avx512.mask.broadcasti64x4.512" || // Added in 6.0 250 Name == "xop.vpcmov" || // Added in 3.8 251 Name == "xop.vpcmov.256" || // Added in 5.0 252 Name.startswith("avx512.mask.move.s") || // Added in 4.0 253 Name.startswith("avx512.cvtmask2") || // Added in 5.0 254 (Name.startswith("xop.vpcom") && // Added in 3.2 255 F->arg_size() == 2)) 256 return true; 257 258 return false; 259 } 260 261 static bool UpgradeX86IntrinsicFunction(Function *F, StringRef Name, 262 Function *&NewFn) { 263 // Only handle intrinsics that start with "x86.". 264 if (!Name.startswith("x86.")) 265 return false; 266 // Remove "x86." prefix. 267 Name = Name.substr(4); 268 269 if (ShouldUpgradeX86Intrinsic(F, Name)) { 270 NewFn = nullptr; 271 return true; 272 } 273 274 // SSE4.1 ptest functions may have an old signature. 275 if (Name.startswith("sse41.ptest")) { // Added in 3.2 276 if (Name.substr(11) == "c") 277 return UpgradePTESTIntrinsic(F, Intrinsic::x86_sse41_ptestc, NewFn); 278 if (Name.substr(11) == "z") 279 return UpgradePTESTIntrinsic(F, Intrinsic::x86_sse41_ptestz, NewFn); 280 if (Name.substr(11) == "nzc") 281 return UpgradePTESTIntrinsic(F, Intrinsic::x86_sse41_ptestnzc, NewFn); 282 } 283 // Several blend and other instructions with masks used the wrong number of 284 // bits. 285 if (Name == "sse41.insertps") // Added in 3.6 286 return UpgradeX86IntrinsicsWith8BitMask(F, Intrinsic::x86_sse41_insertps, 287 NewFn); 288 if (Name == "sse41.dppd") // Added in 3.6 289 return UpgradeX86IntrinsicsWith8BitMask(F, Intrinsic::x86_sse41_dppd, 290 NewFn); 291 if (Name == "sse41.dpps") // Added in 3.6 292 return UpgradeX86IntrinsicsWith8BitMask(F, Intrinsic::x86_sse41_dpps, 293 NewFn); 294 if (Name == "sse41.mpsadbw") // Added in 3.6 295 return UpgradeX86IntrinsicsWith8BitMask(F, Intrinsic::x86_sse41_mpsadbw, 296 NewFn); 297 if (Name == "avx.dp.ps.256") // Added in 3.6 298 return UpgradeX86IntrinsicsWith8BitMask(F, Intrinsic::x86_avx_dp_ps_256, 299 NewFn); 300 if (Name == "avx2.mpsadbw") // Added in 3.6 301 return UpgradeX86IntrinsicsWith8BitMask(F, Intrinsic::x86_avx2_mpsadbw, 302 NewFn); 303 304 // frcz.ss/sd may need to have an argument dropped. Added in 3.2 305 if (Name.startswith("xop.vfrcz.ss") && F->arg_size() == 2) { 306 rename(F); 307 NewFn = Intrinsic::getDeclaration(F->getParent(), 308 Intrinsic::x86_xop_vfrcz_ss); 309 return true; 310 } 311 if (Name.startswith("xop.vfrcz.sd") && F->arg_size() == 2) { 312 rename(F); 313 NewFn = Intrinsic::getDeclaration(F->getParent(), 314 Intrinsic::x86_xop_vfrcz_sd); 315 return true; 316 } 317 // Upgrade any XOP PERMIL2 index operand still using a float/double vector. 318 if (Name.startswith("xop.vpermil2")) { // Added in 3.9 319 auto Idx = F->getFunctionType()->getParamType(2); 320 if (Idx->isFPOrFPVectorTy()) { 321 rename(F); 322 unsigned IdxSize = Idx->getPrimitiveSizeInBits(); 323 unsigned EltSize = Idx->getScalarSizeInBits(); 324 Intrinsic::ID Permil2ID; 325 if (EltSize == 64 && IdxSize == 128) 326 Permil2ID = Intrinsic::x86_xop_vpermil2pd; 327 else if (EltSize == 32 && IdxSize == 128) 328 Permil2ID = Intrinsic::x86_xop_vpermil2ps; 329 else if (EltSize == 64 && IdxSize == 256) 330 Permil2ID = Intrinsic::x86_xop_vpermil2pd_256; 331 else 332 Permil2ID = Intrinsic::x86_xop_vpermil2ps_256; 333 NewFn = Intrinsic::getDeclaration(F->getParent(), Permil2ID); 334 return true; 335 } 336 } 337 338 return false; 339 } 340 341 static bool UpgradeIntrinsicFunction1(Function *F, Function *&NewFn) { 342 assert(F && "Illegal to upgrade a non-existent Function."); 343 344 // Quickly eliminate it, if it's not a candidate. 345 StringRef Name = F->getName(); 346 if (Name.size() <= 8 || !Name.startswith("llvm.")) 347 return false; 348 Name = Name.substr(5); // Strip off "llvm." 349 350 switch (Name[0]) { 351 default: break; 352 case 'a': { 353 if (Name.startswith("arm.rbit") || Name.startswith("aarch64.rbit")) { 354 NewFn = Intrinsic::getDeclaration(F->getParent(), Intrinsic::bitreverse, 355 F->arg_begin()->getType()); 356 return true; 357 } 358 if (Name.startswith("arm.neon.vclz")) { 359 Type* args[2] = { 360 F->arg_begin()->getType(), 361 Type::getInt1Ty(F->getContext()) 362 }; 363 // Can't use Intrinsic::getDeclaration here as it adds a ".i1" to 364 // the end of the name. Change name from llvm.arm.neon.vclz.* to 365 // llvm.ctlz.* 366 FunctionType* fType = FunctionType::get(F->getReturnType(), args, false); 367 NewFn = Function::Create(fType, F->getLinkage(), 368 "llvm.ctlz." + Name.substr(14), F->getParent()); 369 return true; 370 } 371 if (Name.startswith("arm.neon.vcnt")) { 372 NewFn = Intrinsic::getDeclaration(F->getParent(), Intrinsic::ctpop, 373 F->arg_begin()->getType()); 374 return true; 375 } 376 Regex vldRegex("^arm\\.neon\\.vld([1234]|[234]lane)\\.v[a-z0-9]*$"); 377 if (vldRegex.match(Name)) { 378 auto fArgs = F->getFunctionType()->params(); 379 SmallVector<Type *, 4> Tys(fArgs.begin(), fArgs.end()); 380 // Can't use Intrinsic::getDeclaration here as the return types might 381 // then only be structurally equal. 382 FunctionType* fType = FunctionType::get(F->getReturnType(), Tys, false); 383 NewFn = Function::Create(fType, F->getLinkage(), 384 "llvm." + Name + ".p0i8", F->getParent()); 385 return true; 386 } 387 Regex vstRegex("^arm\\.neon\\.vst([1234]|[234]lane)\\.v[a-z0-9]*$"); 388 if (vstRegex.match(Name)) { 389 static const Intrinsic::ID StoreInts[] = {Intrinsic::arm_neon_vst1, 390 Intrinsic::arm_neon_vst2, 391 Intrinsic::arm_neon_vst3, 392 Intrinsic::arm_neon_vst4}; 393 394 static const Intrinsic::ID StoreLaneInts[] = { 395 Intrinsic::arm_neon_vst2lane, Intrinsic::arm_neon_vst3lane, 396 Intrinsic::arm_neon_vst4lane 397 }; 398 399 auto fArgs = F->getFunctionType()->params(); 400 Type *Tys[] = {fArgs[0], fArgs[1]}; 401 if (Name.find("lane") == StringRef::npos) 402 NewFn = Intrinsic::getDeclaration(F->getParent(), 403 StoreInts[fArgs.size() - 3], Tys); 404 else 405 NewFn = Intrinsic::getDeclaration(F->getParent(), 406 StoreLaneInts[fArgs.size() - 5], Tys); 407 return true; 408 } 409 if (Name == "aarch64.thread.pointer" || Name == "arm.thread.pointer") { 410 NewFn = Intrinsic::getDeclaration(F->getParent(), Intrinsic::thread_pointer); 411 return true; 412 } 413 break; 414 } 415 416 case 'c': { 417 if (Name.startswith("ctlz.") && F->arg_size() == 1) { 418 rename(F); 419 NewFn = Intrinsic::getDeclaration(F->getParent(), Intrinsic::ctlz, 420 F->arg_begin()->getType()); 421 return true; 422 } 423 if (Name.startswith("cttz.") && F->arg_size() == 1) { 424 rename(F); 425 NewFn = Intrinsic::getDeclaration(F->getParent(), Intrinsic::cttz, 426 F->arg_begin()->getType()); 427 return true; 428 } 429 break; 430 } 431 case 'd': { 432 if (Name == "dbg.value" && F->arg_size() == 4) { 433 rename(F); 434 NewFn = Intrinsic::getDeclaration(F->getParent(), Intrinsic::dbg_value); 435 return true; 436 } 437 break; 438 } 439 case 'i': 440 case 'l': { 441 bool IsLifetimeStart = Name.startswith("lifetime.start"); 442 if (IsLifetimeStart || Name.startswith("invariant.start")) { 443 Intrinsic::ID ID = IsLifetimeStart ? 444 Intrinsic::lifetime_start : Intrinsic::invariant_start; 445 auto Args = F->getFunctionType()->params(); 446 Type* ObjectPtr[1] = {Args[1]}; 447 if (F->getName() != Intrinsic::getName(ID, ObjectPtr)) { 448 rename(F); 449 NewFn = Intrinsic::getDeclaration(F->getParent(), ID, ObjectPtr); 450 return true; 451 } 452 } 453 454 bool IsLifetimeEnd = Name.startswith("lifetime.end"); 455 if (IsLifetimeEnd || Name.startswith("invariant.end")) { 456 Intrinsic::ID ID = IsLifetimeEnd ? 457 Intrinsic::lifetime_end : Intrinsic::invariant_end; 458 459 auto Args = F->getFunctionType()->params(); 460 Type* ObjectPtr[1] = {Args[IsLifetimeEnd ? 1 : 2]}; 461 if (F->getName() != Intrinsic::getName(ID, ObjectPtr)) { 462 rename(F); 463 NewFn = Intrinsic::getDeclaration(F->getParent(), ID, ObjectPtr); 464 return true; 465 } 466 } 467 break; 468 } 469 case 'm': { 470 if (Name.startswith("masked.load.")) { 471 Type *Tys[] = { F->getReturnType(), F->arg_begin()->getType() }; 472 if (F->getName() != Intrinsic::getName(Intrinsic::masked_load, Tys)) { 473 rename(F); 474 NewFn = Intrinsic::getDeclaration(F->getParent(), 475 Intrinsic::masked_load, 476 Tys); 477 return true; 478 } 479 } 480 if (Name.startswith("masked.store.")) { 481 auto Args = F->getFunctionType()->params(); 482 Type *Tys[] = { Args[0], Args[1] }; 483 if (F->getName() != Intrinsic::getName(Intrinsic::masked_store, Tys)) { 484 rename(F); 485 NewFn = Intrinsic::getDeclaration(F->getParent(), 486 Intrinsic::masked_store, 487 Tys); 488 return true; 489 } 490 } 491 // Renaming gather/scatter intrinsics with no address space overloading 492 // to the new overload which includes an address space 493 if (Name.startswith("masked.gather.")) { 494 Type *Tys[] = {F->getReturnType(), F->arg_begin()->getType()}; 495 if (F->getName() != Intrinsic::getName(Intrinsic::masked_gather, Tys)) { 496 rename(F); 497 NewFn = Intrinsic::getDeclaration(F->getParent(), 498 Intrinsic::masked_gather, Tys); 499 return true; 500 } 501 } 502 if (Name.startswith("masked.scatter.")) { 503 auto Args = F->getFunctionType()->params(); 504 Type *Tys[] = {Args[0], Args[1]}; 505 if (F->getName() != Intrinsic::getName(Intrinsic::masked_scatter, Tys)) { 506 rename(F); 507 NewFn = Intrinsic::getDeclaration(F->getParent(), 508 Intrinsic::masked_scatter, Tys); 509 return true; 510 } 511 } 512 break; 513 } 514 case 'n': { 515 if (Name.startswith("nvvm.")) { 516 Name = Name.substr(5); 517 518 // The following nvvm intrinsics correspond exactly to an LLVM intrinsic. 519 Intrinsic::ID IID = StringSwitch<Intrinsic::ID>(Name) 520 .Cases("brev32", "brev64", Intrinsic::bitreverse) 521 .Case("clz.i", Intrinsic::ctlz) 522 .Case("popc.i", Intrinsic::ctpop) 523 .Default(Intrinsic::not_intrinsic); 524 if (IID != Intrinsic::not_intrinsic && F->arg_size() == 1) { 525 NewFn = Intrinsic::getDeclaration(F->getParent(), IID, 526 {F->getReturnType()}); 527 return true; 528 } 529 530 // The following nvvm intrinsics correspond exactly to an LLVM idiom, but 531 // not to an intrinsic alone. We expand them in UpgradeIntrinsicCall. 532 // 533 // TODO: We could add lohi.i2d. 534 bool Expand = StringSwitch<bool>(Name) 535 .Cases("abs.i", "abs.ll", true) 536 .Cases("clz.ll", "popc.ll", "h2f", true) 537 .Cases("max.i", "max.ll", "max.ui", "max.ull", true) 538 .Cases("min.i", "min.ll", "min.ui", "min.ull", true) 539 .Default(false); 540 if (Expand) { 541 NewFn = nullptr; 542 return true; 543 } 544 } 545 break; 546 } 547 case 'o': 548 // We only need to change the name to match the mangling including the 549 // address space. 550 if (Name.startswith("objectsize.")) { 551 Type *Tys[2] = { F->getReturnType(), F->arg_begin()->getType() }; 552 if (F->arg_size() == 2 || 553 F->getName() != Intrinsic::getName(Intrinsic::objectsize, Tys)) { 554 rename(F); 555 NewFn = Intrinsic::getDeclaration(F->getParent(), Intrinsic::objectsize, 556 Tys); 557 return true; 558 } 559 } 560 break; 561 562 case 's': 563 if (Name == "stackprotectorcheck") { 564 NewFn = nullptr; 565 return true; 566 } 567 break; 568 569 case 'x': 570 if (UpgradeX86IntrinsicFunction(F, Name, NewFn)) 571 return true; 572 } 573 // Remangle our intrinsic since we upgrade the mangling 574 auto Result = llvm::Intrinsic::remangleIntrinsicFunction(F); 575 if (Result != None) { 576 NewFn = Result.getValue(); 577 return true; 578 } 579 580 // This may not belong here. This function is effectively being overloaded 581 // to both detect an intrinsic which needs upgrading, and to provide the 582 // upgraded form of the intrinsic. We should perhaps have two separate 583 // functions for this. 584 return false; 585 } 586 587 bool llvm::UpgradeIntrinsicFunction(Function *F, Function *&NewFn) { 588 NewFn = nullptr; 589 bool Upgraded = UpgradeIntrinsicFunction1(F, NewFn); 590 assert(F != NewFn && "Intrinsic function upgraded to the same function"); 591 592 // Upgrade intrinsic attributes. This does not change the function. 593 if (NewFn) 594 F = NewFn; 595 if (Intrinsic::ID id = F->getIntrinsicID()) 596 F->setAttributes(Intrinsic::getAttributes(F->getContext(), id)); 597 return Upgraded; 598 } 599 600 bool llvm::UpgradeGlobalVariable(GlobalVariable *GV) { 601 // Nothing to do yet. 602 return false; 603 } 604 605 // Handles upgrading SSE2/AVX2/AVX512BW PSLLDQ intrinsics by converting them 606 // to byte shuffles. 607 static Value *UpgradeX86PSLLDQIntrinsics(IRBuilder<> &Builder, 608 Value *Op, unsigned Shift) { 609 Type *ResultTy = Op->getType(); 610 unsigned NumElts = ResultTy->getVectorNumElements() * 8; 611 612 // Bitcast from a 64-bit element type to a byte element type. 613 Type *VecTy = VectorType::get(Builder.getInt8Ty(), NumElts); 614 Op = Builder.CreateBitCast(Op, VecTy, "cast"); 615 616 // We'll be shuffling in zeroes. 617 Value *Res = Constant::getNullValue(VecTy); 618 619 // If shift is less than 16, emit a shuffle to move the bytes. Otherwise, 620 // we'll just return the zero vector. 621 if (Shift < 16) { 622 uint32_t Idxs[64]; 623 // 256/512-bit version is split into 2/4 16-byte lanes. 624 for (unsigned l = 0; l != NumElts; l += 16) 625 for (unsigned i = 0; i != 16; ++i) { 626 unsigned Idx = NumElts + i - Shift; 627 if (Idx < NumElts) 628 Idx -= NumElts - 16; // end of lane, switch operand. 629 Idxs[l + i] = Idx + l; 630 } 631 632 Res = Builder.CreateShuffleVector(Res, Op, makeArrayRef(Idxs, NumElts)); 633 } 634 635 // Bitcast back to a 64-bit element type. 636 return Builder.CreateBitCast(Res, ResultTy, "cast"); 637 } 638 639 // Handles upgrading SSE2/AVX2/AVX512BW PSRLDQ intrinsics by converting them 640 // to byte shuffles. 641 static Value *UpgradeX86PSRLDQIntrinsics(IRBuilder<> &Builder, Value *Op, 642 unsigned Shift) { 643 Type *ResultTy = Op->getType(); 644 unsigned NumElts = ResultTy->getVectorNumElements() * 8; 645 646 // Bitcast from a 64-bit element type to a byte element type. 647 Type *VecTy = VectorType::get(Builder.getInt8Ty(), NumElts); 648 Op = Builder.CreateBitCast(Op, VecTy, "cast"); 649 650 // We'll be shuffling in zeroes. 651 Value *Res = Constant::getNullValue(VecTy); 652 653 // If shift is less than 16, emit a shuffle to move the bytes. Otherwise, 654 // we'll just return the zero vector. 655 if (Shift < 16) { 656 uint32_t Idxs[64]; 657 // 256/512-bit version is split into 2/4 16-byte lanes. 658 for (unsigned l = 0; l != NumElts; l += 16) 659 for (unsigned i = 0; i != 16; ++i) { 660 unsigned Idx = i + Shift; 661 if (Idx >= 16) 662 Idx += NumElts - 16; // end of lane, switch operand. 663 Idxs[l + i] = Idx + l; 664 } 665 666 Res = Builder.CreateShuffleVector(Op, Res, makeArrayRef(Idxs, NumElts)); 667 } 668 669 // Bitcast back to a 64-bit element type. 670 return Builder.CreateBitCast(Res, ResultTy, "cast"); 671 } 672 673 static Value *getX86MaskVec(IRBuilder<> &Builder, Value *Mask, 674 unsigned NumElts) { 675 llvm::VectorType *MaskTy = llvm::VectorType::get(Builder.getInt1Ty(), 676 cast<IntegerType>(Mask->getType())->getBitWidth()); 677 Mask = Builder.CreateBitCast(Mask, MaskTy); 678 679 // If we have less than 8 elements, then the starting mask was an i8 and 680 // we need to extract down to the right number of elements. 681 if (NumElts < 8) { 682 uint32_t Indices[4]; 683 for (unsigned i = 0; i != NumElts; ++i) 684 Indices[i] = i; 685 Mask = Builder.CreateShuffleVector(Mask, Mask, 686 makeArrayRef(Indices, NumElts), 687 "extract"); 688 } 689 690 return Mask; 691 } 692 693 static Value *EmitX86Select(IRBuilder<> &Builder, Value *Mask, 694 Value *Op0, Value *Op1) { 695 // If the mask is all ones just emit the align operation. 696 if (const auto *C = dyn_cast<Constant>(Mask)) 697 if (C->isAllOnesValue()) 698 return Op0; 699 700 Mask = getX86MaskVec(Builder, Mask, Op0->getType()->getVectorNumElements()); 701 return Builder.CreateSelect(Mask, Op0, Op1); 702 } 703 704 // Handle autoupgrade for masked PALIGNR and VALIGND/Q intrinsics. 705 // PALIGNR handles large immediates by shifting while VALIGN masks the immediate 706 // so we need to handle both cases. VALIGN also doesn't have 128-bit lanes. 707 static Value *UpgradeX86ALIGNIntrinsics(IRBuilder<> &Builder, Value *Op0, 708 Value *Op1, Value *Shift, 709 Value *Passthru, Value *Mask, 710 bool IsVALIGN) { 711 unsigned ShiftVal = cast<llvm::ConstantInt>(Shift)->getZExtValue(); 712 713 unsigned NumElts = Op0->getType()->getVectorNumElements(); 714 assert((IsVALIGN || NumElts % 16 == 0) && "Illegal NumElts for PALIGNR!"); 715 assert((!IsVALIGN || NumElts <= 16) && "NumElts too large for VALIGN!"); 716 assert(isPowerOf2_32(NumElts) && "NumElts not a power of 2!"); 717 718 // Mask the immediate for VALIGN. 719 if (IsVALIGN) 720 ShiftVal &= (NumElts - 1); 721 722 // If palignr is shifting the pair of vectors more than the size of two 723 // lanes, emit zero. 724 if (ShiftVal >= 32) 725 return llvm::Constant::getNullValue(Op0->getType()); 726 727 // If palignr is shifting the pair of input vectors more than one lane, 728 // but less than two lanes, convert to shifting in zeroes. 729 if (ShiftVal > 16) { 730 ShiftVal -= 16; 731 Op1 = Op0; 732 Op0 = llvm::Constant::getNullValue(Op0->getType()); 733 } 734 735 uint32_t Indices[64]; 736 // 256-bit palignr operates on 128-bit lanes so we need to handle that 737 for (unsigned l = 0; l < NumElts; l += 16) { 738 for (unsigned i = 0; i != 16; ++i) { 739 unsigned Idx = ShiftVal + i; 740 if (!IsVALIGN && Idx >= 16) // Disable wrap for VALIGN. 741 Idx += NumElts - 16; // End of lane, switch operand. 742 Indices[l + i] = Idx + l; 743 } 744 } 745 746 Value *Align = Builder.CreateShuffleVector(Op1, Op0, 747 makeArrayRef(Indices, NumElts), 748 "palignr"); 749 750 return EmitX86Select(Builder, Mask, Align, Passthru); 751 } 752 753 static Value *UpgradeMaskedStore(IRBuilder<> &Builder, 754 Value *Ptr, Value *Data, Value *Mask, 755 bool Aligned) { 756 // Cast the pointer to the right type. 757 Ptr = Builder.CreateBitCast(Ptr, 758 llvm::PointerType::getUnqual(Data->getType())); 759 unsigned Align = 760 Aligned ? cast<VectorType>(Data->getType())->getBitWidth() / 8 : 1; 761 762 // If the mask is all ones just emit a regular store. 763 if (const auto *C = dyn_cast<Constant>(Mask)) 764 if (C->isAllOnesValue()) 765 return Builder.CreateAlignedStore(Data, Ptr, Align); 766 767 // Convert the mask from an integer type to a vector of i1. 768 unsigned NumElts = Data->getType()->getVectorNumElements(); 769 Mask = getX86MaskVec(Builder, Mask, NumElts); 770 return Builder.CreateMaskedStore(Data, Ptr, Align, Mask); 771 } 772 773 static Value *UpgradeMaskedLoad(IRBuilder<> &Builder, 774 Value *Ptr, Value *Passthru, Value *Mask, 775 bool Aligned) { 776 // Cast the pointer to the right type. 777 Ptr = Builder.CreateBitCast(Ptr, 778 llvm::PointerType::getUnqual(Passthru->getType())); 779 unsigned Align = 780 Aligned ? cast<VectorType>(Passthru->getType())->getBitWidth() / 8 : 1; 781 782 // If the mask is all ones just emit a regular store. 783 if (const auto *C = dyn_cast<Constant>(Mask)) 784 if (C->isAllOnesValue()) 785 return Builder.CreateAlignedLoad(Ptr, Align); 786 787 // Convert the mask from an integer type to a vector of i1. 788 unsigned NumElts = Passthru->getType()->getVectorNumElements(); 789 Mask = getX86MaskVec(Builder, Mask, NumElts); 790 return Builder.CreateMaskedLoad(Ptr, Align, Mask, Passthru); 791 } 792 793 static Value *upgradeIntMinMax(IRBuilder<> &Builder, CallInst &CI, 794 ICmpInst::Predicate Pred) { 795 Value *Op0 = CI.getArgOperand(0); 796 Value *Op1 = CI.getArgOperand(1); 797 Value *Cmp = Builder.CreateICmp(Pred, Op0, Op1); 798 Value *Res = Builder.CreateSelect(Cmp, Op0, Op1); 799 800 if (CI.getNumArgOperands() == 4) 801 Res = EmitX86Select(Builder, CI.getArgOperand(3), Res, CI.getArgOperand(2)); 802 803 return Res; 804 } 805 806 static Value *upgradeMaskedCompare(IRBuilder<> &Builder, CallInst &CI, 807 unsigned CC, bool Signed) { 808 Value *Op0 = CI.getArgOperand(0); 809 unsigned NumElts = Op0->getType()->getVectorNumElements(); 810 811 Value *Cmp; 812 if (CC == 3) { 813 Cmp = Constant::getNullValue(llvm::VectorType::get(Builder.getInt1Ty(), NumElts)); 814 } else if (CC == 7) { 815 Cmp = Constant::getAllOnesValue(llvm::VectorType::get(Builder.getInt1Ty(), NumElts)); 816 } else { 817 ICmpInst::Predicate Pred; 818 switch (CC) { 819 default: llvm_unreachable("Unknown condition code"); 820 case 0: Pred = ICmpInst::ICMP_EQ; break; 821 case 1: Pred = Signed ? ICmpInst::ICMP_SLT : ICmpInst::ICMP_ULT; break; 822 case 2: Pred = Signed ? ICmpInst::ICMP_SLE : ICmpInst::ICMP_ULE; break; 823 case 4: Pred = ICmpInst::ICMP_NE; break; 824 case 5: Pred = Signed ? ICmpInst::ICMP_SGE : ICmpInst::ICMP_UGE; break; 825 case 6: Pred = Signed ? ICmpInst::ICMP_SGT : ICmpInst::ICMP_UGT; break; 826 } 827 Cmp = Builder.CreateICmp(Pred, Op0, CI.getArgOperand(1)); 828 } 829 830 Value *Mask = CI.getArgOperand(CI.getNumArgOperands() - 1); 831 const auto *C = dyn_cast<Constant>(Mask); 832 if (!C || !C->isAllOnesValue()) 833 Cmp = Builder.CreateAnd(Cmp, getX86MaskVec(Builder, Mask, NumElts)); 834 835 if (NumElts < 8) { 836 uint32_t Indices[8]; 837 for (unsigned i = 0; i != NumElts; ++i) 838 Indices[i] = i; 839 for (unsigned i = NumElts; i != 8; ++i) 840 Indices[i] = NumElts + i % NumElts; 841 Cmp = Builder.CreateShuffleVector(Cmp, 842 Constant::getNullValue(Cmp->getType()), 843 Indices); 844 } 845 return Builder.CreateBitCast(Cmp, IntegerType::get(CI.getContext(), 846 std::max(NumElts, 8U))); 847 } 848 849 // Replace a masked intrinsic with an older unmasked intrinsic. 850 static Value *UpgradeX86MaskedShift(IRBuilder<> &Builder, CallInst &CI, 851 Intrinsic::ID IID) { 852 Function *F = CI.getCalledFunction(); 853 Function *Intrin = Intrinsic::getDeclaration(F->getParent(), IID); 854 Value *Rep = Builder.CreateCall(Intrin, 855 { CI.getArgOperand(0), CI.getArgOperand(1) }); 856 return EmitX86Select(Builder, CI.getArgOperand(3), Rep, CI.getArgOperand(2)); 857 } 858 859 static Value* upgradeMaskedMove(IRBuilder<> &Builder, CallInst &CI) { 860 Value* A = CI.getArgOperand(0); 861 Value* B = CI.getArgOperand(1); 862 Value* Src = CI.getArgOperand(2); 863 Value* Mask = CI.getArgOperand(3); 864 865 Value* AndNode = Builder.CreateAnd(Mask, APInt(8, 1)); 866 Value* Cmp = Builder.CreateIsNotNull(AndNode); 867 Value* Extract1 = Builder.CreateExtractElement(B, (uint64_t)0); 868 Value* Extract2 = Builder.CreateExtractElement(Src, (uint64_t)0); 869 Value* Select = Builder.CreateSelect(Cmp, Extract1, Extract2); 870 return Builder.CreateInsertElement(A, Select, (uint64_t)0); 871 } 872 873 874 static Value* UpgradeMaskToInt(IRBuilder<> &Builder, CallInst &CI) { 875 Value* Op = CI.getArgOperand(0); 876 Type* ReturnOp = CI.getType(); 877 unsigned NumElts = CI.getType()->getVectorNumElements(); 878 Value *Mask = getX86MaskVec(Builder, Op, NumElts); 879 return Builder.CreateSExt(Mask, ReturnOp, "vpmovm2"); 880 } 881 882 /// Upgrade a call to an old intrinsic. All argument and return casting must be 883 /// provided to seamlessly integrate with existing context. 884 void llvm::UpgradeIntrinsicCall(CallInst *CI, Function *NewFn) { 885 Function *F = CI->getCalledFunction(); 886 LLVMContext &C = CI->getContext(); 887 IRBuilder<> Builder(C); 888 Builder.SetInsertPoint(CI->getParent(), CI->getIterator()); 889 890 assert(F && "Intrinsic call is not direct?"); 891 892 if (!NewFn) { 893 // Get the Function's name. 894 StringRef Name = F->getName(); 895 896 assert(Name.startswith("llvm.") && "Intrinsic doesn't start with 'llvm.'"); 897 Name = Name.substr(5); 898 899 bool IsX86 = Name.startswith("x86."); 900 if (IsX86) 901 Name = Name.substr(4); 902 bool IsNVVM = Name.startswith("nvvm."); 903 if (IsNVVM) 904 Name = Name.substr(5); 905 906 if (IsX86 && Name.startswith("sse4a.movnt.")) { 907 Module *M = F->getParent(); 908 SmallVector<Metadata *, 1> Elts; 909 Elts.push_back( 910 ConstantAsMetadata::get(ConstantInt::get(Type::getInt32Ty(C), 1))); 911 MDNode *Node = MDNode::get(C, Elts); 912 913 Value *Arg0 = CI->getArgOperand(0); 914 Value *Arg1 = CI->getArgOperand(1); 915 916 // Nontemporal (unaligned) store of the 0'th element of the float/double 917 // vector. 918 Type *SrcEltTy = cast<VectorType>(Arg1->getType())->getElementType(); 919 PointerType *EltPtrTy = PointerType::getUnqual(SrcEltTy); 920 Value *Addr = Builder.CreateBitCast(Arg0, EltPtrTy, "cast"); 921 Value *Extract = 922 Builder.CreateExtractElement(Arg1, (uint64_t)0, "extractelement"); 923 924 StoreInst *SI = Builder.CreateAlignedStore(Extract, Addr, 1); 925 SI->setMetadata(M->getMDKindID("nontemporal"), Node); 926 927 // Remove intrinsic. 928 CI->eraseFromParent(); 929 return; 930 } 931 932 if (IsX86 && (Name.startswith("avx.movnt.") || 933 Name.startswith("avx512.storent."))) { 934 Module *M = F->getParent(); 935 SmallVector<Metadata *, 1> Elts; 936 Elts.push_back( 937 ConstantAsMetadata::get(ConstantInt::get(Type::getInt32Ty(C), 1))); 938 MDNode *Node = MDNode::get(C, Elts); 939 940 Value *Arg0 = CI->getArgOperand(0); 941 Value *Arg1 = CI->getArgOperand(1); 942 943 // Convert the type of the pointer to a pointer to the stored type. 944 Value *BC = Builder.CreateBitCast(Arg0, 945 PointerType::getUnqual(Arg1->getType()), 946 "cast"); 947 VectorType *VTy = cast<VectorType>(Arg1->getType()); 948 StoreInst *SI = Builder.CreateAlignedStore(Arg1, BC, 949 VTy->getBitWidth() / 8); 950 SI->setMetadata(M->getMDKindID("nontemporal"), Node); 951 952 // Remove intrinsic. 953 CI->eraseFromParent(); 954 return; 955 } 956 957 if (IsX86 && Name == "sse2.storel.dq") { 958 Value *Arg0 = CI->getArgOperand(0); 959 Value *Arg1 = CI->getArgOperand(1); 960 961 Type *NewVecTy = VectorType::get(Type::getInt64Ty(C), 2); 962 Value *BC0 = Builder.CreateBitCast(Arg1, NewVecTy, "cast"); 963 Value *Elt = Builder.CreateExtractElement(BC0, (uint64_t)0); 964 Value *BC = Builder.CreateBitCast(Arg0, 965 PointerType::getUnqual(Elt->getType()), 966 "cast"); 967 Builder.CreateAlignedStore(Elt, BC, 1); 968 969 // Remove intrinsic. 970 CI->eraseFromParent(); 971 return; 972 } 973 974 if (IsX86 && (Name.startswith("sse.storeu.") || 975 Name.startswith("sse2.storeu.") || 976 Name.startswith("avx.storeu."))) { 977 Value *Arg0 = CI->getArgOperand(0); 978 Value *Arg1 = CI->getArgOperand(1); 979 980 Arg0 = Builder.CreateBitCast(Arg0, 981 PointerType::getUnqual(Arg1->getType()), 982 "cast"); 983 Builder.CreateAlignedStore(Arg1, Arg0, 1); 984 985 // Remove intrinsic. 986 CI->eraseFromParent(); 987 return; 988 } 989 990 if (IsX86 && (Name.startswith("avx512.mask.store"))) { 991 // "avx512.mask.storeu." or "avx512.mask.store." 992 bool Aligned = Name[17] != 'u'; // "avx512.mask.storeu". 993 UpgradeMaskedStore(Builder, CI->getArgOperand(0), CI->getArgOperand(1), 994 CI->getArgOperand(2), Aligned); 995 996 // Remove intrinsic. 997 CI->eraseFromParent(); 998 return; 999 } 1000 1001 Value *Rep; 1002 // Upgrade packed integer vector compare intrinsics to compare instructions. 1003 if (IsX86 && (Name.startswith("sse2.pcmp") || 1004 Name.startswith("avx2.pcmp"))) { 1005 // "sse2.pcpmpeq." "sse2.pcmpgt." "avx2.pcmpeq." or "avx2.pcmpgt." 1006 bool CmpEq = Name[9] == 'e'; 1007 Rep = Builder.CreateICmp(CmpEq ? ICmpInst::ICMP_EQ : ICmpInst::ICMP_SGT, 1008 CI->getArgOperand(0), CI->getArgOperand(1)); 1009 Rep = Builder.CreateSExt(Rep, CI->getType(), ""); 1010 } else if (IsX86 && (Name == "sse.add.ss" || Name == "sse2.add.sd")) { 1011 Type *I32Ty = Type::getInt32Ty(C); 1012 Value *Elt0 = Builder.CreateExtractElement(CI->getArgOperand(0), 1013 ConstantInt::get(I32Ty, 0)); 1014 Value *Elt1 = Builder.CreateExtractElement(CI->getArgOperand(1), 1015 ConstantInt::get(I32Ty, 0)); 1016 Rep = Builder.CreateInsertElement(CI->getArgOperand(0), 1017 Builder.CreateFAdd(Elt0, Elt1), 1018 ConstantInt::get(I32Ty, 0)); 1019 } else if (IsX86 && (Name == "sse.sub.ss" || Name == "sse2.sub.sd")) { 1020 Type *I32Ty = Type::getInt32Ty(C); 1021 Value *Elt0 = Builder.CreateExtractElement(CI->getArgOperand(0), 1022 ConstantInt::get(I32Ty, 0)); 1023 Value *Elt1 = Builder.CreateExtractElement(CI->getArgOperand(1), 1024 ConstantInt::get(I32Ty, 0)); 1025 Rep = Builder.CreateInsertElement(CI->getArgOperand(0), 1026 Builder.CreateFSub(Elt0, Elt1), 1027 ConstantInt::get(I32Ty, 0)); 1028 } else if (IsX86 && (Name == "sse.mul.ss" || Name == "sse2.mul.sd")) { 1029 Type *I32Ty = Type::getInt32Ty(C); 1030 Value *Elt0 = Builder.CreateExtractElement(CI->getArgOperand(0), 1031 ConstantInt::get(I32Ty, 0)); 1032 Value *Elt1 = Builder.CreateExtractElement(CI->getArgOperand(1), 1033 ConstantInt::get(I32Ty, 0)); 1034 Rep = Builder.CreateInsertElement(CI->getArgOperand(0), 1035 Builder.CreateFMul(Elt0, Elt1), 1036 ConstantInt::get(I32Ty, 0)); 1037 } else if (IsX86 && (Name == "sse.div.ss" || Name == "sse2.div.sd")) { 1038 Type *I32Ty = Type::getInt32Ty(C); 1039 Value *Elt0 = Builder.CreateExtractElement(CI->getArgOperand(0), 1040 ConstantInt::get(I32Ty, 0)); 1041 Value *Elt1 = Builder.CreateExtractElement(CI->getArgOperand(1), 1042 ConstantInt::get(I32Ty, 0)); 1043 Rep = Builder.CreateInsertElement(CI->getArgOperand(0), 1044 Builder.CreateFDiv(Elt0, Elt1), 1045 ConstantInt::get(I32Ty, 0)); 1046 } else if (IsX86 && Name.startswith("avx512.mask.pcmp")) { 1047 // "avx512.mask.pcmpeq." or "avx512.mask.pcmpgt." 1048 bool CmpEq = Name[16] == 'e'; 1049 Rep = upgradeMaskedCompare(Builder, *CI, CmpEq ? 0 : 6, true); 1050 } else if (IsX86 && Name.startswith("avx512.mask.cmp")) { 1051 unsigned Imm = cast<ConstantInt>(CI->getArgOperand(2))->getZExtValue(); 1052 Rep = upgradeMaskedCompare(Builder, *CI, Imm, true); 1053 } else if (IsX86 && Name.startswith("avx512.mask.ucmp")) { 1054 unsigned Imm = cast<ConstantInt>(CI->getArgOperand(2))->getZExtValue(); 1055 Rep = upgradeMaskedCompare(Builder, *CI, Imm, false); 1056 } else if (IsX86 && (Name == "sse41.pmaxsb" || 1057 Name == "sse2.pmaxs.w" || 1058 Name == "sse41.pmaxsd" || 1059 Name.startswith("avx2.pmaxs") || 1060 Name.startswith("avx512.mask.pmaxs"))) { 1061 Rep = upgradeIntMinMax(Builder, *CI, ICmpInst::ICMP_SGT); 1062 } else if (IsX86 && (Name == "sse2.pmaxu.b" || 1063 Name == "sse41.pmaxuw" || 1064 Name == "sse41.pmaxud" || 1065 Name.startswith("avx2.pmaxu") || 1066 Name.startswith("avx512.mask.pmaxu"))) { 1067 Rep = upgradeIntMinMax(Builder, *CI, ICmpInst::ICMP_UGT); 1068 } else if (IsX86 && (Name == "sse41.pminsb" || 1069 Name == "sse2.pmins.w" || 1070 Name == "sse41.pminsd" || 1071 Name.startswith("avx2.pmins") || 1072 Name.startswith("avx512.mask.pmins"))) { 1073 Rep = upgradeIntMinMax(Builder, *CI, ICmpInst::ICMP_SLT); 1074 } else if (IsX86 && (Name == "sse2.pminu.b" || 1075 Name == "sse41.pminuw" || 1076 Name == "sse41.pminud" || 1077 Name.startswith("avx2.pminu") || 1078 Name.startswith("avx512.mask.pminu"))) { 1079 Rep = upgradeIntMinMax(Builder, *CI, ICmpInst::ICMP_ULT); 1080 } else if (IsX86 && (Name == "sse2.cvtdq2pd" || 1081 Name == "sse2.cvtps2pd" || 1082 Name == "avx.cvtdq2.pd.256" || 1083 Name == "avx.cvt.ps2.pd.256" || 1084 Name.startswith("avx512.mask.cvtdq2pd.") || 1085 Name.startswith("avx512.mask.cvtudq2pd."))) { 1086 // Lossless i32/float to double conversion. 1087 // Extract the bottom elements if necessary and convert to double vector. 1088 Value *Src = CI->getArgOperand(0); 1089 VectorType *SrcTy = cast<VectorType>(Src->getType()); 1090 VectorType *DstTy = cast<VectorType>(CI->getType()); 1091 Rep = CI->getArgOperand(0); 1092 1093 unsigned NumDstElts = DstTy->getNumElements(); 1094 if (NumDstElts < SrcTy->getNumElements()) { 1095 assert(NumDstElts == 2 && "Unexpected vector size"); 1096 uint32_t ShuffleMask[2] = { 0, 1 }; 1097 Rep = Builder.CreateShuffleVector(Rep, UndefValue::get(SrcTy), 1098 ShuffleMask); 1099 } 1100 1101 bool SInt2Double = (StringRef::npos != Name.find("cvtdq2")); 1102 bool UInt2Double = (StringRef::npos != Name.find("cvtudq2")); 1103 if (SInt2Double) 1104 Rep = Builder.CreateSIToFP(Rep, DstTy, "cvtdq2pd"); 1105 else if (UInt2Double) 1106 Rep = Builder.CreateUIToFP(Rep, DstTy, "cvtudq2pd"); 1107 else 1108 Rep = Builder.CreateFPExt(Rep, DstTy, "cvtps2pd"); 1109 1110 if (CI->getNumArgOperands() == 3) 1111 Rep = EmitX86Select(Builder, CI->getArgOperand(2), Rep, 1112 CI->getArgOperand(1)); 1113 } else if (IsX86 && (Name.startswith("avx512.mask.loadu."))) { 1114 Rep = UpgradeMaskedLoad(Builder, CI->getArgOperand(0), 1115 CI->getArgOperand(1), CI->getArgOperand(2), 1116 /*Aligned*/false); 1117 } else if (IsX86 && (Name.startswith("avx512.mask.load."))) { 1118 Rep = UpgradeMaskedLoad(Builder, CI->getArgOperand(0), 1119 CI->getArgOperand(1),CI->getArgOperand(2), 1120 /*Aligned*/true); 1121 } else if (IsX86 && Name.startswith("xop.vpcom")) { 1122 Intrinsic::ID intID; 1123 if (Name.endswith("ub")) 1124 intID = Intrinsic::x86_xop_vpcomub; 1125 else if (Name.endswith("uw")) 1126 intID = Intrinsic::x86_xop_vpcomuw; 1127 else if (Name.endswith("ud")) 1128 intID = Intrinsic::x86_xop_vpcomud; 1129 else if (Name.endswith("uq")) 1130 intID = Intrinsic::x86_xop_vpcomuq; 1131 else if (Name.endswith("b")) 1132 intID = Intrinsic::x86_xop_vpcomb; 1133 else if (Name.endswith("w")) 1134 intID = Intrinsic::x86_xop_vpcomw; 1135 else if (Name.endswith("d")) 1136 intID = Intrinsic::x86_xop_vpcomd; 1137 else if (Name.endswith("q")) 1138 intID = Intrinsic::x86_xop_vpcomq; 1139 else 1140 llvm_unreachable("Unknown suffix"); 1141 1142 Name = Name.substr(9); // strip off "xop.vpcom" 1143 unsigned Imm; 1144 if (Name.startswith("lt")) 1145 Imm = 0; 1146 else if (Name.startswith("le")) 1147 Imm = 1; 1148 else if (Name.startswith("gt")) 1149 Imm = 2; 1150 else if (Name.startswith("ge")) 1151 Imm = 3; 1152 else if (Name.startswith("eq")) 1153 Imm = 4; 1154 else if (Name.startswith("ne")) 1155 Imm = 5; 1156 else if (Name.startswith("false")) 1157 Imm = 6; 1158 else if (Name.startswith("true")) 1159 Imm = 7; 1160 else 1161 llvm_unreachable("Unknown condition"); 1162 1163 Function *VPCOM = Intrinsic::getDeclaration(F->getParent(), intID); 1164 Rep = 1165 Builder.CreateCall(VPCOM, {CI->getArgOperand(0), CI->getArgOperand(1), 1166 Builder.getInt8(Imm)}); 1167 } else if (IsX86 && Name.startswith("xop.vpcmov")) { 1168 Value *Sel = CI->getArgOperand(2); 1169 Value *NotSel = Builder.CreateNot(Sel); 1170 Value *Sel0 = Builder.CreateAnd(CI->getArgOperand(0), Sel); 1171 Value *Sel1 = Builder.CreateAnd(CI->getArgOperand(1), NotSel); 1172 Rep = Builder.CreateOr(Sel0, Sel1); 1173 } else if (IsX86 && Name == "sse42.crc32.64.8") { 1174 Function *CRC32 = Intrinsic::getDeclaration(F->getParent(), 1175 Intrinsic::x86_sse42_crc32_32_8); 1176 Value *Trunc0 = Builder.CreateTrunc(CI->getArgOperand(0), Type::getInt32Ty(C)); 1177 Rep = Builder.CreateCall(CRC32, {Trunc0, CI->getArgOperand(1)}); 1178 Rep = Builder.CreateZExt(Rep, CI->getType(), ""); 1179 } else if (IsX86 && Name.startswith("avx.vbroadcast.s")) { 1180 // Replace broadcasts with a series of insertelements. 1181 Type *VecTy = CI->getType(); 1182 Type *EltTy = VecTy->getVectorElementType(); 1183 unsigned EltNum = VecTy->getVectorNumElements(); 1184 Value *Cast = Builder.CreateBitCast(CI->getArgOperand(0), 1185 EltTy->getPointerTo()); 1186 Value *Load = Builder.CreateLoad(EltTy, Cast); 1187 Type *I32Ty = Type::getInt32Ty(C); 1188 Rep = UndefValue::get(VecTy); 1189 for (unsigned I = 0; I < EltNum; ++I) 1190 Rep = Builder.CreateInsertElement(Rep, Load, 1191 ConstantInt::get(I32Ty, I)); 1192 } else if (IsX86 && (Name.startswith("sse41.pmovsx") || 1193 Name.startswith("sse41.pmovzx") || 1194 Name.startswith("avx2.pmovsx") || 1195 Name.startswith("avx2.pmovzx") || 1196 Name.startswith("avx512.mask.pmovsx") || 1197 Name.startswith("avx512.mask.pmovzx"))) { 1198 VectorType *SrcTy = cast<VectorType>(CI->getArgOperand(0)->getType()); 1199 VectorType *DstTy = cast<VectorType>(CI->getType()); 1200 unsigned NumDstElts = DstTy->getNumElements(); 1201 1202 // Extract a subvector of the first NumDstElts lanes and sign/zero extend. 1203 SmallVector<uint32_t, 8> ShuffleMask(NumDstElts); 1204 for (unsigned i = 0; i != NumDstElts; ++i) 1205 ShuffleMask[i] = i; 1206 1207 Value *SV = Builder.CreateShuffleVector( 1208 CI->getArgOperand(0), UndefValue::get(SrcTy), ShuffleMask); 1209 1210 bool DoSext = (StringRef::npos != Name.find("pmovsx")); 1211 Rep = DoSext ? Builder.CreateSExt(SV, DstTy) 1212 : Builder.CreateZExt(SV, DstTy); 1213 // If there are 3 arguments, it's a masked intrinsic so we need a select. 1214 if (CI->getNumArgOperands() == 3) 1215 Rep = EmitX86Select(Builder, CI->getArgOperand(2), Rep, 1216 CI->getArgOperand(1)); 1217 } else if (IsX86 && (Name.startswith("avx.vbroadcastf128") || 1218 Name == "avx2.vbroadcasti128")) { 1219 // Replace vbroadcastf128/vbroadcasti128 with a vector load+shuffle. 1220 Type *EltTy = CI->getType()->getVectorElementType(); 1221 unsigned NumSrcElts = 128 / EltTy->getPrimitiveSizeInBits(); 1222 Type *VT = VectorType::get(EltTy, NumSrcElts); 1223 Value *Op = Builder.CreatePointerCast(CI->getArgOperand(0), 1224 PointerType::getUnqual(VT)); 1225 Value *Load = Builder.CreateAlignedLoad(Op, 1); 1226 if (NumSrcElts == 2) 1227 Rep = Builder.CreateShuffleVector(Load, UndefValue::get(Load->getType()), 1228 { 0, 1, 0, 1 }); 1229 else 1230 Rep = Builder.CreateShuffleVector(Load, UndefValue::get(Load->getType()), 1231 { 0, 1, 2, 3, 0, 1, 2, 3 }); 1232 } else if (IsX86 && (Name.startswith("avx512.mask.broadcastf") || 1233 Name.startswith("avx512.mask.broadcasti"))) { 1234 unsigned NumSrcElts = 1235 CI->getArgOperand(0)->getType()->getVectorNumElements(); 1236 unsigned NumDstElts = CI->getType()->getVectorNumElements(); 1237 1238 SmallVector<uint32_t, 8> ShuffleMask(NumDstElts); 1239 for (unsigned i = 0; i != NumDstElts; ++i) 1240 ShuffleMask[i] = i % NumSrcElts; 1241 1242 Rep = Builder.CreateShuffleVector(CI->getArgOperand(0), 1243 CI->getArgOperand(0), 1244 ShuffleMask); 1245 Rep = EmitX86Select(Builder, CI->getArgOperand(2), Rep, 1246 CI->getArgOperand(1)); 1247 } else if (IsX86 && (Name.startswith("avx2.pbroadcast") || 1248 Name.startswith("avx2.vbroadcast") || 1249 Name.startswith("avx512.pbroadcast") || 1250 Name.startswith("avx512.mask.broadcast.s"))) { 1251 // Replace vp?broadcasts with a vector shuffle. 1252 Value *Op = CI->getArgOperand(0); 1253 unsigned NumElts = CI->getType()->getVectorNumElements(); 1254 Type *MaskTy = VectorType::get(Type::getInt32Ty(C), NumElts); 1255 Rep = Builder.CreateShuffleVector(Op, UndefValue::get(Op->getType()), 1256 Constant::getNullValue(MaskTy)); 1257 1258 if (CI->getNumArgOperands() == 3) 1259 Rep = EmitX86Select(Builder, CI->getArgOperand(2), Rep, 1260 CI->getArgOperand(1)); 1261 } else if (IsX86 && Name.startswith("avx512.mask.palignr.")) { 1262 Rep = UpgradeX86ALIGNIntrinsics(Builder, CI->getArgOperand(0), 1263 CI->getArgOperand(1), 1264 CI->getArgOperand(2), 1265 CI->getArgOperand(3), 1266 CI->getArgOperand(4), 1267 false); 1268 } else if (IsX86 && Name.startswith("avx512.mask.valign.")) { 1269 Rep = UpgradeX86ALIGNIntrinsics(Builder, CI->getArgOperand(0), 1270 CI->getArgOperand(1), 1271 CI->getArgOperand(2), 1272 CI->getArgOperand(3), 1273 CI->getArgOperand(4), 1274 true); 1275 } else if (IsX86 && (Name == "sse2.psll.dq" || 1276 Name == "avx2.psll.dq")) { 1277 // 128/256-bit shift left specified in bits. 1278 unsigned Shift = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue(); 1279 Rep = UpgradeX86PSLLDQIntrinsics(Builder, CI->getArgOperand(0), 1280 Shift / 8); // Shift is in bits. 1281 } else if (IsX86 && (Name == "sse2.psrl.dq" || 1282 Name == "avx2.psrl.dq")) { 1283 // 128/256-bit shift right specified in bits. 1284 unsigned Shift = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue(); 1285 Rep = UpgradeX86PSRLDQIntrinsics(Builder, CI->getArgOperand(0), 1286 Shift / 8); // Shift is in bits. 1287 } else if (IsX86 && (Name == "sse2.psll.dq.bs" || 1288 Name == "avx2.psll.dq.bs" || 1289 Name == "avx512.psll.dq.512")) { 1290 // 128/256/512-bit shift left specified in bytes. 1291 unsigned Shift = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue(); 1292 Rep = UpgradeX86PSLLDQIntrinsics(Builder, CI->getArgOperand(0), Shift); 1293 } else if (IsX86 && (Name == "sse2.psrl.dq.bs" || 1294 Name == "avx2.psrl.dq.bs" || 1295 Name == "avx512.psrl.dq.512")) { 1296 // 128/256/512-bit shift right specified in bytes. 1297 unsigned Shift = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue(); 1298 Rep = UpgradeX86PSRLDQIntrinsics(Builder, CI->getArgOperand(0), Shift); 1299 } else if (IsX86 && (Name == "sse41.pblendw" || 1300 Name.startswith("sse41.blendp") || 1301 Name.startswith("avx.blend.p") || 1302 Name == "avx2.pblendw" || 1303 Name.startswith("avx2.pblendd."))) { 1304 Value *Op0 = CI->getArgOperand(0); 1305 Value *Op1 = CI->getArgOperand(1); 1306 unsigned Imm = cast <ConstantInt>(CI->getArgOperand(2))->getZExtValue(); 1307 VectorType *VecTy = cast<VectorType>(CI->getType()); 1308 unsigned NumElts = VecTy->getNumElements(); 1309 1310 SmallVector<uint32_t, 16> Idxs(NumElts); 1311 for (unsigned i = 0; i != NumElts; ++i) 1312 Idxs[i] = ((Imm >> (i%8)) & 1) ? i + NumElts : i; 1313 1314 Rep = Builder.CreateShuffleVector(Op0, Op1, Idxs); 1315 } else if (IsX86 && (Name.startswith("avx.vinsertf128.") || 1316 Name == "avx2.vinserti128" || 1317 Name.startswith("avx512.mask.insert"))) { 1318 Value *Op0 = CI->getArgOperand(0); 1319 Value *Op1 = CI->getArgOperand(1); 1320 unsigned Imm = cast<ConstantInt>(CI->getArgOperand(2))->getZExtValue(); 1321 unsigned DstNumElts = CI->getType()->getVectorNumElements(); 1322 unsigned SrcNumElts = Op1->getType()->getVectorNumElements(); 1323 unsigned Scale = DstNumElts / SrcNumElts; 1324 1325 // Mask off the high bits of the immediate value; hardware ignores those. 1326 Imm = Imm % Scale; 1327 1328 // Extend the second operand into a vector the size of the destination. 1329 Value *UndefV = UndefValue::get(Op1->getType()); 1330 SmallVector<uint32_t, 8> Idxs(DstNumElts); 1331 for (unsigned i = 0; i != SrcNumElts; ++i) 1332 Idxs[i] = i; 1333 for (unsigned i = SrcNumElts; i != DstNumElts; ++i) 1334 Idxs[i] = SrcNumElts; 1335 Rep = Builder.CreateShuffleVector(Op1, UndefV, Idxs); 1336 1337 // Insert the second operand into the first operand. 1338 1339 // Note that there is no guarantee that instruction lowering will actually 1340 // produce a vinsertf128 instruction for the created shuffles. In 1341 // particular, the 0 immediate case involves no lane changes, so it can 1342 // be handled as a blend. 1343 1344 // Example of shuffle mask for 32-bit elements: 1345 // Imm = 1 <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11> 1346 // Imm = 0 <i32 8, i32 9, i32 10, i32 11, i32 4, i32 5, i32 6, i32 7 > 1347 1348 // First fill with identify mask. 1349 for (unsigned i = 0; i != DstNumElts; ++i) 1350 Idxs[i] = i; 1351 // Then replace the elements where we need to insert. 1352 for (unsigned i = 0; i != SrcNumElts; ++i) 1353 Idxs[i + Imm * SrcNumElts] = i + DstNumElts; 1354 Rep = Builder.CreateShuffleVector(Op0, Rep, Idxs); 1355 1356 // If the intrinsic has a mask operand, handle that. 1357 if (CI->getNumArgOperands() == 5) 1358 Rep = EmitX86Select(Builder, CI->getArgOperand(4), Rep, 1359 CI->getArgOperand(3)); 1360 } else if (IsX86 && (Name.startswith("avx.vextractf128.") || 1361 Name == "avx2.vextracti128" || 1362 Name.startswith("avx512.mask.vextract"))) { 1363 Value *Op0 = CI->getArgOperand(0); 1364 unsigned Imm = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue(); 1365 unsigned DstNumElts = CI->getType()->getVectorNumElements(); 1366 unsigned SrcNumElts = Op0->getType()->getVectorNumElements(); 1367 unsigned Scale = SrcNumElts / DstNumElts; 1368 1369 // Mask off the high bits of the immediate value; hardware ignores those. 1370 Imm = Imm % Scale; 1371 1372 // Get indexes for the subvector of the input vector. 1373 SmallVector<uint32_t, 8> Idxs(DstNumElts); 1374 for (unsigned i = 0; i != DstNumElts; ++i) { 1375 Idxs[i] = i + (Imm * DstNumElts); 1376 } 1377 Rep = Builder.CreateShuffleVector(Op0, Op0, Idxs); 1378 1379 // If the intrinsic has a mask operand, handle that. 1380 if (CI->getNumArgOperands() == 4) 1381 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1382 CI->getArgOperand(2)); 1383 } else if (!IsX86 && Name == "stackprotectorcheck") { 1384 Rep = nullptr; 1385 } else if (IsX86 && (Name.startswith("avx512.mask.perm.df.") || 1386 Name.startswith("avx512.mask.perm.di."))) { 1387 Value *Op0 = CI->getArgOperand(0); 1388 unsigned Imm = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue(); 1389 VectorType *VecTy = cast<VectorType>(CI->getType()); 1390 unsigned NumElts = VecTy->getNumElements(); 1391 1392 SmallVector<uint32_t, 8> Idxs(NumElts); 1393 for (unsigned i = 0; i != NumElts; ++i) 1394 Idxs[i] = (i & ~0x3) + ((Imm >> (2 * (i & 0x3))) & 3); 1395 1396 Rep = Builder.CreateShuffleVector(Op0, Op0, Idxs); 1397 1398 if (CI->getNumArgOperands() == 4) 1399 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1400 CI->getArgOperand(2)); 1401 } else if (IsX86 && (Name.startswith("avx.vpermil.") || 1402 Name == "sse2.pshuf.d" || 1403 Name.startswith("avx512.mask.vpermil.p") || 1404 Name.startswith("avx512.mask.pshuf.d."))) { 1405 Value *Op0 = CI->getArgOperand(0); 1406 unsigned Imm = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue(); 1407 VectorType *VecTy = cast<VectorType>(CI->getType()); 1408 unsigned NumElts = VecTy->getNumElements(); 1409 // Calculate the size of each index in the immediate. 1410 unsigned IdxSize = 64 / VecTy->getScalarSizeInBits(); 1411 unsigned IdxMask = ((1 << IdxSize) - 1); 1412 1413 SmallVector<uint32_t, 8> Idxs(NumElts); 1414 // Lookup the bits for this element, wrapping around the immediate every 1415 // 8-bits. Elements are grouped into sets of 2 or 4 elements so we need 1416 // to offset by the first index of each group. 1417 for (unsigned i = 0; i != NumElts; ++i) 1418 Idxs[i] = ((Imm >> ((i * IdxSize) % 8)) & IdxMask) | (i & ~IdxMask); 1419 1420 Rep = Builder.CreateShuffleVector(Op0, Op0, Idxs); 1421 1422 if (CI->getNumArgOperands() == 4) 1423 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1424 CI->getArgOperand(2)); 1425 } else if (IsX86 && (Name == "sse2.pshufl.w" || 1426 Name.startswith("avx512.mask.pshufl.w."))) { 1427 Value *Op0 = CI->getArgOperand(0); 1428 unsigned Imm = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue(); 1429 unsigned NumElts = CI->getType()->getVectorNumElements(); 1430 1431 SmallVector<uint32_t, 16> Idxs(NumElts); 1432 for (unsigned l = 0; l != NumElts; l += 8) { 1433 for (unsigned i = 0; i != 4; ++i) 1434 Idxs[i + l] = ((Imm >> (2 * i)) & 0x3) + l; 1435 for (unsigned i = 4; i != 8; ++i) 1436 Idxs[i + l] = i + l; 1437 } 1438 1439 Rep = Builder.CreateShuffleVector(Op0, Op0, Idxs); 1440 1441 if (CI->getNumArgOperands() == 4) 1442 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1443 CI->getArgOperand(2)); 1444 } else if (IsX86 && (Name == "sse2.pshufh.w" || 1445 Name.startswith("avx512.mask.pshufh.w."))) { 1446 Value *Op0 = CI->getArgOperand(0); 1447 unsigned Imm = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue(); 1448 unsigned NumElts = CI->getType()->getVectorNumElements(); 1449 1450 SmallVector<uint32_t, 16> Idxs(NumElts); 1451 for (unsigned l = 0; l != NumElts; l += 8) { 1452 for (unsigned i = 0; i != 4; ++i) 1453 Idxs[i + l] = i + l; 1454 for (unsigned i = 0; i != 4; ++i) 1455 Idxs[i + l + 4] = ((Imm >> (2 * i)) & 0x3) + 4 + l; 1456 } 1457 1458 Rep = Builder.CreateShuffleVector(Op0, Op0, Idxs); 1459 1460 if (CI->getNumArgOperands() == 4) 1461 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1462 CI->getArgOperand(2)); 1463 } else if (IsX86 && Name.startswith("avx512.mask.shuf.p")) { 1464 Value *Op0 = CI->getArgOperand(0); 1465 Value *Op1 = CI->getArgOperand(1); 1466 unsigned Imm = cast<ConstantInt>(CI->getArgOperand(2))->getZExtValue(); 1467 unsigned NumElts = CI->getType()->getVectorNumElements(); 1468 1469 unsigned NumLaneElts = 128/CI->getType()->getScalarSizeInBits(); 1470 unsigned HalfLaneElts = NumLaneElts / 2; 1471 1472 SmallVector<uint32_t, 16> Idxs(NumElts); 1473 for (unsigned i = 0; i != NumElts; ++i) { 1474 // Base index is the starting element of the lane. 1475 Idxs[i] = i - (i % NumLaneElts); 1476 // If we are half way through the lane switch to the other source. 1477 if ((i % NumLaneElts) >= HalfLaneElts) 1478 Idxs[i] += NumElts; 1479 // Now select the specific element. By adding HalfLaneElts bits from 1480 // the immediate. Wrapping around the immediate every 8-bits. 1481 Idxs[i] += (Imm >> ((i * HalfLaneElts) % 8)) & ((1 << HalfLaneElts) - 1); 1482 } 1483 1484 Rep = Builder.CreateShuffleVector(Op0, Op1, Idxs); 1485 1486 Rep = EmitX86Select(Builder, CI->getArgOperand(4), Rep, 1487 CI->getArgOperand(3)); 1488 } else if (IsX86 && (Name.startswith("avx512.mask.movddup") || 1489 Name.startswith("avx512.mask.movshdup") || 1490 Name.startswith("avx512.mask.movsldup"))) { 1491 Value *Op0 = CI->getArgOperand(0); 1492 unsigned NumElts = CI->getType()->getVectorNumElements(); 1493 unsigned NumLaneElts = 128/CI->getType()->getScalarSizeInBits(); 1494 1495 unsigned Offset = 0; 1496 if (Name.startswith("avx512.mask.movshdup.")) 1497 Offset = 1; 1498 1499 SmallVector<uint32_t, 16> Idxs(NumElts); 1500 for (unsigned l = 0; l != NumElts; l += NumLaneElts) 1501 for (unsigned i = 0; i != NumLaneElts; i += 2) { 1502 Idxs[i + l + 0] = i + l + Offset; 1503 Idxs[i + l + 1] = i + l + Offset; 1504 } 1505 1506 Rep = Builder.CreateShuffleVector(Op0, Op0, Idxs); 1507 1508 Rep = EmitX86Select(Builder, CI->getArgOperand(2), Rep, 1509 CI->getArgOperand(1)); 1510 } else if (IsX86 && (Name.startswith("avx512.mask.punpckl") || 1511 Name.startswith("avx512.mask.unpckl."))) { 1512 Value *Op0 = CI->getArgOperand(0); 1513 Value *Op1 = CI->getArgOperand(1); 1514 int NumElts = CI->getType()->getVectorNumElements(); 1515 int NumLaneElts = 128/CI->getType()->getScalarSizeInBits(); 1516 1517 SmallVector<uint32_t, 64> Idxs(NumElts); 1518 for (int l = 0; l != NumElts; l += NumLaneElts) 1519 for (int i = 0; i != NumLaneElts; ++i) 1520 Idxs[i + l] = l + (i / 2) + NumElts * (i % 2); 1521 1522 Rep = Builder.CreateShuffleVector(Op0, Op1, Idxs); 1523 1524 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1525 CI->getArgOperand(2)); 1526 } else if (IsX86 && (Name.startswith("avx512.mask.punpckh") || 1527 Name.startswith("avx512.mask.unpckh."))) { 1528 Value *Op0 = CI->getArgOperand(0); 1529 Value *Op1 = CI->getArgOperand(1); 1530 int NumElts = CI->getType()->getVectorNumElements(); 1531 int NumLaneElts = 128/CI->getType()->getScalarSizeInBits(); 1532 1533 SmallVector<uint32_t, 64> Idxs(NumElts); 1534 for (int l = 0; l != NumElts; l += NumLaneElts) 1535 for (int i = 0; i != NumLaneElts; ++i) 1536 Idxs[i + l] = (NumLaneElts / 2) + l + (i / 2) + NumElts * (i % 2); 1537 1538 Rep = Builder.CreateShuffleVector(Op0, Op1, Idxs); 1539 1540 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1541 CI->getArgOperand(2)); 1542 } else if (IsX86 && Name.startswith("avx512.mask.pand.")) { 1543 Rep = Builder.CreateAnd(CI->getArgOperand(0), CI->getArgOperand(1)); 1544 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1545 CI->getArgOperand(2)); 1546 } else if (IsX86 && Name.startswith("avx512.mask.pandn.")) { 1547 Rep = Builder.CreateAnd(Builder.CreateNot(CI->getArgOperand(0)), 1548 CI->getArgOperand(1)); 1549 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1550 CI->getArgOperand(2)); 1551 } else if (IsX86 && Name.startswith("avx512.mask.por.")) { 1552 Rep = Builder.CreateOr(CI->getArgOperand(0), CI->getArgOperand(1)); 1553 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1554 CI->getArgOperand(2)); 1555 } else if (IsX86 && Name.startswith("avx512.mask.pxor.")) { 1556 Rep = Builder.CreateXor(CI->getArgOperand(0), CI->getArgOperand(1)); 1557 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1558 CI->getArgOperand(2)); 1559 } else if (IsX86 && Name.startswith("avx512.mask.and.")) { 1560 VectorType *FTy = cast<VectorType>(CI->getType()); 1561 VectorType *ITy = VectorType::getInteger(FTy); 1562 Rep = Builder.CreateAnd(Builder.CreateBitCast(CI->getArgOperand(0), ITy), 1563 Builder.CreateBitCast(CI->getArgOperand(1), ITy)); 1564 Rep = Builder.CreateBitCast(Rep, FTy); 1565 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1566 CI->getArgOperand(2)); 1567 } else if (IsX86 && Name.startswith("avx512.mask.andn.")) { 1568 VectorType *FTy = cast<VectorType>(CI->getType()); 1569 VectorType *ITy = VectorType::getInteger(FTy); 1570 Rep = Builder.CreateNot(Builder.CreateBitCast(CI->getArgOperand(0), ITy)); 1571 Rep = Builder.CreateAnd(Rep, 1572 Builder.CreateBitCast(CI->getArgOperand(1), ITy)); 1573 Rep = Builder.CreateBitCast(Rep, FTy); 1574 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1575 CI->getArgOperand(2)); 1576 } else if (IsX86 && Name.startswith("avx512.mask.or.")) { 1577 VectorType *FTy = cast<VectorType>(CI->getType()); 1578 VectorType *ITy = VectorType::getInteger(FTy); 1579 Rep = Builder.CreateOr(Builder.CreateBitCast(CI->getArgOperand(0), ITy), 1580 Builder.CreateBitCast(CI->getArgOperand(1), ITy)); 1581 Rep = Builder.CreateBitCast(Rep, FTy); 1582 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1583 CI->getArgOperand(2)); 1584 } else if (IsX86 && Name.startswith("avx512.mask.xor.")) { 1585 VectorType *FTy = cast<VectorType>(CI->getType()); 1586 VectorType *ITy = VectorType::getInteger(FTy); 1587 Rep = Builder.CreateXor(Builder.CreateBitCast(CI->getArgOperand(0), ITy), 1588 Builder.CreateBitCast(CI->getArgOperand(1), ITy)); 1589 Rep = Builder.CreateBitCast(Rep, FTy); 1590 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1591 CI->getArgOperand(2)); 1592 } else if (IsX86 && Name.startswith("avx512.mask.padd.")) { 1593 Rep = Builder.CreateAdd(CI->getArgOperand(0), CI->getArgOperand(1)); 1594 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1595 CI->getArgOperand(2)); 1596 } else if (IsX86 && Name.startswith("avx512.mask.psub.")) { 1597 Rep = Builder.CreateSub(CI->getArgOperand(0), CI->getArgOperand(1)); 1598 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1599 CI->getArgOperand(2)); 1600 } else if (IsX86 && Name.startswith("avx512.mask.pmull.")) { 1601 Rep = Builder.CreateMul(CI->getArgOperand(0), CI->getArgOperand(1)); 1602 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1603 CI->getArgOperand(2)); 1604 } else if (IsX86 && (Name.startswith("avx512.mask.add.p"))) { 1605 Rep = Builder.CreateFAdd(CI->getArgOperand(0), CI->getArgOperand(1)); 1606 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1607 CI->getArgOperand(2)); 1608 } else if (IsX86 && Name.startswith("avx512.mask.div.p")) { 1609 Rep = Builder.CreateFDiv(CI->getArgOperand(0), CI->getArgOperand(1)); 1610 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1611 CI->getArgOperand(2)); 1612 } else if (IsX86 && Name.startswith("avx512.mask.mul.p")) { 1613 Rep = Builder.CreateFMul(CI->getArgOperand(0), CI->getArgOperand(1)); 1614 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1615 CI->getArgOperand(2)); 1616 } else if (IsX86 && Name.startswith("avx512.mask.sub.p")) { 1617 Rep = Builder.CreateFSub(CI->getArgOperand(0), CI->getArgOperand(1)); 1618 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1619 CI->getArgOperand(2)); 1620 } else if (IsX86 && Name.startswith("avx512.mask.lzcnt.")) { 1621 Rep = Builder.CreateCall(Intrinsic::getDeclaration(F->getParent(), 1622 Intrinsic::ctlz, 1623 CI->getType()), 1624 { CI->getArgOperand(0), Builder.getInt1(false) }); 1625 Rep = EmitX86Select(Builder, CI->getArgOperand(2), Rep, 1626 CI->getArgOperand(1)); 1627 } else if (IsX86 && (Name.startswith("avx512.mask.max.p") || 1628 Name.startswith("avx512.mask.min.p"))) { 1629 bool IsMin = Name[13] == 'i'; 1630 VectorType *VecTy = cast<VectorType>(CI->getType()); 1631 unsigned VecWidth = VecTy->getPrimitiveSizeInBits(); 1632 unsigned EltWidth = VecTy->getScalarSizeInBits(); 1633 Intrinsic::ID IID; 1634 if (!IsMin && VecWidth == 128 && EltWidth == 32) 1635 IID = Intrinsic::x86_sse_max_ps; 1636 else if (!IsMin && VecWidth == 128 && EltWidth == 64) 1637 IID = Intrinsic::x86_sse2_max_pd; 1638 else if (!IsMin && VecWidth == 256 && EltWidth == 32) 1639 IID = Intrinsic::x86_avx_max_ps_256; 1640 else if (!IsMin && VecWidth == 256 && EltWidth == 64) 1641 IID = Intrinsic::x86_avx_max_pd_256; 1642 else if (IsMin && VecWidth == 128 && EltWidth == 32) 1643 IID = Intrinsic::x86_sse_min_ps; 1644 else if (IsMin && VecWidth == 128 && EltWidth == 64) 1645 IID = Intrinsic::x86_sse2_min_pd; 1646 else if (IsMin && VecWidth == 256 && EltWidth == 32) 1647 IID = Intrinsic::x86_avx_min_ps_256; 1648 else if (IsMin && VecWidth == 256 && EltWidth == 64) 1649 IID = Intrinsic::x86_avx_min_pd_256; 1650 else 1651 llvm_unreachable("Unexpected intrinsic"); 1652 1653 Rep = Builder.CreateCall(Intrinsic::getDeclaration(F->getParent(), IID), 1654 { CI->getArgOperand(0), CI->getArgOperand(1) }); 1655 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1656 CI->getArgOperand(2)); 1657 } else if (IsX86 && Name.startswith("avx512.mask.pshuf.b.")) { 1658 VectorType *VecTy = cast<VectorType>(CI->getType()); 1659 Intrinsic::ID IID; 1660 if (VecTy->getPrimitiveSizeInBits() == 128) 1661 IID = Intrinsic::x86_ssse3_pshuf_b_128; 1662 else if (VecTy->getPrimitiveSizeInBits() == 256) 1663 IID = Intrinsic::x86_avx2_pshuf_b; 1664 else if (VecTy->getPrimitiveSizeInBits() == 512) 1665 IID = Intrinsic::x86_avx512_pshuf_b_512; 1666 else 1667 llvm_unreachable("Unexpected intrinsic"); 1668 1669 Rep = Builder.CreateCall(Intrinsic::getDeclaration(F->getParent(), IID), 1670 { CI->getArgOperand(0), CI->getArgOperand(1) }); 1671 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1672 CI->getArgOperand(2)); 1673 } else if (IsX86 && (Name.startswith("avx512.mask.pmul.dq.") || 1674 Name.startswith("avx512.mask.pmulu.dq."))) { 1675 bool IsUnsigned = Name[16] == 'u'; 1676 VectorType *VecTy = cast<VectorType>(CI->getType()); 1677 Intrinsic::ID IID; 1678 if (!IsUnsigned && VecTy->getPrimitiveSizeInBits() == 128) 1679 IID = Intrinsic::x86_sse41_pmuldq; 1680 else if (!IsUnsigned && VecTy->getPrimitiveSizeInBits() == 256) 1681 IID = Intrinsic::x86_avx2_pmul_dq; 1682 else if (!IsUnsigned && VecTy->getPrimitiveSizeInBits() == 512) 1683 IID = Intrinsic::x86_avx512_pmul_dq_512; 1684 else if (IsUnsigned && VecTy->getPrimitiveSizeInBits() == 128) 1685 IID = Intrinsic::x86_sse2_pmulu_dq; 1686 else if (IsUnsigned && VecTy->getPrimitiveSizeInBits() == 256) 1687 IID = Intrinsic::x86_avx2_pmulu_dq; 1688 else if (IsUnsigned && VecTy->getPrimitiveSizeInBits() == 512) 1689 IID = Intrinsic::x86_avx512_pmulu_dq_512; 1690 else 1691 llvm_unreachable("Unexpected intrinsic"); 1692 1693 Rep = Builder.CreateCall(Intrinsic::getDeclaration(F->getParent(), IID), 1694 { CI->getArgOperand(0), CI->getArgOperand(1) }); 1695 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1696 CI->getArgOperand(2)); 1697 } else if (IsX86 && Name.startswith("avx512.mask.pack")) { 1698 bool IsUnsigned = Name[16] == 'u'; 1699 bool IsDW = Name[18] == 'd'; 1700 VectorType *VecTy = cast<VectorType>(CI->getType()); 1701 Intrinsic::ID IID; 1702 if (!IsUnsigned && !IsDW && VecTy->getPrimitiveSizeInBits() == 128) 1703 IID = Intrinsic::x86_sse2_packsswb_128; 1704 else if (!IsUnsigned && !IsDW && VecTy->getPrimitiveSizeInBits() == 256) 1705 IID = Intrinsic::x86_avx2_packsswb; 1706 else if (!IsUnsigned && !IsDW && VecTy->getPrimitiveSizeInBits() == 512) 1707 IID = Intrinsic::x86_avx512_packsswb_512; 1708 else if (!IsUnsigned && IsDW && VecTy->getPrimitiveSizeInBits() == 128) 1709 IID = Intrinsic::x86_sse2_packssdw_128; 1710 else if (!IsUnsigned && IsDW && VecTy->getPrimitiveSizeInBits() == 256) 1711 IID = Intrinsic::x86_avx2_packssdw; 1712 else if (!IsUnsigned && IsDW && VecTy->getPrimitiveSizeInBits() == 512) 1713 IID = Intrinsic::x86_avx512_packssdw_512; 1714 else if (IsUnsigned && !IsDW && VecTy->getPrimitiveSizeInBits() == 128) 1715 IID = Intrinsic::x86_sse2_packuswb_128; 1716 else if (IsUnsigned && !IsDW && VecTy->getPrimitiveSizeInBits() == 256) 1717 IID = Intrinsic::x86_avx2_packuswb; 1718 else if (IsUnsigned && !IsDW && VecTy->getPrimitiveSizeInBits() == 512) 1719 IID = Intrinsic::x86_avx512_packuswb_512; 1720 else if (IsUnsigned && IsDW && VecTy->getPrimitiveSizeInBits() == 128) 1721 IID = Intrinsic::x86_sse41_packusdw; 1722 else if (IsUnsigned && IsDW && VecTy->getPrimitiveSizeInBits() == 256) 1723 IID = Intrinsic::x86_avx2_packusdw; 1724 else if (IsUnsigned && IsDW && VecTy->getPrimitiveSizeInBits() == 512) 1725 IID = Intrinsic::x86_avx512_packusdw_512; 1726 else 1727 llvm_unreachable("Unexpected intrinsic"); 1728 1729 Rep = Builder.CreateCall(Intrinsic::getDeclaration(F->getParent(), IID), 1730 { CI->getArgOperand(0), CI->getArgOperand(1) }); 1731 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1732 CI->getArgOperand(2)); 1733 } else if (IsX86 && Name.startswith("avx512.mask.psll")) { 1734 bool IsImmediate = Name[16] == 'i' || 1735 (Name.size() > 18 && Name[18] == 'i'); 1736 bool IsVariable = Name[16] == 'v'; 1737 char Size = Name[16] == '.' ? Name[17] : 1738 Name[17] == '.' ? Name[18] : 1739 Name[18] == '.' ? Name[19] : 1740 Name[20]; 1741 1742 Intrinsic::ID IID; 1743 if (IsVariable && Name[17] != '.') { 1744 if (Size == 'd' && Name[17] == '2') // avx512.mask.psllv2.di 1745 IID = Intrinsic::x86_avx2_psllv_q; 1746 else if (Size == 'd' && Name[17] == '4') // avx512.mask.psllv4.di 1747 IID = Intrinsic::x86_avx2_psllv_q_256; 1748 else if (Size == 's' && Name[17] == '4') // avx512.mask.psllv4.si 1749 IID = Intrinsic::x86_avx2_psllv_d; 1750 else if (Size == 's' && Name[17] == '8') // avx512.mask.psllv8.si 1751 IID = Intrinsic::x86_avx2_psllv_d_256; 1752 else if (Size == 'h' && Name[17] == '8') // avx512.mask.psllv8.hi 1753 IID = Intrinsic::x86_avx512_psllv_w_128; 1754 else if (Size == 'h' && Name[17] == '1') // avx512.mask.psllv16.hi 1755 IID = Intrinsic::x86_avx512_psllv_w_256; 1756 else if (Name[17] == '3' && Name[18] == '2') // avx512.mask.psllv32hi 1757 IID = Intrinsic::x86_avx512_psllv_w_512; 1758 else 1759 llvm_unreachable("Unexpected size"); 1760 } else if (Name.endswith(".128")) { 1761 if (Size == 'd') // avx512.mask.psll.d.128, avx512.mask.psll.di.128 1762 IID = IsImmediate ? Intrinsic::x86_sse2_pslli_d 1763 : Intrinsic::x86_sse2_psll_d; 1764 else if (Size == 'q') // avx512.mask.psll.q.128, avx512.mask.psll.qi.128 1765 IID = IsImmediate ? Intrinsic::x86_sse2_pslli_q 1766 : Intrinsic::x86_sse2_psll_q; 1767 else if (Size == 'w') // avx512.mask.psll.w.128, avx512.mask.psll.wi.128 1768 IID = IsImmediate ? Intrinsic::x86_sse2_pslli_w 1769 : Intrinsic::x86_sse2_psll_w; 1770 else 1771 llvm_unreachable("Unexpected size"); 1772 } else if (Name.endswith(".256")) { 1773 if (Size == 'd') // avx512.mask.psll.d.256, avx512.mask.psll.di.256 1774 IID = IsImmediate ? Intrinsic::x86_avx2_pslli_d 1775 : Intrinsic::x86_avx2_psll_d; 1776 else if (Size == 'q') // avx512.mask.psll.q.256, avx512.mask.psll.qi.256 1777 IID = IsImmediate ? Intrinsic::x86_avx2_pslli_q 1778 : Intrinsic::x86_avx2_psll_q; 1779 else if (Size == 'w') // avx512.mask.psll.w.256, avx512.mask.psll.wi.256 1780 IID = IsImmediate ? Intrinsic::x86_avx2_pslli_w 1781 : Intrinsic::x86_avx2_psll_w; 1782 else 1783 llvm_unreachable("Unexpected size"); 1784 } else { 1785 if (Size == 'd') // psll.di.512, pslli.d, psll.d, psllv.d.512 1786 IID = IsImmediate ? Intrinsic::x86_avx512_pslli_d_512 : 1787 IsVariable ? Intrinsic::x86_avx512_psllv_d_512 : 1788 Intrinsic::x86_avx512_psll_d_512; 1789 else if (Size == 'q') // psll.qi.512, pslli.q, psll.q, psllv.q.512 1790 IID = IsImmediate ? Intrinsic::x86_avx512_pslli_q_512 : 1791 IsVariable ? Intrinsic::x86_avx512_psllv_q_512 : 1792 Intrinsic::x86_avx512_psll_q_512; 1793 else if (Size == 'w') // psll.wi.512, pslli.w, psll.w 1794 IID = IsImmediate ? Intrinsic::x86_avx512_pslli_w_512 1795 : Intrinsic::x86_avx512_psll_w_512; 1796 else 1797 llvm_unreachable("Unexpected size"); 1798 } 1799 1800 Rep = UpgradeX86MaskedShift(Builder, *CI, IID); 1801 } else if (IsX86 && Name.startswith("avx512.mask.psrl")) { 1802 bool IsImmediate = Name[16] == 'i' || 1803 (Name.size() > 18 && Name[18] == 'i'); 1804 bool IsVariable = Name[16] == 'v'; 1805 char Size = Name[16] == '.' ? Name[17] : 1806 Name[17] == '.' ? Name[18] : 1807 Name[18] == '.' ? Name[19] : 1808 Name[20]; 1809 1810 Intrinsic::ID IID; 1811 if (IsVariable && Name[17] != '.') { 1812 if (Size == 'd' && Name[17] == '2') // avx512.mask.psrlv2.di 1813 IID = Intrinsic::x86_avx2_psrlv_q; 1814 else if (Size == 'd' && Name[17] == '4') // avx512.mask.psrlv4.di 1815 IID = Intrinsic::x86_avx2_psrlv_q_256; 1816 else if (Size == 's' && Name[17] == '4') // avx512.mask.psrlv4.si 1817 IID = Intrinsic::x86_avx2_psrlv_d; 1818 else if (Size == 's' && Name[17] == '8') // avx512.mask.psrlv8.si 1819 IID = Intrinsic::x86_avx2_psrlv_d_256; 1820 else if (Size == 'h' && Name[17] == '8') // avx512.mask.psrlv8.hi 1821 IID = Intrinsic::x86_avx512_psrlv_w_128; 1822 else if (Size == 'h' && Name[17] == '1') // avx512.mask.psrlv16.hi 1823 IID = Intrinsic::x86_avx512_psrlv_w_256; 1824 else if (Name[17] == '3' && Name[18] == '2') // avx512.mask.psrlv32hi 1825 IID = Intrinsic::x86_avx512_psrlv_w_512; 1826 else 1827 llvm_unreachable("Unexpected size"); 1828 } else if (Name.endswith(".128")) { 1829 if (Size == 'd') // avx512.mask.psrl.d.128, avx512.mask.psrl.di.128 1830 IID = IsImmediate ? Intrinsic::x86_sse2_psrli_d 1831 : Intrinsic::x86_sse2_psrl_d; 1832 else if (Size == 'q') // avx512.mask.psrl.q.128, avx512.mask.psrl.qi.128 1833 IID = IsImmediate ? Intrinsic::x86_sse2_psrli_q 1834 : Intrinsic::x86_sse2_psrl_q; 1835 else if (Size == 'w') // avx512.mask.psrl.w.128, avx512.mask.psrl.wi.128 1836 IID = IsImmediate ? Intrinsic::x86_sse2_psrli_w 1837 : Intrinsic::x86_sse2_psrl_w; 1838 else 1839 llvm_unreachable("Unexpected size"); 1840 } else if (Name.endswith(".256")) { 1841 if (Size == 'd') // avx512.mask.psrl.d.256, avx512.mask.psrl.di.256 1842 IID = IsImmediate ? Intrinsic::x86_avx2_psrli_d 1843 : Intrinsic::x86_avx2_psrl_d; 1844 else if (Size == 'q') // avx512.mask.psrl.q.256, avx512.mask.psrl.qi.256 1845 IID = IsImmediate ? Intrinsic::x86_avx2_psrli_q 1846 : Intrinsic::x86_avx2_psrl_q; 1847 else if (Size == 'w') // avx512.mask.psrl.w.256, avx512.mask.psrl.wi.256 1848 IID = IsImmediate ? Intrinsic::x86_avx2_psrli_w 1849 : Intrinsic::x86_avx2_psrl_w; 1850 else 1851 llvm_unreachable("Unexpected size"); 1852 } else { 1853 if (Size == 'd') // psrl.di.512, psrli.d, psrl.d, psrl.d.512 1854 IID = IsImmediate ? Intrinsic::x86_avx512_psrli_d_512 : 1855 IsVariable ? Intrinsic::x86_avx512_psrlv_d_512 : 1856 Intrinsic::x86_avx512_psrl_d_512; 1857 else if (Size == 'q') // psrl.qi.512, psrli.q, psrl.q, psrl.q.512 1858 IID = IsImmediate ? Intrinsic::x86_avx512_psrli_q_512 : 1859 IsVariable ? Intrinsic::x86_avx512_psrlv_q_512 : 1860 Intrinsic::x86_avx512_psrl_q_512; 1861 else if (Size == 'w') // psrl.wi.512, psrli.w, psrl.w) 1862 IID = IsImmediate ? Intrinsic::x86_avx512_psrli_w_512 1863 : Intrinsic::x86_avx512_psrl_w_512; 1864 else 1865 llvm_unreachable("Unexpected size"); 1866 } 1867 1868 Rep = UpgradeX86MaskedShift(Builder, *CI, IID); 1869 } else if (IsX86 && Name.startswith("avx512.mask.psra")) { 1870 bool IsImmediate = Name[16] == 'i' || 1871 (Name.size() > 18 && Name[18] == 'i'); 1872 bool IsVariable = Name[16] == 'v'; 1873 char Size = Name[16] == '.' ? Name[17] : 1874 Name[17] == '.' ? Name[18] : 1875 Name[18] == '.' ? Name[19] : 1876 Name[20]; 1877 1878 Intrinsic::ID IID; 1879 if (IsVariable && Name[17] != '.') { 1880 if (Size == 's' && Name[17] == '4') // avx512.mask.psrav4.si 1881 IID = Intrinsic::x86_avx2_psrav_d; 1882 else if (Size == 's' && Name[17] == '8') // avx512.mask.psrav8.si 1883 IID = Intrinsic::x86_avx2_psrav_d_256; 1884 else if (Size == 'h' && Name[17] == '8') // avx512.mask.psrav8.hi 1885 IID = Intrinsic::x86_avx512_psrav_w_128; 1886 else if (Size == 'h' && Name[17] == '1') // avx512.mask.psrav16.hi 1887 IID = Intrinsic::x86_avx512_psrav_w_256; 1888 else if (Name[17] == '3' && Name[18] == '2') // avx512.mask.psrav32hi 1889 IID = Intrinsic::x86_avx512_psrav_w_512; 1890 else 1891 llvm_unreachable("Unexpected size"); 1892 } else if (Name.endswith(".128")) { 1893 if (Size == 'd') // avx512.mask.psra.d.128, avx512.mask.psra.di.128 1894 IID = IsImmediate ? Intrinsic::x86_sse2_psrai_d 1895 : Intrinsic::x86_sse2_psra_d; 1896 else if (Size == 'q') // avx512.mask.psra.q.128, avx512.mask.psra.qi.128 1897 IID = IsImmediate ? Intrinsic::x86_avx512_psrai_q_128 : 1898 IsVariable ? Intrinsic::x86_avx512_psrav_q_128 : 1899 Intrinsic::x86_avx512_psra_q_128; 1900 else if (Size == 'w') // avx512.mask.psra.w.128, avx512.mask.psra.wi.128 1901 IID = IsImmediate ? Intrinsic::x86_sse2_psrai_w 1902 : Intrinsic::x86_sse2_psra_w; 1903 else 1904 llvm_unreachable("Unexpected size"); 1905 } else if (Name.endswith(".256")) { 1906 if (Size == 'd') // avx512.mask.psra.d.256, avx512.mask.psra.di.256 1907 IID = IsImmediate ? Intrinsic::x86_avx2_psrai_d 1908 : Intrinsic::x86_avx2_psra_d; 1909 else if (Size == 'q') // avx512.mask.psra.q.256, avx512.mask.psra.qi.256 1910 IID = IsImmediate ? Intrinsic::x86_avx512_psrai_q_256 : 1911 IsVariable ? Intrinsic::x86_avx512_psrav_q_256 : 1912 Intrinsic::x86_avx512_psra_q_256; 1913 else if (Size == 'w') // avx512.mask.psra.w.256, avx512.mask.psra.wi.256 1914 IID = IsImmediate ? Intrinsic::x86_avx2_psrai_w 1915 : Intrinsic::x86_avx2_psra_w; 1916 else 1917 llvm_unreachable("Unexpected size"); 1918 } else { 1919 if (Size == 'd') // psra.di.512, psrai.d, psra.d, psrav.d.512 1920 IID = IsImmediate ? Intrinsic::x86_avx512_psrai_d_512 : 1921 IsVariable ? Intrinsic::x86_avx512_psrav_d_512 : 1922 Intrinsic::x86_avx512_psra_d_512; 1923 else if (Size == 'q') // psra.qi.512, psrai.q, psra.q 1924 IID = IsImmediate ? Intrinsic::x86_avx512_psrai_q_512 : 1925 IsVariable ? Intrinsic::x86_avx512_psrav_q_512 : 1926 Intrinsic::x86_avx512_psra_q_512; 1927 else if (Size == 'w') // psra.wi.512, psrai.w, psra.w 1928 IID = IsImmediate ? Intrinsic::x86_avx512_psrai_w_512 1929 : Intrinsic::x86_avx512_psra_w_512; 1930 else 1931 llvm_unreachable("Unexpected size"); 1932 } 1933 1934 Rep = UpgradeX86MaskedShift(Builder, *CI, IID); 1935 } else if (IsX86 && Name.startswith("avx512.mask.move.s")) { 1936 Rep = upgradeMaskedMove(Builder, *CI); 1937 } else if (IsX86 && Name.startswith("avx512.cvtmask2")) { 1938 Rep = UpgradeMaskToInt(Builder, *CI); 1939 } else if (IsX86 && Name.startswith("avx512.mask.vpermilvar.")) { 1940 Intrinsic::ID IID; 1941 if (Name.endswith("ps.128")) 1942 IID = Intrinsic::x86_avx_vpermilvar_ps; 1943 else if (Name.endswith("pd.128")) 1944 IID = Intrinsic::x86_avx_vpermilvar_pd; 1945 else if (Name.endswith("ps.256")) 1946 IID = Intrinsic::x86_avx_vpermilvar_ps_256; 1947 else if (Name.endswith("pd.256")) 1948 IID = Intrinsic::x86_avx_vpermilvar_pd_256; 1949 else if (Name.endswith("ps.512")) 1950 IID = Intrinsic::x86_avx512_vpermilvar_ps_512; 1951 else if (Name.endswith("pd.512")) 1952 IID = Intrinsic::x86_avx512_vpermilvar_pd_512; 1953 else 1954 llvm_unreachable("Unexpected vpermilvar intrinsic"); 1955 1956 Function *Intrin = Intrinsic::getDeclaration(F->getParent(), IID); 1957 Rep = Builder.CreateCall(Intrin, 1958 { CI->getArgOperand(0), CI->getArgOperand(1) }); 1959 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1960 CI->getArgOperand(2)); 1961 } else if (IsX86 && Name.endswith(".movntdqa")) { 1962 Module *M = F->getParent(); 1963 MDNode *Node = MDNode::get( 1964 C, ConstantAsMetadata::get(ConstantInt::get(Type::getInt32Ty(C), 1))); 1965 1966 Value *Ptr = CI->getArgOperand(0); 1967 VectorType *VTy = cast<VectorType>(CI->getType()); 1968 1969 // Convert the type of the pointer to a pointer to the stored type. 1970 Value *BC = 1971 Builder.CreateBitCast(Ptr, PointerType::getUnqual(VTy), "cast"); 1972 LoadInst *LI = Builder.CreateAlignedLoad(BC, VTy->getBitWidth() / 8); 1973 LI->setMetadata(M->getMDKindID("nontemporal"), Node); 1974 Rep = LI; 1975 } else if (IsNVVM && (Name == "abs.i" || Name == "abs.ll")) { 1976 Value *Arg = CI->getArgOperand(0); 1977 Value *Neg = Builder.CreateNeg(Arg, "neg"); 1978 Value *Cmp = Builder.CreateICmpSGE( 1979 Arg, llvm::Constant::getNullValue(Arg->getType()), "abs.cond"); 1980 Rep = Builder.CreateSelect(Cmp, Arg, Neg, "abs"); 1981 } else if (IsNVVM && (Name == "max.i" || Name == "max.ll" || 1982 Name == "max.ui" || Name == "max.ull")) { 1983 Value *Arg0 = CI->getArgOperand(0); 1984 Value *Arg1 = CI->getArgOperand(1); 1985 Value *Cmp = Name.endswith(".ui") || Name.endswith(".ull") 1986 ? Builder.CreateICmpUGE(Arg0, Arg1, "max.cond") 1987 : Builder.CreateICmpSGE(Arg0, Arg1, "max.cond"); 1988 Rep = Builder.CreateSelect(Cmp, Arg0, Arg1, "max"); 1989 } else if (IsNVVM && (Name == "min.i" || Name == "min.ll" || 1990 Name == "min.ui" || Name == "min.ull")) { 1991 Value *Arg0 = CI->getArgOperand(0); 1992 Value *Arg1 = CI->getArgOperand(1); 1993 Value *Cmp = Name.endswith(".ui") || Name.endswith(".ull") 1994 ? Builder.CreateICmpULE(Arg0, Arg1, "min.cond") 1995 : Builder.CreateICmpSLE(Arg0, Arg1, "min.cond"); 1996 Rep = Builder.CreateSelect(Cmp, Arg0, Arg1, "min"); 1997 } else if (IsNVVM && Name == "clz.ll") { 1998 // llvm.nvvm.clz.ll returns an i32, but llvm.ctlz.i64 and returns an i64. 1999 Value *Arg = CI->getArgOperand(0); 2000 Value *Ctlz = Builder.CreateCall( 2001 Intrinsic::getDeclaration(F->getParent(), Intrinsic::ctlz, 2002 {Arg->getType()}), 2003 {Arg, Builder.getFalse()}, "ctlz"); 2004 Rep = Builder.CreateTrunc(Ctlz, Builder.getInt32Ty(), "ctlz.trunc"); 2005 } else if (IsNVVM && Name == "popc.ll") { 2006 // llvm.nvvm.popc.ll returns an i32, but llvm.ctpop.i64 and returns an 2007 // i64. 2008 Value *Arg = CI->getArgOperand(0); 2009 Value *Popc = Builder.CreateCall( 2010 Intrinsic::getDeclaration(F->getParent(), Intrinsic::ctpop, 2011 {Arg->getType()}), 2012 Arg, "ctpop"); 2013 Rep = Builder.CreateTrunc(Popc, Builder.getInt32Ty(), "ctpop.trunc"); 2014 } else if (IsNVVM && Name == "h2f") { 2015 Rep = Builder.CreateCall(Intrinsic::getDeclaration( 2016 F->getParent(), Intrinsic::convert_from_fp16, 2017 {Builder.getFloatTy()}), 2018 CI->getArgOperand(0), "h2f"); 2019 } else { 2020 llvm_unreachable("Unknown function for CallInst upgrade."); 2021 } 2022 2023 if (Rep) 2024 CI->replaceAllUsesWith(Rep); 2025 CI->eraseFromParent(); 2026 return; 2027 } 2028 2029 CallInst *NewCall = nullptr; 2030 switch (NewFn->getIntrinsicID()) { 2031 default: { 2032 // Handle generic mangling change, but nothing else 2033 assert( 2034 (CI->getCalledFunction()->getName() != NewFn->getName()) && 2035 "Unknown function for CallInst upgrade and isn't just a name change"); 2036 CI->setCalledFunction(NewFn); 2037 return; 2038 } 2039 2040 case Intrinsic::arm_neon_vld1: 2041 case Intrinsic::arm_neon_vld2: 2042 case Intrinsic::arm_neon_vld3: 2043 case Intrinsic::arm_neon_vld4: 2044 case Intrinsic::arm_neon_vld2lane: 2045 case Intrinsic::arm_neon_vld3lane: 2046 case Intrinsic::arm_neon_vld4lane: 2047 case Intrinsic::arm_neon_vst1: 2048 case Intrinsic::arm_neon_vst2: 2049 case Intrinsic::arm_neon_vst3: 2050 case Intrinsic::arm_neon_vst4: 2051 case Intrinsic::arm_neon_vst2lane: 2052 case Intrinsic::arm_neon_vst3lane: 2053 case Intrinsic::arm_neon_vst4lane: { 2054 SmallVector<Value *, 4> Args(CI->arg_operands().begin(), 2055 CI->arg_operands().end()); 2056 NewCall = Builder.CreateCall(NewFn, Args); 2057 break; 2058 } 2059 2060 case Intrinsic::bitreverse: 2061 NewCall = Builder.CreateCall(NewFn, {CI->getArgOperand(0)}); 2062 break; 2063 2064 case Intrinsic::ctlz: 2065 case Intrinsic::cttz: 2066 assert(CI->getNumArgOperands() == 1 && 2067 "Mismatch between function args and call args"); 2068 NewCall = 2069 Builder.CreateCall(NewFn, {CI->getArgOperand(0), Builder.getFalse()}); 2070 break; 2071 2072 case Intrinsic::objectsize: { 2073 Value *NullIsUnknownSize = CI->getNumArgOperands() == 2 2074 ? Builder.getFalse() 2075 : CI->getArgOperand(2); 2076 NewCall = Builder.CreateCall( 2077 NewFn, {CI->getArgOperand(0), CI->getArgOperand(1), NullIsUnknownSize}); 2078 break; 2079 } 2080 2081 case Intrinsic::ctpop: 2082 NewCall = Builder.CreateCall(NewFn, {CI->getArgOperand(0)}); 2083 break; 2084 2085 case Intrinsic::convert_from_fp16: 2086 NewCall = Builder.CreateCall(NewFn, {CI->getArgOperand(0)}); 2087 break; 2088 2089 case Intrinsic::dbg_value: 2090 // Upgrade from the old version that had an extra offset argument. 2091 assert(CI->getNumArgOperands() == 4); 2092 // Drop nonzero offsets instead of attempting to upgrade them. 2093 if (auto *Offset = dyn_cast_or_null<Constant>(CI->getArgOperand(1))) 2094 if (Offset->isZeroValue()) { 2095 NewCall = Builder.CreateCall( 2096 NewFn, 2097 {CI->getArgOperand(0), CI->getArgOperand(2), CI->getArgOperand(3)}); 2098 break; 2099 } 2100 CI->eraseFromParent(); 2101 return; 2102 2103 case Intrinsic::x86_xop_vfrcz_ss: 2104 case Intrinsic::x86_xop_vfrcz_sd: 2105 NewCall = Builder.CreateCall(NewFn, {CI->getArgOperand(1)}); 2106 break; 2107 2108 case Intrinsic::x86_xop_vpermil2pd: 2109 case Intrinsic::x86_xop_vpermil2ps: 2110 case Intrinsic::x86_xop_vpermil2pd_256: 2111 case Intrinsic::x86_xop_vpermil2ps_256: { 2112 SmallVector<Value *, 4> Args(CI->arg_operands().begin(), 2113 CI->arg_operands().end()); 2114 VectorType *FltIdxTy = cast<VectorType>(Args[2]->getType()); 2115 VectorType *IntIdxTy = VectorType::getInteger(FltIdxTy); 2116 Args[2] = Builder.CreateBitCast(Args[2], IntIdxTy); 2117 NewCall = Builder.CreateCall(NewFn, Args); 2118 break; 2119 } 2120 2121 case Intrinsic::x86_sse41_ptestc: 2122 case Intrinsic::x86_sse41_ptestz: 2123 case Intrinsic::x86_sse41_ptestnzc: { 2124 // The arguments for these intrinsics used to be v4f32, and changed 2125 // to v2i64. This is purely a nop, since those are bitwise intrinsics. 2126 // So, the only thing required is a bitcast for both arguments. 2127 // First, check the arguments have the old type. 2128 Value *Arg0 = CI->getArgOperand(0); 2129 if (Arg0->getType() != VectorType::get(Type::getFloatTy(C), 4)) 2130 return; 2131 2132 // Old intrinsic, add bitcasts 2133 Value *Arg1 = CI->getArgOperand(1); 2134 2135 Type *NewVecTy = VectorType::get(Type::getInt64Ty(C), 2); 2136 2137 Value *BC0 = Builder.CreateBitCast(Arg0, NewVecTy, "cast"); 2138 Value *BC1 = Builder.CreateBitCast(Arg1, NewVecTy, "cast"); 2139 2140 NewCall = Builder.CreateCall(NewFn, {BC0, BC1}); 2141 break; 2142 } 2143 2144 case Intrinsic::x86_sse41_insertps: 2145 case Intrinsic::x86_sse41_dppd: 2146 case Intrinsic::x86_sse41_dpps: 2147 case Intrinsic::x86_sse41_mpsadbw: 2148 case Intrinsic::x86_avx_dp_ps_256: 2149 case Intrinsic::x86_avx2_mpsadbw: { 2150 // Need to truncate the last argument from i32 to i8 -- this argument models 2151 // an inherently 8-bit immediate operand to these x86 instructions. 2152 SmallVector<Value *, 4> Args(CI->arg_operands().begin(), 2153 CI->arg_operands().end()); 2154 2155 // Replace the last argument with a trunc. 2156 Args.back() = Builder.CreateTrunc(Args.back(), Type::getInt8Ty(C), "trunc"); 2157 NewCall = Builder.CreateCall(NewFn, Args); 2158 break; 2159 } 2160 2161 case Intrinsic::thread_pointer: { 2162 NewCall = Builder.CreateCall(NewFn, {}); 2163 break; 2164 } 2165 2166 case Intrinsic::invariant_start: 2167 case Intrinsic::invariant_end: 2168 case Intrinsic::masked_load: 2169 case Intrinsic::masked_store: 2170 case Intrinsic::masked_gather: 2171 case Intrinsic::masked_scatter: { 2172 SmallVector<Value *, 4> Args(CI->arg_operands().begin(), 2173 CI->arg_operands().end()); 2174 NewCall = Builder.CreateCall(NewFn, Args); 2175 break; 2176 } 2177 } 2178 assert(NewCall && "Should have either set this variable or returned through " 2179 "the default case"); 2180 std::string Name = CI->getName(); 2181 if (!Name.empty()) { 2182 CI->setName(Name + ".old"); 2183 NewCall->setName(Name); 2184 } 2185 CI->replaceAllUsesWith(NewCall); 2186 CI->eraseFromParent(); 2187 } 2188 2189 void llvm::UpgradeCallsToIntrinsic(Function *F) { 2190 assert(F && "Illegal attempt to upgrade a non-existent intrinsic."); 2191 2192 // Check if this function should be upgraded and get the replacement function 2193 // if there is one. 2194 Function *NewFn; 2195 if (UpgradeIntrinsicFunction(F, NewFn)) { 2196 // Replace all users of the old function with the new function or new 2197 // instructions. This is not a range loop because the call is deleted. 2198 for (auto UI = F->user_begin(), UE = F->user_end(); UI != UE; ) 2199 if (CallInst *CI = dyn_cast<CallInst>(*UI++)) 2200 UpgradeIntrinsicCall(CI, NewFn); 2201 2202 // Remove old function, no longer used, from the module. 2203 F->eraseFromParent(); 2204 } 2205 } 2206 2207 MDNode *llvm::UpgradeTBAANode(MDNode &MD) { 2208 // Check if the tag uses struct-path aware TBAA format. 2209 if (isa<MDNode>(MD.getOperand(0)) && MD.getNumOperands() >= 3) 2210 return &MD; 2211 2212 auto &Context = MD.getContext(); 2213 if (MD.getNumOperands() == 3) { 2214 Metadata *Elts[] = {MD.getOperand(0), MD.getOperand(1)}; 2215 MDNode *ScalarType = MDNode::get(Context, Elts); 2216 // Create a MDNode <ScalarType, ScalarType, offset 0, const> 2217 Metadata *Elts2[] = {ScalarType, ScalarType, 2218 ConstantAsMetadata::get( 2219 Constant::getNullValue(Type::getInt64Ty(Context))), 2220 MD.getOperand(2)}; 2221 return MDNode::get(Context, Elts2); 2222 } 2223 // Create a MDNode <MD, MD, offset 0> 2224 Metadata *Elts[] = {&MD, &MD, ConstantAsMetadata::get(Constant::getNullValue( 2225 Type::getInt64Ty(Context)))}; 2226 return MDNode::get(Context, Elts); 2227 } 2228 2229 Instruction *llvm::UpgradeBitCastInst(unsigned Opc, Value *V, Type *DestTy, 2230 Instruction *&Temp) { 2231 if (Opc != Instruction::BitCast) 2232 return nullptr; 2233 2234 Temp = nullptr; 2235 Type *SrcTy = V->getType(); 2236 if (SrcTy->isPtrOrPtrVectorTy() && DestTy->isPtrOrPtrVectorTy() && 2237 SrcTy->getPointerAddressSpace() != DestTy->getPointerAddressSpace()) { 2238 LLVMContext &Context = V->getContext(); 2239 2240 // We have no information about target data layout, so we assume that 2241 // the maximum pointer size is 64bit. 2242 Type *MidTy = Type::getInt64Ty(Context); 2243 Temp = CastInst::Create(Instruction::PtrToInt, V, MidTy); 2244 2245 return CastInst::Create(Instruction::IntToPtr, Temp, DestTy); 2246 } 2247 2248 return nullptr; 2249 } 2250 2251 Value *llvm::UpgradeBitCastExpr(unsigned Opc, Constant *C, Type *DestTy) { 2252 if (Opc != Instruction::BitCast) 2253 return nullptr; 2254 2255 Type *SrcTy = C->getType(); 2256 if (SrcTy->isPtrOrPtrVectorTy() && DestTy->isPtrOrPtrVectorTy() && 2257 SrcTy->getPointerAddressSpace() != DestTy->getPointerAddressSpace()) { 2258 LLVMContext &Context = C->getContext(); 2259 2260 // We have no information about target data layout, so we assume that 2261 // the maximum pointer size is 64bit. 2262 Type *MidTy = Type::getInt64Ty(Context); 2263 2264 return ConstantExpr::getIntToPtr(ConstantExpr::getPtrToInt(C, MidTy), 2265 DestTy); 2266 } 2267 2268 return nullptr; 2269 } 2270 2271 /// Check the debug info version number, if it is out-dated, drop the debug 2272 /// info. Return true if module is modified. 2273 bool llvm::UpgradeDebugInfo(Module &M) { 2274 unsigned Version = getDebugMetadataVersionFromModule(M); 2275 if (Version == DEBUG_METADATA_VERSION) 2276 return false; 2277 2278 bool RetCode = StripDebugInfo(M); 2279 if (RetCode) { 2280 DiagnosticInfoDebugMetadataVersion DiagVersion(M, Version); 2281 M.getContext().diagnose(DiagVersion); 2282 } 2283 return RetCode; 2284 } 2285 2286 bool llvm::UpgradeModuleFlags(Module &M) { 2287 NamedMDNode *ModFlags = M.getModuleFlagsMetadata(); 2288 if (!ModFlags) 2289 return false; 2290 2291 bool HasObjCFlag = false, HasClassProperties = false, Changed = false; 2292 for (unsigned I = 0, E = ModFlags->getNumOperands(); I != E; ++I) { 2293 MDNode *Op = ModFlags->getOperand(I); 2294 if (Op->getNumOperands() != 3) 2295 continue; 2296 MDString *ID = dyn_cast_or_null<MDString>(Op->getOperand(1)); 2297 if (!ID) 2298 continue; 2299 if (ID->getString() == "Objective-C Image Info Version") 2300 HasObjCFlag = true; 2301 if (ID->getString() == "Objective-C Class Properties") 2302 HasClassProperties = true; 2303 // Upgrade PIC/PIE Module Flags. The module flag behavior for these two 2304 // field was Error and now they are Max. 2305 if (ID->getString() == "PIC Level" || ID->getString() == "PIE Level") { 2306 if (auto *Behavior = 2307 mdconst::dyn_extract_or_null<ConstantInt>(Op->getOperand(0))) { 2308 if (Behavior->getLimitedValue() == Module::Error) { 2309 Type *Int32Ty = Type::getInt32Ty(M.getContext()); 2310 Metadata *Ops[3] = { 2311 ConstantAsMetadata::get(ConstantInt::get(Int32Ty, Module::Max)), 2312 MDString::get(M.getContext(), ID->getString()), 2313 Op->getOperand(2)}; 2314 ModFlags->setOperand(I, MDNode::get(M.getContext(), Ops)); 2315 Changed = true; 2316 } 2317 } 2318 } 2319 } 2320 2321 // "Objective-C Class Properties" is recently added for Objective-C. We 2322 // upgrade ObjC bitcodes to contain a "Objective-C Class Properties" module 2323 // flag of value 0, so we can correclty downgrade this flag when trying to 2324 // link an ObjC bitcode without this module flag with an ObjC bitcode with 2325 // this module flag. 2326 if (HasObjCFlag && !HasClassProperties) { 2327 M.addModuleFlag(llvm::Module::Override, "Objective-C Class Properties", 2328 (uint32_t)0); 2329 Changed = true; 2330 } 2331 2332 return Changed; 2333 } 2334 2335 static bool isOldLoopArgument(Metadata *MD) { 2336 auto *T = dyn_cast_or_null<MDTuple>(MD); 2337 if (!T) 2338 return false; 2339 if (T->getNumOperands() < 1) 2340 return false; 2341 auto *S = dyn_cast_or_null<MDString>(T->getOperand(0)); 2342 if (!S) 2343 return false; 2344 return S->getString().startswith("llvm.vectorizer."); 2345 } 2346 2347 static MDString *upgradeLoopTag(LLVMContext &C, StringRef OldTag) { 2348 StringRef OldPrefix = "llvm.vectorizer."; 2349 assert(OldTag.startswith(OldPrefix) && "Expected old prefix"); 2350 2351 if (OldTag == "llvm.vectorizer.unroll") 2352 return MDString::get(C, "llvm.loop.interleave.count"); 2353 2354 return MDString::get( 2355 C, (Twine("llvm.loop.vectorize.") + OldTag.drop_front(OldPrefix.size())) 2356 .str()); 2357 } 2358 2359 static Metadata *upgradeLoopArgument(Metadata *MD) { 2360 auto *T = dyn_cast_or_null<MDTuple>(MD); 2361 if (!T) 2362 return MD; 2363 if (T->getNumOperands() < 1) 2364 return MD; 2365 auto *OldTag = dyn_cast_or_null<MDString>(T->getOperand(0)); 2366 if (!OldTag) 2367 return MD; 2368 if (!OldTag->getString().startswith("llvm.vectorizer.")) 2369 return MD; 2370 2371 // This has an old tag. Upgrade it. 2372 SmallVector<Metadata *, 8> Ops; 2373 Ops.reserve(T->getNumOperands()); 2374 Ops.push_back(upgradeLoopTag(T->getContext(), OldTag->getString())); 2375 for (unsigned I = 1, E = T->getNumOperands(); I != E; ++I) 2376 Ops.push_back(T->getOperand(I)); 2377 2378 return MDTuple::get(T->getContext(), Ops); 2379 } 2380 2381 MDNode *llvm::upgradeInstructionLoopAttachment(MDNode &N) { 2382 auto *T = dyn_cast<MDTuple>(&N); 2383 if (!T) 2384 return &N; 2385 2386 if (none_of(T->operands(), isOldLoopArgument)) 2387 return &N; 2388 2389 SmallVector<Metadata *, 8> Ops; 2390 Ops.reserve(T->getNumOperands()); 2391 for (Metadata *MD : T->operands()) 2392 Ops.push_back(upgradeLoopArgument(MD)); 2393 2394 return MDTuple::get(T->getContext(), Ops); 2395 } 2396