1 //===-- AutoUpgrade.cpp - Implement auto-upgrade helper functions ---------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements the auto-upgrade helper functions. 11 // This is where deprecated IR intrinsics and other IR features are updated to 12 // current specifications. 13 // 14 //===----------------------------------------------------------------------===// 15 16 #include "llvm/IR/AutoUpgrade.h" 17 #include "llvm/IR/CFG.h" 18 #include "llvm/IR/CallSite.h" 19 #include "llvm/IR/Constants.h" 20 #include "llvm/IR/DIBuilder.h" 21 #include "llvm/IR/DebugInfo.h" 22 #include "llvm/IR/DiagnosticInfo.h" 23 #include "llvm/IR/Function.h" 24 #include "llvm/IR/IRBuilder.h" 25 #include "llvm/IR/Instruction.h" 26 #include "llvm/IR/IntrinsicInst.h" 27 #include "llvm/IR/LLVMContext.h" 28 #include "llvm/IR/Module.h" 29 #include "llvm/Support/ErrorHandling.h" 30 #include "llvm/Support/Regex.h" 31 #include <cstring> 32 using namespace llvm; 33 34 static void rename(GlobalValue *GV) { GV->setName(GV->getName() + ".old"); } 35 36 // Upgrade the declarations of the SSE4.1 functions whose arguments have 37 // changed their type from v4f32 to v2i64. 38 static bool UpgradeSSE41Function(Function* F, Intrinsic::ID IID, 39 Function *&NewFn) { 40 // Check whether this is an old version of the function, which received 41 // v4f32 arguments. 42 Type *Arg0Type = F->getFunctionType()->getParamType(0); 43 if (Arg0Type != VectorType::get(Type::getFloatTy(F->getContext()), 4)) 44 return false; 45 46 // Yes, it's old, replace it with new version. 47 rename(F); 48 NewFn = Intrinsic::getDeclaration(F->getParent(), IID); 49 return true; 50 } 51 52 // Upgrade the declarations of intrinsic functions whose 8-bit immediate mask 53 // arguments have changed their type from i32 to i8. 54 static bool UpgradeX86IntrinsicsWith8BitMask(Function *F, Intrinsic::ID IID, 55 Function *&NewFn) { 56 // Check that the last argument is an i32. 57 Type *LastArgType = F->getFunctionType()->getParamType( 58 F->getFunctionType()->getNumParams() - 1); 59 if (!LastArgType->isIntegerTy(32)) 60 return false; 61 62 // Move this function aside and map down. 63 rename(F); 64 NewFn = Intrinsic::getDeclaration(F->getParent(), IID); 65 return true; 66 } 67 68 static bool UpgradeIntrinsicFunction1(Function *F, Function *&NewFn) { 69 assert(F && "Illegal to upgrade a non-existent Function."); 70 71 // Quickly eliminate it, if it's not a candidate. 72 StringRef Name = F->getName(); 73 if (Name.size() <= 8 || !Name.startswith("llvm.")) 74 return false; 75 Name = Name.substr(5); // Strip off "llvm." 76 77 switch (Name[0]) { 78 default: break; 79 case 'a': { 80 if (Name.startswith("arm.neon.vclz")) { 81 Type* args[2] = { 82 F->arg_begin()->getType(), 83 Type::getInt1Ty(F->getContext()) 84 }; 85 // Can't use Intrinsic::getDeclaration here as it adds a ".i1" to 86 // the end of the name. Change name from llvm.arm.neon.vclz.* to 87 // llvm.ctlz.* 88 FunctionType* fType = FunctionType::get(F->getReturnType(), args, false); 89 NewFn = Function::Create(fType, F->getLinkage(), 90 "llvm.ctlz." + Name.substr(14), F->getParent()); 91 return true; 92 } 93 if (Name.startswith("arm.neon.vcnt")) { 94 NewFn = Intrinsic::getDeclaration(F->getParent(), Intrinsic::ctpop, 95 F->arg_begin()->getType()); 96 return true; 97 } 98 Regex vldRegex("^arm\\.neon\\.vld([1234]|[234]lane)\\.v[a-z0-9]*$"); 99 if (vldRegex.match(Name)) { 100 auto fArgs = F->getFunctionType()->params(); 101 SmallVector<Type *, 4> Tys(fArgs.begin(), fArgs.end()); 102 // Can't use Intrinsic::getDeclaration here as the return types might 103 // then only be structurally equal. 104 FunctionType* fType = FunctionType::get(F->getReturnType(), Tys, false); 105 NewFn = Function::Create(fType, F->getLinkage(), 106 "llvm." + Name + ".p0i8", F->getParent()); 107 return true; 108 } 109 Regex vstRegex("^arm\\.neon\\.vst([1234]|[234]lane)\\.v[a-z0-9]*$"); 110 if (vstRegex.match(Name)) { 111 static const Intrinsic::ID StoreInts[] = {Intrinsic::arm_neon_vst1, 112 Intrinsic::arm_neon_vst2, 113 Intrinsic::arm_neon_vst3, 114 Intrinsic::arm_neon_vst4}; 115 116 static const Intrinsic::ID StoreLaneInts[] = { 117 Intrinsic::arm_neon_vst2lane, Intrinsic::arm_neon_vst3lane, 118 Intrinsic::arm_neon_vst4lane 119 }; 120 121 auto fArgs = F->getFunctionType()->params(); 122 Type *Tys[] = {fArgs[0], fArgs[1]}; 123 if (Name.find("lane") == StringRef::npos) 124 NewFn = Intrinsic::getDeclaration(F->getParent(), 125 StoreInts[fArgs.size() - 3], Tys); 126 else 127 NewFn = Intrinsic::getDeclaration(F->getParent(), 128 StoreLaneInts[fArgs.size() - 5], Tys); 129 return true; 130 } 131 if (Name == "aarch64.thread.pointer" || Name == "arm.thread.pointer") { 132 NewFn = Intrinsic::getDeclaration(F->getParent(), Intrinsic::thread_pointer); 133 return true; 134 } 135 break; 136 } 137 138 case 'c': { 139 if (Name.startswith("ctlz.") && F->arg_size() == 1) { 140 rename(F); 141 NewFn = Intrinsic::getDeclaration(F->getParent(), Intrinsic::ctlz, 142 F->arg_begin()->getType()); 143 return true; 144 } 145 if (Name.startswith("cttz.") && F->arg_size() == 1) { 146 rename(F); 147 NewFn = Intrinsic::getDeclaration(F->getParent(), Intrinsic::cttz, 148 F->arg_begin()->getType()); 149 return true; 150 } 151 break; 152 } 153 case 'i': { 154 if (Name.startswith("invariant.start")) { 155 auto Args = F->getFunctionType()->params(); 156 Type* ObjectPtr[1] = {Args[1]}; 157 if (F->getName() != 158 Intrinsic::getName(Intrinsic::invariant_start, ObjectPtr)) { 159 rename(F); 160 NewFn = Intrinsic::getDeclaration( 161 F->getParent(), Intrinsic::invariant_start, ObjectPtr); 162 return true; 163 } 164 } 165 if (Name.startswith("invariant.end")) { 166 auto Args = F->getFunctionType()->params(); 167 Type* ObjectPtr[1] = {Args[2]}; 168 if (F->getName() != 169 Intrinsic::getName(Intrinsic::invariant_end, ObjectPtr)) { 170 rename(F); 171 NewFn = Intrinsic::getDeclaration(F->getParent(), 172 Intrinsic::invariant_end, ObjectPtr); 173 return true; 174 } 175 } 176 break; 177 } 178 case 'm': { 179 if (Name.startswith("masked.load.")) { 180 Type *Tys[] = { F->getReturnType(), F->arg_begin()->getType() }; 181 if (F->getName() != Intrinsic::getName(Intrinsic::masked_load, Tys)) { 182 rename(F); 183 NewFn = Intrinsic::getDeclaration(F->getParent(), 184 Intrinsic::masked_load, 185 Tys); 186 return true; 187 } 188 } 189 if (Name.startswith("masked.store.")) { 190 auto Args = F->getFunctionType()->params(); 191 Type *Tys[] = { Args[0], Args[1] }; 192 if (F->getName() != Intrinsic::getName(Intrinsic::masked_store, Tys)) { 193 rename(F); 194 NewFn = Intrinsic::getDeclaration(F->getParent(), 195 Intrinsic::masked_store, 196 Tys); 197 return true; 198 } 199 } 200 break; 201 } 202 203 case 'o': 204 // We only need to change the name to match the mangling including the 205 // address space. 206 if (F->arg_size() == 2 && Name.startswith("objectsize.")) { 207 Type *Tys[2] = { F->getReturnType(), F->arg_begin()->getType() }; 208 if (F->getName() != Intrinsic::getName(Intrinsic::objectsize, Tys)) { 209 rename(F); 210 NewFn = Intrinsic::getDeclaration(F->getParent(), 211 Intrinsic::objectsize, Tys); 212 return true; 213 } 214 } 215 break; 216 217 case 's': 218 if (Name == "stackprotectorcheck") { 219 NewFn = nullptr; 220 return true; 221 } 222 break; 223 224 case 'x': { 225 bool IsX86 = Name.startswith("x86."); 226 if (IsX86) 227 Name = Name.substr(4); 228 229 // All of the intrinsics matches below should be marked with which llvm 230 // version started autoupgrading them. At some point in the future we would 231 // like to use this information to remove upgrade code for some older 232 // intrinsics. It is currently undecided how we will determine that future 233 // point. 234 if (IsX86 && 235 (Name.startswith("sse2.pcmpeq.") || // Added in 3.1 236 Name.startswith("sse2.pcmpgt.") || // Added in 3.1 237 Name.startswith("avx2.pcmpeq.") || // Added in 3.1 238 Name.startswith("avx2.pcmpgt.") || // Added in 3.1 239 Name.startswith("avx512.mask.pcmpeq.") || // Added in 3.9 240 Name.startswith("avx512.mask.pcmpgt.") || // Added in 3.9 241 Name == "sse.add.ss" || // Added in 4.0 242 Name == "sse2.add.sd" || // Added in 4.0 243 Name == "sse.sub.ss" || // Added in 4.0 244 Name == "sse2.sub.sd" || // Added in 4.0 245 Name == "sse.mul.ss" || // Added in 4.0 246 Name == "sse2.mul.sd" || // Added in 4.0 247 Name == "sse.div.ss" || // Added in 4.0 248 Name == "sse2.div.sd" || // Added in 4.0 249 Name == "sse41.pmaxsb" || // Added in 3.9 250 Name == "sse2.pmaxs.w" || // Added in 3.9 251 Name == "sse41.pmaxsd" || // Added in 3.9 252 Name == "sse2.pmaxu.b" || // Added in 3.9 253 Name == "sse41.pmaxuw" || // Added in 3.9 254 Name == "sse41.pmaxud" || // Added in 3.9 255 Name == "sse41.pminsb" || // Added in 3.9 256 Name == "sse2.pmins.w" || // Added in 3.9 257 Name == "sse41.pminsd" || // Added in 3.9 258 Name == "sse2.pminu.b" || // Added in 3.9 259 Name == "sse41.pminuw" || // Added in 3.9 260 Name == "sse41.pminud" || // Added in 3.9 261 Name == "avx512.mask.pshuf.b.128" || // Added in 4.0 262 Name == "avx512.mask.pshuf.b.256" || // Added in 4.0 263 Name.startswith("avx2.pmax") || // Added in 3.9 264 Name.startswith("avx2.pmin") || // Added in 3.9 265 Name.startswith("avx512.mask.pmax") || // Added in 4.0 266 Name.startswith("avx512.mask.pmin") || // Added in 4.0 267 Name.startswith("avx2.vbroadcast") || // Added in 3.8 268 Name.startswith("avx2.pbroadcast") || // Added in 3.8 269 Name.startswith("avx.vpermil.") || // Added in 3.1 270 Name.startswith("sse2.pshuf") || // Added in 3.9 271 Name.startswith("avx512.pbroadcast") || // Added in 3.9 272 Name.startswith("avx512.mask.broadcast.s") || // Added in 3.9 273 Name.startswith("avx512.mask.movddup") || // Added in 3.9 274 Name.startswith("avx512.mask.movshdup") || // Added in 3.9 275 Name.startswith("avx512.mask.movsldup") || // Added in 3.9 276 Name.startswith("avx512.mask.pshuf.d.") || // Added in 3.9 277 Name.startswith("avx512.mask.pshufl.w.") || // Added in 3.9 278 Name.startswith("avx512.mask.pshufh.w.") || // Added in 3.9 279 Name.startswith("avx512.mask.shuf.p") || // Added in 4.0 280 Name.startswith("avx512.mask.vpermil.p") || // Added in 3.9 281 Name.startswith("avx512.mask.perm.df.") || // Added in 3.9 282 Name.startswith("avx512.mask.perm.di.") || // Added in 3.9 283 Name.startswith("avx512.mask.punpckl") || // Added in 3.9 284 Name.startswith("avx512.mask.punpckh") || // Added in 3.9 285 Name.startswith("avx512.mask.unpckl.") || // Added in 3.9 286 Name.startswith("avx512.mask.unpckh.") || // Added in 3.9 287 Name.startswith("avx512.mask.pand.") || // Added in 3.9 288 Name.startswith("avx512.mask.pandn.") || // Added in 3.9 289 Name.startswith("avx512.mask.por.") || // Added in 3.9 290 Name.startswith("avx512.mask.pxor.") || // Added in 3.9 291 Name.startswith("avx512.mask.and.") || // Added in 3.9 292 Name.startswith("avx512.mask.andn.") || // Added in 3.9 293 Name.startswith("avx512.mask.or.") || // Added in 3.9 294 Name.startswith("avx512.mask.xor.") || // Added in 3.9 295 Name.startswith("avx512.mask.padd.") || // Added in 4.0 296 Name.startswith("avx512.mask.psub.") || // Added in 4.0 297 Name.startswith("avx512.mask.pmull.") || // Added in 4.0 298 Name.startswith("avx512.mask.cvtdq2pd.") || // Added in 4.0 299 Name.startswith("avx512.mask.cvtudq2pd.") || // Added in 4.0 300 Name == "avx512.mask.add.pd.128" || // Added in 4.0 301 Name == "avx512.mask.add.pd.256" || // Added in 4.0 302 Name == "avx512.mask.add.ps.128" || // Added in 4.0 303 Name == "avx512.mask.add.ps.256" || // Added in 4.0 304 Name == "avx512.mask.div.pd.128" || // Added in 4.0 305 Name == "avx512.mask.div.pd.256" || // Added in 4.0 306 Name == "avx512.mask.div.ps.128" || // Added in 4.0 307 Name == "avx512.mask.div.ps.256" || // Added in 4.0 308 Name == "avx512.mask.mul.pd.128" || // Added in 4.0 309 Name == "avx512.mask.mul.pd.256" || // Added in 4.0 310 Name == "avx512.mask.mul.ps.128" || // Added in 4.0 311 Name == "avx512.mask.mul.ps.256" || // Added in 4.0 312 Name == "avx512.mask.sub.pd.128" || // Added in 4.0 313 Name == "avx512.mask.sub.pd.256" || // Added in 4.0 314 Name == "avx512.mask.sub.ps.128" || // Added in 4.0 315 Name == "avx512.mask.sub.ps.256" || // Added in 4.0 316 Name.startswith("avx512.mask.psll.d") || // Added in 4.0 317 Name.startswith("avx512.mask.psll.q") || // Added in 4.0 318 Name.startswith("avx512.mask.psll.w") || // Added in 4.0 319 Name.startswith("avx512.mask.psra.d") || // Added in 4.0 320 Name.startswith("avx512.mask.psra.q") || // Added in 4.0 321 Name.startswith("avx512.mask.psra.w") || // Added in 4.0 322 Name.startswith("avx512.mask.psrl.d") || // Added in 4.0 323 Name.startswith("avx512.mask.psrl.q") || // Added in 4.0 324 Name.startswith("avx512.mask.psrl.w") || // Added in 4.0 325 Name.startswith("avx512.mask.pslli") || // Added in 4.0 326 Name.startswith("avx512.mask.psrai") || // Added in 4.0 327 Name.startswith("avx512.mask.psrli") || // Added in 4.0 328 Name.startswith("avx512.mask.psllv") || // Added in 4.0 329 Name.startswith("avx512.mask.psrav") || // Added in 4.0 330 Name.startswith("avx512.mask.psrlv") || // Added in 4.0 331 Name.startswith("sse41.pmovsx") || // Added in 3.8 332 Name.startswith("sse41.pmovzx") || // Added in 3.9 333 Name.startswith("avx2.pmovsx") || // Added in 3.9 334 Name.startswith("avx2.pmovzx") || // Added in 3.9 335 Name.startswith("avx512.mask.pmovsx") || // Added in 4.0 336 Name.startswith("avx512.mask.pmovzx") || // Added in 4.0 337 Name == "sse2.cvtdq2pd" || // Added in 3.9 338 Name == "sse2.cvtps2pd" || // Added in 3.9 339 Name == "avx.cvtdq2.pd.256" || // Added in 3.9 340 Name == "avx.cvt.ps2.pd.256" || // Added in 3.9 341 Name.startswith("avx.vinsertf128.") || // Added in 3.7 342 Name == "avx2.vinserti128" || // Added in 3.7 343 Name.startswith("avx.vextractf128.") || // Added in 3.7 344 Name == "avx2.vextracti128" || // Added in 3.7 345 Name.startswith("sse4a.movnt.") || // Added in 3.9 346 Name.startswith("avx.movnt.") || // Added in 3.2 347 Name.startswith("avx512.storent.") || // Added in 3.9 348 Name == "sse2.storel.dq" || // Added in 3.9 349 Name.startswith("sse.storeu.") || // Added in 3.9 350 Name.startswith("sse2.storeu.") || // Added in 3.9 351 Name.startswith("avx.storeu.") || // Added in 3.9 352 Name.startswith("avx512.mask.storeu.") || // Added in 3.9 353 Name.startswith("avx512.mask.store.p") || // Added in 3.9 354 Name.startswith("avx512.mask.store.b.") || // Added in 3.9 355 Name.startswith("avx512.mask.store.w.") || // Added in 3.9 356 Name.startswith("avx512.mask.store.d.") || // Added in 3.9 357 Name.startswith("avx512.mask.store.q.") || // Added in 3.9 358 Name.startswith("avx512.mask.loadu.") || // Added in 3.9 359 Name.startswith("avx512.mask.load.") || // Added in 3.9 360 Name == "sse42.crc32.64.8" || // Added in 3.4 361 Name.startswith("avx.vbroadcast.s") || // Added in 3.5 362 Name.startswith("avx512.mask.palignr.") || // Added in 3.9 363 Name.startswith("avx512.mask.valign.") || // Added in 4.0 364 Name.startswith("sse2.psll.dq") || // Added in 3.7 365 Name.startswith("sse2.psrl.dq") || // Added in 3.7 366 Name.startswith("avx2.psll.dq") || // Added in 3.7 367 Name.startswith("avx2.psrl.dq") || // Added in 3.7 368 Name.startswith("avx512.psll.dq") || // Added in 3.9 369 Name.startswith("avx512.psrl.dq") || // Added in 3.9 370 Name == "sse41.pblendw" || // Added in 3.7 371 Name.startswith("sse41.blendp") || // Added in 3.7 372 Name.startswith("avx.blend.p") || // Added in 3.7 373 Name == "avx2.pblendw" || // Added in 3.7 374 Name.startswith("avx2.pblendd.") || // Added in 3.7 375 Name.startswith("avx.vbroadcastf128") || // Added in 4.0 376 Name == "avx2.vbroadcasti128" || // Added in 3.7 377 Name == "xop.vpcmov" || // Added in 3.8 378 Name.startswith("avx512.mask.move.s") || // Added in 4.0 379 (Name.startswith("xop.vpcom") && // Added in 3.2 380 F->arg_size() == 2))) { 381 NewFn = nullptr; 382 return true; 383 } 384 // SSE4.1 ptest functions may have an old signature. 385 if (IsX86 && Name.startswith("sse41.ptest")) { // Added in 3.2 386 if (Name.substr(11) == "c") 387 return UpgradeSSE41Function(F, Intrinsic::x86_sse41_ptestc, NewFn); 388 if (Name.substr(11) == "z") 389 return UpgradeSSE41Function(F, Intrinsic::x86_sse41_ptestz, NewFn); 390 if (Name.substr(11) == "nzc") 391 return UpgradeSSE41Function(F, Intrinsic::x86_sse41_ptestnzc, NewFn); 392 } 393 // Several blend and other instructions with masks used the wrong number of 394 // bits. 395 if (IsX86 && Name == "sse41.insertps") // Added in 3.6 396 return UpgradeX86IntrinsicsWith8BitMask(F, Intrinsic::x86_sse41_insertps, 397 NewFn); 398 if (IsX86 && Name == "sse41.dppd") // Added in 3.6 399 return UpgradeX86IntrinsicsWith8BitMask(F, Intrinsic::x86_sse41_dppd, 400 NewFn); 401 if (IsX86 && Name == "sse41.dpps") // Added in 3.6 402 return UpgradeX86IntrinsicsWith8BitMask(F, Intrinsic::x86_sse41_dpps, 403 NewFn); 404 if (IsX86 && Name == "sse41.mpsadbw") // Added in 3.6 405 return UpgradeX86IntrinsicsWith8BitMask(F, Intrinsic::x86_sse41_mpsadbw, 406 NewFn); 407 if (IsX86 && Name == "avx.dp.ps.256") // Added in 3.6 408 return UpgradeX86IntrinsicsWith8BitMask(F, Intrinsic::x86_avx_dp_ps_256, 409 NewFn); 410 if (IsX86 && Name == "avx2.mpsadbw") // Added in 3.6 411 return UpgradeX86IntrinsicsWith8BitMask(F, Intrinsic::x86_avx2_mpsadbw, 412 NewFn); 413 414 // frcz.ss/sd may need to have an argument dropped. Added in 3.2 415 if (IsX86 && Name.startswith("xop.vfrcz.ss") && F->arg_size() == 2) { 416 rename(F); 417 NewFn = Intrinsic::getDeclaration(F->getParent(), 418 Intrinsic::x86_xop_vfrcz_ss); 419 return true; 420 } 421 if (IsX86 && Name.startswith("xop.vfrcz.sd") && F->arg_size() == 2) { 422 rename(F); 423 NewFn = Intrinsic::getDeclaration(F->getParent(), 424 Intrinsic::x86_xop_vfrcz_sd); 425 return true; 426 } 427 // Upgrade any XOP PERMIL2 index operand still using a float/double vector. 428 if (IsX86 && Name.startswith("xop.vpermil2")) { // Added in 3.9 429 auto Params = F->getFunctionType()->params(); 430 auto Idx = Params[2]; 431 if (Idx->getScalarType()->isFloatingPointTy()) { 432 rename(F); 433 unsigned IdxSize = Idx->getPrimitiveSizeInBits(); 434 unsigned EltSize = Idx->getScalarSizeInBits(); 435 Intrinsic::ID Permil2ID; 436 if (EltSize == 64 && IdxSize == 128) 437 Permil2ID = Intrinsic::x86_xop_vpermil2pd; 438 else if (EltSize == 32 && IdxSize == 128) 439 Permil2ID = Intrinsic::x86_xop_vpermil2ps; 440 else if (EltSize == 64 && IdxSize == 256) 441 Permil2ID = Intrinsic::x86_xop_vpermil2pd_256; 442 else 443 Permil2ID = Intrinsic::x86_xop_vpermil2ps_256; 444 NewFn = Intrinsic::getDeclaration(F->getParent(), Permil2ID); 445 return true; 446 } 447 } 448 break; 449 } 450 } 451 452 // This may not belong here. This function is effectively being overloaded 453 // to both detect an intrinsic which needs upgrading, and to provide the 454 // upgraded form of the intrinsic. We should perhaps have two separate 455 // functions for this. 456 return false; 457 } 458 459 bool llvm::UpgradeIntrinsicFunction(Function *F, Function *&NewFn) { 460 NewFn = nullptr; 461 bool Upgraded = UpgradeIntrinsicFunction1(F, NewFn); 462 assert(F != NewFn && "Intrinsic function upgraded to the same function"); 463 464 // Upgrade intrinsic attributes. This does not change the function. 465 if (NewFn) 466 F = NewFn; 467 if (Intrinsic::ID id = F->getIntrinsicID()) 468 F->setAttributes(Intrinsic::getAttributes(F->getContext(), id)); 469 return Upgraded; 470 } 471 472 bool llvm::UpgradeGlobalVariable(GlobalVariable *GV) { 473 // Nothing to do yet. 474 return false; 475 } 476 477 // Handles upgrading SSE2/AVX2/AVX512BW PSLLDQ intrinsics by converting them 478 // to byte shuffles. 479 static Value *UpgradeX86PSLLDQIntrinsics(IRBuilder<> &Builder, 480 Value *Op, unsigned Shift) { 481 Type *ResultTy = Op->getType(); 482 unsigned NumElts = ResultTy->getVectorNumElements() * 8; 483 484 // Bitcast from a 64-bit element type to a byte element type. 485 Type *VecTy = VectorType::get(Builder.getInt8Ty(), NumElts); 486 Op = Builder.CreateBitCast(Op, VecTy, "cast"); 487 488 // We'll be shuffling in zeroes. 489 Value *Res = Constant::getNullValue(VecTy); 490 491 // If shift is less than 16, emit a shuffle to move the bytes. Otherwise, 492 // we'll just return the zero vector. 493 if (Shift < 16) { 494 uint32_t Idxs[64]; 495 // 256/512-bit version is split into 2/4 16-byte lanes. 496 for (unsigned l = 0; l != NumElts; l += 16) 497 for (unsigned i = 0; i != 16; ++i) { 498 unsigned Idx = NumElts + i - Shift; 499 if (Idx < NumElts) 500 Idx -= NumElts - 16; // end of lane, switch operand. 501 Idxs[l + i] = Idx + l; 502 } 503 504 Res = Builder.CreateShuffleVector(Res, Op, makeArrayRef(Idxs, NumElts)); 505 } 506 507 // Bitcast back to a 64-bit element type. 508 return Builder.CreateBitCast(Res, ResultTy, "cast"); 509 } 510 511 // Handles upgrading SSE2/AVX2/AVX512BW PSRLDQ intrinsics by converting them 512 // to byte shuffles. 513 static Value *UpgradeX86PSRLDQIntrinsics(IRBuilder<> &Builder, Value *Op, 514 unsigned Shift) { 515 Type *ResultTy = Op->getType(); 516 unsigned NumElts = ResultTy->getVectorNumElements() * 8; 517 518 // Bitcast from a 64-bit element type to a byte element type. 519 Type *VecTy = VectorType::get(Builder.getInt8Ty(), NumElts); 520 Op = Builder.CreateBitCast(Op, VecTy, "cast"); 521 522 // We'll be shuffling in zeroes. 523 Value *Res = Constant::getNullValue(VecTy); 524 525 // If shift is less than 16, emit a shuffle to move the bytes. Otherwise, 526 // we'll just return the zero vector. 527 if (Shift < 16) { 528 uint32_t Idxs[64]; 529 // 256/512-bit version is split into 2/4 16-byte lanes. 530 for (unsigned l = 0; l != NumElts; l += 16) 531 for (unsigned i = 0; i != 16; ++i) { 532 unsigned Idx = i + Shift; 533 if (Idx >= 16) 534 Idx += NumElts - 16; // end of lane, switch operand. 535 Idxs[l + i] = Idx + l; 536 } 537 538 Res = Builder.CreateShuffleVector(Op, Res, makeArrayRef(Idxs, NumElts)); 539 } 540 541 // Bitcast back to a 64-bit element type. 542 return Builder.CreateBitCast(Res, ResultTy, "cast"); 543 } 544 545 static Value *getX86MaskVec(IRBuilder<> &Builder, Value *Mask, 546 unsigned NumElts) { 547 llvm::VectorType *MaskTy = llvm::VectorType::get(Builder.getInt1Ty(), 548 cast<IntegerType>(Mask->getType())->getBitWidth()); 549 Mask = Builder.CreateBitCast(Mask, MaskTy); 550 551 // If we have less than 8 elements, then the starting mask was an i8 and 552 // we need to extract down to the right number of elements. 553 if (NumElts < 8) { 554 uint32_t Indices[4]; 555 for (unsigned i = 0; i != NumElts; ++i) 556 Indices[i] = i; 557 Mask = Builder.CreateShuffleVector(Mask, Mask, 558 makeArrayRef(Indices, NumElts), 559 "extract"); 560 } 561 562 return Mask; 563 } 564 565 static Value *EmitX86Select(IRBuilder<> &Builder, Value *Mask, 566 Value *Op0, Value *Op1) { 567 // If the mask is all ones just emit the align operation. 568 if (const auto *C = dyn_cast<Constant>(Mask)) 569 if (C->isAllOnesValue()) 570 return Op0; 571 572 Mask = getX86MaskVec(Builder, Mask, Op0->getType()->getVectorNumElements()); 573 return Builder.CreateSelect(Mask, Op0, Op1); 574 } 575 576 // Handle autoupgrade for masked PALIGNR and VALIGND/Q intrinsics. 577 // PALIGNR handles large immediates by shifting while VALIGN masks the immediate 578 // so we need to handle both cases. VALIGN also doesn't have 128-bit lanes. 579 static Value *UpgradeX86ALIGNIntrinsics(IRBuilder<> &Builder, Value *Op0, 580 Value *Op1, Value *Shift, 581 Value *Passthru, Value *Mask, 582 bool IsVALIGN) { 583 unsigned ShiftVal = cast<llvm::ConstantInt>(Shift)->getZExtValue(); 584 585 unsigned NumElts = Op0->getType()->getVectorNumElements(); 586 assert((IsVALIGN || NumElts % 16 == 0) && "Illegal NumElts for PALIGNR!"); 587 assert((!IsVALIGN || NumElts <= 16) && "NumElts too large for VALIGN!"); 588 assert(isPowerOf2_32(NumElts) && "NumElts not a power of 2!"); 589 590 // Mask the immediate for VALIGN. 591 if (IsVALIGN) 592 ShiftVal &= (NumElts - 1); 593 594 // If palignr is shifting the pair of vectors more than the size of two 595 // lanes, emit zero. 596 if (ShiftVal >= 32) 597 return llvm::Constant::getNullValue(Op0->getType()); 598 599 // If palignr is shifting the pair of input vectors more than one lane, 600 // but less than two lanes, convert to shifting in zeroes. 601 if (ShiftVal > 16) { 602 ShiftVal -= 16; 603 Op1 = Op0; 604 Op0 = llvm::Constant::getNullValue(Op0->getType()); 605 } 606 607 uint32_t Indices[64]; 608 // 256-bit palignr operates on 128-bit lanes so we need to handle that 609 for (unsigned l = 0; l < NumElts; l += 16) { 610 for (unsigned i = 0; i != 16; ++i) { 611 unsigned Idx = ShiftVal + i; 612 if (!IsVALIGN && Idx >= 16) // Disable wrap for VALIGN. 613 Idx += NumElts - 16; // End of lane, switch operand. 614 Indices[l + i] = Idx + l; 615 } 616 } 617 618 Value *Align = Builder.CreateShuffleVector(Op1, Op0, 619 makeArrayRef(Indices, NumElts), 620 "palignr"); 621 622 return EmitX86Select(Builder, Mask, Align, Passthru); 623 } 624 625 static Value *UpgradeMaskedStore(IRBuilder<> &Builder, 626 Value *Ptr, Value *Data, Value *Mask, 627 bool Aligned) { 628 // Cast the pointer to the right type. 629 Ptr = Builder.CreateBitCast(Ptr, 630 llvm::PointerType::getUnqual(Data->getType())); 631 unsigned Align = 632 Aligned ? cast<VectorType>(Data->getType())->getBitWidth() / 8 : 1; 633 634 // If the mask is all ones just emit a regular store. 635 if (const auto *C = dyn_cast<Constant>(Mask)) 636 if (C->isAllOnesValue()) 637 return Builder.CreateAlignedStore(Data, Ptr, Align); 638 639 // Convert the mask from an integer type to a vector of i1. 640 unsigned NumElts = Data->getType()->getVectorNumElements(); 641 Mask = getX86MaskVec(Builder, Mask, NumElts); 642 return Builder.CreateMaskedStore(Data, Ptr, Align, Mask); 643 } 644 645 static Value *UpgradeMaskedLoad(IRBuilder<> &Builder, 646 Value *Ptr, Value *Passthru, Value *Mask, 647 bool Aligned) { 648 // Cast the pointer to the right type. 649 Ptr = Builder.CreateBitCast(Ptr, 650 llvm::PointerType::getUnqual(Passthru->getType())); 651 unsigned Align = 652 Aligned ? cast<VectorType>(Passthru->getType())->getBitWidth() / 8 : 1; 653 654 // If the mask is all ones just emit a regular store. 655 if (const auto *C = dyn_cast<Constant>(Mask)) 656 if (C->isAllOnesValue()) 657 return Builder.CreateAlignedLoad(Ptr, Align); 658 659 // Convert the mask from an integer type to a vector of i1. 660 unsigned NumElts = Passthru->getType()->getVectorNumElements(); 661 Mask = getX86MaskVec(Builder, Mask, NumElts); 662 return Builder.CreateMaskedLoad(Ptr, Align, Mask, Passthru); 663 } 664 665 static Value *upgradeIntMinMax(IRBuilder<> &Builder, CallInst &CI, 666 ICmpInst::Predicate Pred) { 667 Value *Op0 = CI.getArgOperand(0); 668 Value *Op1 = CI.getArgOperand(1); 669 Value *Cmp = Builder.CreateICmp(Pred, Op0, Op1); 670 Value *Res = Builder.CreateSelect(Cmp, Op0, Op1); 671 672 if (CI.getNumArgOperands() == 4) 673 Res = EmitX86Select(Builder, CI.getArgOperand(3), Res, CI.getArgOperand(2)); 674 675 return Res; 676 } 677 678 static Value *upgradeMaskedCompare(IRBuilder<> &Builder, CallInst &CI, 679 ICmpInst::Predicate Pred) { 680 Value *Op0 = CI.getArgOperand(0); 681 unsigned NumElts = Op0->getType()->getVectorNumElements(); 682 Value *Cmp = Builder.CreateICmp(Pred, Op0, CI.getArgOperand(1)); 683 684 Value *Mask = CI.getArgOperand(2); 685 const auto *C = dyn_cast<Constant>(Mask); 686 if (!C || !C->isAllOnesValue()) 687 Cmp = Builder.CreateAnd(Cmp, getX86MaskVec(Builder, Mask, NumElts)); 688 689 if (NumElts < 8) { 690 uint32_t Indices[8]; 691 for (unsigned i = 0; i != NumElts; ++i) 692 Indices[i] = i; 693 for (unsigned i = NumElts; i != 8; ++i) 694 Indices[i] = NumElts + i % NumElts; 695 Cmp = Builder.CreateShuffleVector(Cmp, 696 Constant::getNullValue(Cmp->getType()), 697 Indices); 698 } 699 return Builder.CreateBitCast(Cmp, IntegerType::get(CI.getContext(), 700 std::max(NumElts, 8U))); 701 } 702 703 // Replace a masked intrinsic with an older unmasked intrinsic. 704 static Value *UpgradeX86MaskedShift(IRBuilder<> &Builder, CallInst &CI, 705 Intrinsic::ID IID) { 706 Function *F = CI.getCalledFunction(); 707 Function *Intrin = Intrinsic::getDeclaration(F->getParent(), IID); 708 Value *Rep = Builder.CreateCall(Intrin, 709 { CI.getArgOperand(0), CI.getArgOperand(1) }); 710 return EmitX86Select(Builder, CI.getArgOperand(3), Rep, CI.getArgOperand(2)); 711 } 712 713 static Value* upgradeMaskedMove(IRBuilder<> &Builder, CallInst &CI) { 714 Value* A = CI.getArgOperand(0); 715 Value* B = CI.getArgOperand(1); 716 Value* Src = CI.getArgOperand(2); 717 Value* Mask = CI.getArgOperand(3); 718 719 Value* AndNode = Builder.CreateAnd(Mask, APInt(8, 1)); 720 Value* Cmp = Builder.CreateIsNotNull(AndNode); 721 Value* Extract1 = Builder.CreateExtractElement(B, (uint64_t)0); 722 Value* Extract2 = Builder.CreateExtractElement(Src, (uint64_t)0); 723 Value* Select = Builder.CreateSelect(Cmp, Extract1, Extract2); 724 return Builder.CreateInsertElement(A, Select, (uint64_t)0); 725 } 726 727 /// Upgrade a call to an old intrinsic. All argument and return casting must be 728 /// provided to seamlessly integrate with existing context. 729 void llvm::UpgradeIntrinsicCall(CallInst *CI, Function *NewFn) { 730 Function *F = CI->getCalledFunction(); 731 LLVMContext &C = CI->getContext(); 732 IRBuilder<> Builder(C); 733 Builder.SetInsertPoint(CI->getParent(), CI->getIterator()); 734 735 assert(F && "Intrinsic call is not direct?"); 736 737 if (!NewFn) { 738 // Get the Function's name. 739 StringRef Name = F->getName(); 740 741 assert(Name.startswith("llvm.") && "Intrinsic doesn't start with 'llvm.'"); 742 Name = Name.substr(5); 743 744 bool IsX86 = Name.startswith("x86."); 745 if (IsX86) 746 Name = Name.substr(4); 747 748 Value *Rep; 749 // Upgrade packed integer vector compare intrinsics to compare instructions. 750 if (IsX86 && (Name.startswith("sse2.pcmpeq.") || 751 Name.startswith("avx2.pcmpeq."))) { 752 Rep = Builder.CreateICmpEQ(CI->getArgOperand(0), CI->getArgOperand(1), 753 "pcmpeq"); 754 Rep = Builder.CreateSExt(Rep, CI->getType(), ""); 755 } else if (IsX86 && (Name.startswith("sse2.pcmpgt.") || 756 Name.startswith("avx2.pcmpgt."))) { 757 Rep = Builder.CreateICmpSGT(CI->getArgOperand(0), CI->getArgOperand(1), 758 "pcmpgt"); 759 Rep = Builder.CreateSExt(Rep, CI->getType(), ""); 760 } else if (IsX86 && (Name == "sse.add.ss" || Name == "sse2.add.sd")) { 761 Type *I32Ty = Type::getInt32Ty(C); 762 Value *Elt0 = Builder.CreateExtractElement(CI->getArgOperand(0), 763 ConstantInt::get(I32Ty, 0)); 764 Value *Elt1 = Builder.CreateExtractElement(CI->getArgOperand(1), 765 ConstantInt::get(I32Ty, 0)); 766 Rep = Builder.CreateInsertElement(CI->getArgOperand(0), 767 Builder.CreateFAdd(Elt0, Elt1), 768 ConstantInt::get(I32Ty, 0)); 769 } else if (IsX86 && (Name == "sse.sub.ss" || Name == "sse2.sub.sd")) { 770 Type *I32Ty = Type::getInt32Ty(C); 771 Value *Elt0 = Builder.CreateExtractElement(CI->getArgOperand(0), 772 ConstantInt::get(I32Ty, 0)); 773 Value *Elt1 = Builder.CreateExtractElement(CI->getArgOperand(1), 774 ConstantInt::get(I32Ty, 0)); 775 Rep = Builder.CreateInsertElement(CI->getArgOperand(0), 776 Builder.CreateFSub(Elt0, Elt1), 777 ConstantInt::get(I32Ty, 0)); 778 } else if (IsX86 && (Name == "sse.mul.ss" || Name == "sse2.mul.sd")) { 779 Type *I32Ty = Type::getInt32Ty(C); 780 Value *Elt0 = Builder.CreateExtractElement(CI->getArgOperand(0), 781 ConstantInt::get(I32Ty, 0)); 782 Value *Elt1 = Builder.CreateExtractElement(CI->getArgOperand(1), 783 ConstantInt::get(I32Ty, 0)); 784 Rep = Builder.CreateInsertElement(CI->getArgOperand(0), 785 Builder.CreateFMul(Elt0, Elt1), 786 ConstantInt::get(I32Ty, 0)); 787 } else if (IsX86 && (Name == "sse.div.ss" || Name == "sse2.div.sd")) { 788 Type *I32Ty = Type::getInt32Ty(C); 789 Value *Elt0 = Builder.CreateExtractElement(CI->getArgOperand(0), 790 ConstantInt::get(I32Ty, 0)); 791 Value *Elt1 = Builder.CreateExtractElement(CI->getArgOperand(1), 792 ConstantInt::get(I32Ty, 0)); 793 Rep = Builder.CreateInsertElement(CI->getArgOperand(0), 794 Builder.CreateFDiv(Elt0, Elt1), 795 ConstantInt::get(I32Ty, 0)); 796 } else if (IsX86 && Name.startswith("avx512.mask.pcmpeq.")) { 797 Rep = upgradeMaskedCompare(Builder, *CI, ICmpInst::ICMP_EQ); 798 } else if (IsX86 && Name.startswith("avx512.mask.pcmpgt.")) { 799 Rep = upgradeMaskedCompare(Builder, *CI, ICmpInst::ICMP_SGT); 800 } else if (IsX86 && (Name == "sse41.pmaxsb" || 801 Name == "sse2.pmaxs.w" || 802 Name == "sse41.pmaxsd" || 803 Name.startswith("avx2.pmaxs") || 804 Name.startswith("avx512.mask.pmaxs"))) { 805 Rep = upgradeIntMinMax(Builder, *CI, ICmpInst::ICMP_SGT); 806 } else if (IsX86 && (Name == "sse2.pmaxu.b" || 807 Name == "sse41.pmaxuw" || 808 Name == "sse41.pmaxud" || 809 Name.startswith("avx2.pmaxu") || 810 Name.startswith("avx512.mask.pmaxu"))) { 811 Rep = upgradeIntMinMax(Builder, *CI, ICmpInst::ICMP_UGT); 812 } else if (IsX86 && (Name == "sse41.pminsb" || 813 Name == "sse2.pmins.w" || 814 Name == "sse41.pminsd" || 815 Name.startswith("avx2.pmins") || 816 Name.startswith("avx512.mask.pmins"))) { 817 Rep = upgradeIntMinMax(Builder, *CI, ICmpInst::ICMP_SLT); 818 } else if (IsX86 && (Name == "sse2.pminu.b" || 819 Name == "sse41.pminuw" || 820 Name == "sse41.pminud" || 821 Name.startswith("avx2.pminu") || 822 Name.startswith("avx512.mask.pminu"))) { 823 Rep = upgradeIntMinMax(Builder, *CI, ICmpInst::ICMP_ULT); 824 } else if (IsX86 && (Name == "sse2.cvtdq2pd" || 825 Name == "sse2.cvtps2pd" || 826 Name == "avx.cvtdq2.pd.256" || 827 Name == "avx.cvt.ps2.pd.256" || 828 Name.startswith("avx512.mask.cvtdq2pd.") || 829 Name.startswith("avx512.mask.cvtudq2pd."))) { 830 // Lossless i32/float to double conversion. 831 // Extract the bottom elements if necessary and convert to double vector. 832 Value *Src = CI->getArgOperand(0); 833 VectorType *SrcTy = cast<VectorType>(Src->getType()); 834 VectorType *DstTy = cast<VectorType>(CI->getType()); 835 Rep = CI->getArgOperand(0); 836 837 unsigned NumDstElts = DstTy->getNumElements(); 838 if (NumDstElts < SrcTy->getNumElements()) { 839 assert(NumDstElts == 2 && "Unexpected vector size"); 840 uint32_t ShuffleMask[2] = { 0, 1 }; 841 Rep = Builder.CreateShuffleVector(Rep, UndefValue::get(SrcTy), 842 ShuffleMask); 843 } 844 845 bool SInt2Double = (StringRef::npos != Name.find("cvtdq2")); 846 bool UInt2Double = (StringRef::npos != Name.find("cvtudq2")); 847 if (SInt2Double) 848 Rep = Builder.CreateSIToFP(Rep, DstTy, "cvtdq2pd"); 849 else if (UInt2Double) 850 Rep = Builder.CreateUIToFP(Rep, DstTy, "cvtudq2pd"); 851 else 852 Rep = Builder.CreateFPExt(Rep, DstTy, "cvtps2pd"); 853 854 if (CI->getNumArgOperands() == 3) 855 Rep = EmitX86Select(Builder, CI->getArgOperand(2), Rep, 856 CI->getArgOperand(1)); 857 } else if (IsX86 && Name.startswith("sse4a.movnt.")) { 858 Module *M = F->getParent(); 859 SmallVector<Metadata *, 1> Elts; 860 Elts.push_back( 861 ConstantAsMetadata::get(ConstantInt::get(Type::getInt32Ty(C), 1))); 862 MDNode *Node = MDNode::get(C, Elts); 863 864 Value *Arg0 = CI->getArgOperand(0); 865 Value *Arg1 = CI->getArgOperand(1); 866 867 // Nontemporal (unaligned) store of the 0'th element of the float/double 868 // vector. 869 Type *SrcEltTy = cast<VectorType>(Arg1->getType())->getElementType(); 870 PointerType *EltPtrTy = PointerType::getUnqual(SrcEltTy); 871 Value *Addr = Builder.CreateBitCast(Arg0, EltPtrTy, "cast"); 872 Value *Extract = 873 Builder.CreateExtractElement(Arg1, (uint64_t)0, "extractelement"); 874 875 StoreInst *SI = Builder.CreateAlignedStore(Extract, Addr, 1); 876 SI->setMetadata(M->getMDKindID("nontemporal"), Node); 877 878 // Remove intrinsic. 879 CI->eraseFromParent(); 880 return; 881 } else if (IsX86 && (Name.startswith("avx.movnt.") || 882 Name.startswith("avx512.storent."))) { 883 Module *M = F->getParent(); 884 SmallVector<Metadata *, 1> Elts; 885 Elts.push_back( 886 ConstantAsMetadata::get(ConstantInt::get(Type::getInt32Ty(C), 1))); 887 MDNode *Node = MDNode::get(C, Elts); 888 889 Value *Arg0 = CI->getArgOperand(0); 890 Value *Arg1 = CI->getArgOperand(1); 891 892 // Convert the type of the pointer to a pointer to the stored type. 893 Value *BC = Builder.CreateBitCast(Arg0, 894 PointerType::getUnqual(Arg1->getType()), 895 "cast"); 896 VectorType *VTy = cast<VectorType>(Arg1->getType()); 897 StoreInst *SI = Builder.CreateAlignedStore(Arg1, BC, 898 VTy->getBitWidth() / 8); 899 SI->setMetadata(M->getMDKindID("nontemporal"), Node); 900 901 // Remove intrinsic. 902 CI->eraseFromParent(); 903 return; 904 } else if (IsX86 && Name == "sse2.storel.dq") { 905 Value *Arg0 = CI->getArgOperand(0); 906 Value *Arg1 = CI->getArgOperand(1); 907 908 Type *NewVecTy = VectorType::get(Type::getInt64Ty(C), 2); 909 Value *BC0 = Builder.CreateBitCast(Arg1, NewVecTy, "cast"); 910 Value *Elt = Builder.CreateExtractElement(BC0, (uint64_t)0); 911 Value *BC = Builder.CreateBitCast(Arg0, 912 PointerType::getUnqual(Elt->getType()), 913 "cast"); 914 Builder.CreateAlignedStore(Elt, BC, 1); 915 916 // Remove intrinsic. 917 CI->eraseFromParent(); 918 return; 919 } else if (IsX86 && (Name.startswith("sse.storeu.") || 920 Name.startswith("sse2.storeu.") || 921 Name.startswith("avx.storeu."))) { 922 Value *Arg0 = CI->getArgOperand(0); 923 Value *Arg1 = CI->getArgOperand(1); 924 925 Arg0 = Builder.CreateBitCast(Arg0, 926 PointerType::getUnqual(Arg1->getType()), 927 "cast"); 928 Builder.CreateAlignedStore(Arg1, Arg0, 1); 929 930 // Remove intrinsic. 931 CI->eraseFromParent(); 932 return; 933 } else if (IsX86 && (Name.startswith("avx512.mask.storeu."))) { 934 UpgradeMaskedStore(Builder, CI->getArgOperand(0), CI->getArgOperand(1), 935 CI->getArgOperand(2), /*Aligned*/false); 936 937 // Remove intrinsic. 938 CI->eraseFromParent(); 939 return; 940 } else if (IsX86 && (Name.startswith("avx512.mask.store."))) { 941 UpgradeMaskedStore(Builder, CI->getArgOperand(0), CI->getArgOperand(1), 942 CI->getArgOperand(2), /*Aligned*/true); 943 944 // Remove intrinsic. 945 CI->eraseFromParent(); 946 return; 947 } else if (IsX86 && (Name.startswith("avx512.mask.loadu."))) { 948 Rep = UpgradeMaskedLoad(Builder, CI->getArgOperand(0), 949 CI->getArgOperand(1), CI->getArgOperand(2), 950 /*Aligned*/false); 951 } else if (IsX86 && (Name.startswith("avx512.mask.load."))) { 952 Rep = UpgradeMaskedLoad(Builder, CI->getArgOperand(0), 953 CI->getArgOperand(1),CI->getArgOperand(2), 954 /*Aligned*/true); 955 } else if (IsX86 && Name.startswith("xop.vpcom")) { 956 Intrinsic::ID intID; 957 if (Name.endswith("ub")) 958 intID = Intrinsic::x86_xop_vpcomub; 959 else if (Name.endswith("uw")) 960 intID = Intrinsic::x86_xop_vpcomuw; 961 else if (Name.endswith("ud")) 962 intID = Intrinsic::x86_xop_vpcomud; 963 else if (Name.endswith("uq")) 964 intID = Intrinsic::x86_xop_vpcomuq; 965 else if (Name.endswith("b")) 966 intID = Intrinsic::x86_xop_vpcomb; 967 else if (Name.endswith("w")) 968 intID = Intrinsic::x86_xop_vpcomw; 969 else if (Name.endswith("d")) 970 intID = Intrinsic::x86_xop_vpcomd; 971 else if (Name.endswith("q")) 972 intID = Intrinsic::x86_xop_vpcomq; 973 else 974 llvm_unreachable("Unknown suffix"); 975 976 Name = Name.substr(9); // strip off "xop.vpcom" 977 unsigned Imm; 978 if (Name.startswith("lt")) 979 Imm = 0; 980 else if (Name.startswith("le")) 981 Imm = 1; 982 else if (Name.startswith("gt")) 983 Imm = 2; 984 else if (Name.startswith("ge")) 985 Imm = 3; 986 else if (Name.startswith("eq")) 987 Imm = 4; 988 else if (Name.startswith("ne")) 989 Imm = 5; 990 else if (Name.startswith("false")) 991 Imm = 6; 992 else if (Name.startswith("true")) 993 Imm = 7; 994 else 995 llvm_unreachable("Unknown condition"); 996 997 Function *VPCOM = Intrinsic::getDeclaration(F->getParent(), intID); 998 Rep = 999 Builder.CreateCall(VPCOM, {CI->getArgOperand(0), CI->getArgOperand(1), 1000 Builder.getInt8(Imm)}); 1001 } else if (IsX86 && Name == "xop.vpcmov") { 1002 Value *Arg0 = CI->getArgOperand(0); 1003 Value *Arg1 = CI->getArgOperand(1); 1004 Value *Sel = CI->getArgOperand(2); 1005 unsigned NumElts = CI->getType()->getVectorNumElements(); 1006 Constant *MinusOne = ConstantVector::getSplat(NumElts, Builder.getInt64(-1)); 1007 Value *NotSel = Builder.CreateXor(Sel, MinusOne); 1008 Value *Sel0 = Builder.CreateAnd(Arg0, Sel); 1009 Value *Sel1 = Builder.CreateAnd(Arg1, NotSel); 1010 Rep = Builder.CreateOr(Sel0, Sel1); 1011 } else if (IsX86 && Name == "sse42.crc32.64.8") { 1012 Function *CRC32 = Intrinsic::getDeclaration(F->getParent(), 1013 Intrinsic::x86_sse42_crc32_32_8); 1014 Value *Trunc0 = Builder.CreateTrunc(CI->getArgOperand(0), Type::getInt32Ty(C)); 1015 Rep = Builder.CreateCall(CRC32, {Trunc0, CI->getArgOperand(1)}); 1016 Rep = Builder.CreateZExt(Rep, CI->getType(), ""); 1017 } else if (IsX86 && Name.startswith("avx.vbroadcast.s")) { 1018 // Replace broadcasts with a series of insertelements. 1019 Type *VecTy = CI->getType(); 1020 Type *EltTy = VecTy->getVectorElementType(); 1021 unsigned EltNum = VecTy->getVectorNumElements(); 1022 Value *Cast = Builder.CreateBitCast(CI->getArgOperand(0), 1023 EltTy->getPointerTo()); 1024 Value *Load = Builder.CreateLoad(EltTy, Cast); 1025 Type *I32Ty = Type::getInt32Ty(C); 1026 Rep = UndefValue::get(VecTy); 1027 for (unsigned I = 0; I < EltNum; ++I) 1028 Rep = Builder.CreateInsertElement(Rep, Load, 1029 ConstantInt::get(I32Ty, I)); 1030 } else if (IsX86 && (Name.startswith("sse41.pmovsx") || 1031 Name.startswith("sse41.pmovzx") || 1032 Name.startswith("avx2.pmovsx") || 1033 Name.startswith("avx2.pmovzx") || 1034 Name.startswith("avx512.mask.pmovsx") || 1035 Name.startswith("avx512.mask.pmovzx"))) { 1036 VectorType *SrcTy = cast<VectorType>(CI->getArgOperand(0)->getType()); 1037 VectorType *DstTy = cast<VectorType>(CI->getType()); 1038 unsigned NumDstElts = DstTy->getNumElements(); 1039 1040 // Extract a subvector of the first NumDstElts lanes and sign/zero extend. 1041 SmallVector<uint32_t, 8> ShuffleMask(NumDstElts); 1042 for (unsigned i = 0; i != NumDstElts; ++i) 1043 ShuffleMask[i] = i; 1044 1045 Value *SV = Builder.CreateShuffleVector( 1046 CI->getArgOperand(0), UndefValue::get(SrcTy), ShuffleMask); 1047 1048 bool DoSext = (StringRef::npos != Name.find("pmovsx")); 1049 Rep = DoSext ? Builder.CreateSExt(SV, DstTy) 1050 : Builder.CreateZExt(SV, DstTy); 1051 // If there are 3 arguments, it's a masked intrinsic so we need a select. 1052 if (CI->getNumArgOperands() == 3) 1053 Rep = EmitX86Select(Builder, CI->getArgOperand(2), Rep, 1054 CI->getArgOperand(1)); 1055 } else if (IsX86 && (Name.startswith("avx.vbroadcastf128") || 1056 Name == "avx2.vbroadcasti128")) { 1057 // Replace vbroadcastf128/vbroadcasti128 with a vector load+shuffle. 1058 Type *EltTy = CI->getType()->getVectorElementType(); 1059 unsigned NumSrcElts = 128 / EltTy->getPrimitiveSizeInBits(); 1060 Type *VT = VectorType::get(EltTy, NumSrcElts); 1061 Value *Op = Builder.CreatePointerCast(CI->getArgOperand(0), 1062 PointerType::getUnqual(VT)); 1063 Value *Load = Builder.CreateAlignedLoad(Op, 1); 1064 if (NumSrcElts == 2) 1065 Rep = Builder.CreateShuffleVector(Load, UndefValue::get(Load->getType()), 1066 { 0, 1, 0, 1 }); 1067 else 1068 Rep = Builder.CreateShuffleVector(Load, UndefValue::get(Load->getType()), 1069 { 0, 1, 2, 3, 0, 1, 2, 3 }); 1070 } else if (IsX86 && (Name.startswith("avx2.pbroadcast") || 1071 Name.startswith("avx2.vbroadcast") || 1072 Name.startswith("avx512.pbroadcast") || 1073 Name.startswith("avx512.mask.broadcast.s"))) { 1074 // Replace vp?broadcasts with a vector shuffle. 1075 Value *Op = CI->getArgOperand(0); 1076 unsigned NumElts = CI->getType()->getVectorNumElements(); 1077 Type *MaskTy = VectorType::get(Type::getInt32Ty(C), NumElts); 1078 Rep = Builder.CreateShuffleVector(Op, UndefValue::get(Op->getType()), 1079 Constant::getNullValue(MaskTy)); 1080 1081 if (CI->getNumArgOperands() == 3) 1082 Rep = EmitX86Select(Builder, CI->getArgOperand(2), Rep, 1083 CI->getArgOperand(1)); 1084 } else if (IsX86 && Name.startswith("avx512.mask.palignr.")) { 1085 Rep = UpgradeX86ALIGNIntrinsics(Builder, CI->getArgOperand(0), 1086 CI->getArgOperand(1), 1087 CI->getArgOperand(2), 1088 CI->getArgOperand(3), 1089 CI->getArgOperand(4), 1090 false); 1091 } else if (IsX86 && Name.startswith("avx512.mask.valign.")) { 1092 Rep = UpgradeX86ALIGNIntrinsics(Builder, CI->getArgOperand(0), 1093 CI->getArgOperand(1), 1094 CI->getArgOperand(2), 1095 CI->getArgOperand(3), 1096 CI->getArgOperand(4), 1097 true); 1098 } else if (IsX86 && (Name == "sse2.psll.dq" || 1099 Name == "avx2.psll.dq")) { 1100 // 128/256-bit shift left specified in bits. 1101 unsigned Shift = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue(); 1102 Rep = UpgradeX86PSLLDQIntrinsics(Builder, CI->getArgOperand(0), 1103 Shift / 8); // Shift is in bits. 1104 } else if (IsX86 && (Name == "sse2.psrl.dq" || 1105 Name == "avx2.psrl.dq")) { 1106 // 128/256-bit shift right specified in bits. 1107 unsigned Shift = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue(); 1108 Rep = UpgradeX86PSRLDQIntrinsics(Builder, CI->getArgOperand(0), 1109 Shift / 8); // Shift is in bits. 1110 } else if (IsX86 && (Name == "sse2.psll.dq.bs" || 1111 Name == "avx2.psll.dq.bs" || 1112 Name == "avx512.psll.dq.512")) { 1113 // 128/256/512-bit shift left specified in bytes. 1114 unsigned Shift = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue(); 1115 Rep = UpgradeX86PSLLDQIntrinsics(Builder, CI->getArgOperand(0), Shift); 1116 } else if (IsX86 && (Name == "sse2.psrl.dq.bs" || 1117 Name == "avx2.psrl.dq.bs" || 1118 Name == "avx512.psrl.dq.512")) { 1119 // 128/256/512-bit shift right specified in bytes. 1120 unsigned Shift = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue(); 1121 Rep = UpgradeX86PSRLDQIntrinsics(Builder, CI->getArgOperand(0), Shift); 1122 } else if (IsX86 && (Name == "sse41.pblendw" || 1123 Name.startswith("sse41.blendp") || 1124 Name.startswith("avx.blend.p") || 1125 Name == "avx2.pblendw" || 1126 Name.startswith("avx2.pblendd."))) { 1127 Value *Op0 = CI->getArgOperand(0); 1128 Value *Op1 = CI->getArgOperand(1); 1129 unsigned Imm = cast <ConstantInt>(CI->getArgOperand(2))->getZExtValue(); 1130 VectorType *VecTy = cast<VectorType>(CI->getType()); 1131 unsigned NumElts = VecTy->getNumElements(); 1132 1133 SmallVector<uint32_t, 16> Idxs(NumElts); 1134 for (unsigned i = 0; i != NumElts; ++i) 1135 Idxs[i] = ((Imm >> (i%8)) & 1) ? i + NumElts : i; 1136 1137 Rep = Builder.CreateShuffleVector(Op0, Op1, Idxs); 1138 } else if (IsX86 && (Name.startswith("avx.vinsertf128.") || 1139 Name == "avx2.vinserti128")) { 1140 Value *Op0 = CI->getArgOperand(0); 1141 Value *Op1 = CI->getArgOperand(1); 1142 unsigned Imm = cast<ConstantInt>(CI->getArgOperand(2))->getZExtValue(); 1143 VectorType *VecTy = cast<VectorType>(CI->getType()); 1144 unsigned NumElts = VecTy->getNumElements(); 1145 1146 // Mask off the high bits of the immediate value; hardware ignores those. 1147 Imm = Imm & 1; 1148 1149 // Extend the second operand into a vector that is twice as big. 1150 Value *UndefV = UndefValue::get(Op1->getType()); 1151 SmallVector<uint32_t, 8> Idxs(NumElts); 1152 for (unsigned i = 0; i != NumElts; ++i) 1153 Idxs[i] = i; 1154 Rep = Builder.CreateShuffleVector(Op1, UndefV, Idxs); 1155 1156 // Insert the second operand into the first operand. 1157 1158 // Note that there is no guarantee that instruction lowering will actually 1159 // produce a vinsertf128 instruction for the created shuffles. In 1160 // particular, the 0 immediate case involves no lane changes, so it can 1161 // be handled as a blend. 1162 1163 // Example of shuffle mask for 32-bit elements: 1164 // Imm = 1 <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11> 1165 // Imm = 0 <i32 8, i32 9, i32 10, i32 11, i32 4, i32 5, i32 6, i32 7 > 1166 1167 // The low half of the result is either the low half of the 1st operand 1168 // or the low half of the 2nd operand (the inserted vector). 1169 for (unsigned i = 0; i != NumElts / 2; ++i) 1170 Idxs[i] = Imm ? i : (i + NumElts); 1171 // The high half of the result is either the low half of the 2nd operand 1172 // (the inserted vector) or the high half of the 1st operand. 1173 for (unsigned i = NumElts / 2; i != NumElts; ++i) 1174 Idxs[i] = Imm ? (i + NumElts / 2) : i; 1175 Rep = Builder.CreateShuffleVector(Op0, Rep, Idxs); 1176 } else if (IsX86 && (Name.startswith("avx.vextractf128.") || 1177 Name == "avx2.vextracti128")) { 1178 Value *Op0 = CI->getArgOperand(0); 1179 unsigned Imm = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue(); 1180 VectorType *VecTy = cast<VectorType>(CI->getType()); 1181 unsigned NumElts = VecTy->getNumElements(); 1182 1183 // Mask off the high bits of the immediate value; hardware ignores those. 1184 Imm = Imm & 1; 1185 1186 // Get indexes for either the high half or low half of the input vector. 1187 SmallVector<uint32_t, 4> Idxs(NumElts); 1188 for (unsigned i = 0; i != NumElts; ++i) { 1189 Idxs[i] = Imm ? (i + NumElts) : i; 1190 } 1191 1192 Value *UndefV = UndefValue::get(Op0->getType()); 1193 Rep = Builder.CreateShuffleVector(Op0, UndefV, Idxs); 1194 } else if (!IsX86 && Name == "stackprotectorcheck") { 1195 Rep = nullptr; 1196 } else if (IsX86 && (Name.startswith("avx512.mask.perm.df.") || 1197 Name.startswith("avx512.mask.perm.di."))) { 1198 Value *Op0 = CI->getArgOperand(0); 1199 unsigned Imm = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue(); 1200 VectorType *VecTy = cast<VectorType>(CI->getType()); 1201 unsigned NumElts = VecTy->getNumElements(); 1202 1203 SmallVector<uint32_t, 8> Idxs(NumElts); 1204 for (unsigned i = 0; i != NumElts; ++i) 1205 Idxs[i] = (i & ~0x3) + ((Imm >> (2 * (i & 0x3))) & 3); 1206 1207 Rep = Builder.CreateShuffleVector(Op0, Op0, Idxs); 1208 1209 if (CI->getNumArgOperands() == 4) 1210 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1211 CI->getArgOperand(2)); 1212 } else if (IsX86 && (Name.startswith("avx.vpermil.") || 1213 Name == "sse2.pshuf.d" || 1214 Name.startswith("avx512.mask.vpermil.p") || 1215 Name.startswith("avx512.mask.pshuf.d."))) { 1216 Value *Op0 = CI->getArgOperand(0); 1217 unsigned Imm = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue(); 1218 VectorType *VecTy = cast<VectorType>(CI->getType()); 1219 unsigned NumElts = VecTy->getNumElements(); 1220 // Calculate the size of each index in the immediate. 1221 unsigned IdxSize = 64 / VecTy->getScalarSizeInBits(); 1222 unsigned IdxMask = ((1 << IdxSize) - 1); 1223 1224 SmallVector<uint32_t, 8> Idxs(NumElts); 1225 // Lookup the bits for this element, wrapping around the immediate every 1226 // 8-bits. Elements are grouped into sets of 2 or 4 elements so we need 1227 // to offset by the first index of each group. 1228 for (unsigned i = 0; i != NumElts; ++i) 1229 Idxs[i] = ((Imm >> ((i * IdxSize) % 8)) & IdxMask) | (i & ~IdxMask); 1230 1231 Rep = Builder.CreateShuffleVector(Op0, Op0, Idxs); 1232 1233 if (CI->getNumArgOperands() == 4) 1234 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1235 CI->getArgOperand(2)); 1236 } else if (IsX86 && (Name == "sse2.pshufl.w" || 1237 Name.startswith("avx512.mask.pshufl.w."))) { 1238 Value *Op0 = CI->getArgOperand(0); 1239 unsigned Imm = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue(); 1240 unsigned NumElts = CI->getType()->getVectorNumElements(); 1241 1242 SmallVector<uint32_t, 16> Idxs(NumElts); 1243 for (unsigned l = 0; l != NumElts; l += 8) { 1244 for (unsigned i = 0; i != 4; ++i) 1245 Idxs[i + l] = ((Imm >> (2 * i)) & 0x3) + l; 1246 for (unsigned i = 4; i != 8; ++i) 1247 Idxs[i + l] = i + l; 1248 } 1249 1250 Rep = Builder.CreateShuffleVector(Op0, Op0, Idxs); 1251 1252 if (CI->getNumArgOperands() == 4) 1253 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1254 CI->getArgOperand(2)); 1255 } else if (IsX86 && (Name == "sse2.pshufh.w" || 1256 Name.startswith("avx512.mask.pshufh.w."))) { 1257 Value *Op0 = CI->getArgOperand(0); 1258 unsigned Imm = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue(); 1259 unsigned NumElts = CI->getType()->getVectorNumElements(); 1260 1261 SmallVector<uint32_t, 16> Idxs(NumElts); 1262 for (unsigned l = 0; l != NumElts; l += 8) { 1263 for (unsigned i = 0; i != 4; ++i) 1264 Idxs[i + l] = i + l; 1265 for (unsigned i = 0; i != 4; ++i) 1266 Idxs[i + l + 4] = ((Imm >> (2 * i)) & 0x3) + 4 + l; 1267 } 1268 1269 Rep = Builder.CreateShuffleVector(Op0, Op0, Idxs); 1270 1271 if (CI->getNumArgOperands() == 4) 1272 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1273 CI->getArgOperand(2)); 1274 } else if (IsX86 && Name.startswith("avx512.mask.shuf.p")) { 1275 Value *Op0 = CI->getArgOperand(0); 1276 Value *Op1 = CI->getArgOperand(1); 1277 unsigned Imm = cast<ConstantInt>(CI->getArgOperand(2))->getZExtValue(); 1278 unsigned NumElts = CI->getType()->getVectorNumElements(); 1279 1280 unsigned NumLaneElts = 128/CI->getType()->getScalarSizeInBits(); 1281 unsigned HalfLaneElts = NumLaneElts / 2; 1282 1283 SmallVector<uint32_t, 16> Idxs(NumElts); 1284 for (unsigned i = 0; i != NumElts; ++i) { 1285 // Base index is the starting element of the lane. 1286 Idxs[i] = i - (i % NumLaneElts); 1287 // If we are half way through the lane switch to the other source. 1288 if ((i % NumLaneElts) >= HalfLaneElts) 1289 Idxs[i] += NumElts; 1290 // Now select the specific element. By adding HalfLaneElts bits from 1291 // the immediate. Wrapping around the immediate every 8-bits. 1292 Idxs[i] += (Imm >> ((i * HalfLaneElts) % 8)) & ((1 << HalfLaneElts) - 1); 1293 } 1294 1295 Rep = Builder.CreateShuffleVector(Op0, Op1, Idxs); 1296 1297 Rep = EmitX86Select(Builder, CI->getArgOperand(4), Rep, 1298 CI->getArgOperand(3)); 1299 } else if (IsX86 && (Name.startswith("avx512.mask.movddup") || 1300 Name.startswith("avx512.mask.movshdup") || 1301 Name.startswith("avx512.mask.movsldup"))) { 1302 Value *Op0 = CI->getArgOperand(0); 1303 unsigned NumElts = CI->getType()->getVectorNumElements(); 1304 unsigned NumLaneElts = 128/CI->getType()->getScalarSizeInBits(); 1305 1306 unsigned Offset = 0; 1307 if (Name.startswith("avx512.mask.movshdup.")) 1308 Offset = 1; 1309 1310 SmallVector<uint32_t, 16> Idxs(NumElts); 1311 for (unsigned l = 0; l != NumElts; l += NumLaneElts) 1312 for (unsigned i = 0; i != NumLaneElts; i += 2) { 1313 Idxs[i + l + 0] = i + l + Offset; 1314 Idxs[i + l + 1] = i + l + Offset; 1315 } 1316 1317 Rep = Builder.CreateShuffleVector(Op0, Op0, Idxs); 1318 1319 Rep = EmitX86Select(Builder, CI->getArgOperand(2), Rep, 1320 CI->getArgOperand(1)); 1321 } else if (IsX86 && (Name.startswith("avx512.mask.punpckl") || 1322 Name.startswith("avx512.mask.unpckl."))) { 1323 Value *Op0 = CI->getArgOperand(0); 1324 Value *Op1 = CI->getArgOperand(1); 1325 int NumElts = CI->getType()->getVectorNumElements(); 1326 int NumLaneElts = 128/CI->getType()->getScalarSizeInBits(); 1327 1328 SmallVector<uint32_t, 64> Idxs(NumElts); 1329 for (int l = 0; l != NumElts; l += NumLaneElts) 1330 for (int i = 0; i != NumLaneElts; ++i) 1331 Idxs[i + l] = l + (i / 2) + NumElts * (i % 2); 1332 1333 Rep = Builder.CreateShuffleVector(Op0, Op1, Idxs); 1334 1335 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1336 CI->getArgOperand(2)); 1337 } else if (IsX86 && (Name.startswith("avx512.mask.punpckh") || 1338 Name.startswith("avx512.mask.unpckh."))) { 1339 Value *Op0 = CI->getArgOperand(0); 1340 Value *Op1 = CI->getArgOperand(1); 1341 int NumElts = CI->getType()->getVectorNumElements(); 1342 int NumLaneElts = 128/CI->getType()->getScalarSizeInBits(); 1343 1344 SmallVector<uint32_t, 64> Idxs(NumElts); 1345 for (int l = 0; l != NumElts; l += NumLaneElts) 1346 for (int i = 0; i != NumLaneElts; ++i) 1347 Idxs[i + l] = (NumLaneElts / 2) + l + (i / 2) + NumElts * (i % 2); 1348 1349 Rep = Builder.CreateShuffleVector(Op0, Op1, Idxs); 1350 1351 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1352 CI->getArgOperand(2)); 1353 } else if (IsX86 && Name.startswith("avx512.mask.pand.")) { 1354 Rep = Builder.CreateAnd(CI->getArgOperand(0), CI->getArgOperand(1)); 1355 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1356 CI->getArgOperand(2)); 1357 } else if (IsX86 && Name.startswith("avx512.mask.pandn.")) { 1358 Rep = Builder.CreateAnd(Builder.CreateNot(CI->getArgOperand(0)), 1359 CI->getArgOperand(1)); 1360 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1361 CI->getArgOperand(2)); 1362 } else if (IsX86 && Name.startswith("avx512.mask.por.")) { 1363 Rep = Builder.CreateOr(CI->getArgOperand(0), CI->getArgOperand(1)); 1364 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1365 CI->getArgOperand(2)); 1366 } else if (IsX86 && Name.startswith("avx512.mask.pxor.")) { 1367 Rep = Builder.CreateXor(CI->getArgOperand(0), CI->getArgOperand(1)); 1368 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1369 CI->getArgOperand(2)); 1370 } else if (IsX86 && Name.startswith("avx512.mask.and.")) { 1371 VectorType *FTy = cast<VectorType>(CI->getType()); 1372 VectorType *ITy = VectorType::getInteger(FTy); 1373 Rep = Builder.CreateAnd(Builder.CreateBitCast(CI->getArgOperand(0), ITy), 1374 Builder.CreateBitCast(CI->getArgOperand(1), ITy)); 1375 Rep = Builder.CreateBitCast(Rep, FTy); 1376 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1377 CI->getArgOperand(2)); 1378 } else if (IsX86 && Name.startswith("avx512.mask.andn.")) { 1379 VectorType *FTy = cast<VectorType>(CI->getType()); 1380 VectorType *ITy = VectorType::getInteger(FTy); 1381 Rep = Builder.CreateNot(Builder.CreateBitCast(CI->getArgOperand(0), ITy)); 1382 Rep = Builder.CreateAnd(Rep, 1383 Builder.CreateBitCast(CI->getArgOperand(1), ITy)); 1384 Rep = Builder.CreateBitCast(Rep, FTy); 1385 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1386 CI->getArgOperand(2)); 1387 } else if (IsX86 && Name.startswith("avx512.mask.or.")) { 1388 VectorType *FTy = cast<VectorType>(CI->getType()); 1389 VectorType *ITy = VectorType::getInteger(FTy); 1390 Rep = Builder.CreateOr(Builder.CreateBitCast(CI->getArgOperand(0), ITy), 1391 Builder.CreateBitCast(CI->getArgOperand(1), ITy)); 1392 Rep = Builder.CreateBitCast(Rep, FTy); 1393 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1394 CI->getArgOperand(2)); 1395 } else if (IsX86 && Name.startswith("avx512.mask.xor.")) { 1396 VectorType *FTy = cast<VectorType>(CI->getType()); 1397 VectorType *ITy = VectorType::getInteger(FTy); 1398 Rep = Builder.CreateXor(Builder.CreateBitCast(CI->getArgOperand(0), ITy), 1399 Builder.CreateBitCast(CI->getArgOperand(1), ITy)); 1400 Rep = Builder.CreateBitCast(Rep, FTy); 1401 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1402 CI->getArgOperand(2)); 1403 } else if (IsX86 && Name.startswith("avx512.mask.padd.")) { 1404 Rep = Builder.CreateAdd(CI->getArgOperand(0), CI->getArgOperand(1)); 1405 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1406 CI->getArgOperand(2)); 1407 } else if (IsX86 && Name.startswith("avx512.mask.psub.")) { 1408 Rep = Builder.CreateSub(CI->getArgOperand(0), CI->getArgOperand(1)); 1409 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1410 CI->getArgOperand(2)); 1411 } else if (IsX86 && Name.startswith("avx512.mask.pmull.")) { 1412 Rep = Builder.CreateMul(CI->getArgOperand(0), CI->getArgOperand(1)); 1413 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1414 CI->getArgOperand(2)); 1415 } else if (IsX86 && (Name.startswith("avx512.mask.add.p"))) { 1416 Rep = Builder.CreateFAdd(CI->getArgOperand(0), CI->getArgOperand(1)); 1417 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1418 CI->getArgOperand(2)); 1419 } else if (IsX86 && Name.startswith("avx512.mask.div.p")) { 1420 Rep = Builder.CreateFDiv(CI->getArgOperand(0), CI->getArgOperand(1)); 1421 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1422 CI->getArgOperand(2)); 1423 } else if (IsX86 && Name.startswith("avx512.mask.mul.p")) { 1424 Rep = Builder.CreateFMul(CI->getArgOperand(0), CI->getArgOperand(1)); 1425 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1426 CI->getArgOperand(2)); 1427 } else if (IsX86 && Name.startswith("avx512.mask.sub.p")) { 1428 Rep = Builder.CreateFSub(CI->getArgOperand(0), CI->getArgOperand(1)); 1429 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1430 CI->getArgOperand(2)); 1431 } else if (IsX86 && Name.startswith("avx512.mask.pshuf.b.")) { 1432 VectorType *VecTy = cast<VectorType>(CI->getType()); 1433 Intrinsic::ID IID; 1434 if (VecTy->getPrimitiveSizeInBits() == 128) 1435 IID = Intrinsic::x86_ssse3_pshuf_b_128; 1436 else if (VecTy->getPrimitiveSizeInBits() == 256) 1437 IID = Intrinsic::x86_avx2_pshuf_b; 1438 else 1439 llvm_unreachable("Unexpected intrinsic"); 1440 1441 Rep = Builder.CreateCall(Intrinsic::getDeclaration(F->getParent(), IID), 1442 { CI->getArgOperand(0), CI->getArgOperand(1) }); 1443 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1444 CI->getArgOperand(2)); 1445 } else if (IsX86 && Name.startswith("avx512.mask.psll")) { 1446 bool IsImmediate = Name[16] == 'i' || 1447 (Name.size() > 18 && Name[18] == 'i'); 1448 bool IsVariable = Name[16] == 'v'; 1449 char Size = Name[16] == '.' ? Name[17] : 1450 Name[17] == '.' ? Name[18] : 1451 Name[18] == '.' ? Name[19] : 1452 Name[20]; 1453 1454 Intrinsic::ID IID; 1455 if (IsVariable && Name[17] != '.') { 1456 if (Size == 'd' && Name[17] == '2') // avx512.mask.psllv2.di 1457 IID = Intrinsic::x86_avx2_psllv_q; 1458 else if (Size == 'd' && Name[17] == '4') // avx512.mask.psllv4.di 1459 IID = Intrinsic::x86_avx2_psllv_q_256; 1460 else if (Size == 's' && Name[17] == '4') // avx512.mask.psllv4.si 1461 IID = Intrinsic::x86_avx2_psllv_d; 1462 else if (Size == 's' && Name[17] == '8') // avx512.mask.psllv8.si 1463 IID = Intrinsic::x86_avx2_psllv_d_256; 1464 else if (Size == 'h' && Name[17] == '8') // avx512.mask.psllv8.hi 1465 IID = Intrinsic::x86_avx512_psllv_w_128; 1466 else if (Size == 'h' && Name[17] == '1') // avx512.mask.psllv16.hi 1467 IID = Intrinsic::x86_avx512_psllv_w_256; 1468 else if (Name[17] == '3' && Name[18] == '2') // avx512.mask.psllv32hi 1469 IID = Intrinsic::x86_avx512_psllv_w_512; 1470 else 1471 llvm_unreachable("Unexpected size"); 1472 } else if (Name.endswith(".128")) { 1473 if (Size == 'd') // avx512.mask.psll.d.128, avx512.mask.psll.di.128 1474 IID = IsImmediate ? Intrinsic::x86_sse2_pslli_d 1475 : Intrinsic::x86_sse2_psll_d; 1476 else if (Size == 'q') // avx512.mask.psll.q.128, avx512.mask.psll.qi.128 1477 IID = IsImmediate ? Intrinsic::x86_sse2_pslli_q 1478 : Intrinsic::x86_sse2_psll_q; 1479 else if (Size == 'w') // avx512.mask.psll.w.128, avx512.mask.psll.wi.128 1480 IID = IsImmediate ? Intrinsic::x86_sse2_pslli_w 1481 : Intrinsic::x86_sse2_psll_w; 1482 else 1483 llvm_unreachable("Unexpected size"); 1484 } else if (Name.endswith(".256")) { 1485 if (Size == 'd') // avx512.mask.psll.d.256, avx512.mask.psll.di.256 1486 IID = IsImmediate ? Intrinsic::x86_avx2_pslli_d 1487 : Intrinsic::x86_avx2_psll_d; 1488 else if (Size == 'q') // avx512.mask.psll.q.256, avx512.mask.psll.qi.256 1489 IID = IsImmediate ? Intrinsic::x86_avx2_pslli_q 1490 : Intrinsic::x86_avx2_psll_q; 1491 else if (Size == 'w') // avx512.mask.psll.w.256, avx512.mask.psll.wi.256 1492 IID = IsImmediate ? Intrinsic::x86_avx2_pslli_w 1493 : Intrinsic::x86_avx2_psll_w; 1494 else 1495 llvm_unreachable("Unexpected size"); 1496 } else { 1497 if (Size == 'd') // psll.di.512, pslli.d, psll.d, psllv.d.512 1498 IID = IsImmediate ? Intrinsic::x86_avx512_pslli_d_512 : 1499 IsVariable ? Intrinsic::x86_avx512_psllv_d_512 : 1500 Intrinsic::x86_avx512_psll_d_512; 1501 else if (Size == 'q') // psll.qi.512, pslli.q, psll.q, psllv.q.512 1502 IID = IsImmediate ? Intrinsic::x86_avx512_pslli_q_512 : 1503 IsVariable ? Intrinsic::x86_avx512_psllv_q_512 : 1504 Intrinsic::x86_avx512_psll_q_512; 1505 else if (Size == 'w') // psll.wi.512, pslli.w, psll.w 1506 IID = IsImmediate ? Intrinsic::x86_avx512_pslli_w_512 1507 : Intrinsic::x86_avx512_psll_w_512; 1508 else 1509 llvm_unreachable("Unexpected size"); 1510 } 1511 1512 Rep = UpgradeX86MaskedShift(Builder, *CI, IID); 1513 } else if (IsX86 && Name.startswith("avx512.mask.psrl")) { 1514 bool IsImmediate = Name[16] == 'i' || 1515 (Name.size() > 18 && Name[18] == 'i'); 1516 bool IsVariable = Name[16] == 'v'; 1517 char Size = Name[16] == '.' ? Name[17] : 1518 Name[17] == '.' ? Name[18] : 1519 Name[18] == '.' ? Name[19] : 1520 Name[20]; 1521 1522 Intrinsic::ID IID; 1523 if (IsVariable && Name[17] != '.') { 1524 if (Size == 'd' && Name[17] == '2') // avx512.mask.psrlv2.di 1525 IID = Intrinsic::x86_avx2_psrlv_q; 1526 else if (Size == 'd' && Name[17] == '4') // avx512.mask.psrlv4.di 1527 IID = Intrinsic::x86_avx2_psrlv_q_256; 1528 else if (Size == 's' && Name[17] == '4') // avx512.mask.psrlv4.si 1529 IID = Intrinsic::x86_avx2_psrlv_d; 1530 else if (Size == 's' && Name[17] == '8') // avx512.mask.psrlv8.si 1531 IID = Intrinsic::x86_avx2_psrlv_d_256; 1532 else if (Size == 'h' && Name[17] == '8') // avx512.mask.psrlv8.hi 1533 IID = Intrinsic::x86_avx512_psrlv_w_128; 1534 else if (Size == 'h' && Name[17] == '1') // avx512.mask.psrlv16.hi 1535 IID = Intrinsic::x86_avx512_psrlv_w_256; 1536 else if (Name[17] == '3' && Name[18] == '2') // avx512.mask.psrlv32hi 1537 IID = Intrinsic::x86_avx512_psrlv_w_512; 1538 else 1539 llvm_unreachable("Unexpected size"); 1540 } else if (Name.endswith(".128")) { 1541 if (Size == 'd') // avx512.mask.psrl.d.128, avx512.mask.psrl.di.128 1542 IID = IsImmediate ? Intrinsic::x86_sse2_psrli_d 1543 : Intrinsic::x86_sse2_psrl_d; 1544 else if (Size == 'q') // avx512.mask.psrl.q.128, avx512.mask.psrl.qi.128 1545 IID = IsImmediate ? Intrinsic::x86_sse2_psrli_q 1546 : Intrinsic::x86_sse2_psrl_q; 1547 else if (Size == 'w') // avx512.mask.psrl.w.128, avx512.mask.psrl.wi.128 1548 IID = IsImmediate ? Intrinsic::x86_sse2_psrli_w 1549 : Intrinsic::x86_sse2_psrl_w; 1550 else 1551 llvm_unreachable("Unexpected size"); 1552 } else if (Name.endswith(".256")) { 1553 if (Size == 'd') // avx512.mask.psrl.d.256, avx512.mask.psrl.di.256 1554 IID = IsImmediate ? Intrinsic::x86_avx2_psrli_d 1555 : Intrinsic::x86_avx2_psrl_d; 1556 else if (Size == 'q') // avx512.mask.psrl.q.256, avx512.mask.psrl.qi.256 1557 IID = IsImmediate ? Intrinsic::x86_avx2_psrli_q 1558 : Intrinsic::x86_avx2_psrl_q; 1559 else if (Size == 'w') // avx512.mask.psrl.w.256, avx512.mask.psrl.wi.256 1560 IID = IsImmediate ? Intrinsic::x86_avx2_psrli_w 1561 : Intrinsic::x86_avx2_psrl_w; 1562 else 1563 llvm_unreachable("Unexpected size"); 1564 } else { 1565 if (Size == 'd') // psrl.di.512, psrli.d, psrl.d, psrl.d.512 1566 IID = IsImmediate ? Intrinsic::x86_avx512_psrli_d_512 : 1567 IsVariable ? Intrinsic::x86_avx512_psrlv_d_512 : 1568 Intrinsic::x86_avx512_psrl_d_512; 1569 else if (Size == 'q') // psrl.qi.512, psrli.q, psrl.q, psrl.q.512 1570 IID = IsImmediate ? Intrinsic::x86_avx512_psrli_q_512 : 1571 IsVariable ? Intrinsic::x86_avx512_psrlv_q_512 : 1572 Intrinsic::x86_avx512_psrl_q_512; 1573 else if (Size == 'w') // psrl.wi.512, psrli.w, psrl.w) 1574 IID = IsImmediate ? Intrinsic::x86_avx512_psrli_w_512 1575 : Intrinsic::x86_avx512_psrl_w_512; 1576 else 1577 llvm_unreachable("Unexpected size"); 1578 } 1579 1580 Rep = UpgradeX86MaskedShift(Builder, *CI, IID); 1581 } else if (IsX86 && Name.startswith("avx512.mask.psra")) { 1582 bool IsImmediate = Name[16] == 'i' || 1583 (Name.size() > 18 && Name[18] == 'i'); 1584 bool IsVariable = Name[16] == 'v'; 1585 char Size = Name[16] == '.' ? Name[17] : 1586 Name[17] == '.' ? Name[18] : 1587 Name[18] == '.' ? Name[19] : 1588 Name[20]; 1589 1590 Intrinsic::ID IID; 1591 if (IsVariable && Name[17] != '.') { 1592 if (Size == 's' && Name[17] == '4') // avx512.mask.psrav4.si 1593 IID = Intrinsic::x86_avx2_psrav_d; 1594 else if (Size == 's' && Name[17] == '8') // avx512.mask.psrav8.si 1595 IID = Intrinsic::x86_avx2_psrav_d_256; 1596 else if (Size == 'h' && Name[17] == '8') // avx512.mask.psrav8.hi 1597 IID = Intrinsic::x86_avx512_psrav_w_128; 1598 else if (Size == 'h' && Name[17] == '1') // avx512.mask.psrav16.hi 1599 IID = Intrinsic::x86_avx512_psrav_w_256; 1600 else if (Name[17] == '3' && Name[18] == '2') // avx512.mask.psrav32hi 1601 IID = Intrinsic::x86_avx512_psrav_w_512; 1602 else 1603 llvm_unreachable("Unexpected size"); 1604 } else if (Name.endswith(".128")) { 1605 if (Size == 'd') // avx512.mask.psra.d.128, avx512.mask.psra.di.128 1606 IID = IsImmediate ? Intrinsic::x86_sse2_psrai_d 1607 : Intrinsic::x86_sse2_psra_d; 1608 else if (Size == 'q') // avx512.mask.psra.q.128, avx512.mask.psra.qi.128 1609 IID = IsImmediate ? Intrinsic::x86_avx512_psrai_q_128 : 1610 IsVariable ? Intrinsic::x86_avx512_psrav_q_128 : 1611 Intrinsic::x86_avx512_psra_q_128; 1612 else if (Size == 'w') // avx512.mask.psra.w.128, avx512.mask.psra.wi.128 1613 IID = IsImmediate ? Intrinsic::x86_sse2_psrai_w 1614 : Intrinsic::x86_sse2_psra_w; 1615 else 1616 llvm_unreachable("Unexpected size"); 1617 } else if (Name.endswith(".256")) { 1618 if (Size == 'd') // avx512.mask.psra.d.256, avx512.mask.psra.di.256 1619 IID = IsImmediate ? Intrinsic::x86_avx2_psrai_d 1620 : Intrinsic::x86_avx2_psra_d; 1621 else if (Size == 'q') // avx512.mask.psra.q.256, avx512.mask.psra.qi.256 1622 IID = IsImmediate ? Intrinsic::x86_avx512_psrai_q_256 : 1623 IsVariable ? Intrinsic::x86_avx512_psrav_q_256 : 1624 Intrinsic::x86_avx512_psra_q_256; 1625 else if (Size == 'w') // avx512.mask.psra.w.256, avx512.mask.psra.wi.256 1626 IID = IsImmediate ? Intrinsic::x86_avx2_psrai_w 1627 : Intrinsic::x86_avx2_psra_w; 1628 else 1629 llvm_unreachable("Unexpected size"); 1630 } else { 1631 if (Size == 'd') // psra.di.512, psrai.d, psra.d, psrav.d.512 1632 IID = IsImmediate ? Intrinsic::x86_avx512_psrai_d_512 : 1633 IsVariable ? Intrinsic::x86_avx512_psrav_d_512 : 1634 Intrinsic::x86_avx512_psra_d_512; 1635 else if (Size == 'q') // psra.qi.512, psrai.q, psra.q 1636 IID = IsImmediate ? Intrinsic::x86_avx512_psrai_q_512 : 1637 IsVariable ? Intrinsic::x86_avx512_psrav_q_512 : 1638 Intrinsic::x86_avx512_psra_q_512; 1639 else if (Size == 'w') // psra.wi.512, psrai.w, psra.w 1640 IID = IsImmediate ? Intrinsic::x86_avx512_psrai_w_512 1641 : Intrinsic::x86_avx512_psra_w_512; 1642 else 1643 llvm_unreachable("Unexpected size"); 1644 } 1645 1646 Rep = UpgradeX86MaskedShift(Builder, *CI, IID); 1647 } else if (IsX86 && Name.startswith("avx512.mask.move.s")) { 1648 Rep = upgradeMaskedMove(Builder, *CI); 1649 } else { 1650 llvm_unreachable("Unknown function for CallInst upgrade."); 1651 } 1652 1653 if (Rep) 1654 CI->replaceAllUsesWith(Rep); 1655 CI->eraseFromParent(); 1656 return; 1657 } 1658 1659 std::string Name = CI->getName(); 1660 if (!Name.empty()) 1661 CI->setName(Name + ".old"); 1662 1663 switch (NewFn->getIntrinsicID()) { 1664 default: 1665 llvm_unreachable("Unknown function for CallInst upgrade."); 1666 1667 case Intrinsic::arm_neon_vld1: 1668 case Intrinsic::arm_neon_vld2: 1669 case Intrinsic::arm_neon_vld3: 1670 case Intrinsic::arm_neon_vld4: 1671 case Intrinsic::arm_neon_vld2lane: 1672 case Intrinsic::arm_neon_vld3lane: 1673 case Intrinsic::arm_neon_vld4lane: 1674 case Intrinsic::arm_neon_vst1: 1675 case Intrinsic::arm_neon_vst2: 1676 case Intrinsic::arm_neon_vst3: 1677 case Intrinsic::arm_neon_vst4: 1678 case Intrinsic::arm_neon_vst2lane: 1679 case Intrinsic::arm_neon_vst3lane: 1680 case Intrinsic::arm_neon_vst4lane: { 1681 SmallVector<Value *, 4> Args(CI->arg_operands().begin(), 1682 CI->arg_operands().end()); 1683 CI->replaceAllUsesWith(Builder.CreateCall(NewFn, Args)); 1684 CI->eraseFromParent(); 1685 return; 1686 } 1687 1688 case Intrinsic::ctlz: 1689 case Intrinsic::cttz: 1690 assert(CI->getNumArgOperands() == 1 && 1691 "Mismatch between function args and call args"); 1692 CI->replaceAllUsesWith(Builder.CreateCall( 1693 NewFn, {CI->getArgOperand(0), Builder.getFalse()}, Name)); 1694 CI->eraseFromParent(); 1695 return; 1696 1697 case Intrinsic::objectsize: 1698 CI->replaceAllUsesWith(Builder.CreateCall( 1699 NewFn, {CI->getArgOperand(0), CI->getArgOperand(1)}, Name)); 1700 CI->eraseFromParent(); 1701 return; 1702 1703 case Intrinsic::ctpop: { 1704 CI->replaceAllUsesWith(Builder.CreateCall(NewFn, {CI->getArgOperand(0)})); 1705 CI->eraseFromParent(); 1706 return; 1707 } 1708 1709 case Intrinsic::x86_xop_vfrcz_ss: 1710 case Intrinsic::x86_xop_vfrcz_sd: 1711 CI->replaceAllUsesWith( 1712 Builder.CreateCall(NewFn, {CI->getArgOperand(1)}, Name)); 1713 CI->eraseFromParent(); 1714 return; 1715 1716 case Intrinsic::x86_xop_vpermil2pd: 1717 case Intrinsic::x86_xop_vpermil2ps: 1718 case Intrinsic::x86_xop_vpermil2pd_256: 1719 case Intrinsic::x86_xop_vpermil2ps_256: { 1720 SmallVector<Value *, 4> Args(CI->arg_operands().begin(), 1721 CI->arg_operands().end()); 1722 VectorType *FltIdxTy = cast<VectorType>(Args[2]->getType()); 1723 VectorType *IntIdxTy = VectorType::getInteger(FltIdxTy); 1724 Args[2] = Builder.CreateBitCast(Args[2], IntIdxTy); 1725 CI->replaceAllUsesWith(Builder.CreateCall(NewFn, Args, Name)); 1726 CI->eraseFromParent(); 1727 return; 1728 } 1729 1730 case Intrinsic::x86_sse41_ptestc: 1731 case Intrinsic::x86_sse41_ptestz: 1732 case Intrinsic::x86_sse41_ptestnzc: { 1733 // The arguments for these intrinsics used to be v4f32, and changed 1734 // to v2i64. This is purely a nop, since those are bitwise intrinsics. 1735 // So, the only thing required is a bitcast for both arguments. 1736 // First, check the arguments have the old type. 1737 Value *Arg0 = CI->getArgOperand(0); 1738 if (Arg0->getType() != VectorType::get(Type::getFloatTy(C), 4)) 1739 return; 1740 1741 // Old intrinsic, add bitcasts 1742 Value *Arg1 = CI->getArgOperand(1); 1743 1744 Type *NewVecTy = VectorType::get(Type::getInt64Ty(C), 2); 1745 1746 Value *BC0 = Builder.CreateBitCast(Arg0, NewVecTy, "cast"); 1747 Value *BC1 = Builder.CreateBitCast(Arg1, NewVecTy, "cast"); 1748 1749 CallInst *NewCall = Builder.CreateCall(NewFn, {BC0, BC1}, Name); 1750 CI->replaceAllUsesWith(NewCall); 1751 CI->eraseFromParent(); 1752 return; 1753 } 1754 1755 case Intrinsic::x86_sse41_insertps: 1756 case Intrinsic::x86_sse41_dppd: 1757 case Intrinsic::x86_sse41_dpps: 1758 case Intrinsic::x86_sse41_mpsadbw: 1759 case Intrinsic::x86_avx_dp_ps_256: 1760 case Intrinsic::x86_avx2_mpsadbw: { 1761 // Need to truncate the last argument from i32 to i8 -- this argument models 1762 // an inherently 8-bit immediate operand to these x86 instructions. 1763 SmallVector<Value *, 4> Args(CI->arg_operands().begin(), 1764 CI->arg_operands().end()); 1765 1766 // Replace the last argument with a trunc. 1767 Args.back() = Builder.CreateTrunc(Args.back(), Type::getInt8Ty(C), "trunc"); 1768 1769 CallInst *NewCall = Builder.CreateCall(NewFn, Args); 1770 CI->replaceAllUsesWith(NewCall); 1771 CI->eraseFromParent(); 1772 return; 1773 } 1774 1775 case Intrinsic::thread_pointer: { 1776 CI->replaceAllUsesWith(Builder.CreateCall(NewFn, {})); 1777 CI->eraseFromParent(); 1778 return; 1779 } 1780 1781 case Intrinsic::invariant_start: 1782 case Intrinsic::invariant_end: 1783 case Intrinsic::masked_load: 1784 case Intrinsic::masked_store: { 1785 SmallVector<Value *, 4> Args(CI->arg_operands().begin(), 1786 CI->arg_operands().end()); 1787 CI->replaceAllUsesWith(Builder.CreateCall(NewFn, Args)); 1788 CI->eraseFromParent(); 1789 return; 1790 } 1791 } 1792 } 1793 1794 void llvm::UpgradeCallsToIntrinsic(Function *F) { 1795 assert(F && "Illegal attempt to upgrade a non-existent intrinsic."); 1796 1797 // Check if this function should be upgraded and get the replacement function 1798 // if there is one. 1799 Function *NewFn; 1800 if (UpgradeIntrinsicFunction(F, NewFn)) { 1801 // Replace all users of the old function with the new function or new 1802 // instructions. This is not a range loop because the call is deleted. 1803 for (auto UI = F->user_begin(), UE = F->user_end(); UI != UE; ) 1804 if (CallInst *CI = dyn_cast<CallInst>(*UI++)) 1805 UpgradeIntrinsicCall(CI, NewFn); 1806 1807 // Remove old function, no longer used, from the module. 1808 F->eraseFromParent(); 1809 } 1810 } 1811 1812 MDNode *llvm::UpgradeTBAANode(MDNode &MD) { 1813 // Check if the tag uses struct-path aware TBAA format. 1814 if (isa<MDNode>(MD.getOperand(0)) && MD.getNumOperands() >= 3) 1815 return &MD; 1816 1817 auto &Context = MD.getContext(); 1818 if (MD.getNumOperands() == 3) { 1819 Metadata *Elts[] = {MD.getOperand(0), MD.getOperand(1)}; 1820 MDNode *ScalarType = MDNode::get(Context, Elts); 1821 // Create a MDNode <ScalarType, ScalarType, offset 0, const> 1822 Metadata *Elts2[] = {ScalarType, ScalarType, 1823 ConstantAsMetadata::get( 1824 Constant::getNullValue(Type::getInt64Ty(Context))), 1825 MD.getOperand(2)}; 1826 return MDNode::get(Context, Elts2); 1827 } 1828 // Create a MDNode <MD, MD, offset 0> 1829 Metadata *Elts[] = {&MD, &MD, ConstantAsMetadata::get(Constant::getNullValue( 1830 Type::getInt64Ty(Context)))}; 1831 return MDNode::get(Context, Elts); 1832 } 1833 1834 Instruction *llvm::UpgradeBitCastInst(unsigned Opc, Value *V, Type *DestTy, 1835 Instruction *&Temp) { 1836 if (Opc != Instruction::BitCast) 1837 return nullptr; 1838 1839 Temp = nullptr; 1840 Type *SrcTy = V->getType(); 1841 if (SrcTy->isPtrOrPtrVectorTy() && DestTy->isPtrOrPtrVectorTy() && 1842 SrcTy->getPointerAddressSpace() != DestTy->getPointerAddressSpace()) { 1843 LLVMContext &Context = V->getContext(); 1844 1845 // We have no information about target data layout, so we assume that 1846 // the maximum pointer size is 64bit. 1847 Type *MidTy = Type::getInt64Ty(Context); 1848 Temp = CastInst::Create(Instruction::PtrToInt, V, MidTy); 1849 1850 return CastInst::Create(Instruction::IntToPtr, Temp, DestTy); 1851 } 1852 1853 return nullptr; 1854 } 1855 1856 Value *llvm::UpgradeBitCastExpr(unsigned Opc, Constant *C, Type *DestTy) { 1857 if (Opc != Instruction::BitCast) 1858 return nullptr; 1859 1860 Type *SrcTy = C->getType(); 1861 if (SrcTy->isPtrOrPtrVectorTy() && DestTy->isPtrOrPtrVectorTy() && 1862 SrcTy->getPointerAddressSpace() != DestTy->getPointerAddressSpace()) { 1863 LLVMContext &Context = C->getContext(); 1864 1865 // We have no information about target data layout, so we assume that 1866 // the maximum pointer size is 64bit. 1867 Type *MidTy = Type::getInt64Ty(Context); 1868 1869 return ConstantExpr::getIntToPtr(ConstantExpr::getPtrToInt(C, MidTy), 1870 DestTy); 1871 } 1872 1873 return nullptr; 1874 } 1875 1876 /// Check the debug info version number, if it is out-dated, drop the debug 1877 /// info. Return true if module is modified. 1878 bool llvm::UpgradeDebugInfo(Module &M) { 1879 unsigned Version = getDebugMetadataVersionFromModule(M); 1880 if (Version == DEBUG_METADATA_VERSION) 1881 return false; 1882 1883 bool RetCode = StripDebugInfo(M); 1884 if (RetCode) { 1885 DiagnosticInfoDebugMetadataVersion DiagVersion(M, Version); 1886 M.getContext().diagnose(DiagVersion); 1887 } 1888 return RetCode; 1889 } 1890 1891 bool llvm::UpgradeModuleFlags(Module &M) { 1892 const NamedMDNode *ModFlags = M.getModuleFlagsMetadata(); 1893 if (!ModFlags) 1894 return false; 1895 1896 bool HasObjCFlag = false, HasClassProperties = false; 1897 for (unsigned I = 0, E = ModFlags->getNumOperands(); I != E; ++I) { 1898 MDNode *Op = ModFlags->getOperand(I); 1899 if (Op->getNumOperands() < 2) 1900 continue; 1901 MDString *ID = dyn_cast_or_null<MDString>(Op->getOperand(1)); 1902 if (!ID) 1903 continue; 1904 if (ID->getString() == "Objective-C Image Info Version") 1905 HasObjCFlag = true; 1906 if (ID->getString() == "Objective-C Class Properties") 1907 HasClassProperties = true; 1908 } 1909 // "Objective-C Class Properties" is recently added for Objective-C. We 1910 // upgrade ObjC bitcodes to contain a "Objective-C Class Properties" module 1911 // flag of value 0, so we can correclty downgrade this flag when trying to 1912 // link an ObjC bitcode without this module flag with an ObjC bitcode with 1913 // this module flag. 1914 if (HasObjCFlag && !HasClassProperties) { 1915 M.addModuleFlag(llvm::Module::Override, "Objective-C Class Properties", 1916 (uint32_t)0); 1917 return true; 1918 } 1919 return false; 1920 } 1921 1922 static bool isOldLoopArgument(Metadata *MD) { 1923 auto *T = dyn_cast_or_null<MDTuple>(MD); 1924 if (!T) 1925 return false; 1926 if (T->getNumOperands() < 1) 1927 return false; 1928 auto *S = dyn_cast_or_null<MDString>(T->getOperand(0)); 1929 if (!S) 1930 return false; 1931 return S->getString().startswith("llvm.vectorizer."); 1932 } 1933 1934 static MDString *upgradeLoopTag(LLVMContext &C, StringRef OldTag) { 1935 StringRef OldPrefix = "llvm.vectorizer."; 1936 assert(OldTag.startswith(OldPrefix) && "Expected old prefix"); 1937 1938 if (OldTag == "llvm.vectorizer.unroll") 1939 return MDString::get(C, "llvm.loop.interleave.count"); 1940 1941 return MDString::get( 1942 C, (Twine("llvm.loop.vectorize.") + OldTag.drop_front(OldPrefix.size())) 1943 .str()); 1944 } 1945 1946 static Metadata *upgradeLoopArgument(Metadata *MD) { 1947 auto *T = dyn_cast_or_null<MDTuple>(MD); 1948 if (!T) 1949 return MD; 1950 if (T->getNumOperands() < 1) 1951 return MD; 1952 auto *OldTag = dyn_cast_or_null<MDString>(T->getOperand(0)); 1953 if (!OldTag) 1954 return MD; 1955 if (!OldTag->getString().startswith("llvm.vectorizer.")) 1956 return MD; 1957 1958 // This has an old tag. Upgrade it. 1959 SmallVector<Metadata *, 8> Ops; 1960 Ops.reserve(T->getNumOperands()); 1961 Ops.push_back(upgradeLoopTag(T->getContext(), OldTag->getString())); 1962 for (unsigned I = 1, E = T->getNumOperands(); I != E; ++I) 1963 Ops.push_back(T->getOperand(I)); 1964 1965 return MDTuple::get(T->getContext(), Ops); 1966 } 1967 1968 MDNode *llvm::upgradeInstructionLoopAttachment(MDNode &N) { 1969 auto *T = dyn_cast<MDTuple>(&N); 1970 if (!T) 1971 return &N; 1972 1973 if (none_of(T->operands(), isOldLoopArgument)) 1974 return &N; 1975 1976 SmallVector<Metadata *, 8> Ops; 1977 Ops.reserve(T->getNumOperands()); 1978 for (Metadata *MD : T->operands()) 1979 Ops.push_back(upgradeLoopArgument(MD)); 1980 1981 return MDTuple::get(T->getContext(), Ops); 1982 } 1983