1 //===-- AutoUpgrade.cpp - Implement auto-upgrade helper functions ---------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements the auto-upgrade helper functions. 11 // This is where deprecated IR intrinsics and other IR features are updated to 12 // current specifications. 13 // 14 //===----------------------------------------------------------------------===// 15 16 #include "llvm/IR/AutoUpgrade.h" 17 #include "llvm/ADT/StringSwitch.h" 18 #include "llvm/IR/CFG.h" 19 #include "llvm/IR/CallSite.h" 20 #include "llvm/IR/Constants.h" 21 #include "llvm/IR/DIBuilder.h" 22 #include "llvm/IR/DebugInfo.h" 23 #include "llvm/IR/DiagnosticInfo.h" 24 #include "llvm/IR/Function.h" 25 #include "llvm/IR/IRBuilder.h" 26 #include "llvm/IR/Instruction.h" 27 #include "llvm/IR/IntrinsicInst.h" 28 #include "llvm/IR/LLVMContext.h" 29 #include "llvm/IR/Module.h" 30 #include "llvm/IR/Verifier.h" 31 #include "llvm/Support/ErrorHandling.h" 32 #include "llvm/Support/Regex.h" 33 #include <cstring> 34 using namespace llvm; 35 36 static void rename(GlobalValue *GV) { GV->setName(GV->getName() + ".old"); } 37 38 // Upgrade the declarations of the SSE4.1 ptest intrinsics whose arguments have 39 // changed their type from v4f32 to v2i64. 40 static bool UpgradePTESTIntrinsic(Function* F, Intrinsic::ID IID, 41 Function *&NewFn) { 42 // Check whether this is an old version of the function, which received 43 // v4f32 arguments. 44 Type *Arg0Type = F->getFunctionType()->getParamType(0); 45 if (Arg0Type != VectorType::get(Type::getFloatTy(F->getContext()), 4)) 46 return false; 47 48 // Yes, it's old, replace it with new version. 49 rename(F); 50 NewFn = Intrinsic::getDeclaration(F->getParent(), IID); 51 return true; 52 } 53 54 // Upgrade the declarations of intrinsic functions whose 8-bit immediate mask 55 // arguments have changed their type from i32 to i8. 56 static bool UpgradeX86IntrinsicsWith8BitMask(Function *F, Intrinsic::ID IID, 57 Function *&NewFn) { 58 // Check that the last argument is an i32. 59 Type *LastArgType = F->getFunctionType()->getParamType( 60 F->getFunctionType()->getNumParams() - 1); 61 if (!LastArgType->isIntegerTy(32)) 62 return false; 63 64 // Move this function aside and map down. 65 rename(F); 66 NewFn = Intrinsic::getDeclaration(F->getParent(), IID); 67 return true; 68 } 69 70 static bool ShouldUpgradeX86Intrinsic(Function *F, StringRef Name) { 71 // All of the intrinsics matches below should be marked with which llvm 72 // version started autoupgrading them. At some point in the future we would 73 // like to use this information to remove upgrade code for some older 74 // intrinsics. It is currently undecided how we will determine that future 75 // point. 76 if (Name=="ssse3.pabs.b.128" || // Added in 6.0 77 Name=="ssse3.pabs.w.128" || // Added in 6.0 78 Name=="ssse3.pabs.d.128" || // Added in 6.0 79 Name.startswith("avx512.mask.shuf.i") || // Added in 6.0 80 Name.startswith("avx512.mask.shuf.f") || // Added in 6.0 81 Name.startswith("avx512.kunpck") || //added in 6.0 82 Name.startswith("avx2.pabs.") || // Added in 6.0 83 Name.startswith("avx512.mask.pabs.") || // Added in 6.0 84 Name.startswith("avx512.broadcastm") || // Added in 6.0 85 Name.startswith("avx512.mask.pbroadcast") || // Added in 6.0 86 Name.startswith("sse2.pcmpeq.") || // Added in 3.1 87 Name.startswith("sse2.pcmpgt.") || // Added in 3.1 88 Name.startswith("avx2.pcmpeq.") || // Added in 3.1 89 Name.startswith("avx2.pcmpgt.") || // Added in 3.1 90 Name.startswith("avx512.mask.pcmpeq.") || // Added in 3.9 91 Name.startswith("avx512.mask.pcmpgt.") || // Added in 3.9 92 Name.startswith("avx.vperm2f128.") || // Added in 6.0 93 Name == "avx2.vperm2i128" || // Added in 6.0 94 Name == "sse.add.ss" || // Added in 4.0 95 Name == "sse2.add.sd" || // Added in 4.0 96 Name == "sse.sub.ss" || // Added in 4.0 97 Name == "sse2.sub.sd" || // Added in 4.0 98 Name == "sse.mul.ss" || // Added in 4.0 99 Name == "sse2.mul.sd" || // Added in 4.0 100 Name == "sse.div.ss" || // Added in 4.0 101 Name == "sse2.div.sd" || // Added in 4.0 102 Name == "sse41.pmaxsb" || // Added in 3.9 103 Name == "sse2.pmaxs.w" || // Added in 3.9 104 Name == "sse41.pmaxsd" || // Added in 3.9 105 Name == "sse2.pmaxu.b" || // Added in 3.9 106 Name == "sse41.pmaxuw" || // Added in 3.9 107 Name == "sse41.pmaxud" || // Added in 3.9 108 Name == "sse41.pminsb" || // Added in 3.9 109 Name == "sse2.pmins.w" || // Added in 3.9 110 Name == "sse41.pminsd" || // Added in 3.9 111 Name == "sse2.pminu.b" || // Added in 3.9 112 Name == "sse41.pminuw" || // Added in 3.9 113 Name == "sse41.pminud" || // Added in 3.9 114 Name.startswith("avx512.mask.pshuf.b.") || // Added in 4.0 115 Name.startswith("avx2.pmax") || // Added in 3.9 116 Name.startswith("avx2.pmin") || // Added in 3.9 117 Name.startswith("avx512.mask.pmax") || // Added in 4.0 118 Name.startswith("avx512.mask.pmin") || // Added in 4.0 119 Name.startswith("avx2.vbroadcast") || // Added in 3.8 120 Name.startswith("avx2.pbroadcast") || // Added in 3.8 121 Name.startswith("avx.vpermil.") || // Added in 3.1 122 Name.startswith("sse2.pshuf") || // Added in 3.9 123 Name.startswith("avx512.pbroadcast") || // Added in 3.9 124 Name.startswith("avx512.mask.broadcast.s") || // Added in 3.9 125 Name.startswith("avx512.mask.movddup") || // Added in 3.9 126 Name.startswith("avx512.mask.movshdup") || // Added in 3.9 127 Name.startswith("avx512.mask.movsldup") || // Added in 3.9 128 Name.startswith("avx512.mask.pshuf.d.") || // Added in 3.9 129 Name.startswith("avx512.mask.pshufl.w.") || // Added in 3.9 130 Name.startswith("avx512.mask.pshufh.w.") || // Added in 3.9 131 Name.startswith("avx512.mask.shuf.p") || // Added in 4.0 132 Name.startswith("avx512.mask.vpermil.p") || // Added in 3.9 133 Name.startswith("avx512.mask.perm.df.") || // Added in 3.9 134 Name.startswith("avx512.mask.perm.di.") || // Added in 3.9 135 Name.startswith("avx512.mask.punpckl") || // Added in 3.9 136 Name.startswith("avx512.mask.punpckh") || // Added in 3.9 137 Name.startswith("avx512.mask.unpckl.") || // Added in 3.9 138 Name.startswith("avx512.mask.unpckh.") || // Added in 3.9 139 Name.startswith("avx512.mask.pand.") || // Added in 3.9 140 Name.startswith("avx512.mask.pandn.") || // Added in 3.9 141 Name.startswith("avx512.mask.por.") || // Added in 3.9 142 Name.startswith("avx512.mask.pxor.") || // Added in 3.9 143 Name.startswith("avx512.mask.and.") || // Added in 3.9 144 Name.startswith("avx512.mask.andn.") || // Added in 3.9 145 Name.startswith("avx512.mask.or.") || // Added in 3.9 146 Name.startswith("avx512.mask.xor.") || // Added in 3.9 147 Name.startswith("avx512.mask.padd.") || // Added in 4.0 148 Name.startswith("avx512.mask.psub.") || // Added in 4.0 149 Name.startswith("avx512.mask.pmull.") || // Added in 4.0 150 Name.startswith("avx512.mask.cvtdq2pd.") || // Added in 4.0 151 Name.startswith("avx512.mask.cvtudq2pd.") || // Added in 4.0 152 Name.startswith("avx512.mask.pmul.dq.") || // Added in 4.0 153 Name.startswith("avx512.mask.pmulu.dq.") || // Added in 4.0 154 Name.startswith("avx512.mask.packsswb.") || // Added in 5.0 155 Name.startswith("avx512.mask.packssdw.") || // Added in 5.0 156 Name.startswith("avx512.mask.packuswb.") || // Added in 5.0 157 Name.startswith("avx512.mask.packusdw.") || // Added in 5.0 158 Name.startswith("avx512.mask.cmp.b") || // Added in 5.0 159 Name.startswith("avx512.mask.cmp.d") || // Added in 5.0 160 Name.startswith("avx512.mask.cmp.q") || // Added in 5.0 161 Name.startswith("avx512.mask.cmp.w") || // Added in 5.0 162 Name.startswith("avx512.mask.ucmp.") || // Added in 5.0 163 Name == "avx512.mask.add.pd.128" || // Added in 4.0 164 Name == "avx512.mask.add.pd.256" || // Added in 4.0 165 Name == "avx512.mask.add.ps.128" || // Added in 4.0 166 Name == "avx512.mask.add.ps.256" || // Added in 4.0 167 Name == "avx512.mask.div.pd.128" || // Added in 4.0 168 Name == "avx512.mask.div.pd.256" || // Added in 4.0 169 Name == "avx512.mask.div.ps.128" || // Added in 4.0 170 Name == "avx512.mask.div.ps.256" || // Added in 4.0 171 Name == "avx512.mask.mul.pd.128" || // Added in 4.0 172 Name == "avx512.mask.mul.pd.256" || // Added in 4.0 173 Name == "avx512.mask.mul.ps.128" || // Added in 4.0 174 Name == "avx512.mask.mul.ps.256" || // Added in 4.0 175 Name == "avx512.mask.sub.pd.128" || // Added in 4.0 176 Name == "avx512.mask.sub.pd.256" || // Added in 4.0 177 Name == "avx512.mask.sub.ps.128" || // Added in 4.0 178 Name == "avx512.mask.sub.ps.256" || // Added in 4.0 179 Name == "avx512.mask.max.pd.128" || // Added in 5.0 180 Name == "avx512.mask.max.pd.256" || // Added in 5.0 181 Name == "avx512.mask.max.ps.128" || // Added in 5.0 182 Name == "avx512.mask.max.ps.256" || // Added in 5.0 183 Name == "avx512.mask.min.pd.128" || // Added in 5.0 184 Name == "avx512.mask.min.pd.256" || // Added in 5.0 185 Name == "avx512.mask.min.ps.128" || // Added in 5.0 186 Name == "avx512.mask.min.ps.256" || // Added in 5.0 187 Name.startswith("avx512.mask.vpermilvar.") || // Added in 4.0 188 Name.startswith("avx512.mask.psll.d") || // Added in 4.0 189 Name.startswith("avx512.mask.psll.q") || // Added in 4.0 190 Name.startswith("avx512.mask.psll.w") || // Added in 4.0 191 Name.startswith("avx512.mask.psra.d") || // Added in 4.0 192 Name.startswith("avx512.mask.psra.q") || // Added in 4.0 193 Name.startswith("avx512.mask.psra.w") || // Added in 4.0 194 Name.startswith("avx512.mask.psrl.d") || // Added in 4.0 195 Name.startswith("avx512.mask.psrl.q") || // Added in 4.0 196 Name.startswith("avx512.mask.psrl.w") || // Added in 4.0 197 Name.startswith("avx512.mask.pslli") || // Added in 4.0 198 Name.startswith("avx512.mask.psrai") || // Added in 4.0 199 Name.startswith("avx512.mask.psrli") || // Added in 4.0 200 Name.startswith("avx512.mask.psllv") || // Added in 4.0 201 Name.startswith("avx512.mask.psrav") || // Added in 4.0 202 Name.startswith("avx512.mask.psrlv") || // Added in 4.0 203 Name.startswith("sse41.pmovsx") || // Added in 3.8 204 Name.startswith("sse41.pmovzx") || // Added in 3.9 205 Name.startswith("avx2.pmovsx") || // Added in 3.9 206 Name.startswith("avx2.pmovzx") || // Added in 3.9 207 Name.startswith("avx512.mask.pmovsx") || // Added in 4.0 208 Name.startswith("avx512.mask.pmovzx") || // Added in 4.0 209 Name.startswith("avx512.mask.lzcnt.") || // Added in 5.0 210 Name == "sse2.cvtdq2pd" || // Added in 3.9 211 Name == "sse2.cvtps2pd" || // Added in 3.9 212 Name == "avx.cvtdq2.pd.256" || // Added in 3.9 213 Name == "avx.cvt.ps2.pd.256" || // Added in 3.9 214 Name.startswith("avx.vinsertf128.") || // Added in 3.7 215 Name == "avx2.vinserti128" || // Added in 3.7 216 Name.startswith("avx512.mask.insert") || // Added in 4.0 217 Name.startswith("avx.vextractf128.") || // Added in 3.7 218 Name == "avx2.vextracti128" || // Added in 3.7 219 Name.startswith("avx512.mask.vextract") || // Added in 4.0 220 Name.startswith("sse4a.movnt.") || // Added in 3.9 221 Name.startswith("avx.movnt.") || // Added in 3.2 222 Name.startswith("avx512.storent.") || // Added in 3.9 223 Name == "sse41.movntdqa" || // Added in 5.0 224 Name == "avx2.movntdqa" || // Added in 5.0 225 Name == "avx512.movntdqa" || // Added in 5.0 226 Name == "sse2.storel.dq" || // Added in 3.9 227 Name.startswith("sse.storeu.") || // Added in 3.9 228 Name.startswith("sse2.storeu.") || // Added in 3.9 229 Name.startswith("avx.storeu.") || // Added in 3.9 230 Name.startswith("avx512.mask.storeu.") || // Added in 3.9 231 Name.startswith("avx512.mask.store.p") || // Added in 3.9 232 Name.startswith("avx512.mask.store.b.") || // Added in 3.9 233 Name.startswith("avx512.mask.store.w.") || // Added in 3.9 234 Name.startswith("avx512.mask.store.d.") || // Added in 3.9 235 Name.startswith("avx512.mask.store.q.") || // Added in 3.9 236 Name.startswith("avx512.mask.loadu.") || // Added in 3.9 237 Name.startswith("avx512.mask.load.") || // Added in 3.9 238 Name == "sse42.crc32.64.8" || // Added in 3.4 239 Name.startswith("avx.vbroadcast.s") || // Added in 3.5 240 Name.startswith("avx512.mask.palignr.") || // Added in 3.9 241 Name.startswith("avx512.mask.valign.") || // Added in 4.0 242 Name.startswith("sse2.psll.dq") || // Added in 3.7 243 Name.startswith("sse2.psrl.dq") || // Added in 3.7 244 Name.startswith("avx2.psll.dq") || // Added in 3.7 245 Name.startswith("avx2.psrl.dq") || // Added in 3.7 246 Name.startswith("avx512.psll.dq") || // Added in 3.9 247 Name.startswith("avx512.psrl.dq") || // Added in 3.9 248 Name == "sse41.pblendw" || // Added in 3.7 249 Name.startswith("sse41.blendp") || // Added in 3.7 250 Name.startswith("avx.blend.p") || // Added in 3.7 251 Name == "avx2.pblendw" || // Added in 3.7 252 Name.startswith("avx2.pblendd.") || // Added in 3.7 253 Name.startswith("avx.vbroadcastf128") || // Added in 4.0 254 Name == "avx2.vbroadcasti128" || // Added in 3.7 255 Name.startswith("avx512.mask.broadcastf") || // Added in 6.0 256 Name.startswith("avx512.mask.broadcasti") || // Added in 6.0 257 Name == "xop.vpcmov" || // Added in 3.8 258 Name == "xop.vpcmov.256" || // Added in 5.0 259 Name.startswith("avx512.mask.move.s") || // Added in 4.0 260 Name.startswith("avx512.cvtmask2") || // Added in 5.0 261 (Name.startswith("xop.vpcom") && // Added in 3.2 262 F->arg_size() == 2) || 263 Name.startswith("avx512.ptestm") || //Added in 6.0 264 Name.startswith("avx512.ptestnm") || //Added in 6.0 265 Name.startswith("sse2.pavg") || // Added in 6.0 266 Name.startswith("avx2.pavg") || // Added in 6.0 267 Name.startswith("avx512.mask.pavg")) // Added in 6.0 268 return true; 269 270 return false; 271 } 272 273 static bool UpgradeX86IntrinsicFunction(Function *F, StringRef Name, 274 Function *&NewFn) { 275 // Only handle intrinsics that start with "x86.". 276 if (!Name.startswith("x86.")) 277 return false; 278 // Remove "x86." prefix. 279 Name = Name.substr(4); 280 281 if (ShouldUpgradeX86Intrinsic(F, Name)) { 282 NewFn = nullptr; 283 return true; 284 } 285 286 // SSE4.1 ptest functions may have an old signature. 287 if (Name.startswith("sse41.ptest")) { // Added in 3.2 288 if (Name.substr(11) == "c") 289 return UpgradePTESTIntrinsic(F, Intrinsic::x86_sse41_ptestc, NewFn); 290 if (Name.substr(11) == "z") 291 return UpgradePTESTIntrinsic(F, Intrinsic::x86_sse41_ptestz, NewFn); 292 if (Name.substr(11) == "nzc") 293 return UpgradePTESTIntrinsic(F, Intrinsic::x86_sse41_ptestnzc, NewFn); 294 } 295 // Several blend and other instructions with masks used the wrong number of 296 // bits. 297 if (Name == "sse41.insertps") // Added in 3.6 298 return UpgradeX86IntrinsicsWith8BitMask(F, Intrinsic::x86_sse41_insertps, 299 NewFn); 300 if (Name == "sse41.dppd") // Added in 3.6 301 return UpgradeX86IntrinsicsWith8BitMask(F, Intrinsic::x86_sse41_dppd, 302 NewFn); 303 if (Name == "sse41.dpps") // Added in 3.6 304 return UpgradeX86IntrinsicsWith8BitMask(F, Intrinsic::x86_sse41_dpps, 305 NewFn); 306 if (Name == "sse41.mpsadbw") // Added in 3.6 307 return UpgradeX86IntrinsicsWith8BitMask(F, Intrinsic::x86_sse41_mpsadbw, 308 NewFn); 309 if (Name == "avx.dp.ps.256") // Added in 3.6 310 return UpgradeX86IntrinsicsWith8BitMask(F, Intrinsic::x86_avx_dp_ps_256, 311 NewFn); 312 if (Name == "avx2.mpsadbw") // Added in 3.6 313 return UpgradeX86IntrinsicsWith8BitMask(F, Intrinsic::x86_avx2_mpsadbw, 314 NewFn); 315 316 // frcz.ss/sd may need to have an argument dropped. Added in 3.2 317 if (Name.startswith("xop.vfrcz.ss") && F->arg_size() == 2) { 318 rename(F); 319 NewFn = Intrinsic::getDeclaration(F->getParent(), 320 Intrinsic::x86_xop_vfrcz_ss); 321 return true; 322 } 323 if (Name.startswith("xop.vfrcz.sd") && F->arg_size() == 2) { 324 rename(F); 325 NewFn = Intrinsic::getDeclaration(F->getParent(), 326 Intrinsic::x86_xop_vfrcz_sd); 327 return true; 328 } 329 // Upgrade any XOP PERMIL2 index operand still using a float/double vector. 330 if (Name.startswith("xop.vpermil2")) { // Added in 3.9 331 auto Idx = F->getFunctionType()->getParamType(2); 332 if (Idx->isFPOrFPVectorTy()) { 333 rename(F); 334 unsigned IdxSize = Idx->getPrimitiveSizeInBits(); 335 unsigned EltSize = Idx->getScalarSizeInBits(); 336 Intrinsic::ID Permil2ID; 337 if (EltSize == 64 && IdxSize == 128) 338 Permil2ID = Intrinsic::x86_xop_vpermil2pd; 339 else if (EltSize == 32 && IdxSize == 128) 340 Permil2ID = Intrinsic::x86_xop_vpermil2ps; 341 else if (EltSize == 64 && IdxSize == 256) 342 Permil2ID = Intrinsic::x86_xop_vpermil2pd_256; 343 else 344 Permil2ID = Intrinsic::x86_xop_vpermil2ps_256; 345 NewFn = Intrinsic::getDeclaration(F->getParent(), Permil2ID); 346 return true; 347 } 348 } 349 350 return false; 351 } 352 353 static bool UpgradeIntrinsicFunction1(Function *F, Function *&NewFn) { 354 assert(F && "Illegal to upgrade a non-existent Function."); 355 356 // Quickly eliminate it, if it's not a candidate. 357 StringRef Name = F->getName(); 358 if (Name.size() <= 8 || !Name.startswith("llvm.")) 359 return false; 360 Name = Name.substr(5); // Strip off "llvm." 361 362 switch (Name[0]) { 363 default: break; 364 case 'a': { 365 if (Name.startswith("arm.rbit") || Name.startswith("aarch64.rbit")) { 366 NewFn = Intrinsic::getDeclaration(F->getParent(), Intrinsic::bitreverse, 367 F->arg_begin()->getType()); 368 return true; 369 } 370 if (Name.startswith("arm.neon.vclz")) { 371 Type* args[2] = { 372 F->arg_begin()->getType(), 373 Type::getInt1Ty(F->getContext()) 374 }; 375 // Can't use Intrinsic::getDeclaration here as it adds a ".i1" to 376 // the end of the name. Change name from llvm.arm.neon.vclz.* to 377 // llvm.ctlz.* 378 FunctionType* fType = FunctionType::get(F->getReturnType(), args, false); 379 NewFn = Function::Create(fType, F->getLinkage(), 380 "llvm.ctlz." + Name.substr(14), F->getParent()); 381 return true; 382 } 383 if (Name.startswith("arm.neon.vcnt")) { 384 NewFn = Intrinsic::getDeclaration(F->getParent(), Intrinsic::ctpop, 385 F->arg_begin()->getType()); 386 return true; 387 } 388 Regex vldRegex("^arm\\.neon\\.vld([1234]|[234]lane)\\.v[a-z0-9]*$"); 389 if (vldRegex.match(Name)) { 390 auto fArgs = F->getFunctionType()->params(); 391 SmallVector<Type *, 4> Tys(fArgs.begin(), fArgs.end()); 392 // Can't use Intrinsic::getDeclaration here as the return types might 393 // then only be structurally equal. 394 FunctionType* fType = FunctionType::get(F->getReturnType(), Tys, false); 395 NewFn = Function::Create(fType, F->getLinkage(), 396 "llvm." + Name + ".p0i8", F->getParent()); 397 return true; 398 } 399 Regex vstRegex("^arm\\.neon\\.vst([1234]|[234]lane)\\.v[a-z0-9]*$"); 400 if (vstRegex.match(Name)) { 401 static const Intrinsic::ID StoreInts[] = {Intrinsic::arm_neon_vst1, 402 Intrinsic::arm_neon_vst2, 403 Intrinsic::arm_neon_vst3, 404 Intrinsic::arm_neon_vst4}; 405 406 static const Intrinsic::ID StoreLaneInts[] = { 407 Intrinsic::arm_neon_vst2lane, Intrinsic::arm_neon_vst3lane, 408 Intrinsic::arm_neon_vst4lane 409 }; 410 411 auto fArgs = F->getFunctionType()->params(); 412 Type *Tys[] = {fArgs[0], fArgs[1]}; 413 if (Name.find("lane") == StringRef::npos) 414 NewFn = Intrinsic::getDeclaration(F->getParent(), 415 StoreInts[fArgs.size() - 3], Tys); 416 else 417 NewFn = Intrinsic::getDeclaration(F->getParent(), 418 StoreLaneInts[fArgs.size() - 5], Tys); 419 return true; 420 } 421 if (Name == "aarch64.thread.pointer" || Name == "arm.thread.pointer") { 422 NewFn = Intrinsic::getDeclaration(F->getParent(), Intrinsic::thread_pointer); 423 return true; 424 } 425 break; 426 } 427 428 case 'c': { 429 if (Name.startswith("ctlz.") && F->arg_size() == 1) { 430 rename(F); 431 NewFn = Intrinsic::getDeclaration(F->getParent(), Intrinsic::ctlz, 432 F->arg_begin()->getType()); 433 return true; 434 } 435 if (Name.startswith("cttz.") && F->arg_size() == 1) { 436 rename(F); 437 NewFn = Intrinsic::getDeclaration(F->getParent(), Intrinsic::cttz, 438 F->arg_begin()->getType()); 439 return true; 440 } 441 break; 442 } 443 case 'd': { 444 if (Name == "dbg.value" && F->arg_size() == 4) { 445 rename(F); 446 NewFn = Intrinsic::getDeclaration(F->getParent(), Intrinsic::dbg_value); 447 return true; 448 } 449 break; 450 } 451 case 'i': 452 case 'l': { 453 bool IsLifetimeStart = Name.startswith("lifetime.start"); 454 if (IsLifetimeStart || Name.startswith("invariant.start")) { 455 Intrinsic::ID ID = IsLifetimeStart ? 456 Intrinsic::lifetime_start : Intrinsic::invariant_start; 457 auto Args = F->getFunctionType()->params(); 458 Type* ObjectPtr[1] = {Args[1]}; 459 if (F->getName() != Intrinsic::getName(ID, ObjectPtr)) { 460 rename(F); 461 NewFn = Intrinsic::getDeclaration(F->getParent(), ID, ObjectPtr); 462 return true; 463 } 464 } 465 466 bool IsLifetimeEnd = Name.startswith("lifetime.end"); 467 if (IsLifetimeEnd || Name.startswith("invariant.end")) { 468 Intrinsic::ID ID = IsLifetimeEnd ? 469 Intrinsic::lifetime_end : Intrinsic::invariant_end; 470 471 auto Args = F->getFunctionType()->params(); 472 Type* ObjectPtr[1] = {Args[IsLifetimeEnd ? 1 : 2]}; 473 if (F->getName() != Intrinsic::getName(ID, ObjectPtr)) { 474 rename(F); 475 NewFn = Intrinsic::getDeclaration(F->getParent(), ID, ObjectPtr); 476 return true; 477 } 478 } 479 break; 480 } 481 case 'm': { 482 if (Name.startswith("masked.load.")) { 483 Type *Tys[] = { F->getReturnType(), F->arg_begin()->getType() }; 484 if (F->getName() != Intrinsic::getName(Intrinsic::masked_load, Tys)) { 485 rename(F); 486 NewFn = Intrinsic::getDeclaration(F->getParent(), 487 Intrinsic::masked_load, 488 Tys); 489 return true; 490 } 491 } 492 if (Name.startswith("masked.store.")) { 493 auto Args = F->getFunctionType()->params(); 494 Type *Tys[] = { Args[0], Args[1] }; 495 if (F->getName() != Intrinsic::getName(Intrinsic::masked_store, Tys)) { 496 rename(F); 497 NewFn = Intrinsic::getDeclaration(F->getParent(), 498 Intrinsic::masked_store, 499 Tys); 500 return true; 501 } 502 } 503 // Renaming gather/scatter intrinsics with no address space overloading 504 // to the new overload which includes an address space 505 if (Name.startswith("masked.gather.")) { 506 Type *Tys[] = {F->getReturnType(), F->arg_begin()->getType()}; 507 if (F->getName() != Intrinsic::getName(Intrinsic::masked_gather, Tys)) { 508 rename(F); 509 NewFn = Intrinsic::getDeclaration(F->getParent(), 510 Intrinsic::masked_gather, Tys); 511 return true; 512 } 513 } 514 if (Name.startswith("masked.scatter.")) { 515 auto Args = F->getFunctionType()->params(); 516 Type *Tys[] = {Args[0], Args[1]}; 517 if (F->getName() != Intrinsic::getName(Intrinsic::masked_scatter, Tys)) { 518 rename(F); 519 NewFn = Intrinsic::getDeclaration(F->getParent(), 520 Intrinsic::masked_scatter, Tys); 521 return true; 522 } 523 } 524 break; 525 } 526 case 'n': { 527 if (Name.startswith("nvvm.")) { 528 Name = Name.substr(5); 529 530 // The following nvvm intrinsics correspond exactly to an LLVM intrinsic. 531 Intrinsic::ID IID = StringSwitch<Intrinsic::ID>(Name) 532 .Cases("brev32", "brev64", Intrinsic::bitreverse) 533 .Case("clz.i", Intrinsic::ctlz) 534 .Case("popc.i", Intrinsic::ctpop) 535 .Default(Intrinsic::not_intrinsic); 536 if (IID != Intrinsic::not_intrinsic && F->arg_size() == 1) { 537 NewFn = Intrinsic::getDeclaration(F->getParent(), IID, 538 {F->getReturnType()}); 539 return true; 540 } 541 542 // The following nvvm intrinsics correspond exactly to an LLVM idiom, but 543 // not to an intrinsic alone. We expand them in UpgradeIntrinsicCall. 544 // 545 // TODO: We could add lohi.i2d. 546 bool Expand = StringSwitch<bool>(Name) 547 .Cases("abs.i", "abs.ll", true) 548 .Cases("clz.ll", "popc.ll", "h2f", true) 549 .Cases("max.i", "max.ll", "max.ui", "max.ull", true) 550 .Cases("min.i", "min.ll", "min.ui", "min.ull", true) 551 .Default(false); 552 if (Expand) { 553 NewFn = nullptr; 554 return true; 555 } 556 } 557 break; 558 } 559 case 'o': 560 // We only need to change the name to match the mangling including the 561 // address space. 562 if (Name.startswith("objectsize.")) { 563 Type *Tys[2] = { F->getReturnType(), F->arg_begin()->getType() }; 564 if (F->arg_size() == 2 || 565 F->getName() != Intrinsic::getName(Intrinsic::objectsize, Tys)) { 566 rename(F); 567 NewFn = Intrinsic::getDeclaration(F->getParent(), Intrinsic::objectsize, 568 Tys); 569 return true; 570 } 571 } 572 break; 573 574 case 's': 575 if (Name == "stackprotectorcheck") { 576 NewFn = nullptr; 577 return true; 578 } 579 break; 580 581 case 'x': 582 if (UpgradeX86IntrinsicFunction(F, Name, NewFn)) 583 return true; 584 } 585 // Remangle our intrinsic since we upgrade the mangling 586 auto Result = llvm::Intrinsic::remangleIntrinsicFunction(F); 587 if (Result != None) { 588 NewFn = Result.getValue(); 589 return true; 590 } 591 592 // This may not belong here. This function is effectively being overloaded 593 // to both detect an intrinsic which needs upgrading, and to provide the 594 // upgraded form of the intrinsic. We should perhaps have two separate 595 // functions for this. 596 return false; 597 } 598 599 bool llvm::UpgradeIntrinsicFunction(Function *F, Function *&NewFn) { 600 NewFn = nullptr; 601 bool Upgraded = UpgradeIntrinsicFunction1(F, NewFn); 602 assert(F != NewFn && "Intrinsic function upgraded to the same function"); 603 604 // Upgrade intrinsic attributes. This does not change the function. 605 if (NewFn) 606 F = NewFn; 607 if (Intrinsic::ID id = F->getIntrinsicID()) 608 F->setAttributes(Intrinsic::getAttributes(F->getContext(), id)); 609 return Upgraded; 610 } 611 612 bool llvm::UpgradeGlobalVariable(GlobalVariable *GV) { 613 // Nothing to do yet. 614 return false; 615 } 616 617 // Handles upgrading SSE2/AVX2/AVX512BW PSLLDQ intrinsics by converting them 618 // to byte shuffles. 619 static Value *UpgradeX86PSLLDQIntrinsics(IRBuilder<> &Builder, 620 Value *Op, unsigned Shift) { 621 Type *ResultTy = Op->getType(); 622 unsigned NumElts = ResultTy->getVectorNumElements() * 8; 623 624 // Bitcast from a 64-bit element type to a byte element type. 625 Type *VecTy = VectorType::get(Builder.getInt8Ty(), NumElts); 626 Op = Builder.CreateBitCast(Op, VecTy, "cast"); 627 628 // We'll be shuffling in zeroes. 629 Value *Res = Constant::getNullValue(VecTy); 630 631 // If shift is less than 16, emit a shuffle to move the bytes. Otherwise, 632 // we'll just return the zero vector. 633 if (Shift < 16) { 634 uint32_t Idxs[64]; 635 // 256/512-bit version is split into 2/4 16-byte lanes. 636 for (unsigned l = 0; l != NumElts; l += 16) 637 for (unsigned i = 0; i != 16; ++i) { 638 unsigned Idx = NumElts + i - Shift; 639 if (Idx < NumElts) 640 Idx -= NumElts - 16; // end of lane, switch operand. 641 Idxs[l + i] = Idx + l; 642 } 643 644 Res = Builder.CreateShuffleVector(Res, Op, makeArrayRef(Idxs, NumElts)); 645 } 646 647 // Bitcast back to a 64-bit element type. 648 return Builder.CreateBitCast(Res, ResultTy, "cast"); 649 } 650 651 // Handles upgrading SSE2/AVX2/AVX512BW PSRLDQ intrinsics by converting them 652 // to byte shuffles. 653 static Value *UpgradeX86PSRLDQIntrinsics(IRBuilder<> &Builder, Value *Op, 654 unsigned Shift) { 655 Type *ResultTy = Op->getType(); 656 unsigned NumElts = ResultTy->getVectorNumElements() * 8; 657 658 // Bitcast from a 64-bit element type to a byte element type. 659 Type *VecTy = VectorType::get(Builder.getInt8Ty(), NumElts); 660 Op = Builder.CreateBitCast(Op, VecTy, "cast"); 661 662 // We'll be shuffling in zeroes. 663 Value *Res = Constant::getNullValue(VecTy); 664 665 // If shift is less than 16, emit a shuffle to move the bytes. Otherwise, 666 // we'll just return the zero vector. 667 if (Shift < 16) { 668 uint32_t Idxs[64]; 669 // 256/512-bit version is split into 2/4 16-byte lanes. 670 for (unsigned l = 0; l != NumElts; l += 16) 671 for (unsigned i = 0; i != 16; ++i) { 672 unsigned Idx = i + Shift; 673 if (Idx >= 16) 674 Idx += NumElts - 16; // end of lane, switch operand. 675 Idxs[l + i] = Idx + l; 676 } 677 678 Res = Builder.CreateShuffleVector(Op, Res, makeArrayRef(Idxs, NumElts)); 679 } 680 681 // Bitcast back to a 64-bit element type. 682 return Builder.CreateBitCast(Res, ResultTy, "cast"); 683 } 684 685 static Value *getX86MaskVec(IRBuilder<> &Builder, Value *Mask, 686 unsigned NumElts) { 687 llvm::VectorType *MaskTy = llvm::VectorType::get(Builder.getInt1Ty(), 688 cast<IntegerType>(Mask->getType())->getBitWidth()); 689 Mask = Builder.CreateBitCast(Mask, MaskTy); 690 691 // If we have less than 8 elements, then the starting mask was an i8 and 692 // we need to extract down to the right number of elements. 693 if (NumElts < 8) { 694 uint32_t Indices[4]; 695 for (unsigned i = 0; i != NumElts; ++i) 696 Indices[i] = i; 697 Mask = Builder.CreateShuffleVector(Mask, Mask, 698 makeArrayRef(Indices, NumElts), 699 "extract"); 700 } 701 702 return Mask; 703 } 704 705 static Value *EmitX86Select(IRBuilder<> &Builder, Value *Mask, 706 Value *Op0, Value *Op1) { 707 // If the mask is all ones just emit the align operation. 708 if (const auto *C = dyn_cast<Constant>(Mask)) 709 if (C->isAllOnesValue()) 710 return Op0; 711 712 Mask = getX86MaskVec(Builder, Mask, Op0->getType()->getVectorNumElements()); 713 return Builder.CreateSelect(Mask, Op0, Op1); 714 } 715 716 // Handle autoupgrade for masked PALIGNR and VALIGND/Q intrinsics. 717 // PALIGNR handles large immediates by shifting while VALIGN masks the immediate 718 // so we need to handle both cases. VALIGN also doesn't have 128-bit lanes. 719 static Value *UpgradeX86ALIGNIntrinsics(IRBuilder<> &Builder, Value *Op0, 720 Value *Op1, Value *Shift, 721 Value *Passthru, Value *Mask, 722 bool IsVALIGN) { 723 unsigned ShiftVal = cast<llvm::ConstantInt>(Shift)->getZExtValue(); 724 725 unsigned NumElts = Op0->getType()->getVectorNumElements(); 726 assert((IsVALIGN || NumElts % 16 == 0) && "Illegal NumElts for PALIGNR!"); 727 assert((!IsVALIGN || NumElts <= 16) && "NumElts too large for VALIGN!"); 728 assert(isPowerOf2_32(NumElts) && "NumElts not a power of 2!"); 729 730 // Mask the immediate for VALIGN. 731 if (IsVALIGN) 732 ShiftVal &= (NumElts - 1); 733 734 // If palignr is shifting the pair of vectors more than the size of two 735 // lanes, emit zero. 736 if (ShiftVal >= 32) 737 return llvm::Constant::getNullValue(Op0->getType()); 738 739 // If palignr is shifting the pair of input vectors more than one lane, 740 // but less than two lanes, convert to shifting in zeroes. 741 if (ShiftVal > 16) { 742 ShiftVal -= 16; 743 Op1 = Op0; 744 Op0 = llvm::Constant::getNullValue(Op0->getType()); 745 } 746 747 uint32_t Indices[64]; 748 // 256-bit palignr operates on 128-bit lanes so we need to handle that 749 for (unsigned l = 0; l < NumElts; l += 16) { 750 for (unsigned i = 0; i != 16; ++i) { 751 unsigned Idx = ShiftVal + i; 752 if (!IsVALIGN && Idx >= 16) // Disable wrap for VALIGN. 753 Idx += NumElts - 16; // End of lane, switch operand. 754 Indices[l + i] = Idx + l; 755 } 756 } 757 758 Value *Align = Builder.CreateShuffleVector(Op1, Op0, 759 makeArrayRef(Indices, NumElts), 760 "palignr"); 761 762 return EmitX86Select(Builder, Mask, Align, Passthru); 763 } 764 765 static Value *UpgradeMaskedStore(IRBuilder<> &Builder, 766 Value *Ptr, Value *Data, Value *Mask, 767 bool Aligned) { 768 // Cast the pointer to the right type. 769 Ptr = Builder.CreateBitCast(Ptr, 770 llvm::PointerType::getUnqual(Data->getType())); 771 unsigned Align = 772 Aligned ? cast<VectorType>(Data->getType())->getBitWidth() / 8 : 1; 773 774 // If the mask is all ones just emit a regular store. 775 if (const auto *C = dyn_cast<Constant>(Mask)) 776 if (C->isAllOnesValue()) 777 return Builder.CreateAlignedStore(Data, Ptr, Align); 778 779 // Convert the mask from an integer type to a vector of i1. 780 unsigned NumElts = Data->getType()->getVectorNumElements(); 781 Mask = getX86MaskVec(Builder, Mask, NumElts); 782 return Builder.CreateMaskedStore(Data, Ptr, Align, Mask); 783 } 784 785 static Value *UpgradeMaskedLoad(IRBuilder<> &Builder, 786 Value *Ptr, Value *Passthru, Value *Mask, 787 bool Aligned) { 788 // Cast the pointer to the right type. 789 Ptr = Builder.CreateBitCast(Ptr, 790 llvm::PointerType::getUnqual(Passthru->getType())); 791 unsigned Align = 792 Aligned ? cast<VectorType>(Passthru->getType())->getBitWidth() / 8 : 1; 793 794 // If the mask is all ones just emit a regular store. 795 if (const auto *C = dyn_cast<Constant>(Mask)) 796 if (C->isAllOnesValue()) 797 return Builder.CreateAlignedLoad(Ptr, Align); 798 799 // Convert the mask from an integer type to a vector of i1. 800 unsigned NumElts = Passthru->getType()->getVectorNumElements(); 801 Mask = getX86MaskVec(Builder, Mask, NumElts); 802 return Builder.CreateMaskedLoad(Ptr, Align, Mask, Passthru); 803 } 804 805 static Value *upgradeAbs(IRBuilder<> &Builder, CallInst &CI) { 806 Value *Op0 = CI.getArgOperand(0); 807 llvm::Type *Ty = Op0->getType(); 808 Value *Zero = llvm::Constant::getNullValue(Ty); 809 Value *Cmp = Builder.CreateICmp(ICmpInst::ICMP_SGT, Op0, Zero); 810 Value *Neg = Builder.CreateNeg(Op0); 811 Value *Res = Builder.CreateSelect(Cmp, Op0, Neg); 812 813 if (CI.getNumArgOperands() == 3) 814 Res = EmitX86Select(Builder,CI.getArgOperand(2), Res, CI.getArgOperand(1)); 815 816 return Res; 817 } 818 819 static Value *upgradeIntMinMax(IRBuilder<> &Builder, CallInst &CI, 820 ICmpInst::Predicate Pred) { 821 Value *Op0 = CI.getArgOperand(0); 822 Value *Op1 = CI.getArgOperand(1); 823 Value *Cmp = Builder.CreateICmp(Pred, Op0, Op1); 824 Value *Res = Builder.CreateSelect(Cmp, Op0, Op1); 825 826 if (CI.getNumArgOperands() == 4) 827 Res = EmitX86Select(Builder, CI.getArgOperand(3), Res, CI.getArgOperand(2)); 828 829 return Res; 830 } 831 832 // Applying mask on vector of i1's and make sure result is at least 8 bits wide. 833 static Value *ApplyX86MaskOn1BitsVec(IRBuilder<> &Builder,Value *Vec, Value *Mask, 834 unsigned NumElts) { 835 const auto *C = dyn_cast<Constant>(Mask); 836 if (!C || !C->isAllOnesValue()) 837 Vec = Builder.CreateAnd(Vec, getX86MaskVec(Builder, Mask, NumElts)); 838 839 if (NumElts < 8) { 840 uint32_t Indices[8]; 841 for (unsigned i = 0; i != NumElts; ++i) 842 Indices[i] = i; 843 for (unsigned i = NumElts; i != 8; ++i) 844 Indices[i] = NumElts + i % NumElts; 845 Vec = Builder.CreateShuffleVector(Vec, 846 Constant::getNullValue(Vec->getType()), 847 Indices); 848 } 849 return Builder.CreateBitCast(Vec, Builder.getIntNTy(std::max(NumElts, 8U))); 850 } 851 852 static Value *upgradeMaskedCompare(IRBuilder<> &Builder, CallInst &CI, 853 unsigned CC, bool Signed) { 854 Value *Op0 = CI.getArgOperand(0); 855 unsigned NumElts = Op0->getType()->getVectorNumElements(); 856 857 Value *Cmp; 858 if (CC == 3) { 859 Cmp = Constant::getNullValue(llvm::VectorType::get(Builder.getInt1Ty(), NumElts)); 860 } else if (CC == 7) { 861 Cmp = Constant::getAllOnesValue(llvm::VectorType::get(Builder.getInt1Ty(), NumElts)); 862 } else { 863 ICmpInst::Predicate Pred; 864 switch (CC) { 865 default: llvm_unreachable("Unknown condition code"); 866 case 0: Pred = ICmpInst::ICMP_EQ; break; 867 case 1: Pred = Signed ? ICmpInst::ICMP_SLT : ICmpInst::ICMP_ULT; break; 868 case 2: Pred = Signed ? ICmpInst::ICMP_SLE : ICmpInst::ICMP_ULE; break; 869 case 4: Pred = ICmpInst::ICMP_NE; break; 870 case 5: Pred = Signed ? ICmpInst::ICMP_SGE : ICmpInst::ICMP_UGE; break; 871 case 6: Pred = Signed ? ICmpInst::ICMP_SGT : ICmpInst::ICMP_UGT; break; 872 } 873 Cmp = Builder.CreateICmp(Pred, Op0, CI.getArgOperand(1)); 874 } 875 876 Value *Mask = CI.getArgOperand(CI.getNumArgOperands() - 1); 877 878 return ApplyX86MaskOn1BitsVec(Builder, Cmp, Mask, NumElts); 879 } 880 881 // Replace a masked intrinsic with an older unmasked intrinsic. 882 static Value *UpgradeX86MaskedShift(IRBuilder<> &Builder, CallInst &CI, 883 Intrinsic::ID IID) { 884 Function *F = CI.getCalledFunction(); 885 Function *Intrin = Intrinsic::getDeclaration(F->getParent(), IID); 886 Value *Rep = Builder.CreateCall(Intrin, 887 { CI.getArgOperand(0), CI.getArgOperand(1) }); 888 return EmitX86Select(Builder, CI.getArgOperand(3), Rep, CI.getArgOperand(2)); 889 } 890 891 static Value* upgradeMaskedMove(IRBuilder<> &Builder, CallInst &CI) { 892 Value* A = CI.getArgOperand(0); 893 Value* B = CI.getArgOperand(1); 894 Value* Src = CI.getArgOperand(2); 895 Value* Mask = CI.getArgOperand(3); 896 897 Value* AndNode = Builder.CreateAnd(Mask, APInt(8, 1)); 898 Value* Cmp = Builder.CreateIsNotNull(AndNode); 899 Value* Extract1 = Builder.CreateExtractElement(B, (uint64_t)0); 900 Value* Extract2 = Builder.CreateExtractElement(Src, (uint64_t)0); 901 Value* Select = Builder.CreateSelect(Cmp, Extract1, Extract2); 902 return Builder.CreateInsertElement(A, Select, (uint64_t)0); 903 } 904 905 906 static Value* UpgradeMaskToInt(IRBuilder<> &Builder, CallInst &CI) { 907 Value* Op = CI.getArgOperand(0); 908 Type* ReturnOp = CI.getType(); 909 unsigned NumElts = CI.getType()->getVectorNumElements(); 910 Value *Mask = getX86MaskVec(Builder, Op, NumElts); 911 return Builder.CreateSExt(Mask, ReturnOp, "vpmovm2"); 912 } 913 914 /// Upgrade a call to an old intrinsic. All argument and return casting must be 915 /// provided to seamlessly integrate with existing context. 916 void llvm::UpgradeIntrinsicCall(CallInst *CI, Function *NewFn) { 917 Function *F = CI->getCalledFunction(); 918 LLVMContext &C = CI->getContext(); 919 IRBuilder<> Builder(C); 920 Builder.SetInsertPoint(CI->getParent(), CI->getIterator()); 921 922 assert(F && "Intrinsic call is not direct?"); 923 924 if (!NewFn) { 925 // Get the Function's name. 926 StringRef Name = F->getName(); 927 928 assert(Name.startswith("llvm.") && "Intrinsic doesn't start with 'llvm.'"); 929 Name = Name.substr(5); 930 931 bool IsX86 = Name.startswith("x86."); 932 if (IsX86) 933 Name = Name.substr(4); 934 bool IsNVVM = Name.startswith("nvvm."); 935 if (IsNVVM) 936 Name = Name.substr(5); 937 938 if (IsX86 && Name.startswith("sse4a.movnt.")) { 939 Module *M = F->getParent(); 940 SmallVector<Metadata *, 1> Elts; 941 Elts.push_back( 942 ConstantAsMetadata::get(ConstantInt::get(Type::getInt32Ty(C), 1))); 943 MDNode *Node = MDNode::get(C, Elts); 944 945 Value *Arg0 = CI->getArgOperand(0); 946 Value *Arg1 = CI->getArgOperand(1); 947 948 // Nontemporal (unaligned) store of the 0'th element of the float/double 949 // vector. 950 Type *SrcEltTy = cast<VectorType>(Arg1->getType())->getElementType(); 951 PointerType *EltPtrTy = PointerType::getUnqual(SrcEltTy); 952 Value *Addr = Builder.CreateBitCast(Arg0, EltPtrTy, "cast"); 953 Value *Extract = 954 Builder.CreateExtractElement(Arg1, (uint64_t)0, "extractelement"); 955 956 StoreInst *SI = Builder.CreateAlignedStore(Extract, Addr, 1); 957 SI->setMetadata(M->getMDKindID("nontemporal"), Node); 958 959 // Remove intrinsic. 960 CI->eraseFromParent(); 961 return; 962 } 963 964 if (IsX86 && (Name.startswith("avx.movnt.") || 965 Name.startswith("avx512.storent."))) { 966 Module *M = F->getParent(); 967 SmallVector<Metadata *, 1> Elts; 968 Elts.push_back( 969 ConstantAsMetadata::get(ConstantInt::get(Type::getInt32Ty(C), 1))); 970 MDNode *Node = MDNode::get(C, Elts); 971 972 Value *Arg0 = CI->getArgOperand(0); 973 Value *Arg1 = CI->getArgOperand(1); 974 975 // Convert the type of the pointer to a pointer to the stored type. 976 Value *BC = Builder.CreateBitCast(Arg0, 977 PointerType::getUnqual(Arg1->getType()), 978 "cast"); 979 VectorType *VTy = cast<VectorType>(Arg1->getType()); 980 StoreInst *SI = Builder.CreateAlignedStore(Arg1, BC, 981 VTy->getBitWidth() / 8); 982 SI->setMetadata(M->getMDKindID("nontemporal"), Node); 983 984 // Remove intrinsic. 985 CI->eraseFromParent(); 986 return; 987 } 988 989 if (IsX86 && Name == "sse2.storel.dq") { 990 Value *Arg0 = CI->getArgOperand(0); 991 Value *Arg1 = CI->getArgOperand(1); 992 993 Type *NewVecTy = VectorType::get(Type::getInt64Ty(C), 2); 994 Value *BC0 = Builder.CreateBitCast(Arg1, NewVecTy, "cast"); 995 Value *Elt = Builder.CreateExtractElement(BC0, (uint64_t)0); 996 Value *BC = Builder.CreateBitCast(Arg0, 997 PointerType::getUnqual(Elt->getType()), 998 "cast"); 999 Builder.CreateAlignedStore(Elt, BC, 1); 1000 1001 // Remove intrinsic. 1002 CI->eraseFromParent(); 1003 return; 1004 } 1005 1006 if (IsX86 && (Name.startswith("sse.storeu.") || 1007 Name.startswith("sse2.storeu.") || 1008 Name.startswith("avx.storeu."))) { 1009 Value *Arg0 = CI->getArgOperand(0); 1010 Value *Arg1 = CI->getArgOperand(1); 1011 1012 Arg0 = Builder.CreateBitCast(Arg0, 1013 PointerType::getUnqual(Arg1->getType()), 1014 "cast"); 1015 Builder.CreateAlignedStore(Arg1, Arg0, 1); 1016 1017 // Remove intrinsic. 1018 CI->eraseFromParent(); 1019 return; 1020 } 1021 1022 if (IsX86 && (Name.startswith("avx512.mask.store"))) { 1023 // "avx512.mask.storeu." or "avx512.mask.store." 1024 bool Aligned = Name[17] != 'u'; // "avx512.mask.storeu". 1025 UpgradeMaskedStore(Builder, CI->getArgOperand(0), CI->getArgOperand(1), 1026 CI->getArgOperand(2), Aligned); 1027 1028 // Remove intrinsic. 1029 CI->eraseFromParent(); 1030 return; 1031 } 1032 1033 Value *Rep; 1034 // Upgrade packed integer vector compare intrinsics to compare instructions. 1035 if (IsX86 && (Name.startswith("sse2.pcmp") || 1036 Name.startswith("avx2.pcmp"))) { 1037 // "sse2.pcpmpeq." "sse2.pcmpgt." "avx2.pcmpeq." or "avx2.pcmpgt." 1038 bool CmpEq = Name[9] == 'e'; 1039 Rep = Builder.CreateICmp(CmpEq ? ICmpInst::ICMP_EQ : ICmpInst::ICMP_SGT, 1040 CI->getArgOperand(0), CI->getArgOperand(1)); 1041 Rep = Builder.CreateSExt(Rep, CI->getType(), ""); 1042 } else if (IsX86 && (Name.startswith("avx512.broadcastm"))) { 1043 Type *ExtTy = Type::getInt32Ty(C); 1044 if (CI->getOperand(0)->getType()->isIntegerTy(8)) 1045 ExtTy = Type::getInt64Ty(C); 1046 unsigned NumElts = CI->getType()->getPrimitiveSizeInBits() / 1047 ExtTy->getPrimitiveSizeInBits(); 1048 Rep = Builder.CreateZExt(CI->getArgOperand(0), ExtTy); 1049 Rep = Builder.CreateVectorSplat(NumElts, Rep); 1050 } else if (IsX86 && (Name.startswith("avx512.ptestm") || 1051 Name.startswith("avx512.ptestnm"))) { 1052 Value *Op0 = CI->getArgOperand(0); 1053 Value *Op1 = CI->getArgOperand(1); 1054 Value *Mask = CI->getArgOperand(2); 1055 Rep = Builder.CreateAnd(Op0, Op1); 1056 llvm::Type *Ty = Op0->getType(); 1057 Value *Zero = llvm::Constant::getNullValue(Ty); 1058 ICmpInst::Predicate Pred = 1059 Name.startswith("avx512.ptestm") ? ICmpInst::ICMP_NE : ICmpInst::ICMP_EQ; 1060 Rep = Builder.CreateICmp(Pred, Rep, Zero); 1061 unsigned NumElts = Op0->getType()->getVectorNumElements(); 1062 Rep = ApplyX86MaskOn1BitsVec(Builder, Rep, Mask, NumElts); 1063 } else if (IsX86 && (Name.startswith("avx512.mask.pbroadcast"))){ 1064 unsigned NumElts = 1065 CI->getArgOperand(1)->getType()->getVectorNumElements(); 1066 Rep = Builder.CreateVectorSplat(NumElts, CI->getArgOperand(0)); 1067 Rep = EmitX86Select(Builder, CI->getArgOperand(2), Rep, 1068 CI->getArgOperand(1)); 1069 } else if (IsX86 && (Name.startswith("avx512.kunpck"))) { 1070 uint64_t Shift = CI->getType()->getScalarSizeInBits() / 2; 1071 uint64_t And = (1ULL << Shift) - 1; 1072 Value* LowBits = Builder.CreateAnd(CI->getArgOperand(0), And); 1073 Value* HighBits = Builder.CreateShl(CI->getArgOperand(1), Shift); 1074 Rep = Builder.CreateOr(LowBits, HighBits); 1075 } else if (IsX86 && (Name == "sse.add.ss" || Name == "sse2.add.sd")) { 1076 Type *I32Ty = Type::getInt32Ty(C); 1077 Value *Elt0 = Builder.CreateExtractElement(CI->getArgOperand(0), 1078 ConstantInt::get(I32Ty, 0)); 1079 Value *Elt1 = Builder.CreateExtractElement(CI->getArgOperand(1), 1080 ConstantInt::get(I32Ty, 0)); 1081 Rep = Builder.CreateInsertElement(CI->getArgOperand(0), 1082 Builder.CreateFAdd(Elt0, Elt1), 1083 ConstantInt::get(I32Ty, 0)); 1084 } else if (IsX86 && (Name == "sse.sub.ss" || Name == "sse2.sub.sd")) { 1085 Type *I32Ty = Type::getInt32Ty(C); 1086 Value *Elt0 = Builder.CreateExtractElement(CI->getArgOperand(0), 1087 ConstantInt::get(I32Ty, 0)); 1088 Value *Elt1 = Builder.CreateExtractElement(CI->getArgOperand(1), 1089 ConstantInt::get(I32Ty, 0)); 1090 Rep = Builder.CreateInsertElement(CI->getArgOperand(0), 1091 Builder.CreateFSub(Elt0, Elt1), 1092 ConstantInt::get(I32Ty, 0)); 1093 } else if (IsX86 && (Name == "sse.mul.ss" || Name == "sse2.mul.sd")) { 1094 Type *I32Ty = Type::getInt32Ty(C); 1095 Value *Elt0 = Builder.CreateExtractElement(CI->getArgOperand(0), 1096 ConstantInt::get(I32Ty, 0)); 1097 Value *Elt1 = Builder.CreateExtractElement(CI->getArgOperand(1), 1098 ConstantInt::get(I32Ty, 0)); 1099 Rep = Builder.CreateInsertElement(CI->getArgOperand(0), 1100 Builder.CreateFMul(Elt0, Elt1), 1101 ConstantInt::get(I32Ty, 0)); 1102 } else if (IsX86 && (Name == "sse.div.ss" || Name == "sse2.div.sd")) { 1103 Type *I32Ty = Type::getInt32Ty(C); 1104 Value *Elt0 = Builder.CreateExtractElement(CI->getArgOperand(0), 1105 ConstantInt::get(I32Ty, 0)); 1106 Value *Elt1 = Builder.CreateExtractElement(CI->getArgOperand(1), 1107 ConstantInt::get(I32Ty, 0)); 1108 Rep = Builder.CreateInsertElement(CI->getArgOperand(0), 1109 Builder.CreateFDiv(Elt0, Elt1), 1110 ConstantInt::get(I32Ty, 0)); 1111 } else if (IsX86 && Name.startswith("avx512.mask.pcmp")) { 1112 // "avx512.mask.pcmpeq." or "avx512.mask.pcmpgt." 1113 bool CmpEq = Name[16] == 'e'; 1114 Rep = upgradeMaskedCompare(Builder, *CI, CmpEq ? 0 : 6, true); 1115 } else if (IsX86 && Name.startswith("avx512.mask.cmp")) { 1116 unsigned Imm = cast<ConstantInt>(CI->getArgOperand(2))->getZExtValue(); 1117 Rep = upgradeMaskedCompare(Builder, *CI, Imm, true); 1118 } else if (IsX86 && Name.startswith("avx512.mask.ucmp")) { 1119 unsigned Imm = cast<ConstantInt>(CI->getArgOperand(2))->getZExtValue(); 1120 Rep = upgradeMaskedCompare(Builder, *CI, Imm, false); 1121 } else if(IsX86 && (Name == "ssse3.pabs.b.128" || 1122 Name == "ssse3.pabs.w.128" || 1123 Name == "ssse3.pabs.d.128" || 1124 Name.startswith("avx2.pabs") || 1125 Name.startswith("avx512.mask.pabs"))) { 1126 Rep = upgradeAbs(Builder, *CI); 1127 } else if (IsX86 && (Name == "sse41.pmaxsb" || 1128 Name == "sse2.pmaxs.w" || 1129 Name == "sse41.pmaxsd" || 1130 Name.startswith("avx2.pmaxs") || 1131 Name.startswith("avx512.mask.pmaxs"))) { 1132 Rep = upgradeIntMinMax(Builder, *CI, ICmpInst::ICMP_SGT); 1133 } else if (IsX86 && (Name == "sse2.pmaxu.b" || 1134 Name == "sse41.pmaxuw" || 1135 Name == "sse41.pmaxud" || 1136 Name.startswith("avx2.pmaxu") || 1137 Name.startswith("avx512.mask.pmaxu"))) { 1138 Rep = upgradeIntMinMax(Builder, *CI, ICmpInst::ICMP_UGT); 1139 } else if (IsX86 && (Name == "sse41.pminsb" || 1140 Name == "sse2.pmins.w" || 1141 Name == "sse41.pminsd" || 1142 Name.startswith("avx2.pmins") || 1143 Name.startswith("avx512.mask.pmins"))) { 1144 Rep = upgradeIntMinMax(Builder, *CI, ICmpInst::ICMP_SLT); 1145 } else if (IsX86 && (Name == "sse2.pminu.b" || 1146 Name == "sse41.pminuw" || 1147 Name == "sse41.pminud" || 1148 Name.startswith("avx2.pminu") || 1149 Name.startswith("avx512.mask.pminu"))) { 1150 Rep = upgradeIntMinMax(Builder, *CI, ICmpInst::ICMP_ULT); 1151 } else if (IsX86 && (Name == "sse2.cvtdq2pd" || 1152 Name == "sse2.cvtps2pd" || 1153 Name == "avx.cvtdq2.pd.256" || 1154 Name == "avx.cvt.ps2.pd.256" || 1155 Name.startswith("avx512.mask.cvtdq2pd.") || 1156 Name.startswith("avx512.mask.cvtudq2pd."))) { 1157 // Lossless i32/float to double conversion. 1158 // Extract the bottom elements if necessary and convert to double vector. 1159 Value *Src = CI->getArgOperand(0); 1160 VectorType *SrcTy = cast<VectorType>(Src->getType()); 1161 VectorType *DstTy = cast<VectorType>(CI->getType()); 1162 Rep = CI->getArgOperand(0); 1163 1164 unsigned NumDstElts = DstTy->getNumElements(); 1165 if (NumDstElts < SrcTy->getNumElements()) { 1166 assert(NumDstElts == 2 && "Unexpected vector size"); 1167 uint32_t ShuffleMask[2] = { 0, 1 }; 1168 Rep = Builder.CreateShuffleVector(Rep, UndefValue::get(SrcTy), 1169 ShuffleMask); 1170 } 1171 1172 bool SInt2Double = (StringRef::npos != Name.find("cvtdq2")); 1173 bool UInt2Double = (StringRef::npos != Name.find("cvtudq2")); 1174 if (SInt2Double) 1175 Rep = Builder.CreateSIToFP(Rep, DstTy, "cvtdq2pd"); 1176 else if (UInt2Double) 1177 Rep = Builder.CreateUIToFP(Rep, DstTy, "cvtudq2pd"); 1178 else 1179 Rep = Builder.CreateFPExt(Rep, DstTy, "cvtps2pd"); 1180 1181 if (CI->getNumArgOperands() == 3) 1182 Rep = EmitX86Select(Builder, CI->getArgOperand(2), Rep, 1183 CI->getArgOperand(1)); 1184 } else if (IsX86 && (Name.startswith("avx512.mask.loadu."))) { 1185 Rep = UpgradeMaskedLoad(Builder, CI->getArgOperand(0), 1186 CI->getArgOperand(1), CI->getArgOperand(2), 1187 /*Aligned*/false); 1188 } else if (IsX86 && (Name.startswith("avx512.mask.load."))) { 1189 Rep = UpgradeMaskedLoad(Builder, CI->getArgOperand(0), 1190 CI->getArgOperand(1),CI->getArgOperand(2), 1191 /*Aligned*/true); 1192 } else if (IsX86 && Name.startswith("xop.vpcom")) { 1193 Intrinsic::ID intID; 1194 if (Name.endswith("ub")) 1195 intID = Intrinsic::x86_xop_vpcomub; 1196 else if (Name.endswith("uw")) 1197 intID = Intrinsic::x86_xop_vpcomuw; 1198 else if (Name.endswith("ud")) 1199 intID = Intrinsic::x86_xop_vpcomud; 1200 else if (Name.endswith("uq")) 1201 intID = Intrinsic::x86_xop_vpcomuq; 1202 else if (Name.endswith("b")) 1203 intID = Intrinsic::x86_xop_vpcomb; 1204 else if (Name.endswith("w")) 1205 intID = Intrinsic::x86_xop_vpcomw; 1206 else if (Name.endswith("d")) 1207 intID = Intrinsic::x86_xop_vpcomd; 1208 else if (Name.endswith("q")) 1209 intID = Intrinsic::x86_xop_vpcomq; 1210 else 1211 llvm_unreachable("Unknown suffix"); 1212 1213 Name = Name.substr(9); // strip off "xop.vpcom" 1214 unsigned Imm; 1215 if (Name.startswith("lt")) 1216 Imm = 0; 1217 else if (Name.startswith("le")) 1218 Imm = 1; 1219 else if (Name.startswith("gt")) 1220 Imm = 2; 1221 else if (Name.startswith("ge")) 1222 Imm = 3; 1223 else if (Name.startswith("eq")) 1224 Imm = 4; 1225 else if (Name.startswith("ne")) 1226 Imm = 5; 1227 else if (Name.startswith("false")) 1228 Imm = 6; 1229 else if (Name.startswith("true")) 1230 Imm = 7; 1231 else 1232 llvm_unreachable("Unknown condition"); 1233 1234 Function *VPCOM = Intrinsic::getDeclaration(F->getParent(), intID); 1235 Rep = 1236 Builder.CreateCall(VPCOM, {CI->getArgOperand(0), CI->getArgOperand(1), 1237 Builder.getInt8(Imm)}); 1238 } else if (IsX86 && Name.startswith("xop.vpcmov")) { 1239 Value *Sel = CI->getArgOperand(2); 1240 Value *NotSel = Builder.CreateNot(Sel); 1241 Value *Sel0 = Builder.CreateAnd(CI->getArgOperand(0), Sel); 1242 Value *Sel1 = Builder.CreateAnd(CI->getArgOperand(1), NotSel); 1243 Rep = Builder.CreateOr(Sel0, Sel1); 1244 } else if (IsX86 && Name == "sse42.crc32.64.8") { 1245 Function *CRC32 = Intrinsic::getDeclaration(F->getParent(), 1246 Intrinsic::x86_sse42_crc32_32_8); 1247 Value *Trunc0 = Builder.CreateTrunc(CI->getArgOperand(0), Type::getInt32Ty(C)); 1248 Rep = Builder.CreateCall(CRC32, {Trunc0, CI->getArgOperand(1)}); 1249 Rep = Builder.CreateZExt(Rep, CI->getType(), ""); 1250 } else if (IsX86 && Name.startswith("avx.vbroadcast.s")) { 1251 // Replace broadcasts with a series of insertelements. 1252 Type *VecTy = CI->getType(); 1253 Type *EltTy = VecTy->getVectorElementType(); 1254 unsigned EltNum = VecTy->getVectorNumElements(); 1255 Value *Cast = Builder.CreateBitCast(CI->getArgOperand(0), 1256 EltTy->getPointerTo()); 1257 Value *Load = Builder.CreateLoad(EltTy, Cast); 1258 Type *I32Ty = Type::getInt32Ty(C); 1259 Rep = UndefValue::get(VecTy); 1260 for (unsigned I = 0; I < EltNum; ++I) 1261 Rep = Builder.CreateInsertElement(Rep, Load, 1262 ConstantInt::get(I32Ty, I)); 1263 } else if (IsX86 && (Name.startswith("sse41.pmovsx") || 1264 Name.startswith("sse41.pmovzx") || 1265 Name.startswith("avx2.pmovsx") || 1266 Name.startswith("avx2.pmovzx") || 1267 Name.startswith("avx512.mask.pmovsx") || 1268 Name.startswith("avx512.mask.pmovzx"))) { 1269 VectorType *SrcTy = cast<VectorType>(CI->getArgOperand(0)->getType()); 1270 VectorType *DstTy = cast<VectorType>(CI->getType()); 1271 unsigned NumDstElts = DstTy->getNumElements(); 1272 1273 // Extract a subvector of the first NumDstElts lanes and sign/zero extend. 1274 SmallVector<uint32_t, 8> ShuffleMask(NumDstElts); 1275 for (unsigned i = 0; i != NumDstElts; ++i) 1276 ShuffleMask[i] = i; 1277 1278 Value *SV = Builder.CreateShuffleVector( 1279 CI->getArgOperand(0), UndefValue::get(SrcTy), ShuffleMask); 1280 1281 bool DoSext = (StringRef::npos != Name.find("pmovsx")); 1282 Rep = DoSext ? Builder.CreateSExt(SV, DstTy) 1283 : Builder.CreateZExt(SV, DstTy); 1284 // If there are 3 arguments, it's a masked intrinsic so we need a select. 1285 if (CI->getNumArgOperands() == 3) 1286 Rep = EmitX86Select(Builder, CI->getArgOperand(2), Rep, 1287 CI->getArgOperand(1)); 1288 } else if (IsX86 && (Name.startswith("avx.vbroadcastf128") || 1289 Name == "avx2.vbroadcasti128")) { 1290 // Replace vbroadcastf128/vbroadcasti128 with a vector load+shuffle. 1291 Type *EltTy = CI->getType()->getVectorElementType(); 1292 unsigned NumSrcElts = 128 / EltTy->getPrimitiveSizeInBits(); 1293 Type *VT = VectorType::get(EltTy, NumSrcElts); 1294 Value *Op = Builder.CreatePointerCast(CI->getArgOperand(0), 1295 PointerType::getUnqual(VT)); 1296 Value *Load = Builder.CreateAlignedLoad(Op, 1); 1297 if (NumSrcElts == 2) 1298 Rep = Builder.CreateShuffleVector(Load, UndefValue::get(Load->getType()), 1299 { 0, 1, 0, 1 }); 1300 else 1301 Rep = Builder.CreateShuffleVector(Load, UndefValue::get(Load->getType()), 1302 { 0, 1, 2, 3, 0, 1, 2, 3 }); 1303 } else if (IsX86 && (Name.startswith("avx512.mask.shuf.i") || 1304 Name.startswith("avx512.mask.shuf.f"))) { 1305 unsigned Imm = cast<ConstantInt>(CI->getArgOperand(2))->getZExtValue(); 1306 Type *VT = CI->getType(); 1307 unsigned NumLanes = VT->getPrimitiveSizeInBits() / 128; 1308 unsigned NumElementsInLane = 128 / VT->getScalarSizeInBits(); 1309 unsigned ControlBitsMask = NumLanes - 1; 1310 unsigned NumControlBits = NumLanes / 2; 1311 SmallVector<uint32_t, 8> ShuffleMask(0); 1312 1313 for (unsigned l = 0; l != NumLanes; ++l) { 1314 unsigned LaneMask = (Imm >> (l * NumControlBits)) & ControlBitsMask; 1315 // We actually need the other source. 1316 if (l >= NumLanes / 2) 1317 LaneMask += NumLanes; 1318 for (unsigned i = 0; i != NumElementsInLane; ++i) 1319 ShuffleMask.push_back(LaneMask * NumElementsInLane + i); 1320 } 1321 Rep = Builder.CreateShuffleVector(CI->getArgOperand(0), 1322 CI->getArgOperand(1), ShuffleMask); 1323 Rep = EmitX86Select(Builder, CI->getArgOperand(4), Rep, 1324 CI->getArgOperand(3)); 1325 }else if (IsX86 && (Name.startswith("avx512.mask.broadcastf") || 1326 Name.startswith("avx512.mask.broadcasti"))) { 1327 unsigned NumSrcElts = 1328 CI->getArgOperand(0)->getType()->getVectorNumElements(); 1329 unsigned NumDstElts = CI->getType()->getVectorNumElements(); 1330 1331 SmallVector<uint32_t, 8> ShuffleMask(NumDstElts); 1332 for (unsigned i = 0; i != NumDstElts; ++i) 1333 ShuffleMask[i] = i % NumSrcElts; 1334 1335 Rep = Builder.CreateShuffleVector(CI->getArgOperand(0), 1336 CI->getArgOperand(0), 1337 ShuffleMask); 1338 Rep = EmitX86Select(Builder, CI->getArgOperand(2), Rep, 1339 CI->getArgOperand(1)); 1340 } else if (IsX86 && (Name.startswith("avx2.pbroadcast") || 1341 Name.startswith("avx2.vbroadcast") || 1342 Name.startswith("avx512.pbroadcast") || 1343 Name.startswith("avx512.mask.broadcast.s"))) { 1344 // Replace vp?broadcasts with a vector shuffle. 1345 Value *Op = CI->getArgOperand(0); 1346 unsigned NumElts = CI->getType()->getVectorNumElements(); 1347 Type *MaskTy = VectorType::get(Type::getInt32Ty(C), NumElts); 1348 Rep = Builder.CreateShuffleVector(Op, UndefValue::get(Op->getType()), 1349 Constant::getNullValue(MaskTy)); 1350 1351 if (CI->getNumArgOperands() == 3) 1352 Rep = EmitX86Select(Builder, CI->getArgOperand(2), Rep, 1353 CI->getArgOperand(1)); 1354 } else if (IsX86 && Name.startswith("avx512.mask.palignr.")) { 1355 Rep = UpgradeX86ALIGNIntrinsics(Builder, CI->getArgOperand(0), 1356 CI->getArgOperand(1), 1357 CI->getArgOperand(2), 1358 CI->getArgOperand(3), 1359 CI->getArgOperand(4), 1360 false); 1361 } else if (IsX86 && Name.startswith("avx512.mask.valign.")) { 1362 Rep = UpgradeX86ALIGNIntrinsics(Builder, CI->getArgOperand(0), 1363 CI->getArgOperand(1), 1364 CI->getArgOperand(2), 1365 CI->getArgOperand(3), 1366 CI->getArgOperand(4), 1367 true); 1368 } else if (IsX86 && (Name == "sse2.psll.dq" || 1369 Name == "avx2.psll.dq")) { 1370 // 128/256-bit shift left specified in bits. 1371 unsigned Shift = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue(); 1372 Rep = UpgradeX86PSLLDQIntrinsics(Builder, CI->getArgOperand(0), 1373 Shift / 8); // Shift is in bits. 1374 } else if (IsX86 && (Name == "sse2.psrl.dq" || 1375 Name == "avx2.psrl.dq")) { 1376 // 128/256-bit shift right specified in bits. 1377 unsigned Shift = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue(); 1378 Rep = UpgradeX86PSRLDQIntrinsics(Builder, CI->getArgOperand(0), 1379 Shift / 8); // Shift is in bits. 1380 } else if (IsX86 && (Name == "sse2.psll.dq.bs" || 1381 Name == "avx2.psll.dq.bs" || 1382 Name == "avx512.psll.dq.512")) { 1383 // 128/256/512-bit shift left specified in bytes. 1384 unsigned Shift = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue(); 1385 Rep = UpgradeX86PSLLDQIntrinsics(Builder, CI->getArgOperand(0), Shift); 1386 } else if (IsX86 && (Name == "sse2.psrl.dq.bs" || 1387 Name == "avx2.psrl.dq.bs" || 1388 Name == "avx512.psrl.dq.512")) { 1389 // 128/256/512-bit shift right specified in bytes. 1390 unsigned Shift = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue(); 1391 Rep = UpgradeX86PSRLDQIntrinsics(Builder, CI->getArgOperand(0), Shift); 1392 } else if (IsX86 && (Name == "sse41.pblendw" || 1393 Name.startswith("sse41.blendp") || 1394 Name.startswith("avx.blend.p") || 1395 Name == "avx2.pblendw" || 1396 Name.startswith("avx2.pblendd."))) { 1397 Value *Op0 = CI->getArgOperand(0); 1398 Value *Op1 = CI->getArgOperand(1); 1399 unsigned Imm = cast <ConstantInt>(CI->getArgOperand(2))->getZExtValue(); 1400 VectorType *VecTy = cast<VectorType>(CI->getType()); 1401 unsigned NumElts = VecTy->getNumElements(); 1402 1403 SmallVector<uint32_t, 16> Idxs(NumElts); 1404 for (unsigned i = 0; i != NumElts; ++i) 1405 Idxs[i] = ((Imm >> (i%8)) & 1) ? i + NumElts : i; 1406 1407 Rep = Builder.CreateShuffleVector(Op0, Op1, Idxs); 1408 } else if (IsX86 && (Name.startswith("avx.vinsertf128.") || 1409 Name == "avx2.vinserti128" || 1410 Name.startswith("avx512.mask.insert"))) { 1411 Value *Op0 = CI->getArgOperand(0); 1412 Value *Op1 = CI->getArgOperand(1); 1413 unsigned Imm = cast<ConstantInt>(CI->getArgOperand(2))->getZExtValue(); 1414 unsigned DstNumElts = CI->getType()->getVectorNumElements(); 1415 unsigned SrcNumElts = Op1->getType()->getVectorNumElements(); 1416 unsigned Scale = DstNumElts / SrcNumElts; 1417 1418 // Mask off the high bits of the immediate value; hardware ignores those. 1419 Imm = Imm % Scale; 1420 1421 // Extend the second operand into a vector the size of the destination. 1422 Value *UndefV = UndefValue::get(Op1->getType()); 1423 SmallVector<uint32_t, 8> Idxs(DstNumElts); 1424 for (unsigned i = 0; i != SrcNumElts; ++i) 1425 Idxs[i] = i; 1426 for (unsigned i = SrcNumElts; i != DstNumElts; ++i) 1427 Idxs[i] = SrcNumElts; 1428 Rep = Builder.CreateShuffleVector(Op1, UndefV, Idxs); 1429 1430 // Insert the second operand into the first operand. 1431 1432 // Note that there is no guarantee that instruction lowering will actually 1433 // produce a vinsertf128 instruction for the created shuffles. In 1434 // particular, the 0 immediate case involves no lane changes, so it can 1435 // be handled as a blend. 1436 1437 // Example of shuffle mask for 32-bit elements: 1438 // Imm = 1 <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11> 1439 // Imm = 0 <i32 8, i32 9, i32 10, i32 11, i32 4, i32 5, i32 6, i32 7 > 1440 1441 // First fill with identify mask. 1442 for (unsigned i = 0; i != DstNumElts; ++i) 1443 Idxs[i] = i; 1444 // Then replace the elements where we need to insert. 1445 for (unsigned i = 0; i != SrcNumElts; ++i) 1446 Idxs[i + Imm * SrcNumElts] = i + DstNumElts; 1447 Rep = Builder.CreateShuffleVector(Op0, Rep, Idxs); 1448 1449 // If the intrinsic has a mask operand, handle that. 1450 if (CI->getNumArgOperands() == 5) 1451 Rep = EmitX86Select(Builder, CI->getArgOperand(4), Rep, 1452 CI->getArgOperand(3)); 1453 } else if (IsX86 && (Name.startswith("avx.vextractf128.") || 1454 Name == "avx2.vextracti128" || 1455 Name.startswith("avx512.mask.vextract"))) { 1456 Value *Op0 = CI->getArgOperand(0); 1457 unsigned Imm = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue(); 1458 unsigned DstNumElts = CI->getType()->getVectorNumElements(); 1459 unsigned SrcNumElts = Op0->getType()->getVectorNumElements(); 1460 unsigned Scale = SrcNumElts / DstNumElts; 1461 1462 // Mask off the high bits of the immediate value; hardware ignores those. 1463 Imm = Imm % Scale; 1464 1465 // Get indexes for the subvector of the input vector. 1466 SmallVector<uint32_t, 8> Idxs(DstNumElts); 1467 for (unsigned i = 0; i != DstNumElts; ++i) { 1468 Idxs[i] = i + (Imm * DstNumElts); 1469 } 1470 Rep = Builder.CreateShuffleVector(Op0, Op0, Idxs); 1471 1472 // If the intrinsic has a mask operand, handle that. 1473 if (CI->getNumArgOperands() == 4) 1474 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1475 CI->getArgOperand(2)); 1476 } else if (!IsX86 && Name == "stackprotectorcheck") { 1477 Rep = nullptr; 1478 } else if (IsX86 && (Name.startswith("avx512.mask.perm.df.") || 1479 Name.startswith("avx512.mask.perm.di."))) { 1480 Value *Op0 = CI->getArgOperand(0); 1481 unsigned Imm = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue(); 1482 VectorType *VecTy = cast<VectorType>(CI->getType()); 1483 unsigned NumElts = VecTy->getNumElements(); 1484 1485 SmallVector<uint32_t, 8> Idxs(NumElts); 1486 for (unsigned i = 0; i != NumElts; ++i) 1487 Idxs[i] = (i & ~0x3) + ((Imm >> (2 * (i & 0x3))) & 3); 1488 1489 Rep = Builder.CreateShuffleVector(Op0, Op0, Idxs); 1490 1491 if (CI->getNumArgOperands() == 4) 1492 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1493 CI->getArgOperand(2)); 1494 } else if (IsX86 && (Name.startswith("avx.vperm2f128.") || 1495 Name == "avx2.vperm2i128")) { 1496 // The immediate permute control byte looks like this: 1497 // [1:0] - select 128 bits from sources for low half of destination 1498 // [2] - ignore 1499 // [3] - zero low half of destination 1500 // [5:4] - select 128 bits from sources for high half of destination 1501 // [6] - ignore 1502 // [7] - zero high half of destination 1503 1504 uint8_t Imm = cast<ConstantInt>(CI->getArgOperand(2))->getZExtValue(); 1505 1506 unsigned NumElts = CI->getType()->getVectorNumElements(); 1507 unsigned HalfSize = NumElts / 2; 1508 SmallVector<uint32_t, 8> ShuffleMask(NumElts); 1509 1510 // Determine which operand(s) are actually in use for this instruction. 1511 Value *V0 = (Imm & 0x02) ? CI->getArgOperand(1) : CI->getArgOperand(0); 1512 Value *V1 = (Imm & 0x20) ? CI->getArgOperand(1) : CI->getArgOperand(0); 1513 1514 // If needed, replace operands based on zero mask. 1515 V0 = (Imm & 0x08) ? ConstantAggregateZero::get(CI->getType()) : V0; 1516 V1 = (Imm & 0x80) ? ConstantAggregateZero::get(CI->getType()) : V1; 1517 1518 // Permute low half of result. 1519 unsigned StartIndex = (Imm & 0x01) ? HalfSize : 0; 1520 for (unsigned i = 0; i < HalfSize; ++i) 1521 ShuffleMask[i] = StartIndex + i; 1522 1523 // Permute high half of result. 1524 StartIndex = (Imm & 0x10) ? HalfSize : 0; 1525 for (unsigned i = 0; i < HalfSize; ++i) 1526 ShuffleMask[i + HalfSize] = NumElts + StartIndex + i; 1527 1528 Rep = Builder.CreateShuffleVector(V0, V1, ShuffleMask); 1529 1530 } else if (IsX86 && (Name.startswith("avx.vpermil.") || 1531 Name == "sse2.pshuf.d" || 1532 Name.startswith("avx512.mask.vpermil.p") || 1533 Name.startswith("avx512.mask.pshuf.d."))) { 1534 Value *Op0 = CI->getArgOperand(0); 1535 unsigned Imm = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue(); 1536 VectorType *VecTy = cast<VectorType>(CI->getType()); 1537 unsigned NumElts = VecTy->getNumElements(); 1538 // Calculate the size of each index in the immediate. 1539 unsigned IdxSize = 64 / VecTy->getScalarSizeInBits(); 1540 unsigned IdxMask = ((1 << IdxSize) - 1); 1541 1542 SmallVector<uint32_t, 8> Idxs(NumElts); 1543 // Lookup the bits for this element, wrapping around the immediate every 1544 // 8-bits. Elements are grouped into sets of 2 or 4 elements so we need 1545 // to offset by the first index of each group. 1546 for (unsigned i = 0; i != NumElts; ++i) 1547 Idxs[i] = ((Imm >> ((i * IdxSize) % 8)) & IdxMask) | (i & ~IdxMask); 1548 1549 Rep = Builder.CreateShuffleVector(Op0, Op0, Idxs); 1550 1551 if (CI->getNumArgOperands() == 4) 1552 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1553 CI->getArgOperand(2)); 1554 } else if (IsX86 && (Name == "sse2.pshufl.w" || 1555 Name.startswith("avx512.mask.pshufl.w."))) { 1556 Value *Op0 = CI->getArgOperand(0); 1557 unsigned Imm = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue(); 1558 unsigned NumElts = CI->getType()->getVectorNumElements(); 1559 1560 SmallVector<uint32_t, 16> Idxs(NumElts); 1561 for (unsigned l = 0; l != NumElts; l += 8) { 1562 for (unsigned i = 0; i != 4; ++i) 1563 Idxs[i + l] = ((Imm >> (2 * i)) & 0x3) + l; 1564 for (unsigned i = 4; i != 8; ++i) 1565 Idxs[i + l] = i + l; 1566 } 1567 1568 Rep = Builder.CreateShuffleVector(Op0, Op0, Idxs); 1569 1570 if (CI->getNumArgOperands() == 4) 1571 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1572 CI->getArgOperand(2)); 1573 } else if (IsX86 && (Name == "sse2.pshufh.w" || 1574 Name.startswith("avx512.mask.pshufh.w."))) { 1575 Value *Op0 = CI->getArgOperand(0); 1576 unsigned Imm = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue(); 1577 unsigned NumElts = CI->getType()->getVectorNumElements(); 1578 1579 SmallVector<uint32_t, 16> Idxs(NumElts); 1580 for (unsigned l = 0; l != NumElts; l += 8) { 1581 for (unsigned i = 0; i != 4; ++i) 1582 Idxs[i + l] = i + l; 1583 for (unsigned i = 0; i != 4; ++i) 1584 Idxs[i + l + 4] = ((Imm >> (2 * i)) & 0x3) + 4 + l; 1585 } 1586 1587 Rep = Builder.CreateShuffleVector(Op0, Op0, Idxs); 1588 1589 if (CI->getNumArgOperands() == 4) 1590 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1591 CI->getArgOperand(2)); 1592 } else if (IsX86 && Name.startswith("avx512.mask.shuf.p")) { 1593 Value *Op0 = CI->getArgOperand(0); 1594 Value *Op1 = CI->getArgOperand(1); 1595 unsigned Imm = cast<ConstantInt>(CI->getArgOperand(2))->getZExtValue(); 1596 unsigned NumElts = CI->getType()->getVectorNumElements(); 1597 1598 unsigned NumLaneElts = 128/CI->getType()->getScalarSizeInBits(); 1599 unsigned HalfLaneElts = NumLaneElts / 2; 1600 1601 SmallVector<uint32_t, 16> Idxs(NumElts); 1602 for (unsigned i = 0; i != NumElts; ++i) { 1603 // Base index is the starting element of the lane. 1604 Idxs[i] = i - (i % NumLaneElts); 1605 // If we are half way through the lane switch to the other source. 1606 if ((i % NumLaneElts) >= HalfLaneElts) 1607 Idxs[i] += NumElts; 1608 // Now select the specific element. By adding HalfLaneElts bits from 1609 // the immediate. Wrapping around the immediate every 8-bits. 1610 Idxs[i] += (Imm >> ((i * HalfLaneElts) % 8)) & ((1 << HalfLaneElts) - 1); 1611 } 1612 1613 Rep = Builder.CreateShuffleVector(Op0, Op1, Idxs); 1614 1615 Rep = EmitX86Select(Builder, CI->getArgOperand(4), Rep, 1616 CI->getArgOperand(3)); 1617 } else if (IsX86 && (Name.startswith("avx512.mask.movddup") || 1618 Name.startswith("avx512.mask.movshdup") || 1619 Name.startswith("avx512.mask.movsldup"))) { 1620 Value *Op0 = CI->getArgOperand(0); 1621 unsigned NumElts = CI->getType()->getVectorNumElements(); 1622 unsigned NumLaneElts = 128/CI->getType()->getScalarSizeInBits(); 1623 1624 unsigned Offset = 0; 1625 if (Name.startswith("avx512.mask.movshdup.")) 1626 Offset = 1; 1627 1628 SmallVector<uint32_t, 16> Idxs(NumElts); 1629 for (unsigned l = 0; l != NumElts; l += NumLaneElts) 1630 for (unsigned i = 0; i != NumLaneElts; i += 2) { 1631 Idxs[i + l + 0] = i + l + Offset; 1632 Idxs[i + l + 1] = i + l + Offset; 1633 } 1634 1635 Rep = Builder.CreateShuffleVector(Op0, Op0, Idxs); 1636 1637 Rep = EmitX86Select(Builder, CI->getArgOperand(2), Rep, 1638 CI->getArgOperand(1)); 1639 } else if (IsX86 && (Name.startswith("avx512.mask.punpckl") || 1640 Name.startswith("avx512.mask.unpckl."))) { 1641 Value *Op0 = CI->getArgOperand(0); 1642 Value *Op1 = CI->getArgOperand(1); 1643 int NumElts = CI->getType()->getVectorNumElements(); 1644 int NumLaneElts = 128/CI->getType()->getScalarSizeInBits(); 1645 1646 SmallVector<uint32_t, 64> Idxs(NumElts); 1647 for (int l = 0; l != NumElts; l += NumLaneElts) 1648 for (int i = 0; i != NumLaneElts; ++i) 1649 Idxs[i + l] = l + (i / 2) + NumElts * (i % 2); 1650 1651 Rep = Builder.CreateShuffleVector(Op0, Op1, Idxs); 1652 1653 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1654 CI->getArgOperand(2)); 1655 } else if (IsX86 && (Name.startswith("avx512.mask.punpckh") || 1656 Name.startswith("avx512.mask.unpckh."))) { 1657 Value *Op0 = CI->getArgOperand(0); 1658 Value *Op1 = CI->getArgOperand(1); 1659 int NumElts = CI->getType()->getVectorNumElements(); 1660 int NumLaneElts = 128/CI->getType()->getScalarSizeInBits(); 1661 1662 SmallVector<uint32_t, 64> Idxs(NumElts); 1663 for (int l = 0; l != NumElts; l += NumLaneElts) 1664 for (int i = 0; i != NumLaneElts; ++i) 1665 Idxs[i + l] = (NumLaneElts / 2) + l + (i / 2) + NumElts * (i % 2); 1666 1667 Rep = Builder.CreateShuffleVector(Op0, Op1, Idxs); 1668 1669 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1670 CI->getArgOperand(2)); 1671 } else if (IsX86 && Name.startswith("avx512.mask.pand.")) { 1672 Rep = Builder.CreateAnd(CI->getArgOperand(0), CI->getArgOperand(1)); 1673 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1674 CI->getArgOperand(2)); 1675 } else if (IsX86 && Name.startswith("avx512.mask.pandn.")) { 1676 Rep = Builder.CreateAnd(Builder.CreateNot(CI->getArgOperand(0)), 1677 CI->getArgOperand(1)); 1678 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1679 CI->getArgOperand(2)); 1680 } else if (IsX86 && Name.startswith("avx512.mask.por.")) { 1681 Rep = Builder.CreateOr(CI->getArgOperand(0), CI->getArgOperand(1)); 1682 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1683 CI->getArgOperand(2)); 1684 } else if (IsX86 && Name.startswith("avx512.mask.pxor.")) { 1685 Rep = Builder.CreateXor(CI->getArgOperand(0), CI->getArgOperand(1)); 1686 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1687 CI->getArgOperand(2)); 1688 } else if (IsX86 && Name.startswith("avx512.mask.and.")) { 1689 VectorType *FTy = cast<VectorType>(CI->getType()); 1690 VectorType *ITy = VectorType::getInteger(FTy); 1691 Rep = Builder.CreateAnd(Builder.CreateBitCast(CI->getArgOperand(0), ITy), 1692 Builder.CreateBitCast(CI->getArgOperand(1), ITy)); 1693 Rep = Builder.CreateBitCast(Rep, FTy); 1694 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1695 CI->getArgOperand(2)); 1696 } else if (IsX86 && Name.startswith("avx512.mask.andn.")) { 1697 VectorType *FTy = cast<VectorType>(CI->getType()); 1698 VectorType *ITy = VectorType::getInteger(FTy); 1699 Rep = Builder.CreateNot(Builder.CreateBitCast(CI->getArgOperand(0), ITy)); 1700 Rep = Builder.CreateAnd(Rep, 1701 Builder.CreateBitCast(CI->getArgOperand(1), ITy)); 1702 Rep = Builder.CreateBitCast(Rep, FTy); 1703 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1704 CI->getArgOperand(2)); 1705 } else if (IsX86 && Name.startswith("avx512.mask.or.")) { 1706 VectorType *FTy = cast<VectorType>(CI->getType()); 1707 VectorType *ITy = VectorType::getInteger(FTy); 1708 Rep = Builder.CreateOr(Builder.CreateBitCast(CI->getArgOperand(0), ITy), 1709 Builder.CreateBitCast(CI->getArgOperand(1), ITy)); 1710 Rep = Builder.CreateBitCast(Rep, FTy); 1711 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1712 CI->getArgOperand(2)); 1713 } else if (IsX86 && Name.startswith("avx512.mask.xor.")) { 1714 VectorType *FTy = cast<VectorType>(CI->getType()); 1715 VectorType *ITy = VectorType::getInteger(FTy); 1716 Rep = Builder.CreateXor(Builder.CreateBitCast(CI->getArgOperand(0), ITy), 1717 Builder.CreateBitCast(CI->getArgOperand(1), ITy)); 1718 Rep = Builder.CreateBitCast(Rep, FTy); 1719 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1720 CI->getArgOperand(2)); 1721 } else if (IsX86 && Name.startswith("avx512.mask.padd.")) { 1722 Rep = Builder.CreateAdd(CI->getArgOperand(0), CI->getArgOperand(1)); 1723 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1724 CI->getArgOperand(2)); 1725 } else if (IsX86 && Name.startswith("avx512.mask.psub.")) { 1726 Rep = Builder.CreateSub(CI->getArgOperand(0), CI->getArgOperand(1)); 1727 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1728 CI->getArgOperand(2)); 1729 } else if (IsX86 && Name.startswith("avx512.mask.pmull.")) { 1730 Rep = Builder.CreateMul(CI->getArgOperand(0), CI->getArgOperand(1)); 1731 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1732 CI->getArgOperand(2)); 1733 } else if (IsX86 && (Name.startswith("avx512.mask.add.p"))) { 1734 Rep = Builder.CreateFAdd(CI->getArgOperand(0), CI->getArgOperand(1)); 1735 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1736 CI->getArgOperand(2)); 1737 } else if (IsX86 && Name.startswith("avx512.mask.div.p")) { 1738 Rep = Builder.CreateFDiv(CI->getArgOperand(0), CI->getArgOperand(1)); 1739 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1740 CI->getArgOperand(2)); 1741 } else if (IsX86 && Name.startswith("avx512.mask.mul.p")) { 1742 Rep = Builder.CreateFMul(CI->getArgOperand(0), CI->getArgOperand(1)); 1743 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1744 CI->getArgOperand(2)); 1745 } else if (IsX86 && Name.startswith("avx512.mask.sub.p")) { 1746 Rep = Builder.CreateFSub(CI->getArgOperand(0), CI->getArgOperand(1)); 1747 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1748 CI->getArgOperand(2)); 1749 } else if (IsX86 && Name.startswith("avx512.mask.lzcnt.")) { 1750 Rep = Builder.CreateCall(Intrinsic::getDeclaration(F->getParent(), 1751 Intrinsic::ctlz, 1752 CI->getType()), 1753 { CI->getArgOperand(0), Builder.getInt1(false) }); 1754 Rep = EmitX86Select(Builder, CI->getArgOperand(2), Rep, 1755 CI->getArgOperand(1)); 1756 } else if (IsX86 && (Name.startswith("avx512.mask.max.p") || 1757 Name.startswith("avx512.mask.min.p"))) { 1758 bool IsMin = Name[13] == 'i'; 1759 VectorType *VecTy = cast<VectorType>(CI->getType()); 1760 unsigned VecWidth = VecTy->getPrimitiveSizeInBits(); 1761 unsigned EltWidth = VecTy->getScalarSizeInBits(); 1762 Intrinsic::ID IID; 1763 if (!IsMin && VecWidth == 128 && EltWidth == 32) 1764 IID = Intrinsic::x86_sse_max_ps; 1765 else if (!IsMin && VecWidth == 128 && EltWidth == 64) 1766 IID = Intrinsic::x86_sse2_max_pd; 1767 else if (!IsMin && VecWidth == 256 && EltWidth == 32) 1768 IID = Intrinsic::x86_avx_max_ps_256; 1769 else if (!IsMin && VecWidth == 256 && EltWidth == 64) 1770 IID = Intrinsic::x86_avx_max_pd_256; 1771 else if (IsMin && VecWidth == 128 && EltWidth == 32) 1772 IID = Intrinsic::x86_sse_min_ps; 1773 else if (IsMin && VecWidth == 128 && EltWidth == 64) 1774 IID = Intrinsic::x86_sse2_min_pd; 1775 else if (IsMin && VecWidth == 256 && EltWidth == 32) 1776 IID = Intrinsic::x86_avx_min_ps_256; 1777 else if (IsMin && VecWidth == 256 && EltWidth == 64) 1778 IID = Intrinsic::x86_avx_min_pd_256; 1779 else 1780 llvm_unreachable("Unexpected intrinsic"); 1781 1782 Rep = Builder.CreateCall(Intrinsic::getDeclaration(F->getParent(), IID), 1783 { CI->getArgOperand(0), CI->getArgOperand(1) }); 1784 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1785 CI->getArgOperand(2)); 1786 } else if (IsX86 && Name.startswith("avx512.mask.pshuf.b.")) { 1787 VectorType *VecTy = cast<VectorType>(CI->getType()); 1788 Intrinsic::ID IID; 1789 if (VecTy->getPrimitiveSizeInBits() == 128) 1790 IID = Intrinsic::x86_ssse3_pshuf_b_128; 1791 else if (VecTy->getPrimitiveSizeInBits() == 256) 1792 IID = Intrinsic::x86_avx2_pshuf_b; 1793 else if (VecTy->getPrimitiveSizeInBits() == 512) 1794 IID = Intrinsic::x86_avx512_pshuf_b_512; 1795 else 1796 llvm_unreachable("Unexpected intrinsic"); 1797 1798 Rep = Builder.CreateCall(Intrinsic::getDeclaration(F->getParent(), IID), 1799 { CI->getArgOperand(0), CI->getArgOperand(1) }); 1800 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1801 CI->getArgOperand(2)); 1802 } else if (IsX86 && (Name.startswith("avx512.mask.pmul.dq.") || 1803 Name.startswith("avx512.mask.pmulu.dq."))) { 1804 bool IsUnsigned = Name[16] == 'u'; 1805 VectorType *VecTy = cast<VectorType>(CI->getType()); 1806 Intrinsic::ID IID; 1807 if (!IsUnsigned && VecTy->getPrimitiveSizeInBits() == 128) 1808 IID = Intrinsic::x86_sse41_pmuldq; 1809 else if (!IsUnsigned && VecTy->getPrimitiveSizeInBits() == 256) 1810 IID = Intrinsic::x86_avx2_pmul_dq; 1811 else if (!IsUnsigned && VecTy->getPrimitiveSizeInBits() == 512) 1812 IID = Intrinsic::x86_avx512_pmul_dq_512; 1813 else if (IsUnsigned && VecTy->getPrimitiveSizeInBits() == 128) 1814 IID = Intrinsic::x86_sse2_pmulu_dq; 1815 else if (IsUnsigned && VecTy->getPrimitiveSizeInBits() == 256) 1816 IID = Intrinsic::x86_avx2_pmulu_dq; 1817 else if (IsUnsigned && VecTy->getPrimitiveSizeInBits() == 512) 1818 IID = Intrinsic::x86_avx512_pmulu_dq_512; 1819 else 1820 llvm_unreachable("Unexpected intrinsic"); 1821 1822 Rep = Builder.CreateCall(Intrinsic::getDeclaration(F->getParent(), IID), 1823 { CI->getArgOperand(0), CI->getArgOperand(1) }); 1824 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1825 CI->getArgOperand(2)); 1826 } else if (IsX86 && Name.startswith("avx512.mask.pack")) { 1827 bool IsUnsigned = Name[16] == 'u'; 1828 bool IsDW = Name[18] == 'd'; 1829 VectorType *VecTy = cast<VectorType>(CI->getType()); 1830 Intrinsic::ID IID; 1831 if (!IsUnsigned && !IsDW && VecTy->getPrimitiveSizeInBits() == 128) 1832 IID = Intrinsic::x86_sse2_packsswb_128; 1833 else if (!IsUnsigned && !IsDW && VecTy->getPrimitiveSizeInBits() == 256) 1834 IID = Intrinsic::x86_avx2_packsswb; 1835 else if (!IsUnsigned && !IsDW && VecTy->getPrimitiveSizeInBits() == 512) 1836 IID = Intrinsic::x86_avx512_packsswb_512; 1837 else if (!IsUnsigned && IsDW && VecTy->getPrimitiveSizeInBits() == 128) 1838 IID = Intrinsic::x86_sse2_packssdw_128; 1839 else if (!IsUnsigned && IsDW && VecTy->getPrimitiveSizeInBits() == 256) 1840 IID = Intrinsic::x86_avx2_packssdw; 1841 else if (!IsUnsigned && IsDW && VecTy->getPrimitiveSizeInBits() == 512) 1842 IID = Intrinsic::x86_avx512_packssdw_512; 1843 else if (IsUnsigned && !IsDW && VecTy->getPrimitiveSizeInBits() == 128) 1844 IID = Intrinsic::x86_sse2_packuswb_128; 1845 else if (IsUnsigned && !IsDW && VecTy->getPrimitiveSizeInBits() == 256) 1846 IID = Intrinsic::x86_avx2_packuswb; 1847 else if (IsUnsigned && !IsDW && VecTy->getPrimitiveSizeInBits() == 512) 1848 IID = Intrinsic::x86_avx512_packuswb_512; 1849 else if (IsUnsigned && IsDW && VecTy->getPrimitiveSizeInBits() == 128) 1850 IID = Intrinsic::x86_sse41_packusdw; 1851 else if (IsUnsigned && IsDW && VecTy->getPrimitiveSizeInBits() == 256) 1852 IID = Intrinsic::x86_avx2_packusdw; 1853 else if (IsUnsigned && IsDW && VecTy->getPrimitiveSizeInBits() == 512) 1854 IID = Intrinsic::x86_avx512_packusdw_512; 1855 else 1856 llvm_unreachable("Unexpected intrinsic"); 1857 1858 Rep = Builder.CreateCall(Intrinsic::getDeclaration(F->getParent(), IID), 1859 { CI->getArgOperand(0), CI->getArgOperand(1) }); 1860 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1861 CI->getArgOperand(2)); 1862 } else if (IsX86 && Name.startswith("avx512.mask.psll")) { 1863 bool IsImmediate = Name[16] == 'i' || 1864 (Name.size() > 18 && Name[18] == 'i'); 1865 bool IsVariable = Name[16] == 'v'; 1866 char Size = Name[16] == '.' ? Name[17] : 1867 Name[17] == '.' ? Name[18] : 1868 Name[18] == '.' ? Name[19] : 1869 Name[20]; 1870 1871 Intrinsic::ID IID; 1872 if (IsVariable && Name[17] != '.') { 1873 if (Size == 'd' && Name[17] == '2') // avx512.mask.psllv2.di 1874 IID = Intrinsic::x86_avx2_psllv_q; 1875 else if (Size == 'd' && Name[17] == '4') // avx512.mask.psllv4.di 1876 IID = Intrinsic::x86_avx2_psllv_q_256; 1877 else if (Size == 's' && Name[17] == '4') // avx512.mask.psllv4.si 1878 IID = Intrinsic::x86_avx2_psllv_d; 1879 else if (Size == 's' && Name[17] == '8') // avx512.mask.psllv8.si 1880 IID = Intrinsic::x86_avx2_psllv_d_256; 1881 else if (Size == 'h' && Name[17] == '8') // avx512.mask.psllv8.hi 1882 IID = Intrinsic::x86_avx512_psllv_w_128; 1883 else if (Size == 'h' && Name[17] == '1') // avx512.mask.psllv16.hi 1884 IID = Intrinsic::x86_avx512_psllv_w_256; 1885 else if (Name[17] == '3' && Name[18] == '2') // avx512.mask.psllv32hi 1886 IID = Intrinsic::x86_avx512_psllv_w_512; 1887 else 1888 llvm_unreachable("Unexpected size"); 1889 } else if (Name.endswith(".128")) { 1890 if (Size == 'd') // avx512.mask.psll.d.128, avx512.mask.psll.di.128 1891 IID = IsImmediate ? Intrinsic::x86_sse2_pslli_d 1892 : Intrinsic::x86_sse2_psll_d; 1893 else if (Size == 'q') // avx512.mask.psll.q.128, avx512.mask.psll.qi.128 1894 IID = IsImmediate ? Intrinsic::x86_sse2_pslli_q 1895 : Intrinsic::x86_sse2_psll_q; 1896 else if (Size == 'w') // avx512.mask.psll.w.128, avx512.mask.psll.wi.128 1897 IID = IsImmediate ? Intrinsic::x86_sse2_pslli_w 1898 : Intrinsic::x86_sse2_psll_w; 1899 else 1900 llvm_unreachable("Unexpected size"); 1901 } else if (Name.endswith(".256")) { 1902 if (Size == 'd') // avx512.mask.psll.d.256, avx512.mask.psll.di.256 1903 IID = IsImmediate ? Intrinsic::x86_avx2_pslli_d 1904 : Intrinsic::x86_avx2_psll_d; 1905 else if (Size == 'q') // avx512.mask.psll.q.256, avx512.mask.psll.qi.256 1906 IID = IsImmediate ? Intrinsic::x86_avx2_pslli_q 1907 : Intrinsic::x86_avx2_psll_q; 1908 else if (Size == 'w') // avx512.mask.psll.w.256, avx512.mask.psll.wi.256 1909 IID = IsImmediate ? Intrinsic::x86_avx2_pslli_w 1910 : Intrinsic::x86_avx2_psll_w; 1911 else 1912 llvm_unreachable("Unexpected size"); 1913 } else { 1914 if (Size == 'd') // psll.di.512, pslli.d, psll.d, psllv.d.512 1915 IID = IsImmediate ? Intrinsic::x86_avx512_pslli_d_512 : 1916 IsVariable ? Intrinsic::x86_avx512_psllv_d_512 : 1917 Intrinsic::x86_avx512_psll_d_512; 1918 else if (Size == 'q') // psll.qi.512, pslli.q, psll.q, psllv.q.512 1919 IID = IsImmediate ? Intrinsic::x86_avx512_pslli_q_512 : 1920 IsVariable ? Intrinsic::x86_avx512_psllv_q_512 : 1921 Intrinsic::x86_avx512_psll_q_512; 1922 else if (Size == 'w') // psll.wi.512, pslli.w, psll.w 1923 IID = IsImmediate ? Intrinsic::x86_avx512_pslli_w_512 1924 : Intrinsic::x86_avx512_psll_w_512; 1925 else 1926 llvm_unreachable("Unexpected size"); 1927 } 1928 1929 Rep = UpgradeX86MaskedShift(Builder, *CI, IID); 1930 } else if (IsX86 && Name.startswith("avx512.mask.psrl")) { 1931 bool IsImmediate = Name[16] == 'i' || 1932 (Name.size() > 18 && Name[18] == 'i'); 1933 bool IsVariable = Name[16] == 'v'; 1934 char Size = Name[16] == '.' ? Name[17] : 1935 Name[17] == '.' ? Name[18] : 1936 Name[18] == '.' ? Name[19] : 1937 Name[20]; 1938 1939 Intrinsic::ID IID; 1940 if (IsVariable && Name[17] != '.') { 1941 if (Size == 'd' && Name[17] == '2') // avx512.mask.psrlv2.di 1942 IID = Intrinsic::x86_avx2_psrlv_q; 1943 else if (Size == 'd' && Name[17] == '4') // avx512.mask.psrlv4.di 1944 IID = Intrinsic::x86_avx2_psrlv_q_256; 1945 else if (Size == 's' && Name[17] == '4') // avx512.mask.psrlv4.si 1946 IID = Intrinsic::x86_avx2_psrlv_d; 1947 else if (Size == 's' && Name[17] == '8') // avx512.mask.psrlv8.si 1948 IID = Intrinsic::x86_avx2_psrlv_d_256; 1949 else if (Size == 'h' && Name[17] == '8') // avx512.mask.psrlv8.hi 1950 IID = Intrinsic::x86_avx512_psrlv_w_128; 1951 else if (Size == 'h' && Name[17] == '1') // avx512.mask.psrlv16.hi 1952 IID = Intrinsic::x86_avx512_psrlv_w_256; 1953 else if (Name[17] == '3' && Name[18] == '2') // avx512.mask.psrlv32hi 1954 IID = Intrinsic::x86_avx512_psrlv_w_512; 1955 else 1956 llvm_unreachable("Unexpected size"); 1957 } else if (Name.endswith(".128")) { 1958 if (Size == 'd') // avx512.mask.psrl.d.128, avx512.mask.psrl.di.128 1959 IID = IsImmediate ? Intrinsic::x86_sse2_psrli_d 1960 : Intrinsic::x86_sse2_psrl_d; 1961 else if (Size == 'q') // avx512.mask.psrl.q.128, avx512.mask.psrl.qi.128 1962 IID = IsImmediate ? Intrinsic::x86_sse2_psrli_q 1963 : Intrinsic::x86_sse2_psrl_q; 1964 else if (Size == 'w') // avx512.mask.psrl.w.128, avx512.mask.psrl.wi.128 1965 IID = IsImmediate ? Intrinsic::x86_sse2_psrli_w 1966 : Intrinsic::x86_sse2_psrl_w; 1967 else 1968 llvm_unreachable("Unexpected size"); 1969 } else if (Name.endswith(".256")) { 1970 if (Size == 'd') // avx512.mask.psrl.d.256, avx512.mask.psrl.di.256 1971 IID = IsImmediate ? Intrinsic::x86_avx2_psrli_d 1972 : Intrinsic::x86_avx2_psrl_d; 1973 else if (Size == 'q') // avx512.mask.psrl.q.256, avx512.mask.psrl.qi.256 1974 IID = IsImmediate ? Intrinsic::x86_avx2_psrli_q 1975 : Intrinsic::x86_avx2_psrl_q; 1976 else if (Size == 'w') // avx512.mask.psrl.w.256, avx512.mask.psrl.wi.256 1977 IID = IsImmediate ? Intrinsic::x86_avx2_psrli_w 1978 : Intrinsic::x86_avx2_psrl_w; 1979 else 1980 llvm_unreachable("Unexpected size"); 1981 } else { 1982 if (Size == 'd') // psrl.di.512, psrli.d, psrl.d, psrl.d.512 1983 IID = IsImmediate ? Intrinsic::x86_avx512_psrli_d_512 : 1984 IsVariable ? Intrinsic::x86_avx512_psrlv_d_512 : 1985 Intrinsic::x86_avx512_psrl_d_512; 1986 else if (Size == 'q') // psrl.qi.512, psrli.q, psrl.q, psrl.q.512 1987 IID = IsImmediate ? Intrinsic::x86_avx512_psrli_q_512 : 1988 IsVariable ? Intrinsic::x86_avx512_psrlv_q_512 : 1989 Intrinsic::x86_avx512_psrl_q_512; 1990 else if (Size == 'w') // psrl.wi.512, psrli.w, psrl.w) 1991 IID = IsImmediate ? Intrinsic::x86_avx512_psrli_w_512 1992 : Intrinsic::x86_avx512_psrl_w_512; 1993 else 1994 llvm_unreachable("Unexpected size"); 1995 } 1996 1997 Rep = UpgradeX86MaskedShift(Builder, *CI, IID); 1998 } else if (IsX86 && Name.startswith("avx512.mask.psra")) { 1999 bool IsImmediate = Name[16] == 'i' || 2000 (Name.size() > 18 && Name[18] == 'i'); 2001 bool IsVariable = Name[16] == 'v'; 2002 char Size = Name[16] == '.' ? Name[17] : 2003 Name[17] == '.' ? Name[18] : 2004 Name[18] == '.' ? Name[19] : 2005 Name[20]; 2006 2007 Intrinsic::ID IID; 2008 if (IsVariable && Name[17] != '.') { 2009 if (Size == 's' && Name[17] == '4') // avx512.mask.psrav4.si 2010 IID = Intrinsic::x86_avx2_psrav_d; 2011 else if (Size == 's' && Name[17] == '8') // avx512.mask.psrav8.si 2012 IID = Intrinsic::x86_avx2_psrav_d_256; 2013 else if (Size == 'h' && Name[17] == '8') // avx512.mask.psrav8.hi 2014 IID = Intrinsic::x86_avx512_psrav_w_128; 2015 else if (Size == 'h' && Name[17] == '1') // avx512.mask.psrav16.hi 2016 IID = Intrinsic::x86_avx512_psrav_w_256; 2017 else if (Name[17] == '3' && Name[18] == '2') // avx512.mask.psrav32hi 2018 IID = Intrinsic::x86_avx512_psrav_w_512; 2019 else 2020 llvm_unreachable("Unexpected size"); 2021 } else if (Name.endswith(".128")) { 2022 if (Size == 'd') // avx512.mask.psra.d.128, avx512.mask.psra.di.128 2023 IID = IsImmediate ? Intrinsic::x86_sse2_psrai_d 2024 : Intrinsic::x86_sse2_psra_d; 2025 else if (Size == 'q') // avx512.mask.psra.q.128, avx512.mask.psra.qi.128 2026 IID = IsImmediate ? Intrinsic::x86_avx512_psrai_q_128 : 2027 IsVariable ? Intrinsic::x86_avx512_psrav_q_128 : 2028 Intrinsic::x86_avx512_psra_q_128; 2029 else if (Size == 'w') // avx512.mask.psra.w.128, avx512.mask.psra.wi.128 2030 IID = IsImmediate ? Intrinsic::x86_sse2_psrai_w 2031 : Intrinsic::x86_sse2_psra_w; 2032 else 2033 llvm_unreachable("Unexpected size"); 2034 } else if (Name.endswith(".256")) { 2035 if (Size == 'd') // avx512.mask.psra.d.256, avx512.mask.psra.di.256 2036 IID = IsImmediate ? Intrinsic::x86_avx2_psrai_d 2037 : Intrinsic::x86_avx2_psra_d; 2038 else if (Size == 'q') // avx512.mask.psra.q.256, avx512.mask.psra.qi.256 2039 IID = IsImmediate ? Intrinsic::x86_avx512_psrai_q_256 : 2040 IsVariable ? Intrinsic::x86_avx512_psrav_q_256 : 2041 Intrinsic::x86_avx512_psra_q_256; 2042 else if (Size == 'w') // avx512.mask.psra.w.256, avx512.mask.psra.wi.256 2043 IID = IsImmediate ? Intrinsic::x86_avx2_psrai_w 2044 : Intrinsic::x86_avx2_psra_w; 2045 else 2046 llvm_unreachable("Unexpected size"); 2047 } else { 2048 if (Size == 'd') // psra.di.512, psrai.d, psra.d, psrav.d.512 2049 IID = IsImmediate ? Intrinsic::x86_avx512_psrai_d_512 : 2050 IsVariable ? Intrinsic::x86_avx512_psrav_d_512 : 2051 Intrinsic::x86_avx512_psra_d_512; 2052 else if (Size == 'q') // psra.qi.512, psrai.q, psra.q 2053 IID = IsImmediate ? Intrinsic::x86_avx512_psrai_q_512 : 2054 IsVariable ? Intrinsic::x86_avx512_psrav_q_512 : 2055 Intrinsic::x86_avx512_psra_q_512; 2056 else if (Size == 'w') // psra.wi.512, psrai.w, psra.w 2057 IID = IsImmediate ? Intrinsic::x86_avx512_psrai_w_512 2058 : Intrinsic::x86_avx512_psra_w_512; 2059 else 2060 llvm_unreachable("Unexpected size"); 2061 } 2062 2063 Rep = UpgradeX86MaskedShift(Builder, *CI, IID); 2064 } else if (IsX86 && Name.startswith("avx512.mask.move.s")) { 2065 Rep = upgradeMaskedMove(Builder, *CI); 2066 } else if (IsX86 && Name.startswith("avx512.cvtmask2")) { 2067 Rep = UpgradeMaskToInt(Builder, *CI); 2068 } else if (IsX86 && Name.startswith("avx512.mask.vpermilvar.")) { 2069 Intrinsic::ID IID; 2070 if (Name.endswith("ps.128")) 2071 IID = Intrinsic::x86_avx_vpermilvar_ps; 2072 else if (Name.endswith("pd.128")) 2073 IID = Intrinsic::x86_avx_vpermilvar_pd; 2074 else if (Name.endswith("ps.256")) 2075 IID = Intrinsic::x86_avx_vpermilvar_ps_256; 2076 else if (Name.endswith("pd.256")) 2077 IID = Intrinsic::x86_avx_vpermilvar_pd_256; 2078 else if (Name.endswith("ps.512")) 2079 IID = Intrinsic::x86_avx512_vpermilvar_ps_512; 2080 else if (Name.endswith("pd.512")) 2081 IID = Intrinsic::x86_avx512_vpermilvar_pd_512; 2082 else 2083 llvm_unreachable("Unexpected vpermilvar intrinsic"); 2084 2085 Function *Intrin = Intrinsic::getDeclaration(F->getParent(), IID); 2086 Rep = Builder.CreateCall(Intrin, 2087 { CI->getArgOperand(0), CI->getArgOperand(1) }); 2088 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 2089 CI->getArgOperand(2)); 2090 } else if (IsX86 && Name.endswith(".movntdqa")) { 2091 Module *M = F->getParent(); 2092 MDNode *Node = MDNode::get( 2093 C, ConstantAsMetadata::get(ConstantInt::get(Type::getInt32Ty(C), 1))); 2094 2095 Value *Ptr = CI->getArgOperand(0); 2096 VectorType *VTy = cast<VectorType>(CI->getType()); 2097 2098 // Convert the type of the pointer to a pointer to the stored type. 2099 Value *BC = 2100 Builder.CreateBitCast(Ptr, PointerType::getUnqual(VTy), "cast"); 2101 LoadInst *LI = Builder.CreateAlignedLoad(BC, VTy->getBitWidth() / 8); 2102 LI->setMetadata(M->getMDKindID("nontemporal"), Node); 2103 Rep = LI; 2104 } else if (IsX86 && 2105 (Name.startswith("sse2.pavg") || Name.startswith("avx2.pavg") || 2106 Name.startswith("avx512.mask.pavg"))) { 2107 // llvm.x86.sse2.pavg.b/w, llvm.x86.avx2.pavg.b/w, 2108 // llvm.x86.avx512.mask.pavg.b/w 2109 Value *A = CI->getArgOperand(0); 2110 Value *B = CI->getArgOperand(1); 2111 VectorType *ZextType = VectorType::getExtendedElementVectorType( 2112 cast<VectorType>(A->getType())); 2113 Value *ExtendedA = Builder.CreateZExt(A, ZextType); 2114 Value *ExtendedB = Builder.CreateZExt(B, ZextType); 2115 Value *Sum = Builder.CreateAdd(ExtendedA, ExtendedB); 2116 Value *AddOne = Builder.CreateAdd(Sum, ConstantInt::get(ZextType, 1)); 2117 Value *ShiftR = Builder.CreateLShr(AddOne, ConstantInt::get(ZextType, 1)); 2118 Rep = Builder.CreateTrunc(ShiftR, A->getType()); 2119 if (CI->getNumArgOperands() > 2) { 2120 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 2121 CI->getArgOperand(2)); 2122 } 2123 } else if (IsNVVM && (Name == "abs.i" || Name == "abs.ll")) { 2124 Value *Arg = CI->getArgOperand(0); 2125 Value *Neg = Builder.CreateNeg(Arg, "neg"); 2126 Value *Cmp = Builder.CreateICmpSGE( 2127 Arg, llvm::Constant::getNullValue(Arg->getType()), "abs.cond"); 2128 Rep = Builder.CreateSelect(Cmp, Arg, Neg, "abs"); 2129 } else if (IsNVVM && (Name == "max.i" || Name == "max.ll" || 2130 Name == "max.ui" || Name == "max.ull")) { 2131 Value *Arg0 = CI->getArgOperand(0); 2132 Value *Arg1 = CI->getArgOperand(1); 2133 Value *Cmp = Name.endswith(".ui") || Name.endswith(".ull") 2134 ? Builder.CreateICmpUGE(Arg0, Arg1, "max.cond") 2135 : Builder.CreateICmpSGE(Arg0, Arg1, "max.cond"); 2136 Rep = Builder.CreateSelect(Cmp, Arg0, Arg1, "max"); 2137 } else if (IsNVVM && (Name == "min.i" || Name == "min.ll" || 2138 Name == "min.ui" || Name == "min.ull")) { 2139 Value *Arg0 = CI->getArgOperand(0); 2140 Value *Arg1 = CI->getArgOperand(1); 2141 Value *Cmp = Name.endswith(".ui") || Name.endswith(".ull") 2142 ? Builder.CreateICmpULE(Arg0, Arg1, "min.cond") 2143 : Builder.CreateICmpSLE(Arg0, Arg1, "min.cond"); 2144 Rep = Builder.CreateSelect(Cmp, Arg0, Arg1, "min"); 2145 } else if (IsNVVM && Name == "clz.ll") { 2146 // llvm.nvvm.clz.ll returns an i32, but llvm.ctlz.i64 and returns an i64. 2147 Value *Arg = CI->getArgOperand(0); 2148 Value *Ctlz = Builder.CreateCall( 2149 Intrinsic::getDeclaration(F->getParent(), Intrinsic::ctlz, 2150 {Arg->getType()}), 2151 {Arg, Builder.getFalse()}, "ctlz"); 2152 Rep = Builder.CreateTrunc(Ctlz, Builder.getInt32Ty(), "ctlz.trunc"); 2153 } else if (IsNVVM && Name == "popc.ll") { 2154 // llvm.nvvm.popc.ll returns an i32, but llvm.ctpop.i64 and returns an 2155 // i64. 2156 Value *Arg = CI->getArgOperand(0); 2157 Value *Popc = Builder.CreateCall( 2158 Intrinsic::getDeclaration(F->getParent(), Intrinsic::ctpop, 2159 {Arg->getType()}), 2160 Arg, "ctpop"); 2161 Rep = Builder.CreateTrunc(Popc, Builder.getInt32Ty(), "ctpop.trunc"); 2162 } else if (IsNVVM && Name == "h2f") { 2163 Rep = Builder.CreateCall(Intrinsic::getDeclaration( 2164 F->getParent(), Intrinsic::convert_from_fp16, 2165 {Builder.getFloatTy()}), 2166 CI->getArgOperand(0), "h2f"); 2167 } else { 2168 llvm_unreachable("Unknown function for CallInst upgrade."); 2169 } 2170 2171 if (Rep) 2172 CI->replaceAllUsesWith(Rep); 2173 CI->eraseFromParent(); 2174 return; 2175 } 2176 2177 CallInst *NewCall = nullptr; 2178 switch (NewFn->getIntrinsicID()) { 2179 default: { 2180 // Handle generic mangling change, but nothing else 2181 assert( 2182 (CI->getCalledFunction()->getName() != NewFn->getName()) && 2183 "Unknown function for CallInst upgrade and isn't just a name change"); 2184 CI->setCalledFunction(NewFn); 2185 return; 2186 } 2187 2188 case Intrinsic::arm_neon_vld1: 2189 case Intrinsic::arm_neon_vld2: 2190 case Intrinsic::arm_neon_vld3: 2191 case Intrinsic::arm_neon_vld4: 2192 case Intrinsic::arm_neon_vld2lane: 2193 case Intrinsic::arm_neon_vld3lane: 2194 case Intrinsic::arm_neon_vld4lane: 2195 case Intrinsic::arm_neon_vst1: 2196 case Intrinsic::arm_neon_vst2: 2197 case Intrinsic::arm_neon_vst3: 2198 case Intrinsic::arm_neon_vst4: 2199 case Intrinsic::arm_neon_vst2lane: 2200 case Intrinsic::arm_neon_vst3lane: 2201 case Intrinsic::arm_neon_vst4lane: { 2202 SmallVector<Value *, 4> Args(CI->arg_operands().begin(), 2203 CI->arg_operands().end()); 2204 NewCall = Builder.CreateCall(NewFn, Args); 2205 break; 2206 } 2207 2208 case Intrinsic::bitreverse: 2209 NewCall = Builder.CreateCall(NewFn, {CI->getArgOperand(0)}); 2210 break; 2211 2212 case Intrinsic::ctlz: 2213 case Intrinsic::cttz: 2214 assert(CI->getNumArgOperands() == 1 && 2215 "Mismatch between function args and call args"); 2216 NewCall = 2217 Builder.CreateCall(NewFn, {CI->getArgOperand(0), Builder.getFalse()}); 2218 break; 2219 2220 case Intrinsic::objectsize: { 2221 Value *NullIsUnknownSize = CI->getNumArgOperands() == 2 2222 ? Builder.getFalse() 2223 : CI->getArgOperand(2); 2224 NewCall = Builder.CreateCall( 2225 NewFn, {CI->getArgOperand(0), CI->getArgOperand(1), NullIsUnknownSize}); 2226 break; 2227 } 2228 2229 case Intrinsic::ctpop: 2230 NewCall = Builder.CreateCall(NewFn, {CI->getArgOperand(0)}); 2231 break; 2232 2233 case Intrinsic::convert_from_fp16: 2234 NewCall = Builder.CreateCall(NewFn, {CI->getArgOperand(0)}); 2235 break; 2236 2237 case Intrinsic::dbg_value: 2238 // Upgrade from the old version that had an extra offset argument. 2239 assert(CI->getNumArgOperands() == 4); 2240 // Drop nonzero offsets instead of attempting to upgrade them. 2241 if (auto *Offset = dyn_cast_or_null<Constant>(CI->getArgOperand(1))) 2242 if (Offset->isZeroValue()) { 2243 NewCall = Builder.CreateCall( 2244 NewFn, 2245 {CI->getArgOperand(0), CI->getArgOperand(2), CI->getArgOperand(3)}); 2246 break; 2247 } 2248 CI->eraseFromParent(); 2249 return; 2250 2251 case Intrinsic::x86_xop_vfrcz_ss: 2252 case Intrinsic::x86_xop_vfrcz_sd: 2253 NewCall = Builder.CreateCall(NewFn, {CI->getArgOperand(1)}); 2254 break; 2255 2256 case Intrinsic::x86_xop_vpermil2pd: 2257 case Intrinsic::x86_xop_vpermil2ps: 2258 case Intrinsic::x86_xop_vpermil2pd_256: 2259 case Intrinsic::x86_xop_vpermil2ps_256: { 2260 SmallVector<Value *, 4> Args(CI->arg_operands().begin(), 2261 CI->arg_operands().end()); 2262 VectorType *FltIdxTy = cast<VectorType>(Args[2]->getType()); 2263 VectorType *IntIdxTy = VectorType::getInteger(FltIdxTy); 2264 Args[2] = Builder.CreateBitCast(Args[2], IntIdxTy); 2265 NewCall = Builder.CreateCall(NewFn, Args); 2266 break; 2267 } 2268 2269 case Intrinsic::x86_sse41_ptestc: 2270 case Intrinsic::x86_sse41_ptestz: 2271 case Intrinsic::x86_sse41_ptestnzc: { 2272 // The arguments for these intrinsics used to be v4f32, and changed 2273 // to v2i64. This is purely a nop, since those are bitwise intrinsics. 2274 // So, the only thing required is a bitcast for both arguments. 2275 // First, check the arguments have the old type. 2276 Value *Arg0 = CI->getArgOperand(0); 2277 if (Arg0->getType() != VectorType::get(Type::getFloatTy(C), 4)) 2278 return; 2279 2280 // Old intrinsic, add bitcasts 2281 Value *Arg1 = CI->getArgOperand(1); 2282 2283 Type *NewVecTy = VectorType::get(Type::getInt64Ty(C), 2); 2284 2285 Value *BC0 = Builder.CreateBitCast(Arg0, NewVecTy, "cast"); 2286 Value *BC1 = Builder.CreateBitCast(Arg1, NewVecTy, "cast"); 2287 2288 NewCall = Builder.CreateCall(NewFn, {BC0, BC1}); 2289 break; 2290 } 2291 2292 case Intrinsic::x86_sse41_insertps: 2293 case Intrinsic::x86_sse41_dppd: 2294 case Intrinsic::x86_sse41_dpps: 2295 case Intrinsic::x86_sse41_mpsadbw: 2296 case Intrinsic::x86_avx_dp_ps_256: 2297 case Intrinsic::x86_avx2_mpsadbw: { 2298 // Need to truncate the last argument from i32 to i8 -- this argument models 2299 // an inherently 8-bit immediate operand to these x86 instructions. 2300 SmallVector<Value *, 4> Args(CI->arg_operands().begin(), 2301 CI->arg_operands().end()); 2302 2303 // Replace the last argument with a trunc. 2304 Args.back() = Builder.CreateTrunc(Args.back(), Type::getInt8Ty(C), "trunc"); 2305 NewCall = Builder.CreateCall(NewFn, Args); 2306 break; 2307 } 2308 2309 case Intrinsic::thread_pointer: { 2310 NewCall = Builder.CreateCall(NewFn, {}); 2311 break; 2312 } 2313 2314 case Intrinsic::invariant_start: 2315 case Intrinsic::invariant_end: 2316 case Intrinsic::masked_load: 2317 case Intrinsic::masked_store: 2318 case Intrinsic::masked_gather: 2319 case Intrinsic::masked_scatter: { 2320 SmallVector<Value *, 4> Args(CI->arg_operands().begin(), 2321 CI->arg_operands().end()); 2322 NewCall = Builder.CreateCall(NewFn, Args); 2323 break; 2324 } 2325 } 2326 assert(NewCall && "Should have either set this variable or returned through " 2327 "the default case"); 2328 std::string Name = CI->getName(); 2329 if (!Name.empty()) { 2330 CI->setName(Name + ".old"); 2331 NewCall->setName(Name); 2332 } 2333 CI->replaceAllUsesWith(NewCall); 2334 CI->eraseFromParent(); 2335 } 2336 2337 void llvm::UpgradeCallsToIntrinsic(Function *F) { 2338 assert(F && "Illegal attempt to upgrade a non-existent intrinsic."); 2339 2340 // Check if this function should be upgraded and get the replacement function 2341 // if there is one. 2342 Function *NewFn; 2343 if (UpgradeIntrinsicFunction(F, NewFn)) { 2344 // Replace all users of the old function with the new function or new 2345 // instructions. This is not a range loop because the call is deleted. 2346 for (auto UI = F->user_begin(), UE = F->user_end(); UI != UE; ) 2347 if (CallInst *CI = dyn_cast<CallInst>(*UI++)) 2348 UpgradeIntrinsicCall(CI, NewFn); 2349 2350 // Remove old function, no longer used, from the module. 2351 F->eraseFromParent(); 2352 } 2353 } 2354 2355 MDNode *llvm::UpgradeTBAANode(MDNode &MD) { 2356 // Check if the tag uses struct-path aware TBAA format. 2357 if (isa<MDNode>(MD.getOperand(0)) && MD.getNumOperands() >= 3) 2358 return &MD; 2359 2360 auto &Context = MD.getContext(); 2361 if (MD.getNumOperands() == 3) { 2362 Metadata *Elts[] = {MD.getOperand(0), MD.getOperand(1)}; 2363 MDNode *ScalarType = MDNode::get(Context, Elts); 2364 // Create a MDNode <ScalarType, ScalarType, offset 0, const> 2365 Metadata *Elts2[] = {ScalarType, ScalarType, 2366 ConstantAsMetadata::get( 2367 Constant::getNullValue(Type::getInt64Ty(Context))), 2368 MD.getOperand(2)}; 2369 return MDNode::get(Context, Elts2); 2370 } 2371 // Create a MDNode <MD, MD, offset 0> 2372 Metadata *Elts[] = {&MD, &MD, ConstantAsMetadata::get(Constant::getNullValue( 2373 Type::getInt64Ty(Context)))}; 2374 return MDNode::get(Context, Elts); 2375 } 2376 2377 Instruction *llvm::UpgradeBitCastInst(unsigned Opc, Value *V, Type *DestTy, 2378 Instruction *&Temp) { 2379 if (Opc != Instruction::BitCast) 2380 return nullptr; 2381 2382 Temp = nullptr; 2383 Type *SrcTy = V->getType(); 2384 if (SrcTy->isPtrOrPtrVectorTy() && DestTy->isPtrOrPtrVectorTy() && 2385 SrcTy->getPointerAddressSpace() != DestTy->getPointerAddressSpace()) { 2386 LLVMContext &Context = V->getContext(); 2387 2388 // We have no information about target data layout, so we assume that 2389 // the maximum pointer size is 64bit. 2390 Type *MidTy = Type::getInt64Ty(Context); 2391 Temp = CastInst::Create(Instruction::PtrToInt, V, MidTy); 2392 2393 return CastInst::Create(Instruction::IntToPtr, Temp, DestTy); 2394 } 2395 2396 return nullptr; 2397 } 2398 2399 Value *llvm::UpgradeBitCastExpr(unsigned Opc, Constant *C, Type *DestTy) { 2400 if (Opc != Instruction::BitCast) 2401 return nullptr; 2402 2403 Type *SrcTy = C->getType(); 2404 if (SrcTy->isPtrOrPtrVectorTy() && DestTy->isPtrOrPtrVectorTy() && 2405 SrcTy->getPointerAddressSpace() != DestTy->getPointerAddressSpace()) { 2406 LLVMContext &Context = C->getContext(); 2407 2408 // We have no information about target data layout, so we assume that 2409 // the maximum pointer size is 64bit. 2410 Type *MidTy = Type::getInt64Ty(Context); 2411 2412 return ConstantExpr::getIntToPtr(ConstantExpr::getPtrToInt(C, MidTy), 2413 DestTy); 2414 } 2415 2416 return nullptr; 2417 } 2418 2419 /// Check the debug info version number, if it is out-dated, drop the debug 2420 /// info. Return true if module is modified. 2421 bool llvm::UpgradeDebugInfo(Module &M) { 2422 unsigned Version = getDebugMetadataVersionFromModule(M); 2423 if (Version == DEBUG_METADATA_VERSION) { 2424 bool BrokenDebugInfo = false; 2425 if (verifyModule(M, &llvm::errs(), &BrokenDebugInfo)) 2426 report_fatal_error("Broken module found, compilation aborted!"); 2427 if (!BrokenDebugInfo) 2428 // Everything is ok. 2429 return false; 2430 else { 2431 // Diagnose malformed debug info. 2432 DiagnosticInfoIgnoringInvalidDebugMetadata Diag(M); 2433 M.getContext().diagnose(Diag); 2434 } 2435 } 2436 bool Modified = StripDebugInfo(M); 2437 if (Modified && Version != DEBUG_METADATA_VERSION) { 2438 // Diagnose a version mismatch. 2439 DiagnosticInfoDebugMetadataVersion DiagVersion(M, Version); 2440 M.getContext().diagnose(DiagVersion); 2441 } 2442 return Modified; 2443 } 2444 2445 bool llvm::UpgradeModuleFlags(Module &M) { 2446 NamedMDNode *ModFlags = M.getModuleFlagsMetadata(); 2447 if (!ModFlags) 2448 return false; 2449 2450 bool HasObjCFlag = false, HasClassProperties = false, Changed = false; 2451 for (unsigned I = 0, E = ModFlags->getNumOperands(); I != E; ++I) { 2452 MDNode *Op = ModFlags->getOperand(I); 2453 if (Op->getNumOperands() != 3) 2454 continue; 2455 MDString *ID = dyn_cast_or_null<MDString>(Op->getOperand(1)); 2456 if (!ID) 2457 continue; 2458 if (ID->getString() == "Objective-C Image Info Version") 2459 HasObjCFlag = true; 2460 if (ID->getString() == "Objective-C Class Properties") 2461 HasClassProperties = true; 2462 // Upgrade PIC/PIE Module Flags. The module flag behavior for these two 2463 // field was Error and now they are Max. 2464 if (ID->getString() == "PIC Level" || ID->getString() == "PIE Level") { 2465 if (auto *Behavior = 2466 mdconst::dyn_extract_or_null<ConstantInt>(Op->getOperand(0))) { 2467 if (Behavior->getLimitedValue() == Module::Error) { 2468 Type *Int32Ty = Type::getInt32Ty(M.getContext()); 2469 Metadata *Ops[3] = { 2470 ConstantAsMetadata::get(ConstantInt::get(Int32Ty, Module::Max)), 2471 MDString::get(M.getContext(), ID->getString()), 2472 Op->getOperand(2)}; 2473 ModFlags->setOperand(I, MDNode::get(M.getContext(), Ops)); 2474 Changed = true; 2475 } 2476 } 2477 } 2478 // Upgrade Objective-C Image Info Section. Removed the whitespce in the 2479 // section name so that llvm-lto will not complain about mismatching 2480 // module flags that is functionally the same. 2481 if (ID->getString() == "Objective-C Image Info Section") { 2482 if (auto *Value = dyn_cast_or_null<MDString>(Op->getOperand(2))) { 2483 SmallVector<StringRef, 4> ValueComp; 2484 Value->getString().split(ValueComp, " "); 2485 if (ValueComp.size() != 1) { 2486 std::string NewValue; 2487 for (auto &S : ValueComp) 2488 NewValue += S.str(); 2489 Metadata *Ops[3] = {Op->getOperand(0), Op->getOperand(1), 2490 MDString::get(M.getContext(), NewValue)}; 2491 ModFlags->setOperand(I, MDNode::get(M.getContext(), Ops)); 2492 Changed = true; 2493 } 2494 } 2495 } 2496 } 2497 2498 // "Objective-C Class Properties" is recently added for Objective-C. We 2499 // upgrade ObjC bitcodes to contain a "Objective-C Class Properties" module 2500 // flag of value 0, so we can correclty downgrade this flag when trying to 2501 // link an ObjC bitcode without this module flag with an ObjC bitcode with 2502 // this module flag. 2503 if (HasObjCFlag && !HasClassProperties) { 2504 M.addModuleFlag(llvm::Module::Override, "Objective-C Class Properties", 2505 (uint32_t)0); 2506 Changed = true; 2507 } 2508 2509 return Changed; 2510 } 2511 2512 void llvm::UpgradeSectionAttributes(Module &M) { 2513 auto TrimSpaces = [](StringRef Section) -> std::string { 2514 SmallVector<StringRef, 5> Components; 2515 Section.split(Components, ','); 2516 2517 SmallString<32> Buffer; 2518 raw_svector_ostream OS(Buffer); 2519 2520 for (auto Component : Components) 2521 OS << ',' << Component.trim(); 2522 2523 return OS.str().substr(1); 2524 }; 2525 2526 for (auto &GV : M.globals()) { 2527 if (!GV.hasSection()) 2528 continue; 2529 2530 StringRef Section = GV.getSection(); 2531 2532 if (!Section.startswith("__DATA, __objc_catlist")) 2533 continue; 2534 2535 // __DATA, __objc_catlist, regular, no_dead_strip 2536 // __DATA,__objc_catlist,regular,no_dead_strip 2537 GV.setSection(TrimSpaces(Section)); 2538 } 2539 } 2540 2541 static bool isOldLoopArgument(Metadata *MD) { 2542 auto *T = dyn_cast_or_null<MDTuple>(MD); 2543 if (!T) 2544 return false; 2545 if (T->getNumOperands() < 1) 2546 return false; 2547 auto *S = dyn_cast_or_null<MDString>(T->getOperand(0)); 2548 if (!S) 2549 return false; 2550 return S->getString().startswith("llvm.vectorizer."); 2551 } 2552 2553 static MDString *upgradeLoopTag(LLVMContext &C, StringRef OldTag) { 2554 StringRef OldPrefix = "llvm.vectorizer."; 2555 assert(OldTag.startswith(OldPrefix) && "Expected old prefix"); 2556 2557 if (OldTag == "llvm.vectorizer.unroll") 2558 return MDString::get(C, "llvm.loop.interleave.count"); 2559 2560 return MDString::get( 2561 C, (Twine("llvm.loop.vectorize.") + OldTag.drop_front(OldPrefix.size())) 2562 .str()); 2563 } 2564 2565 static Metadata *upgradeLoopArgument(Metadata *MD) { 2566 auto *T = dyn_cast_or_null<MDTuple>(MD); 2567 if (!T) 2568 return MD; 2569 if (T->getNumOperands() < 1) 2570 return MD; 2571 auto *OldTag = dyn_cast_or_null<MDString>(T->getOperand(0)); 2572 if (!OldTag) 2573 return MD; 2574 if (!OldTag->getString().startswith("llvm.vectorizer.")) 2575 return MD; 2576 2577 // This has an old tag. Upgrade it. 2578 SmallVector<Metadata *, 8> Ops; 2579 Ops.reserve(T->getNumOperands()); 2580 Ops.push_back(upgradeLoopTag(T->getContext(), OldTag->getString())); 2581 for (unsigned I = 1, E = T->getNumOperands(); I != E; ++I) 2582 Ops.push_back(T->getOperand(I)); 2583 2584 return MDTuple::get(T->getContext(), Ops); 2585 } 2586 2587 MDNode *llvm::upgradeInstructionLoopAttachment(MDNode &N) { 2588 auto *T = dyn_cast<MDTuple>(&N); 2589 if (!T) 2590 return &N; 2591 2592 if (none_of(T->operands(), isOldLoopArgument)) 2593 return &N; 2594 2595 SmallVector<Metadata *, 8> Ops; 2596 Ops.reserve(T->getNumOperands()); 2597 for (Metadata *MD : T->operands()) 2598 Ops.push_back(upgradeLoopArgument(MD)); 2599 2600 return MDTuple::get(T->getContext(), Ops); 2601 } 2602