1 //===-- AutoUpgrade.cpp - Implement auto-upgrade helper functions ---------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements the auto-upgrade helper functions. 11 // This is where deprecated IR intrinsics and other IR features are updated to 12 // current specifications. 13 // 14 //===----------------------------------------------------------------------===// 15 16 #include "llvm/IR/AutoUpgrade.h" 17 #include "llvm/ADT/StringSwitch.h" 18 #include "llvm/IR/CFG.h" 19 #include "llvm/IR/CallSite.h" 20 #include "llvm/IR/Constants.h" 21 #include "llvm/IR/DIBuilder.h" 22 #include "llvm/IR/DebugInfo.h" 23 #include "llvm/IR/DiagnosticInfo.h" 24 #include "llvm/IR/Function.h" 25 #include "llvm/IR/IRBuilder.h" 26 #include "llvm/IR/Instruction.h" 27 #include "llvm/IR/IntrinsicInst.h" 28 #include "llvm/IR/LLVMContext.h" 29 #include "llvm/IR/Module.h" 30 #include "llvm/IR/Verifier.h" 31 #include "llvm/Support/ErrorHandling.h" 32 #include "llvm/Support/Regex.h" 33 #include <cstring> 34 using namespace llvm; 35 36 static void rename(GlobalValue *GV) { GV->setName(GV->getName() + ".old"); } 37 38 // Upgrade the declarations of the SSE4.1 ptest intrinsics whose arguments have 39 // changed their type from v4f32 to v2i64. 40 static bool UpgradePTESTIntrinsic(Function* F, Intrinsic::ID IID, 41 Function *&NewFn) { 42 // Check whether this is an old version of the function, which received 43 // v4f32 arguments. 44 Type *Arg0Type = F->getFunctionType()->getParamType(0); 45 if (Arg0Type != VectorType::get(Type::getFloatTy(F->getContext()), 4)) 46 return false; 47 48 // Yes, it's old, replace it with new version. 49 rename(F); 50 NewFn = Intrinsic::getDeclaration(F->getParent(), IID); 51 return true; 52 } 53 54 // Upgrade the declarations of intrinsic functions whose 8-bit immediate mask 55 // arguments have changed their type from i32 to i8. 56 static bool UpgradeX86IntrinsicsWith8BitMask(Function *F, Intrinsic::ID IID, 57 Function *&NewFn) { 58 // Check that the last argument is an i32. 59 Type *LastArgType = F->getFunctionType()->getParamType( 60 F->getFunctionType()->getNumParams() - 1); 61 if (!LastArgType->isIntegerTy(32)) 62 return false; 63 64 // Move this function aside and map down. 65 rename(F); 66 NewFn = Intrinsic::getDeclaration(F->getParent(), IID); 67 return true; 68 } 69 70 static bool ShouldUpgradeX86Intrinsic(Function *F, StringRef Name) { 71 // All of the intrinsics matches below should be marked with which llvm 72 // version started autoupgrading them. At some point in the future we would 73 // like to use this information to remove upgrade code for some older 74 // intrinsics. It is currently undecided how we will determine that future 75 // point. 76 if (Name=="ssse3.pabs.b.128" || // Added in 6.0 77 Name=="ssse3.pabs.w.128" || // Added in 6.0 78 Name=="ssse3.pabs.d.128" || // Added in 6.0 79 Name.startswith("avx512.mask.shuf.i") || // Added in 6.0 80 Name.startswith("avx512.mask.shuf.f") || // Added in 6.0 81 Name.startswith("avx2.pabs.") || // Added in 6.0 82 Name.startswith("avx512.mask.pabs.") || // Added in 6.0 83 Name.startswith("avx512.broadcastm") || // Added in 6.0 84 Name.startswith("avx512.mask.pbroadcast") || // Added in 6.0 85 Name.startswith("sse2.pcmpeq.") || // Added in 3.1 86 Name.startswith("sse2.pcmpgt.") || // Added in 3.1 87 Name.startswith("avx2.pcmpeq.") || // Added in 3.1 88 Name.startswith("avx2.pcmpgt.") || // Added in 3.1 89 Name.startswith("avx512.mask.pcmpeq.") || // Added in 3.9 90 Name.startswith("avx512.mask.pcmpgt.") || // Added in 3.9 91 Name.startswith("avx.vperm2f128.") || // Added in 6.0 92 Name == "avx2.vperm2i128" || // Added in 6.0 93 Name == "sse.add.ss" || // Added in 4.0 94 Name == "sse2.add.sd" || // Added in 4.0 95 Name == "sse.sub.ss" || // Added in 4.0 96 Name == "sse2.sub.sd" || // Added in 4.0 97 Name == "sse.mul.ss" || // Added in 4.0 98 Name == "sse2.mul.sd" || // Added in 4.0 99 Name == "sse.div.ss" || // Added in 4.0 100 Name == "sse2.div.sd" || // Added in 4.0 101 Name == "sse41.pmaxsb" || // Added in 3.9 102 Name == "sse2.pmaxs.w" || // Added in 3.9 103 Name == "sse41.pmaxsd" || // Added in 3.9 104 Name == "sse2.pmaxu.b" || // Added in 3.9 105 Name == "sse41.pmaxuw" || // Added in 3.9 106 Name == "sse41.pmaxud" || // Added in 3.9 107 Name == "sse41.pminsb" || // Added in 3.9 108 Name == "sse2.pmins.w" || // Added in 3.9 109 Name == "sse41.pminsd" || // Added in 3.9 110 Name == "sse2.pminu.b" || // Added in 3.9 111 Name == "sse41.pminuw" || // Added in 3.9 112 Name == "sse41.pminud" || // Added in 3.9 113 Name.startswith("avx512.mask.pshuf.b.") || // Added in 4.0 114 Name.startswith("avx2.pmax") || // Added in 3.9 115 Name.startswith("avx2.pmin") || // Added in 3.9 116 Name.startswith("avx512.mask.pmax") || // Added in 4.0 117 Name.startswith("avx512.mask.pmin") || // Added in 4.0 118 Name.startswith("avx2.vbroadcast") || // Added in 3.8 119 Name.startswith("avx2.pbroadcast") || // Added in 3.8 120 Name.startswith("avx.vpermil.") || // Added in 3.1 121 Name.startswith("sse2.pshuf") || // Added in 3.9 122 Name.startswith("avx512.pbroadcast") || // Added in 3.9 123 Name.startswith("avx512.mask.broadcast.s") || // Added in 3.9 124 Name.startswith("avx512.mask.movddup") || // Added in 3.9 125 Name.startswith("avx512.mask.movshdup") || // Added in 3.9 126 Name.startswith("avx512.mask.movsldup") || // Added in 3.9 127 Name.startswith("avx512.mask.pshuf.d.") || // Added in 3.9 128 Name.startswith("avx512.mask.pshufl.w.") || // Added in 3.9 129 Name.startswith("avx512.mask.pshufh.w.") || // Added in 3.9 130 Name.startswith("avx512.mask.shuf.p") || // Added in 4.0 131 Name.startswith("avx512.mask.vpermil.p") || // Added in 3.9 132 Name.startswith("avx512.mask.perm.df.") || // Added in 3.9 133 Name.startswith("avx512.mask.perm.di.") || // Added in 3.9 134 Name.startswith("avx512.mask.punpckl") || // Added in 3.9 135 Name.startswith("avx512.mask.punpckh") || // Added in 3.9 136 Name.startswith("avx512.mask.unpckl.") || // Added in 3.9 137 Name.startswith("avx512.mask.unpckh.") || // Added in 3.9 138 Name.startswith("avx512.mask.pand.") || // Added in 3.9 139 Name.startswith("avx512.mask.pandn.") || // Added in 3.9 140 Name.startswith("avx512.mask.por.") || // Added in 3.9 141 Name.startswith("avx512.mask.pxor.") || // Added in 3.9 142 Name.startswith("avx512.mask.and.") || // Added in 3.9 143 Name.startswith("avx512.mask.andn.") || // Added in 3.9 144 Name.startswith("avx512.mask.or.") || // Added in 3.9 145 Name.startswith("avx512.mask.xor.") || // Added in 3.9 146 Name.startswith("avx512.mask.padd.") || // Added in 4.0 147 Name.startswith("avx512.mask.psub.") || // Added in 4.0 148 Name.startswith("avx512.mask.pmull.") || // Added in 4.0 149 Name.startswith("avx512.mask.cvtdq2pd.") || // Added in 4.0 150 Name.startswith("avx512.mask.cvtudq2pd.") || // Added in 4.0 151 Name.startswith("avx512.mask.pmul.dq.") || // Added in 4.0 152 Name.startswith("avx512.mask.pmulu.dq.") || // Added in 4.0 153 Name.startswith("avx512.mask.packsswb.") || // Added in 5.0 154 Name.startswith("avx512.mask.packssdw.") || // Added in 5.0 155 Name.startswith("avx512.mask.packuswb.") || // Added in 5.0 156 Name.startswith("avx512.mask.packusdw.") || // Added in 5.0 157 Name.startswith("avx512.mask.cmp.b") || // Added in 5.0 158 Name.startswith("avx512.mask.cmp.d") || // Added in 5.0 159 Name.startswith("avx512.mask.cmp.q") || // Added in 5.0 160 Name.startswith("avx512.mask.cmp.w") || // Added in 5.0 161 Name.startswith("avx512.mask.ucmp.") || // Added in 5.0 162 Name == "avx512.mask.add.pd.128" || // Added in 4.0 163 Name == "avx512.mask.add.pd.256" || // Added in 4.0 164 Name == "avx512.mask.add.ps.128" || // Added in 4.0 165 Name == "avx512.mask.add.ps.256" || // Added in 4.0 166 Name == "avx512.mask.div.pd.128" || // Added in 4.0 167 Name == "avx512.mask.div.pd.256" || // Added in 4.0 168 Name == "avx512.mask.div.ps.128" || // Added in 4.0 169 Name == "avx512.mask.div.ps.256" || // Added in 4.0 170 Name == "avx512.mask.mul.pd.128" || // Added in 4.0 171 Name == "avx512.mask.mul.pd.256" || // Added in 4.0 172 Name == "avx512.mask.mul.ps.128" || // Added in 4.0 173 Name == "avx512.mask.mul.ps.256" || // Added in 4.0 174 Name == "avx512.mask.sub.pd.128" || // Added in 4.0 175 Name == "avx512.mask.sub.pd.256" || // Added in 4.0 176 Name == "avx512.mask.sub.ps.128" || // Added in 4.0 177 Name == "avx512.mask.sub.ps.256" || // Added in 4.0 178 Name == "avx512.mask.max.pd.128" || // Added in 5.0 179 Name == "avx512.mask.max.pd.256" || // Added in 5.0 180 Name == "avx512.mask.max.ps.128" || // Added in 5.0 181 Name == "avx512.mask.max.ps.256" || // Added in 5.0 182 Name == "avx512.mask.min.pd.128" || // Added in 5.0 183 Name == "avx512.mask.min.pd.256" || // Added in 5.0 184 Name == "avx512.mask.min.ps.128" || // Added in 5.0 185 Name == "avx512.mask.min.ps.256" || // Added in 5.0 186 Name.startswith("avx512.mask.vpermilvar.") || // Added in 4.0 187 Name.startswith("avx512.mask.psll.d") || // Added in 4.0 188 Name.startswith("avx512.mask.psll.q") || // Added in 4.0 189 Name.startswith("avx512.mask.psll.w") || // Added in 4.0 190 Name.startswith("avx512.mask.psra.d") || // Added in 4.0 191 Name.startswith("avx512.mask.psra.q") || // Added in 4.0 192 Name.startswith("avx512.mask.psra.w") || // Added in 4.0 193 Name.startswith("avx512.mask.psrl.d") || // Added in 4.0 194 Name.startswith("avx512.mask.psrl.q") || // Added in 4.0 195 Name.startswith("avx512.mask.psrl.w") || // Added in 4.0 196 Name.startswith("avx512.mask.pslli") || // Added in 4.0 197 Name.startswith("avx512.mask.psrai") || // Added in 4.0 198 Name.startswith("avx512.mask.psrli") || // Added in 4.0 199 Name.startswith("avx512.mask.psllv") || // Added in 4.0 200 Name.startswith("avx512.mask.psrav") || // Added in 4.0 201 Name.startswith("avx512.mask.psrlv") || // Added in 4.0 202 Name.startswith("sse41.pmovsx") || // Added in 3.8 203 Name.startswith("sse41.pmovzx") || // Added in 3.9 204 Name.startswith("avx2.pmovsx") || // Added in 3.9 205 Name.startswith("avx2.pmovzx") || // Added in 3.9 206 Name.startswith("avx512.mask.pmovsx") || // Added in 4.0 207 Name.startswith("avx512.mask.pmovzx") || // Added in 4.0 208 Name.startswith("avx512.mask.lzcnt.") || // Added in 5.0 209 Name == "sse2.cvtdq2pd" || // Added in 3.9 210 Name == "sse2.cvtps2pd" || // Added in 3.9 211 Name == "avx.cvtdq2.pd.256" || // Added in 3.9 212 Name == "avx.cvt.ps2.pd.256" || // Added in 3.9 213 Name.startswith("avx.vinsertf128.") || // Added in 3.7 214 Name == "avx2.vinserti128" || // Added in 3.7 215 Name.startswith("avx512.mask.insert") || // Added in 4.0 216 Name.startswith("avx.vextractf128.") || // Added in 3.7 217 Name == "avx2.vextracti128" || // Added in 3.7 218 Name.startswith("avx512.mask.vextract") || // Added in 4.0 219 Name.startswith("sse4a.movnt.") || // Added in 3.9 220 Name.startswith("avx.movnt.") || // Added in 3.2 221 Name.startswith("avx512.storent.") || // Added in 3.9 222 Name == "sse41.movntdqa" || // Added in 5.0 223 Name == "avx2.movntdqa" || // Added in 5.0 224 Name == "avx512.movntdqa" || // Added in 5.0 225 Name == "sse2.storel.dq" || // Added in 3.9 226 Name.startswith("sse.storeu.") || // Added in 3.9 227 Name.startswith("sse2.storeu.") || // Added in 3.9 228 Name.startswith("avx.storeu.") || // Added in 3.9 229 Name.startswith("avx512.mask.storeu.") || // Added in 3.9 230 Name.startswith("avx512.mask.store.p") || // Added in 3.9 231 Name.startswith("avx512.mask.store.b.") || // Added in 3.9 232 Name.startswith("avx512.mask.store.w.") || // Added in 3.9 233 Name.startswith("avx512.mask.store.d.") || // Added in 3.9 234 Name.startswith("avx512.mask.store.q.") || // Added in 3.9 235 Name.startswith("avx512.mask.loadu.") || // Added in 3.9 236 Name.startswith("avx512.mask.load.") || // Added in 3.9 237 Name == "sse42.crc32.64.8" || // Added in 3.4 238 Name.startswith("avx.vbroadcast.s") || // Added in 3.5 239 Name.startswith("avx512.mask.palignr.") || // Added in 3.9 240 Name.startswith("avx512.mask.valign.") || // Added in 4.0 241 Name.startswith("sse2.psll.dq") || // Added in 3.7 242 Name.startswith("sse2.psrl.dq") || // Added in 3.7 243 Name.startswith("avx2.psll.dq") || // Added in 3.7 244 Name.startswith("avx2.psrl.dq") || // Added in 3.7 245 Name.startswith("avx512.psll.dq") || // Added in 3.9 246 Name.startswith("avx512.psrl.dq") || // Added in 3.9 247 Name == "sse41.pblendw" || // Added in 3.7 248 Name.startswith("sse41.blendp") || // Added in 3.7 249 Name.startswith("avx.blend.p") || // Added in 3.7 250 Name == "avx2.pblendw" || // Added in 3.7 251 Name.startswith("avx2.pblendd.") || // Added in 3.7 252 Name.startswith("avx.vbroadcastf128") || // Added in 4.0 253 Name == "avx2.vbroadcasti128" || // Added in 3.7 254 Name.startswith("avx512.mask.broadcastf") || // Added in 6.0 255 Name.startswith("avx512.mask.broadcasti") || // Added in 6.0 256 Name == "xop.vpcmov" || // Added in 3.8 257 Name == "xop.vpcmov.256" || // Added in 5.0 258 Name.startswith("avx512.mask.move.s") || // Added in 4.0 259 Name.startswith("avx512.cvtmask2") || // Added in 5.0 260 (Name.startswith("xop.vpcom") && // Added in 3.2 261 F->arg_size() == 2) || 262 Name.startswith("avx512.ptestm") || //Added in 6.0 263 Name.startswith("avx512.ptestnm") || //Added in 6.0 264 Name.startswith("sse2.pavg") || // Added in 6.0 265 Name.startswith("avx2.pavg") || // Added in 6.0 266 Name.startswith("avx512.mask.pavg")) // Added in 6.0 267 return true; 268 269 return false; 270 } 271 272 static bool UpgradeX86IntrinsicFunction(Function *F, StringRef Name, 273 Function *&NewFn) { 274 // Only handle intrinsics that start with "x86.". 275 if (!Name.startswith("x86.")) 276 return false; 277 // Remove "x86." prefix. 278 Name = Name.substr(4); 279 280 if (ShouldUpgradeX86Intrinsic(F, Name)) { 281 NewFn = nullptr; 282 return true; 283 } 284 285 // SSE4.1 ptest functions may have an old signature. 286 if (Name.startswith("sse41.ptest")) { // Added in 3.2 287 if (Name.substr(11) == "c") 288 return UpgradePTESTIntrinsic(F, Intrinsic::x86_sse41_ptestc, NewFn); 289 if (Name.substr(11) == "z") 290 return UpgradePTESTIntrinsic(F, Intrinsic::x86_sse41_ptestz, NewFn); 291 if (Name.substr(11) == "nzc") 292 return UpgradePTESTIntrinsic(F, Intrinsic::x86_sse41_ptestnzc, NewFn); 293 } 294 // Several blend and other instructions with masks used the wrong number of 295 // bits. 296 if (Name == "sse41.insertps") // Added in 3.6 297 return UpgradeX86IntrinsicsWith8BitMask(F, Intrinsic::x86_sse41_insertps, 298 NewFn); 299 if (Name == "sse41.dppd") // Added in 3.6 300 return UpgradeX86IntrinsicsWith8BitMask(F, Intrinsic::x86_sse41_dppd, 301 NewFn); 302 if (Name == "sse41.dpps") // Added in 3.6 303 return UpgradeX86IntrinsicsWith8BitMask(F, Intrinsic::x86_sse41_dpps, 304 NewFn); 305 if (Name == "sse41.mpsadbw") // Added in 3.6 306 return UpgradeX86IntrinsicsWith8BitMask(F, Intrinsic::x86_sse41_mpsadbw, 307 NewFn); 308 if (Name == "avx.dp.ps.256") // Added in 3.6 309 return UpgradeX86IntrinsicsWith8BitMask(F, Intrinsic::x86_avx_dp_ps_256, 310 NewFn); 311 if (Name == "avx2.mpsadbw") // Added in 3.6 312 return UpgradeX86IntrinsicsWith8BitMask(F, Intrinsic::x86_avx2_mpsadbw, 313 NewFn); 314 315 // frcz.ss/sd may need to have an argument dropped. Added in 3.2 316 if (Name.startswith("xop.vfrcz.ss") && F->arg_size() == 2) { 317 rename(F); 318 NewFn = Intrinsic::getDeclaration(F->getParent(), 319 Intrinsic::x86_xop_vfrcz_ss); 320 return true; 321 } 322 if (Name.startswith("xop.vfrcz.sd") && F->arg_size() == 2) { 323 rename(F); 324 NewFn = Intrinsic::getDeclaration(F->getParent(), 325 Intrinsic::x86_xop_vfrcz_sd); 326 return true; 327 } 328 // Upgrade any XOP PERMIL2 index operand still using a float/double vector. 329 if (Name.startswith("xop.vpermil2")) { // Added in 3.9 330 auto Idx = F->getFunctionType()->getParamType(2); 331 if (Idx->isFPOrFPVectorTy()) { 332 rename(F); 333 unsigned IdxSize = Idx->getPrimitiveSizeInBits(); 334 unsigned EltSize = Idx->getScalarSizeInBits(); 335 Intrinsic::ID Permil2ID; 336 if (EltSize == 64 && IdxSize == 128) 337 Permil2ID = Intrinsic::x86_xop_vpermil2pd; 338 else if (EltSize == 32 && IdxSize == 128) 339 Permil2ID = Intrinsic::x86_xop_vpermil2ps; 340 else if (EltSize == 64 && IdxSize == 256) 341 Permil2ID = Intrinsic::x86_xop_vpermil2pd_256; 342 else 343 Permil2ID = Intrinsic::x86_xop_vpermil2ps_256; 344 NewFn = Intrinsic::getDeclaration(F->getParent(), Permil2ID); 345 return true; 346 } 347 } 348 349 return false; 350 } 351 352 static bool UpgradeIntrinsicFunction1(Function *F, Function *&NewFn) { 353 assert(F && "Illegal to upgrade a non-existent Function."); 354 355 // Quickly eliminate it, if it's not a candidate. 356 StringRef Name = F->getName(); 357 if (Name.size() <= 8 || !Name.startswith("llvm.")) 358 return false; 359 Name = Name.substr(5); // Strip off "llvm." 360 361 switch (Name[0]) { 362 default: break; 363 case 'a': { 364 if (Name.startswith("arm.rbit") || Name.startswith("aarch64.rbit")) { 365 NewFn = Intrinsic::getDeclaration(F->getParent(), Intrinsic::bitreverse, 366 F->arg_begin()->getType()); 367 return true; 368 } 369 if (Name.startswith("arm.neon.vclz")) { 370 Type* args[2] = { 371 F->arg_begin()->getType(), 372 Type::getInt1Ty(F->getContext()) 373 }; 374 // Can't use Intrinsic::getDeclaration here as it adds a ".i1" to 375 // the end of the name. Change name from llvm.arm.neon.vclz.* to 376 // llvm.ctlz.* 377 FunctionType* fType = FunctionType::get(F->getReturnType(), args, false); 378 NewFn = Function::Create(fType, F->getLinkage(), 379 "llvm.ctlz." + Name.substr(14), F->getParent()); 380 return true; 381 } 382 if (Name.startswith("arm.neon.vcnt")) { 383 NewFn = Intrinsic::getDeclaration(F->getParent(), Intrinsic::ctpop, 384 F->arg_begin()->getType()); 385 return true; 386 } 387 Regex vldRegex("^arm\\.neon\\.vld([1234]|[234]lane)\\.v[a-z0-9]*$"); 388 if (vldRegex.match(Name)) { 389 auto fArgs = F->getFunctionType()->params(); 390 SmallVector<Type *, 4> Tys(fArgs.begin(), fArgs.end()); 391 // Can't use Intrinsic::getDeclaration here as the return types might 392 // then only be structurally equal. 393 FunctionType* fType = FunctionType::get(F->getReturnType(), Tys, false); 394 NewFn = Function::Create(fType, F->getLinkage(), 395 "llvm." + Name + ".p0i8", F->getParent()); 396 return true; 397 } 398 Regex vstRegex("^arm\\.neon\\.vst([1234]|[234]lane)\\.v[a-z0-9]*$"); 399 if (vstRegex.match(Name)) { 400 static const Intrinsic::ID StoreInts[] = {Intrinsic::arm_neon_vst1, 401 Intrinsic::arm_neon_vst2, 402 Intrinsic::arm_neon_vst3, 403 Intrinsic::arm_neon_vst4}; 404 405 static const Intrinsic::ID StoreLaneInts[] = { 406 Intrinsic::arm_neon_vst2lane, Intrinsic::arm_neon_vst3lane, 407 Intrinsic::arm_neon_vst4lane 408 }; 409 410 auto fArgs = F->getFunctionType()->params(); 411 Type *Tys[] = {fArgs[0], fArgs[1]}; 412 if (Name.find("lane") == StringRef::npos) 413 NewFn = Intrinsic::getDeclaration(F->getParent(), 414 StoreInts[fArgs.size() - 3], Tys); 415 else 416 NewFn = Intrinsic::getDeclaration(F->getParent(), 417 StoreLaneInts[fArgs.size() - 5], Tys); 418 return true; 419 } 420 if (Name == "aarch64.thread.pointer" || Name == "arm.thread.pointer") { 421 NewFn = Intrinsic::getDeclaration(F->getParent(), Intrinsic::thread_pointer); 422 return true; 423 } 424 break; 425 } 426 427 case 'c': { 428 if (Name.startswith("ctlz.") && F->arg_size() == 1) { 429 rename(F); 430 NewFn = Intrinsic::getDeclaration(F->getParent(), Intrinsic::ctlz, 431 F->arg_begin()->getType()); 432 return true; 433 } 434 if (Name.startswith("cttz.") && F->arg_size() == 1) { 435 rename(F); 436 NewFn = Intrinsic::getDeclaration(F->getParent(), Intrinsic::cttz, 437 F->arg_begin()->getType()); 438 return true; 439 } 440 break; 441 } 442 case 'd': { 443 if (Name == "dbg.value" && F->arg_size() == 4) { 444 rename(F); 445 NewFn = Intrinsic::getDeclaration(F->getParent(), Intrinsic::dbg_value); 446 return true; 447 } 448 break; 449 } 450 case 'i': 451 case 'l': { 452 bool IsLifetimeStart = Name.startswith("lifetime.start"); 453 if (IsLifetimeStart || Name.startswith("invariant.start")) { 454 Intrinsic::ID ID = IsLifetimeStart ? 455 Intrinsic::lifetime_start : Intrinsic::invariant_start; 456 auto Args = F->getFunctionType()->params(); 457 Type* ObjectPtr[1] = {Args[1]}; 458 if (F->getName() != Intrinsic::getName(ID, ObjectPtr)) { 459 rename(F); 460 NewFn = Intrinsic::getDeclaration(F->getParent(), ID, ObjectPtr); 461 return true; 462 } 463 } 464 465 bool IsLifetimeEnd = Name.startswith("lifetime.end"); 466 if (IsLifetimeEnd || Name.startswith("invariant.end")) { 467 Intrinsic::ID ID = IsLifetimeEnd ? 468 Intrinsic::lifetime_end : Intrinsic::invariant_end; 469 470 auto Args = F->getFunctionType()->params(); 471 Type* ObjectPtr[1] = {Args[IsLifetimeEnd ? 1 : 2]}; 472 if (F->getName() != Intrinsic::getName(ID, ObjectPtr)) { 473 rename(F); 474 NewFn = Intrinsic::getDeclaration(F->getParent(), ID, ObjectPtr); 475 return true; 476 } 477 } 478 break; 479 } 480 case 'm': { 481 if (Name.startswith("masked.load.")) { 482 Type *Tys[] = { F->getReturnType(), F->arg_begin()->getType() }; 483 if (F->getName() != Intrinsic::getName(Intrinsic::masked_load, Tys)) { 484 rename(F); 485 NewFn = Intrinsic::getDeclaration(F->getParent(), 486 Intrinsic::masked_load, 487 Tys); 488 return true; 489 } 490 } 491 if (Name.startswith("masked.store.")) { 492 auto Args = F->getFunctionType()->params(); 493 Type *Tys[] = { Args[0], Args[1] }; 494 if (F->getName() != Intrinsic::getName(Intrinsic::masked_store, Tys)) { 495 rename(F); 496 NewFn = Intrinsic::getDeclaration(F->getParent(), 497 Intrinsic::masked_store, 498 Tys); 499 return true; 500 } 501 } 502 // Renaming gather/scatter intrinsics with no address space overloading 503 // to the new overload which includes an address space 504 if (Name.startswith("masked.gather.")) { 505 Type *Tys[] = {F->getReturnType(), F->arg_begin()->getType()}; 506 if (F->getName() != Intrinsic::getName(Intrinsic::masked_gather, Tys)) { 507 rename(F); 508 NewFn = Intrinsic::getDeclaration(F->getParent(), 509 Intrinsic::masked_gather, Tys); 510 return true; 511 } 512 } 513 if (Name.startswith("masked.scatter.")) { 514 auto Args = F->getFunctionType()->params(); 515 Type *Tys[] = {Args[0], Args[1]}; 516 if (F->getName() != Intrinsic::getName(Intrinsic::masked_scatter, Tys)) { 517 rename(F); 518 NewFn = Intrinsic::getDeclaration(F->getParent(), 519 Intrinsic::masked_scatter, Tys); 520 return true; 521 } 522 } 523 break; 524 } 525 case 'n': { 526 if (Name.startswith("nvvm.")) { 527 Name = Name.substr(5); 528 529 // The following nvvm intrinsics correspond exactly to an LLVM intrinsic. 530 Intrinsic::ID IID = StringSwitch<Intrinsic::ID>(Name) 531 .Cases("brev32", "brev64", Intrinsic::bitreverse) 532 .Case("clz.i", Intrinsic::ctlz) 533 .Case("popc.i", Intrinsic::ctpop) 534 .Default(Intrinsic::not_intrinsic); 535 if (IID != Intrinsic::not_intrinsic && F->arg_size() == 1) { 536 NewFn = Intrinsic::getDeclaration(F->getParent(), IID, 537 {F->getReturnType()}); 538 return true; 539 } 540 541 // The following nvvm intrinsics correspond exactly to an LLVM idiom, but 542 // not to an intrinsic alone. We expand them in UpgradeIntrinsicCall. 543 // 544 // TODO: We could add lohi.i2d. 545 bool Expand = StringSwitch<bool>(Name) 546 .Cases("abs.i", "abs.ll", true) 547 .Cases("clz.ll", "popc.ll", "h2f", true) 548 .Cases("max.i", "max.ll", "max.ui", "max.ull", true) 549 .Cases("min.i", "min.ll", "min.ui", "min.ull", true) 550 .Default(false); 551 if (Expand) { 552 NewFn = nullptr; 553 return true; 554 } 555 } 556 break; 557 } 558 case 'o': 559 // We only need to change the name to match the mangling including the 560 // address space. 561 if (Name.startswith("objectsize.")) { 562 Type *Tys[2] = { F->getReturnType(), F->arg_begin()->getType() }; 563 if (F->arg_size() == 2 || 564 F->getName() != Intrinsic::getName(Intrinsic::objectsize, Tys)) { 565 rename(F); 566 NewFn = Intrinsic::getDeclaration(F->getParent(), Intrinsic::objectsize, 567 Tys); 568 return true; 569 } 570 } 571 break; 572 573 case 's': 574 if (Name == "stackprotectorcheck") { 575 NewFn = nullptr; 576 return true; 577 } 578 break; 579 580 case 'x': 581 if (UpgradeX86IntrinsicFunction(F, Name, NewFn)) 582 return true; 583 } 584 // Remangle our intrinsic since we upgrade the mangling 585 auto Result = llvm::Intrinsic::remangleIntrinsicFunction(F); 586 if (Result != None) { 587 NewFn = Result.getValue(); 588 return true; 589 } 590 591 // This may not belong here. This function is effectively being overloaded 592 // to both detect an intrinsic which needs upgrading, and to provide the 593 // upgraded form of the intrinsic. We should perhaps have two separate 594 // functions for this. 595 return false; 596 } 597 598 bool llvm::UpgradeIntrinsicFunction(Function *F, Function *&NewFn) { 599 NewFn = nullptr; 600 bool Upgraded = UpgradeIntrinsicFunction1(F, NewFn); 601 assert(F != NewFn && "Intrinsic function upgraded to the same function"); 602 603 // Upgrade intrinsic attributes. This does not change the function. 604 if (NewFn) 605 F = NewFn; 606 if (Intrinsic::ID id = F->getIntrinsicID()) 607 F->setAttributes(Intrinsic::getAttributes(F->getContext(), id)); 608 return Upgraded; 609 } 610 611 bool llvm::UpgradeGlobalVariable(GlobalVariable *GV) { 612 // Nothing to do yet. 613 return false; 614 } 615 616 // Handles upgrading SSE2/AVX2/AVX512BW PSLLDQ intrinsics by converting them 617 // to byte shuffles. 618 static Value *UpgradeX86PSLLDQIntrinsics(IRBuilder<> &Builder, 619 Value *Op, unsigned Shift) { 620 Type *ResultTy = Op->getType(); 621 unsigned NumElts = ResultTy->getVectorNumElements() * 8; 622 623 // Bitcast from a 64-bit element type to a byte element type. 624 Type *VecTy = VectorType::get(Builder.getInt8Ty(), NumElts); 625 Op = Builder.CreateBitCast(Op, VecTy, "cast"); 626 627 // We'll be shuffling in zeroes. 628 Value *Res = Constant::getNullValue(VecTy); 629 630 // If shift is less than 16, emit a shuffle to move the bytes. Otherwise, 631 // we'll just return the zero vector. 632 if (Shift < 16) { 633 uint32_t Idxs[64]; 634 // 256/512-bit version is split into 2/4 16-byte lanes. 635 for (unsigned l = 0; l != NumElts; l += 16) 636 for (unsigned i = 0; i != 16; ++i) { 637 unsigned Idx = NumElts + i - Shift; 638 if (Idx < NumElts) 639 Idx -= NumElts - 16; // end of lane, switch operand. 640 Idxs[l + i] = Idx + l; 641 } 642 643 Res = Builder.CreateShuffleVector(Res, Op, makeArrayRef(Idxs, NumElts)); 644 } 645 646 // Bitcast back to a 64-bit element type. 647 return Builder.CreateBitCast(Res, ResultTy, "cast"); 648 } 649 650 // Handles upgrading SSE2/AVX2/AVX512BW PSRLDQ intrinsics by converting them 651 // to byte shuffles. 652 static Value *UpgradeX86PSRLDQIntrinsics(IRBuilder<> &Builder, Value *Op, 653 unsigned Shift) { 654 Type *ResultTy = Op->getType(); 655 unsigned NumElts = ResultTy->getVectorNumElements() * 8; 656 657 // Bitcast from a 64-bit element type to a byte element type. 658 Type *VecTy = VectorType::get(Builder.getInt8Ty(), NumElts); 659 Op = Builder.CreateBitCast(Op, VecTy, "cast"); 660 661 // We'll be shuffling in zeroes. 662 Value *Res = Constant::getNullValue(VecTy); 663 664 // If shift is less than 16, emit a shuffle to move the bytes. Otherwise, 665 // we'll just return the zero vector. 666 if (Shift < 16) { 667 uint32_t Idxs[64]; 668 // 256/512-bit version is split into 2/4 16-byte lanes. 669 for (unsigned l = 0; l != NumElts; l += 16) 670 for (unsigned i = 0; i != 16; ++i) { 671 unsigned Idx = i + Shift; 672 if (Idx >= 16) 673 Idx += NumElts - 16; // end of lane, switch operand. 674 Idxs[l + i] = Idx + l; 675 } 676 677 Res = Builder.CreateShuffleVector(Op, Res, makeArrayRef(Idxs, NumElts)); 678 } 679 680 // Bitcast back to a 64-bit element type. 681 return Builder.CreateBitCast(Res, ResultTy, "cast"); 682 } 683 684 static Value *getX86MaskVec(IRBuilder<> &Builder, Value *Mask, 685 unsigned NumElts) { 686 llvm::VectorType *MaskTy = llvm::VectorType::get(Builder.getInt1Ty(), 687 cast<IntegerType>(Mask->getType())->getBitWidth()); 688 Mask = Builder.CreateBitCast(Mask, MaskTy); 689 690 // If we have less than 8 elements, then the starting mask was an i8 and 691 // we need to extract down to the right number of elements. 692 if (NumElts < 8) { 693 uint32_t Indices[4]; 694 for (unsigned i = 0; i != NumElts; ++i) 695 Indices[i] = i; 696 Mask = Builder.CreateShuffleVector(Mask, Mask, 697 makeArrayRef(Indices, NumElts), 698 "extract"); 699 } 700 701 return Mask; 702 } 703 704 static Value *EmitX86Select(IRBuilder<> &Builder, Value *Mask, 705 Value *Op0, Value *Op1) { 706 // If the mask is all ones just emit the align operation. 707 if (const auto *C = dyn_cast<Constant>(Mask)) 708 if (C->isAllOnesValue()) 709 return Op0; 710 711 Mask = getX86MaskVec(Builder, Mask, Op0->getType()->getVectorNumElements()); 712 return Builder.CreateSelect(Mask, Op0, Op1); 713 } 714 715 // Handle autoupgrade for masked PALIGNR and VALIGND/Q intrinsics. 716 // PALIGNR handles large immediates by shifting while VALIGN masks the immediate 717 // so we need to handle both cases. VALIGN also doesn't have 128-bit lanes. 718 static Value *UpgradeX86ALIGNIntrinsics(IRBuilder<> &Builder, Value *Op0, 719 Value *Op1, Value *Shift, 720 Value *Passthru, Value *Mask, 721 bool IsVALIGN) { 722 unsigned ShiftVal = cast<llvm::ConstantInt>(Shift)->getZExtValue(); 723 724 unsigned NumElts = Op0->getType()->getVectorNumElements(); 725 assert((IsVALIGN || NumElts % 16 == 0) && "Illegal NumElts for PALIGNR!"); 726 assert((!IsVALIGN || NumElts <= 16) && "NumElts too large for VALIGN!"); 727 assert(isPowerOf2_32(NumElts) && "NumElts not a power of 2!"); 728 729 // Mask the immediate for VALIGN. 730 if (IsVALIGN) 731 ShiftVal &= (NumElts - 1); 732 733 // If palignr is shifting the pair of vectors more than the size of two 734 // lanes, emit zero. 735 if (ShiftVal >= 32) 736 return llvm::Constant::getNullValue(Op0->getType()); 737 738 // If palignr is shifting the pair of input vectors more than one lane, 739 // but less than two lanes, convert to shifting in zeroes. 740 if (ShiftVal > 16) { 741 ShiftVal -= 16; 742 Op1 = Op0; 743 Op0 = llvm::Constant::getNullValue(Op0->getType()); 744 } 745 746 uint32_t Indices[64]; 747 // 256-bit palignr operates on 128-bit lanes so we need to handle that 748 for (unsigned l = 0; l < NumElts; l += 16) { 749 for (unsigned i = 0; i != 16; ++i) { 750 unsigned Idx = ShiftVal + i; 751 if (!IsVALIGN && Idx >= 16) // Disable wrap for VALIGN. 752 Idx += NumElts - 16; // End of lane, switch operand. 753 Indices[l + i] = Idx + l; 754 } 755 } 756 757 Value *Align = Builder.CreateShuffleVector(Op1, Op0, 758 makeArrayRef(Indices, NumElts), 759 "palignr"); 760 761 return EmitX86Select(Builder, Mask, Align, Passthru); 762 } 763 764 static Value *UpgradeMaskedStore(IRBuilder<> &Builder, 765 Value *Ptr, Value *Data, Value *Mask, 766 bool Aligned) { 767 // Cast the pointer to the right type. 768 Ptr = Builder.CreateBitCast(Ptr, 769 llvm::PointerType::getUnqual(Data->getType())); 770 unsigned Align = 771 Aligned ? cast<VectorType>(Data->getType())->getBitWidth() / 8 : 1; 772 773 // If the mask is all ones just emit a regular store. 774 if (const auto *C = dyn_cast<Constant>(Mask)) 775 if (C->isAllOnesValue()) 776 return Builder.CreateAlignedStore(Data, Ptr, Align); 777 778 // Convert the mask from an integer type to a vector of i1. 779 unsigned NumElts = Data->getType()->getVectorNumElements(); 780 Mask = getX86MaskVec(Builder, Mask, NumElts); 781 return Builder.CreateMaskedStore(Data, Ptr, Align, Mask); 782 } 783 784 static Value *UpgradeMaskedLoad(IRBuilder<> &Builder, 785 Value *Ptr, Value *Passthru, Value *Mask, 786 bool Aligned) { 787 // Cast the pointer to the right type. 788 Ptr = Builder.CreateBitCast(Ptr, 789 llvm::PointerType::getUnqual(Passthru->getType())); 790 unsigned Align = 791 Aligned ? cast<VectorType>(Passthru->getType())->getBitWidth() / 8 : 1; 792 793 // If the mask is all ones just emit a regular store. 794 if (const auto *C = dyn_cast<Constant>(Mask)) 795 if (C->isAllOnesValue()) 796 return Builder.CreateAlignedLoad(Ptr, Align); 797 798 // Convert the mask from an integer type to a vector of i1. 799 unsigned NumElts = Passthru->getType()->getVectorNumElements(); 800 Mask = getX86MaskVec(Builder, Mask, NumElts); 801 return Builder.CreateMaskedLoad(Ptr, Align, Mask, Passthru); 802 } 803 804 static Value *upgradeAbs(IRBuilder<> &Builder, CallInst &CI) { 805 Value *Op0 = CI.getArgOperand(0); 806 llvm::Type *Ty = Op0->getType(); 807 Value *Zero = llvm::Constant::getNullValue(Ty); 808 Value *Cmp = Builder.CreateICmp(ICmpInst::ICMP_SGT, Op0, Zero); 809 Value *Neg = Builder.CreateNeg(Op0); 810 Value *Res = Builder.CreateSelect(Cmp, Op0, Neg); 811 812 if (CI.getNumArgOperands() == 3) 813 Res = EmitX86Select(Builder,CI.getArgOperand(2), Res, CI.getArgOperand(1)); 814 815 return Res; 816 } 817 818 static Value *upgradeIntMinMax(IRBuilder<> &Builder, CallInst &CI, 819 ICmpInst::Predicate Pred) { 820 Value *Op0 = CI.getArgOperand(0); 821 Value *Op1 = CI.getArgOperand(1); 822 Value *Cmp = Builder.CreateICmp(Pred, Op0, Op1); 823 Value *Res = Builder.CreateSelect(Cmp, Op0, Op1); 824 825 if (CI.getNumArgOperands() == 4) 826 Res = EmitX86Select(Builder, CI.getArgOperand(3), Res, CI.getArgOperand(2)); 827 828 return Res; 829 } 830 831 // Applying mask on vector of i1's and make sure result is at least 8 bits wide. 832 static Value *ApplyX86MaskOn1BitsVec(IRBuilder<> &Builder,Value *Vec, Value *Mask, 833 unsigned NumElts) { 834 const auto *C = dyn_cast<Constant>(Mask); 835 if (!C || !C->isAllOnesValue()) 836 Vec = Builder.CreateAnd(Vec, getX86MaskVec(Builder, Mask, NumElts)); 837 838 if (NumElts < 8) { 839 uint32_t Indices[8]; 840 for (unsigned i = 0; i != NumElts; ++i) 841 Indices[i] = i; 842 for (unsigned i = NumElts; i != 8; ++i) 843 Indices[i] = NumElts + i % NumElts; 844 Vec = Builder.CreateShuffleVector(Vec, 845 Constant::getNullValue(Vec->getType()), 846 Indices); 847 } 848 return Builder.CreateBitCast(Vec, Builder.getIntNTy(std::max(NumElts, 8U))); 849 } 850 851 static Value *upgradeMaskedCompare(IRBuilder<> &Builder, CallInst &CI, 852 unsigned CC, bool Signed) { 853 Value *Op0 = CI.getArgOperand(0); 854 unsigned NumElts = Op0->getType()->getVectorNumElements(); 855 856 Value *Cmp; 857 if (CC == 3) { 858 Cmp = Constant::getNullValue(llvm::VectorType::get(Builder.getInt1Ty(), NumElts)); 859 } else if (CC == 7) { 860 Cmp = Constant::getAllOnesValue(llvm::VectorType::get(Builder.getInt1Ty(), NumElts)); 861 } else { 862 ICmpInst::Predicate Pred; 863 switch (CC) { 864 default: llvm_unreachable("Unknown condition code"); 865 case 0: Pred = ICmpInst::ICMP_EQ; break; 866 case 1: Pred = Signed ? ICmpInst::ICMP_SLT : ICmpInst::ICMP_ULT; break; 867 case 2: Pred = Signed ? ICmpInst::ICMP_SLE : ICmpInst::ICMP_ULE; break; 868 case 4: Pred = ICmpInst::ICMP_NE; break; 869 case 5: Pred = Signed ? ICmpInst::ICMP_SGE : ICmpInst::ICMP_UGE; break; 870 case 6: Pred = Signed ? ICmpInst::ICMP_SGT : ICmpInst::ICMP_UGT; break; 871 } 872 Cmp = Builder.CreateICmp(Pred, Op0, CI.getArgOperand(1)); 873 } 874 875 Value *Mask = CI.getArgOperand(CI.getNumArgOperands() - 1); 876 877 return ApplyX86MaskOn1BitsVec(Builder, Cmp, Mask, NumElts); 878 } 879 880 // Replace a masked intrinsic with an older unmasked intrinsic. 881 static Value *UpgradeX86MaskedShift(IRBuilder<> &Builder, CallInst &CI, 882 Intrinsic::ID IID) { 883 Function *F = CI.getCalledFunction(); 884 Function *Intrin = Intrinsic::getDeclaration(F->getParent(), IID); 885 Value *Rep = Builder.CreateCall(Intrin, 886 { CI.getArgOperand(0), CI.getArgOperand(1) }); 887 return EmitX86Select(Builder, CI.getArgOperand(3), Rep, CI.getArgOperand(2)); 888 } 889 890 static Value* upgradeMaskedMove(IRBuilder<> &Builder, CallInst &CI) { 891 Value* A = CI.getArgOperand(0); 892 Value* B = CI.getArgOperand(1); 893 Value* Src = CI.getArgOperand(2); 894 Value* Mask = CI.getArgOperand(3); 895 896 Value* AndNode = Builder.CreateAnd(Mask, APInt(8, 1)); 897 Value* Cmp = Builder.CreateIsNotNull(AndNode); 898 Value* Extract1 = Builder.CreateExtractElement(B, (uint64_t)0); 899 Value* Extract2 = Builder.CreateExtractElement(Src, (uint64_t)0); 900 Value* Select = Builder.CreateSelect(Cmp, Extract1, Extract2); 901 return Builder.CreateInsertElement(A, Select, (uint64_t)0); 902 } 903 904 905 static Value* UpgradeMaskToInt(IRBuilder<> &Builder, CallInst &CI) { 906 Value* Op = CI.getArgOperand(0); 907 Type* ReturnOp = CI.getType(); 908 unsigned NumElts = CI.getType()->getVectorNumElements(); 909 Value *Mask = getX86MaskVec(Builder, Op, NumElts); 910 return Builder.CreateSExt(Mask, ReturnOp, "vpmovm2"); 911 } 912 913 /// Upgrade a call to an old intrinsic. All argument and return casting must be 914 /// provided to seamlessly integrate with existing context. 915 void llvm::UpgradeIntrinsicCall(CallInst *CI, Function *NewFn) { 916 Function *F = CI->getCalledFunction(); 917 LLVMContext &C = CI->getContext(); 918 IRBuilder<> Builder(C); 919 Builder.SetInsertPoint(CI->getParent(), CI->getIterator()); 920 921 assert(F && "Intrinsic call is not direct?"); 922 923 if (!NewFn) { 924 // Get the Function's name. 925 StringRef Name = F->getName(); 926 927 assert(Name.startswith("llvm.") && "Intrinsic doesn't start with 'llvm.'"); 928 Name = Name.substr(5); 929 930 bool IsX86 = Name.startswith("x86."); 931 if (IsX86) 932 Name = Name.substr(4); 933 bool IsNVVM = Name.startswith("nvvm."); 934 if (IsNVVM) 935 Name = Name.substr(5); 936 937 if (IsX86 && Name.startswith("sse4a.movnt.")) { 938 Module *M = F->getParent(); 939 SmallVector<Metadata *, 1> Elts; 940 Elts.push_back( 941 ConstantAsMetadata::get(ConstantInt::get(Type::getInt32Ty(C), 1))); 942 MDNode *Node = MDNode::get(C, Elts); 943 944 Value *Arg0 = CI->getArgOperand(0); 945 Value *Arg1 = CI->getArgOperand(1); 946 947 // Nontemporal (unaligned) store of the 0'th element of the float/double 948 // vector. 949 Type *SrcEltTy = cast<VectorType>(Arg1->getType())->getElementType(); 950 PointerType *EltPtrTy = PointerType::getUnqual(SrcEltTy); 951 Value *Addr = Builder.CreateBitCast(Arg0, EltPtrTy, "cast"); 952 Value *Extract = 953 Builder.CreateExtractElement(Arg1, (uint64_t)0, "extractelement"); 954 955 StoreInst *SI = Builder.CreateAlignedStore(Extract, Addr, 1); 956 SI->setMetadata(M->getMDKindID("nontemporal"), Node); 957 958 // Remove intrinsic. 959 CI->eraseFromParent(); 960 return; 961 } 962 963 if (IsX86 && (Name.startswith("avx.movnt.") || 964 Name.startswith("avx512.storent."))) { 965 Module *M = F->getParent(); 966 SmallVector<Metadata *, 1> Elts; 967 Elts.push_back( 968 ConstantAsMetadata::get(ConstantInt::get(Type::getInt32Ty(C), 1))); 969 MDNode *Node = MDNode::get(C, Elts); 970 971 Value *Arg0 = CI->getArgOperand(0); 972 Value *Arg1 = CI->getArgOperand(1); 973 974 // Convert the type of the pointer to a pointer to the stored type. 975 Value *BC = Builder.CreateBitCast(Arg0, 976 PointerType::getUnqual(Arg1->getType()), 977 "cast"); 978 VectorType *VTy = cast<VectorType>(Arg1->getType()); 979 StoreInst *SI = Builder.CreateAlignedStore(Arg1, BC, 980 VTy->getBitWidth() / 8); 981 SI->setMetadata(M->getMDKindID("nontemporal"), Node); 982 983 // Remove intrinsic. 984 CI->eraseFromParent(); 985 return; 986 } 987 988 if (IsX86 && Name == "sse2.storel.dq") { 989 Value *Arg0 = CI->getArgOperand(0); 990 Value *Arg1 = CI->getArgOperand(1); 991 992 Type *NewVecTy = VectorType::get(Type::getInt64Ty(C), 2); 993 Value *BC0 = Builder.CreateBitCast(Arg1, NewVecTy, "cast"); 994 Value *Elt = Builder.CreateExtractElement(BC0, (uint64_t)0); 995 Value *BC = Builder.CreateBitCast(Arg0, 996 PointerType::getUnqual(Elt->getType()), 997 "cast"); 998 Builder.CreateAlignedStore(Elt, BC, 1); 999 1000 // Remove intrinsic. 1001 CI->eraseFromParent(); 1002 return; 1003 } 1004 1005 if (IsX86 && (Name.startswith("sse.storeu.") || 1006 Name.startswith("sse2.storeu.") || 1007 Name.startswith("avx.storeu."))) { 1008 Value *Arg0 = CI->getArgOperand(0); 1009 Value *Arg1 = CI->getArgOperand(1); 1010 1011 Arg0 = Builder.CreateBitCast(Arg0, 1012 PointerType::getUnqual(Arg1->getType()), 1013 "cast"); 1014 Builder.CreateAlignedStore(Arg1, Arg0, 1); 1015 1016 // Remove intrinsic. 1017 CI->eraseFromParent(); 1018 return; 1019 } 1020 1021 if (IsX86 && (Name.startswith("avx512.mask.store"))) { 1022 // "avx512.mask.storeu." or "avx512.mask.store." 1023 bool Aligned = Name[17] != 'u'; // "avx512.mask.storeu". 1024 UpgradeMaskedStore(Builder, CI->getArgOperand(0), CI->getArgOperand(1), 1025 CI->getArgOperand(2), Aligned); 1026 1027 // Remove intrinsic. 1028 CI->eraseFromParent(); 1029 return; 1030 } 1031 1032 Value *Rep; 1033 // Upgrade packed integer vector compare intrinsics to compare instructions. 1034 if (IsX86 && (Name.startswith("sse2.pcmp") || 1035 Name.startswith("avx2.pcmp"))) { 1036 // "sse2.pcpmpeq." "sse2.pcmpgt." "avx2.pcmpeq." or "avx2.pcmpgt." 1037 bool CmpEq = Name[9] == 'e'; 1038 Rep = Builder.CreateICmp(CmpEq ? ICmpInst::ICMP_EQ : ICmpInst::ICMP_SGT, 1039 CI->getArgOperand(0), CI->getArgOperand(1)); 1040 Rep = Builder.CreateSExt(Rep, CI->getType(), ""); 1041 } else if (IsX86 && (Name.startswith("avx512.broadcastm"))) { 1042 Type *ExtTy = Type::getInt32Ty(C); 1043 if (CI->getOperand(0)->getType()->isIntegerTy(8)) 1044 ExtTy = Type::getInt64Ty(C); 1045 unsigned NumElts = CI->getType()->getPrimitiveSizeInBits() / 1046 ExtTy->getPrimitiveSizeInBits(); 1047 Rep = Builder.CreateZExt(CI->getArgOperand(0), ExtTy); 1048 Rep = Builder.CreateVectorSplat(NumElts, Rep); 1049 } else if (IsX86 && (Name.startswith("avx512.ptestm") || 1050 Name.startswith("avx512.ptestnm"))) { 1051 Value *Op0 = CI->getArgOperand(0); 1052 Value *Op1 = CI->getArgOperand(1); 1053 Value *Mask = CI->getArgOperand(2); 1054 Rep = Builder.CreateAnd(Op0, Op1); 1055 llvm::Type *Ty = Op0->getType(); 1056 Value *Zero = llvm::Constant::getNullValue(Ty); 1057 ICmpInst::Predicate Pred = 1058 Name.startswith("avx512.ptestm") ? ICmpInst::ICMP_NE : ICmpInst::ICMP_EQ; 1059 Rep = Builder.CreateICmp(Pred, Rep, Zero); 1060 unsigned NumElts = Op0->getType()->getVectorNumElements(); 1061 Rep = ApplyX86MaskOn1BitsVec(Builder, Rep, Mask, NumElts); 1062 } else if (IsX86 && (Name.startswith("avx512.mask.pbroadcast"))){ 1063 unsigned NumElts = 1064 CI->getArgOperand(1)->getType()->getVectorNumElements(); 1065 Rep = Builder.CreateVectorSplat(NumElts, CI->getArgOperand(0)); 1066 Rep = EmitX86Select(Builder, CI->getArgOperand(2), Rep, 1067 CI->getArgOperand(1)); 1068 } else if (IsX86 && (Name == "sse.add.ss" || Name == "sse2.add.sd")) { 1069 Type *I32Ty = Type::getInt32Ty(C); 1070 Value *Elt0 = Builder.CreateExtractElement(CI->getArgOperand(0), 1071 ConstantInt::get(I32Ty, 0)); 1072 Value *Elt1 = Builder.CreateExtractElement(CI->getArgOperand(1), 1073 ConstantInt::get(I32Ty, 0)); 1074 Rep = Builder.CreateInsertElement(CI->getArgOperand(0), 1075 Builder.CreateFAdd(Elt0, Elt1), 1076 ConstantInt::get(I32Ty, 0)); 1077 } else if (IsX86 && (Name == "sse.sub.ss" || Name == "sse2.sub.sd")) { 1078 Type *I32Ty = Type::getInt32Ty(C); 1079 Value *Elt0 = Builder.CreateExtractElement(CI->getArgOperand(0), 1080 ConstantInt::get(I32Ty, 0)); 1081 Value *Elt1 = Builder.CreateExtractElement(CI->getArgOperand(1), 1082 ConstantInt::get(I32Ty, 0)); 1083 Rep = Builder.CreateInsertElement(CI->getArgOperand(0), 1084 Builder.CreateFSub(Elt0, Elt1), 1085 ConstantInt::get(I32Ty, 0)); 1086 } else if (IsX86 && (Name == "sse.mul.ss" || Name == "sse2.mul.sd")) { 1087 Type *I32Ty = Type::getInt32Ty(C); 1088 Value *Elt0 = Builder.CreateExtractElement(CI->getArgOperand(0), 1089 ConstantInt::get(I32Ty, 0)); 1090 Value *Elt1 = Builder.CreateExtractElement(CI->getArgOperand(1), 1091 ConstantInt::get(I32Ty, 0)); 1092 Rep = Builder.CreateInsertElement(CI->getArgOperand(0), 1093 Builder.CreateFMul(Elt0, Elt1), 1094 ConstantInt::get(I32Ty, 0)); 1095 } else if (IsX86 && (Name == "sse.div.ss" || Name == "sse2.div.sd")) { 1096 Type *I32Ty = Type::getInt32Ty(C); 1097 Value *Elt0 = Builder.CreateExtractElement(CI->getArgOperand(0), 1098 ConstantInt::get(I32Ty, 0)); 1099 Value *Elt1 = Builder.CreateExtractElement(CI->getArgOperand(1), 1100 ConstantInt::get(I32Ty, 0)); 1101 Rep = Builder.CreateInsertElement(CI->getArgOperand(0), 1102 Builder.CreateFDiv(Elt0, Elt1), 1103 ConstantInt::get(I32Ty, 0)); 1104 } else if (IsX86 && Name.startswith("avx512.mask.pcmp")) { 1105 // "avx512.mask.pcmpeq." or "avx512.mask.pcmpgt." 1106 bool CmpEq = Name[16] == 'e'; 1107 Rep = upgradeMaskedCompare(Builder, *CI, CmpEq ? 0 : 6, true); 1108 } else if (IsX86 && Name.startswith("avx512.mask.cmp")) { 1109 unsigned Imm = cast<ConstantInt>(CI->getArgOperand(2))->getZExtValue(); 1110 Rep = upgradeMaskedCompare(Builder, *CI, Imm, true); 1111 } else if (IsX86 && Name.startswith("avx512.mask.ucmp")) { 1112 unsigned Imm = cast<ConstantInt>(CI->getArgOperand(2))->getZExtValue(); 1113 Rep = upgradeMaskedCompare(Builder, *CI, Imm, false); 1114 } else if(IsX86 && (Name == "ssse3.pabs.b.128" || 1115 Name == "ssse3.pabs.w.128" || 1116 Name == "ssse3.pabs.d.128" || 1117 Name.startswith("avx2.pabs") || 1118 Name.startswith("avx512.mask.pabs"))) { 1119 Rep = upgradeAbs(Builder, *CI); 1120 } else if (IsX86 && (Name == "sse41.pmaxsb" || 1121 Name == "sse2.pmaxs.w" || 1122 Name == "sse41.pmaxsd" || 1123 Name.startswith("avx2.pmaxs") || 1124 Name.startswith("avx512.mask.pmaxs"))) { 1125 Rep = upgradeIntMinMax(Builder, *CI, ICmpInst::ICMP_SGT); 1126 } else if (IsX86 && (Name == "sse2.pmaxu.b" || 1127 Name == "sse41.pmaxuw" || 1128 Name == "sse41.pmaxud" || 1129 Name.startswith("avx2.pmaxu") || 1130 Name.startswith("avx512.mask.pmaxu"))) { 1131 Rep = upgradeIntMinMax(Builder, *CI, ICmpInst::ICMP_UGT); 1132 } else if (IsX86 && (Name == "sse41.pminsb" || 1133 Name == "sse2.pmins.w" || 1134 Name == "sse41.pminsd" || 1135 Name.startswith("avx2.pmins") || 1136 Name.startswith("avx512.mask.pmins"))) { 1137 Rep = upgradeIntMinMax(Builder, *CI, ICmpInst::ICMP_SLT); 1138 } else if (IsX86 && (Name == "sse2.pminu.b" || 1139 Name == "sse41.pminuw" || 1140 Name == "sse41.pminud" || 1141 Name.startswith("avx2.pminu") || 1142 Name.startswith("avx512.mask.pminu"))) { 1143 Rep = upgradeIntMinMax(Builder, *CI, ICmpInst::ICMP_ULT); 1144 } else if (IsX86 && (Name == "sse2.cvtdq2pd" || 1145 Name == "sse2.cvtps2pd" || 1146 Name == "avx.cvtdq2.pd.256" || 1147 Name == "avx.cvt.ps2.pd.256" || 1148 Name.startswith("avx512.mask.cvtdq2pd.") || 1149 Name.startswith("avx512.mask.cvtudq2pd."))) { 1150 // Lossless i32/float to double conversion. 1151 // Extract the bottom elements if necessary and convert to double vector. 1152 Value *Src = CI->getArgOperand(0); 1153 VectorType *SrcTy = cast<VectorType>(Src->getType()); 1154 VectorType *DstTy = cast<VectorType>(CI->getType()); 1155 Rep = CI->getArgOperand(0); 1156 1157 unsigned NumDstElts = DstTy->getNumElements(); 1158 if (NumDstElts < SrcTy->getNumElements()) { 1159 assert(NumDstElts == 2 && "Unexpected vector size"); 1160 uint32_t ShuffleMask[2] = { 0, 1 }; 1161 Rep = Builder.CreateShuffleVector(Rep, UndefValue::get(SrcTy), 1162 ShuffleMask); 1163 } 1164 1165 bool SInt2Double = (StringRef::npos != Name.find("cvtdq2")); 1166 bool UInt2Double = (StringRef::npos != Name.find("cvtudq2")); 1167 if (SInt2Double) 1168 Rep = Builder.CreateSIToFP(Rep, DstTy, "cvtdq2pd"); 1169 else if (UInt2Double) 1170 Rep = Builder.CreateUIToFP(Rep, DstTy, "cvtudq2pd"); 1171 else 1172 Rep = Builder.CreateFPExt(Rep, DstTy, "cvtps2pd"); 1173 1174 if (CI->getNumArgOperands() == 3) 1175 Rep = EmitX86Select(Builder, CI->getArgOperand(2), Rep, 1176 CI->getArgOperand(1)); 1177 } else if (IsX86 && (Name.startswith("avx512.mask.loadu."))) { 1178 Rep = UpgradeMaskedLoad(Builder, CI->getArgOperand(0), 1179 CI->getArgOperand(1), CI->getArgOperand(2), 1180 /*Aligned*/false); 1181 } else if (IsX86 && (Name.startswith("avx512.mask.load."))) { 1182 Rep = UpgradeMaskedLoad(Builder, CI->getArgOperand(0), 1183 CI->getArgOperand(1),CI->getArgOperand(2), 1184 /*Aligned*/true); 1185 } else if (IsX86 && Name.startswith("xop.vpcom")) { 1186 Intrinsic::ID intID; 1187 if (Name.endswith("ub")) 1188 intID = Intrinsic::x86_xop_vpcomub; 1189 else if (Name.endswith("uw")) 1190 intID = Intrinsic::x86_xop_vpcomuw; 1191 else if (Name.endswith("ud")) 1192 intID = Intrinsic::x86_xop_vpcomud; 1193 else if (Name.endswith("uq")) 1194 intID = Intrinsic::x86_xop_vpcomuq; 1195 else if (Name.endswith("b")) 1196 intID = Intrinsic::x86_xop_vpcomb; 1197 else if (Name.endswith("w")) 1198 intID = Intrinsic::x86_xop_vpcomw; 1199 else if (Name.endswith("d")) 1200 intID = Intrinsic::x86_xop_vpcomd; 1201 else if (Name.endswith("q")) 1202 intID = Intrinsic::x86_xop_vpcomq; 1203 else 1204 llvm_unreachable("Unknown suffix"); 1205 1206 Name = Name.substr(9); // strip off "xop.vpcom" 1207 unsigned Imm; 1208 if (Name.startswith("lt")) 1209 Imm = 0; 1210 else if (Name.startswith("le")) 1211 Imm = 1; 1212 else if (Name.startswith("gt")) 1213 Imm = 2; 1214 else if (Name.startswith("ge")) 1215 Imm = 3; 1216 else if (Name.startswith("eq")) 1217 Imm = 4; 1218 else if (Name.startswith("ne")) 1219 Imm = 5; 1220 else if (Name.startswith("false")) 1221 Imm = 6; 1222 else if (Name.startswith("true")) 1223 Imm = 7; 1224 else 1225 llvm_unreachable("Unknown condition"); 1226 1227 Function *VPCOM = Intrinsic::getDeclaration(F->getParent(), intID); 1228 Rep = 1229 Builder.CreateCall(VPCOM, {CI->getArgOperand(0), CI->getArgOperand(1), 1230 Builder.getInt8(Imm)}); 1231 } else if (IsX86 && Name.startswith("xop.vpcmov")) { 1232 Value *Sel = CI->getArgOperand(2); 1233 Value *NotSel = Builder.CreateNot(Sel); 1234 Value *Sel0 = Builder.CreateAnd(CI->getArgOperand(0), Sel); 1235 Value *Sel1 = Builder.CreateAnd(CI->getArgOperand(1), NotSel); 1236 Rep = Builder.CreateOr(Sel0, Sel1); 1237 } else if (IsX86 && Name == "sse42.crc32.64.8") { 1238 Function *CRC32 = Intrinsic::getDeclaration(F->getParent(), 1239 Intrinsic::x86_sse42_crc32_32_8); 1240 Value *Trunc0 = Builder.CreateTrunc(CI->getArgOperand(0), Type::getInt32Ty(C)); 1241 Rep = Builder.CreateCall(CRC32, {Trunc0, CI->getArgOperand(1)}); 1242 Rep = Builder.CreateZExt(Rep, CI->getType(), ""); 1243 } else if (IsX86 && Name.startswith("avx.vbroadcast.s")) { 1244 // Replace broadcasts with a series of insertelements. 1245 Type *VecTy = CI->getType(); 1246 Type *EltTy = VecTy->getVectorElementType(); 1247 unsigned EltNum = VecTy->getVectorNumElements(); 1248 Value *Cast = Builder.CreateBitCast(CI->getArgOperand(0), 1249 EltTy->getPointerTo()); 1250 Value *Load = Builder.CreateLoad(EltTy, Cast); 1251 Type *I32Ty = Type::getInt32Ty(C); 1252 Rep = UndefValue::get(VecTy); 1253 for (unsigned I = 0; I < EltNum; ++I) 1254 Rep = Builder.CreateInsertElement(Rep, Load, 1255 ConstantInt::get(I32Ty, I)); 1256 } else if (IsX86 && (Name.startswith("sse41.pmovsx") || 1257 Name.startswith("sse41.pmovzx") || 1258 Name.startswith("avx2.pmovsx") || 1259 Name.startswith("avx2.pmovzx") || 1260 Name.startswith("avx512.mask.pmovsx") || 1261 Name.startswith("avx512.mask.pmovzx"))) { 1262 VectorType *SrcTy = cast<VectorType>(CI->getArgOperand(0)->getType()); 1263 VectorType *DstTy = cast<VectorType>(CI->getType()); 1264 unsigned NumDstElts = DstTy->getNumElements(); 1265 1266 // Extract a subvector of the first NumDstElts lanes and sign/zero extend. 1267 SmallVector<uint32_t, 8> ShuffleMask(NumDstElts); 1268 for (unsigned i = 0; i != NumDstElts; ++i) 1269 ShuffleMask[i] = i; 1270 1271 Value *SV = Builder.CreateShuffleVector( 1272 CI->getArgOperand(0), UndefValue::get(SrcTy), ShuffleMask); 1273 1274 bool DoSext = (StringRef::npos != Name.find("pmovsx")); 1275 Rep = DoSext ? Builder.CreateSExt(SV, DstTy) 1276 : Builder.CreateZExt(SV, DstTy); 1277 // If there are 3 arguments, it's a masked intrinsic so we need a select. 1278 if (CI->getNumArgOperands() == 3) 1279 Rep = EmitX86Select(Builder, CI->getArgOperand(2), Rep, 1280 CI->getArgOperand(1)); 1281 } else if (IsX86 && (Name.startswith("avx.vbroadcastf128") || 1282 Name == "avx2.vbroadcasti128")) { 1283 // Replace vbroadcastf128/vbroadcasti128 with a vector load+shuffle. 1284 Type *EltTy = CI->getType()->getVectorElementType(); 1285 unsigned NumSrcElts = 128 / EltTy->getPrimitiveSizeInBits(); 1286 Type *VT = VectorType::get(EltTy, NumSrcElts); 1287 Value *Op = Builder.CreatePointerCast(CI->getArgOperand(0), 1288 PointerType::getUnqual(VT)); 1289 Value *Load = Builder.CreateAlignedLoad(Op, 1); 1290 if (NumSrcElts == 2) 1291 Rep = Builder.CreateShuffleVector(Load, UndefValue::get(Load->getType()), 1292 { 0, 1, 0, 1 }); 1293 else 1294 Rep = Builder.CreateShuffleVector(Load, UndefValue::get(Load->getType()), 1295 { 0, 1, 2, 3, 0, 1, 2, 3 }); 1296 } else if (IsX86 && (Name.startswith("avx512.mask.shuf.i") || 1297 Name.startswith("avx512.mask.shuf.f"))) { 1298 unsigned Imm = cast<ConstantInt>(CI->getArgOperand(2))->getZExtValue(); 1299 Type *VT = CI->getType(); 1300 unsigned NumLanes = VT->getPrimitiveSizeInBits() / 128; 1301 unsigned NumElementsInLane = 128 / VT->getScalarSizeInBits(); 1302 unsigned ControlBitsMask = NumLanes - 1; 1303 unsigned NumControlBits = NumLanes / 2; 1304 SmallVector<uint32_t, 8> ShuffleMask(0); 1305 1306 for (unsigned l = 0; l != NumLanes; ++l) { 1307 unsigned LaneMask = (Imm >> (l * NumControlBits)) & ControlBitsMask; 1308 // We actually need the other source. 1309 if (l >= NumLanes / 2) 1310 LaneMask += NumLanes; 1311 for (unsigned i = 0; i != NumElementsInLane; ++i) 1312 ShuffleMask.push_back(LaneMask * NumElementsInLane + i); 1313 } 1314 Rep = Builder.CreateShuffleVector(CI->getArgOperand(0), 1315 CI->getArgOperand(1), ShuffleMask); 1316 Rep = EmitX86Select(Builder, CI->getArgOperand(4), Rep, 1317 CI->getArgOperand(3)); 1318 }else if (IsX86 && (Name.startswith("avx512.mask.broadcastf") || 1319 Name.startswith("avx512.mask.broadcasti"))) { 1320 unsigned NumSrcElts = 1321 CI->getArgOperand(0)->getType()->getVectorNumElements(); 1322 unsigned NumDstElts = CI->getType()->getVectorNumElements(); 1323 1324 SmallVector<uint32_t, 8> ShuffleMask(NumDstElts); 1325 for (unsigned i = 0; i != NumDstElts; ++i) 1326 ShuffleMask[i] = i % NumSrcElts; 1327 1328 Rep = Builder.CreateShuffleVector(CI->getArgOperand(0), 1329 CI->getArgOperand(0), 1330 ShuffleMask); 1331 Rep = EmitX86Select(Builder, CI->getArgOperand(2), Rep, 1332 CI->getArgOperand(1)); 1333 } else if (IsX86 && (Name.startswith("avx2.pbroadcast") || 1334 Name.startswith("avx2.vbroadcast") || 1335 Name.startswith("avx512.pbroadcast") || 1336 Name.startswith("avx512.mask.broadcast.s"))) { 1337 // Replace vp?broadcasts with a vector shuffle. 1338 Value *Op = CI->getArgOperand(0); 1339 unsigned NumElts = CI->getType()->getVectorNumElements(); 1340 Type *MaskTy = VectorType::get(Type::getInt32Ty(C), NumElts); 1341 Rep = Builder.CreateShuffleVector(Op, UndefValue::get(Op->getType()), 1342 Constant::getNullValue(MaskTy)); 1343 1344 if (CI->getNumArgOperands() == 3) 1345 Rep = EmitX86Select(Builder, CI->getArgOperand(2), Rep, 1346 CI->getArgOperand(1)); 1347 } else if (IsX86 && Name.startswith("avx512.mask.palignr.")) { 1348 Rep = UpgradeX86ALIGNIntrinsics(Builder, CI->getArgOperand(0), 1349 CI->getArgOperand(1), 1350 CI->getArgOperand(2), 1351 CI->getArgOperand(3), 1352 CI->getArgOperand(4), 1353 false); 1354 } else if (IsX86 && Name.startswith("avx512.mask.valign.")) { 1355 Rep = UpgradeX86ALIGNIntrinsics(Builder, CI->getArgOperand(0), 1356 CI->getArgOperand(1), 1357 CI->getArgOperand(2), 1358 CI->getArgOperand(3), 1359 CI->getArgOperand(4), 1360 true); 1361 } else if (IsX86 && (Name == "sse2.psll.dq" || 1362 Name == "avx2.psll.dq")) { 1363 // 128/256-bit shift left specified in bits. 1364 unsigned Shift = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue(); 1365 Rep = UpgradeX86PSLLDQIntrinsics(Builder, CI->getArgOperand(0), 1366 Shift / 8); // Shift is in bits. 1367 } else if (IsX86 && (Name == "sse2.psrl.dq" || 1368 Name == "avx2.psrl.dq")) { 1369 // 128/256-bit shift right specified in bits. 1370 unsigned Shift = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue(); 1371 Rep = UpgradeX86PSRLDQIntrinsics(Builder, CI->getArgOperand(0), 1372 Shift / 8); // Shift is in bits. 1373 } else if (IsX86 && (Name == "sse2.psll.dq.bs" || 1374 Name == "avx2.psll.dq.bs" || 1375 Name == "avx512.psll.dq.512")) { 1376 // 128/256/512-bit shift left specified in bytes. 1377 unsigned Shift = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue(); 1378 Rep = UpgradeX86PSLLDQIntrinsics(Builder, CI->getArgOperand(0), Shift); 1379 } else if (IsX86 && (Name == "sse2.psrl.dq.bs" || 1380 Name == "avx2.psrl.dq.bs" || 1381 Name == "avx512.psrl.dq.512")) { 1382 // 128/256/512-bit shift right specified in bytes. 1383 unsigned Shift = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue(); 1384 Rep = UpgradeX86PSRLDQIntrinsics(Builder, CI->getArgOperand(0), Shift); 1385 } else if (IsX86 && (Name == "sse41.pblendw" || 1386 Name.startswith("sse41.blendp") || 1387 Name.startswith("avx.blend.p") || 1388 Name == "avx2.pblendw" || 1389 Name.startswith("avx2.pblendd."))) { 1390 Value *Op0 = CI->getArgOperand(0); 1391 Value *Op1 = CI->getArgOperand(1); 1392 unsigned Imm = cast <ConstantInt>(CI->getArgOperand(2))->getZExtValue(); 1393 VectorType *VecTy = cast<VectorType>(CI->getType()); 1394 unsigned NumElts = VecTy->getNumElements(); 1395 1396 SmallVector<uint32_t, 16> Idxs(NumElts); 1397 for (unsigned i = 0; i != NumElts; ++i) 1398 Idxs[i] = ((Imm >> (i%8)) & 1) ? i + NumElts : i; 1399 1400 Rep = Builder.CreateShuffleVector(Op0, Op1, Idxs); 1401 } else if (IsX86 && (Name.startswith("avx.vinsertf128.") || 1402 Name == "avx2.vinserti128" || 1403 Name.startswith("avx512.mask.insert"))) { 1404 Value *Op0 = CI->getArgOperand(0); 1405 Value *Op1 = CI->getArgOperand(1); 1406 unsigned Imm = cast<ConstantInt>(CI->getArgOperand(2))->getZExtValue(); 1407 unsigned DstNumElts = CI->getType()->getVectorNumElements(); 1408 unsigned SrcNumElts = Op1->getType()->getVectorNumElements(); 1409 unsigned Scale = DstNumElts / SrcNumElts; 1410 1411 // Mask off the high bits of the immediate value; hardware ignores those. 1412 Imm = Imm % Scale; 1413 1414 // Extend the second operand into a vector the size of the destination. 1415 Value *UndefV = UndefValue::get(Op1->getType()); 1416 SmallVector<uint32_t, 8> Idxs(DstNumElts); 1417 for (unsigned i = 0; i != SrcNumElts; ++i) 1418 Idxs[i] = i; 1419 for (unsigned i = SrcNumElts; i != DstNumElts; ++i) 1420 Idxs[i] = SrcNumElts; 1421 Rep = Builder.CreateShuffleVector(Op1, UndefV, Idxs); 1422 1423 // Insert the second operand into the first operand. 1424 1425 // Note that there is no guarantee that instruction lowering will actually 1426 // produce a vinsertf128 instruction for the created shuffles. In 1427 // particular, the 0 immediate case involves no lane changes, so it can 1428 // be handled as a blend. 1429 1430 // Example of shuffle mask for 32-bit elements: 1431 // Imm = 1 <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11> 1432 // Imm = 0 <i32 8, i32 9, i32 10, i32 11, i32 4, i32 5, i32 6, i32 7 > 1433 1434 // First fill with identify mask. 1435 for (unsigned i = 0; i != DstNumElts; ++i) 1436 Idxs[i] = i; 1437 // Then replace the elements where we need to insert. 1438 for (unsigned i = 0; i != SrcNumElts; ++i) 1439 Idxs[i + Imm * SrcNumElts] = i + DstNumElts; 1440 Rep = Builder.CreateShuffleVector(Op0, Rep, Idxs); 1441 1442 // If the intrinsic has a mask operand, handle that. 1443 if (CI->getNumArgOperands() == 5) 1444 Rep = EmitX86Select(Builder, CI->getArgOperand(4), Rep, 1445 CI->getArgOperand(3)); 1446 } else if (IsX86 && (Name.startswith("avx.vextractf128.") || 1447 Name == "avx2.vextracti128" || 1448 Name.startswith("avx512.mask.vextract"))) { 1449 Value *Op0 = CI->getArgOperand(0); 1450 unsigned Imm = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue(); 1451 unsigned DstNumElts = CI->getType()->getVectorNumElements(); 1452 unsigned SrcNumElts = Op0->getType()->getVectorNumElements(); 1453 unsigned Scale = SrcNumElts / DstNumElts; 1454 1455 // Mask off the high bits of the immediate value; hardware ignores those. 1456 Imm = Imm % Scale; 1457 1458 // Get indexes for the subvector of the input vector. 1459 SmallVector<uint32_t, 8> Idxs(DstNumElts); 1460 for (unsigned i = 0; i != DstNumElts; ++i) { 1461 Idxs[i] = i + (Imm * DstNumElts); 1462 } 1463 Rep = Builder.CreateShuffleVector(Op0, Op0, Idxs); 1464 1465 // If the intrinsic has a mask operand, handle that. 1466 if (CI->getNumArgOperands() == 4) 1467 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1468 CI->getArgOperand(2)); 1469 } else if (!IsX86 && Name == "stackprotectorcheck") { 1470 Rep = nullptr; 1471 } else if (IsX86 && (Name.startswith("avx512.mask.perm.df.") || 1472 Name.startswith("avx512.mask.perm.di."))) { 1473 Value *Op0 = CI->getArgOperand(0); 1474 unsigned Imm = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue(); 1475 VectorType *VecTy = cast<VectorType>(CI->getType()); 1476 unsigned NumElts = VecTy->getNumElements(); 1477 1478 SmallVector<uint32_t, 8> Idxs(NumElts); 1479 for (unsigned i = 0; i != NumElts; ++i) 1480 Idxs[i] = (i & ~0x3) + ((Imm >> (2 * (i & 0x3))) & 3); 1481 1482 Rep = Builder.CreateShuffleVector(Op0, Op0, Idxs); 1483 1484 if (CI->getNumArgOperands() == 4) 1485 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1486 CI->getArgOperand(2)); 1487 } else if (IsX86 && (Name.startswith("avx.vperm2f128.") || 1488 Name == "avx2.vperm2i128")) { 1489 // The immediate permute control byte looks like this: 1490 // [1:0] - select 128 bits from sources for low half of destination 1491 // [2] - ignore 1492 // [3] - zero low half of destination 1493 // [5:4] - select 128 bits from sources for high half of destination 1494 // [6] - ignore 1495 // [7] - zero high half of destination 1496 1497 uint8_t Imm = cast<ConstantInt>(CI->getArgOperand(2))->getZExtValue(); 1498 1499 unsigned NumElts = CI->getType()->getVectorNumElements(); 1500 unsigned HalfSize = NumElts / 2; 1501 SmallVector<uint32_t, 8> ShuffleMask(NumElts); 1502 1503 // Determine which operand(s) are actually in use for this instruction. 1504 Value *V0 = (Imm & 0x02) ? CI->getArgOperand(1) : CI->getArgOperand(0); 1505 Value *V1 = (Imm & 0x20) ? CI->getArgOperand(1) : CI->getArgOperand(0); 1506 1507 // If needed, replace operands based on zero mask. 1508 V0 = (Imm & 0x08) ? ConstantAggregateZero::get(CI->getType()) : V0; 1509 V1 = (Imm & 0x80) ? ConstantAggregateZero::get(CI->getType()) : V1; 1510 1511 // Permute low half of result. 1512 unsigned StartIndex = (Imm & 0x01) ? HalfSize : 0; 1513 for (unsigned i = 0; i < HalfSize; ++i) 1514 ShuffleMask[i] = StartIndex + i; 1515 1516 // Permute high half of result. 1517 StartIndex = (Imm & 0x10) ? HalfSize : 0; 1518 for (unsigned i = 0; i < HalfSize; ++i) 1519 ShuffleMask[i + HalfSize] = NumElts + StartIndex + i; 1520 1521 Rep = Builder.CreateShuffleVector(V0, V1, ShuffleMask); 1522 1523 } else if (IsX86 && (Name.startswith("avx.vpermil.") || 1524 Name == "sse2.pshuf.d" || 1525 Name.startswith("avx512.mask.vpermil.p") || 1526 Name.startswith("avx512.mask.pshuf.d."))) { 1527 Value *Op0 = CI->getArgOperand(0); 1528 unsigned Imm = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue(); 1529 VectorType *VecTy = cast<VectorType>(CI->getType()); 1530 unsigned NumElts = VecTy->getNumElements(); 1531 // Calculate the size of each index in the immediate. 1532 unsigned IdxSize = 64 / VecTy->getScalarSizeInBits(); 1533 unsigned IdxMask = ((1 << IdxSize) - 1); 1534 1535 SmallVector<uint32_t, 8> Idxs(NumElts); 1536 // Lookup the bits for this element, wrapping around the immediate every 1537 // 8-bits. Elements are grouped into sets of 2 or 4 elements so we need 1538 // to offset by the first index of each group. 1539 for (unsigned i = 0; i != NumElts; ++i) 1540 Idxs[i] = ((Imm >> ((i * IdxSize) % 8)) & IdxMask) | (i & ~IdxMask); 1541 1542 Rep = Builder.CreateShuffleVector(Op0, Op0, Idxs); 1543 1544 if (CI->getNumArgOperands() == 4) 1545 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1546 CI->getArgOperand(2)); 1547 } else if (IsX86 && (Name == "sse2.pshufl.w" || 1548 Name.startswith("avx512.mask.pshufl.w."))) { 1549 Value *Op0 = CI->getArgOperand(0); 1550 unsigned Imm = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue(); 1551 unsigned NumElts = CI->getType()->getVectorNumElements(); 1552 1553 SmallVector<uint32_t, 16> Idxs(NumElts); 1554 for (unsigned l = 0; l != NumElts; l += 8) { 1555 for (unsigned i = 0; i != 4; ++i) 1556 Idxs[i + l] = ((Imm >> (2 * i)) & 0x3) + l; 1557 for (unsigned i = 4; i != 8; ++i) 1558 Idxs[i + l] = i + l; 1559 } 1560 1561 Rep = Builder.CreateShuffleVector(Op0, Op0, Idxs); 1562 1563 if (CI->getNumArgOperands() == 4) 1564 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1565 CI->getArgOperand(2)); 1566 } else if (IsX86 && (Name == "sse2.pshufh.w" || 1567 Name.startswith("avx512.mask.pshufh.w."))) { 1568 Value *Op0 = CI->getArgOperand(0); 1569 unsigned Imm = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue(); 1570 unsigned NumElts = CI->getType()->getVectorNumElements(); 1571 1572 SmallVector<uint32_t, 16> Idxs(NumElts); 1573 for (unsigned l = 0; l != NumElts; l += 8) { 1574 for (unsigned i = 0; i != 4; ++i) 1575 Idxs[i + l] = i + l; 1576 for (unsigned i = 0; i != 4; ++i) 1577 Idxs[i + l + 4] = ((Imm >> (2 * i)) & 0x3) + 4 + l; 1578 } 1579 1580 Rep = Builder.CreateShuffleVector(Op0, Op0, Idxs); 1581 1582 if (CI->getNumArgOperands() == 4) 1583 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1584 CI->getArgOperand(2)); 1585 } else if (IsX86 && Name.startswith("avx512.mask.shuf.p")) { 1586 Value *Op0 = CI->getArgOperand(0); 1587 Value *Op1 = CI->getArgOperand(1); 1588 unsigned Imm = cast<ConstantInt>(CI->getArgOperand(2))->getZExtValue(); 1589 unsigned NumElts = CI->getType()->getVectorNumElements(); 1590 1591 unsigned NumLaneElts = 128/CI->getType()->getScalarSizeInBits(); 1592 unsigned HalfLaneElts = NumLaneElts / 2; 1593 1594 SmallVector<uint32_t, 16> Idxs(NumElts); 1595 for (unsigned i = 0; i != NumElts; ++i) { 1596 // Base index is the starting element of the lane. 1597 Idxs[i] = i - (i % NumLaneElts); 1598 // If we are half way through the lane switch to the other source. 1599 if ((i % NumLaneElts) >= HalfLaneElts) 1600 Idxs[i] += NumElts; 1601 // Now select the specific element. By adding HalfLaneElts bits from 1602 // the immediate. Wrapping around the immediate every 8-bits. 1603 Idxs[i] += (Imm >> ((i * HalfLaneElts) % 8)) & ((1 << HalfLaneElts) - 1); 1604 } 1605 1606 Rep = Builder.CreateShuffleVector(Op0, Op1, Idxs); 1607 1608 Rep = EmitX86Select(Builder, CI->getArgOperand(4), Rep, 1609 CI->getArgOperand(3)); 1610 } else if (IsX86 && (Name.startswith("avx512.mask.movddup") || 1611 Name.startswith("avx512.mask.movshdup") || 1612 Name.startswith("avx512.mask.movsldup"))) { 1613 Value *Op0 = CI->getArgOperand(0); 1614 unsigned NumElts = CI->getType()->getVectorNumElements(); 1615 unsigned NumLaneElts = 128/CI->getType()->getScalarSizeInBits(); 1616 1617 unsigned Offset = 0; 1618 if (Name.startswith("avx512.mask.movshdup.")) 1619 Offset = 1; 1620 1621 SmallVector<uint32_t, 16> Idxs(NumElts); 1622 for (unsigned l = 0; l != NumElts; l += NumLaneElts) 1623 for (unsigned i = 0; i != NumLaneElts; i += 2) { 1624 Idxs[i + l + 0] = i + l + Offset; 1625 Idxs[i + l + 1] = i + l + Offset; 1626 } 1627 1628 Rep = Builder.CreateShuffleVector(Op0, Op0, Idxs); 1629 1630 Rep = EmitX86Select(Builder, CI->getArgOperand(2), Rep, 1631 CI->getArgOperand(1)); 1632 } else if (IsX86 && (Name.startswith("avx512.mask.punpckl") || 1633 Name.startswith("avx512.mask.unpckl."))) { 1634 Value *Op0 = CI->getArgOperand(0); 1635 Value *Op1 = CI->getArgOperand(1); 1636 int NumElts = CI->getType()->getVectorNumElements(); 1637 int NumLaneElts = 128/CI->getType()->getScalarSizeInBits(); 1638 1639 SmallVector<uint32_t, 64> Idxs(NumElts); 1640 for (int l = 0; l != NumElts; l += NumLaneElts) 1641 for (int i = 0; i != NumLaneElts; ++i) 1642 Idxs[i + l] = l + (i / 2) + NumElts * (i % 2); 1643 1644 Rep = Builder.CreateShuffleVector(Op0, Op1, Idxs); 1645 1646 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1647 CI->getArgOperand(2)); 1648 } else if (IsX86 && (Name.startswith("avx512.mask.punpckh") || 1649 Name.startswith("avx512.mask.unpckh."))) { 1650 Value *Op0 = CI->getArgOperand(0); 1651 Value *Op1 = CI->getArgOperand(1); 1652 int NumElts = CI->getType()->getVectorNumElements(); 1653 int NumLaneElts = 128/CI->getType()->getScalarSizeInBits(); 1654 1655 SmallVector<uint32_t, 64> Idxs(NumElts); 1656 for (int l = 0; l != NumElts; l += NumLaneElts) 1657 for (int i = 0; i != NumLaneElts; ++i) 1658 Idxs[i + l] = (NumLaneElts / 2) + l + (i / 2) + NumElts * (i % 2); 1659 1660 Rep = Builder.CreateShuffleVector(Op0, Op1, Idxs); 1661 1662 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1663 CI->getArgOperand(2)); 1664 } else if (IsX86 && Name.startswith("avx512.mask.pand.")) { 1665 Rep = Builder.CreateAnd(CI->getArgOperand(0), CI->getArgOperand(1)); 1666 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1667 CI->getArgOperand(2)); 1668 } else if (IsX86 && Name.startswith("avx512.mask.pandn.")) { 1669 Rep = Builder.CreateAnd(Builder.CreateNot(CI->getArgOperand(0)), 1670 CI->getArgOperand(1)); 1671 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1672 CI->getArgOperand(2)); 1673 } else if (IsX86 && Name.startswith("avx512.mask.por.")) { 1674 Rep = Builder.CreateOr(CI->getArgOperand(0), CI->getArgOperand(1)); 1675 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1676 CI->getArgOperand(2)); 1677 } else if (IsX86 && Name.startswith("avx512.mask.pxor.")) { 1678 Rep = Builder.CreateXor(CI->getArgOperand(0), CI->getArgOperand(1)); 1679 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1680 CI->getArgOperand(2)); 1681 } else if (IsX86 && Name.startswith("avx512.mask.and.")) { 1682 VectorType *FTy = cast<VectorType>(CI->getType()); 1683 VectorType *ITy = VectorType::getInteger(FTy); 1684 Rep = Builder.CreateAnd(Builder.CreateBitCast(CI->getArgOperand(0), ITy), 1685 Builder.CreateBitCast(CI->getArgOperand(1), ITy)); 1686 Rep = Builder.CreateBitCast(Rep, FTy); 1687 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1688 CI->getArgOperand(2)); 1689 } else if (IsX86 && Name.startswith("avx512.mask.andn.")) { 1690 VectorType *FTy = cast<VectorType>(CI->getType()); 1691 VectorType *ITy = VectorType::getInteger(FTy); 1692 Rep = Builder.CreateNot(Builder.CreateBitCast(CI->getArgOperand(0), ITy)); 1693 Rep = Builder.CreateAnd(Rep, 1694 Builder.CreateBitCast(CI->getArgOperand(1), ITy)); 1695 Rep = Builder.CreateBitCast(Rep, FTy); 1696 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1697 CI->getArgOperand(2)); 1698 } else if (IsX86 && Name.startswith("avx512.mask.or.")) { 1699 VectorType *FTy = cast<VectorType>(CI->getType()); 1700 VectorType *ITy = VectorType::getInteger(FTy); 1701 Rep = Builder.CreateOr(Builder.CreateBitCast(CI->getArgOperand(0), ITy), 1702 Builder.CreateBitCast(CI->getArgOperand(1), ITy)); 1703 Rep = Builder.CreateBitCast(Rep, FTy); 1704 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1705 CI->getArgOperand(2)); 1706 } else if (IsX86 && Name.startswith("avx512.mask.xor.")) { 1707 VectorType *FTy = cast<VectorType>(CI->getType()); 1708 VectorType *ITy = VectorType::getInteger(FTy); 1709 Rep = Builder.CreateXor(Builder.CreateBitCast(CI->getArgOperand(0), ITy), 1710 Builder.CreateBitCast(CI->getArgOperand(1), ITy)); 1711 Rep = Builder.CreateBitCast(Rep, FTy); 1712 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1713 CI->getArgOperand(2)); 1714 } else if (IsX86 && Name.startswith("avx512.mask.padd.")) { 1715 Rep = Builder.CreateAdd(CI->getArgOperand(0), CI->getArgOperand(1)); 1716 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1717 CI->getArgOperand(2)); 1718 } else if (IsX86 && Name.startswith("avx512.mask.psub.")) { 1719 Rep = Builder.CreateSub(CI->getArgOperand(0), CI->getArgOperand(1)); 1720 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1721 CI->getArgOperand(2)); 1722 } else if (IsX86 && Name.startswith("avx512.mask.pmull.")) { 1723 Rep = Builder.CreateMul(CI->getArgOperand(0), CI->getArgOperand(1)); 1724 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1725 CI->getArgOperand(2)); 1726 } else if (IsX86 && (Name.startswith("avx512.mask.add.p"))) { 1727 Rep = Builder.CreateFAdd(CI->getArgOperand(0), CI->getArgOperand(1)); 1728 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1729 CI->getArgOperand(2)); 1730 } else if (IsX86 && Name.startswith("avx512.mask.div.p")) { 1731 Rep = Builder.CreateFDiv(CI->getArgOperand(0), CI->getArgOperand(1)); 1732 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1733 CI->getArgOperand(2)); 1734 } else if (IsX86 && Name.startswith("avx512.mask.mul.p")) { 1735 Rep = Builder.CreateFMul(CI->getArgOperand(0), CI->getArgOperand(1)); 1736 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1737 CI->getArgOperand(2)); 1738 } else if (IsX86 && Name.startswith("avx512.mask.sub.p")) { 1739 Rep = Builder.CreateFSub(CI->getArgOperand(0), CI->getArgOperand(1)); 1740 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1741 CI->getArgOperand(2)); 1742 } else if (IsX86 && Name.startswith("avx512.mask.lzcnt.")) { 1743 Rep = Builder.CreateCall(Intrinsic::getDeclaration(F->getParent(), 1744 Intrinsic::ctlz, 1745 CI->getType()), 1746 { CI->getArgOperand(0), Builder.getInt1(false) }); 1747 Rep = EmitX86Select(Builder, CI->getArgOperand(2), Rep, 1748 CI->getArgOperand(1)); 1749 } else if (IsX86 && (Name.startswith("avx512.mask.max.p") || 1750 Name.startswith("avx512.mask.min.p"))) { 1751 bool IsMin = Name[13] == 'i'; 1752 VectorType *VecTy = cast<VectorType>(CI->getType()); 1753 unsigned VecWidth = VecTy->getPrimitiveSizeInBits(); 1754 unsigned EltWidth = VecTy->getScalarSizeInBits(); 1755 Intrinsic::ID IID; 1756 if (!IsMin && VecWidth == 128 && EltWidth == 32) 1757 IID = Intrinsic::x86_sse_max_ps; 1758 else if (!IsMin && VecWidth == 128 && EltWidth == 64) 1759 IID = Intrinsic::x86_sse2_max_pd; 1760 else if (!IsMin && VecWidth == 256 && EltWidth == 32) 1761 IID = Intrinsic::x86_avx_max_ps_256; 1762 else if (!IsMin && VecWidth == 256 && EltWidth == 64) 1763 IID = Intrinsic::x86_avx_max_pd_256; 1764 else if (IsMin && VecWidth == 128 && EltWidth == 32) 1765 IID = Intrinsic::x86_sse_min_ps; 1766 else if (IsMin && VecWidth == 128 && EltWidth == 64) 1767 IID = Intrinsic::x86_sse2_min_pd; 1768 else if (IsMin && VecWidth == 256 && EltWidth == 32) 1769 IID = Intrinsic::x86_avx_min_ps_256; 1770 else if (IsMin && VecWidth == 256 && EltWidth == 64) 1771 IID = Intrinsic::x86_avx_min_pd_256; 1772 else 1773 llvm_unreachable("Unexpected intrinsic"); 1774 1775 Rep = Builder.CreateCall(Intrinsic::getDeclaration(F->getParent(), IID), 1776 { CI->getArgOperand(0), CI->getArgOperand(1) }); 1777 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1778 CI->getArgOperand(2)); 1779 } else if (IsX86 && Name.startswith("avx512.mask.pshuf.b.")) { 1780 VectorType *VecTy = cast<VectorType>(CI->getType()); 1781 Intrinsic::ID IID; 1782 if (VecTy->getPrimitiveSizeInBits() == 128) 1783 IID = Intrinsic::x86_ssse3_pshuf_b_128; 1784 else if (VecTy->getPrimitiveSizeInBits() == 256) 1785 IID = Intrinsic::x86_avx2_pshuf_b; 1786 else if (VecTy->getPrimitiveSizeInBits() == 512) 1787 IID = Intrinsic::x86_avx512_pshuf_b_512; 1788 else 1789 llvm_unreachable("Unexpected intrinsic"); 1790 1791 Rep = Builder.CreateCall(Intrinsic::getDeclaration(F->getParent(), IID), 1792 { CI->getArgOperand(0), CI->getArgOperand(1) }); 1793 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1794 CI->getArgOperand(2)); 1795 } else if (IsX86 && (Name.startswith("avx512.mask.pmul.dq.") || 1796 Name.startswith("avx512.mask.pmulu.dq."))) { 1797 bool IsUnsigned = Name[16] == 'u'; 1798 VectorType *VecTy = cast<VectorType>(CI->getType()); 1799 Intrinsic::ID IID; 1800 if (!IsUnsigned && VecTy->getPrimitiveSizeInBits() == 128) 1801 IID = Intrinsic::x86_sse41_pmuldq; 1802 else if (!IsUnsigned && VecTy->getPrimitiveSizeInBits() == 256) 1803 IID = Intrinsic::x86_avx2_pmul_dq; 1804 else if (!IsUnsigned && VecTy->getPrimitiveSizeInBits() == 512) 1805 IID = Intrinsic::x86_avx512_pmul_dq_512; 1806 else if (IsUnsigned && VecTy->getPrimitiveSizeInBits() == 128) 1807 IID = Intrinsic::x86_sse2_pmulu_dq; 1808 else if (IsUnsigned && VecTy->getPrimitiveSizeInBits() == 256) 1809 IID = Intrinsic::x86_avx2_pmulu_dq; 1810 else if (IsUnsigned && VecTy->getPrimitiveSizeInBits() == 512) 1811 IID = Intrinsic::x86_avx512_pmulu_dq_512; 1812 else 1813 llvm_unreachable("Unexpected intrinsic"); 1814 1815 Rep = Builder.CreateCall(Intrinsic::getDeclaration(F->getParent(), IID), 1816 { CI->getArgOperand(0), CI->getArgOperand(1) }); 1817 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1818 CI->getArgOperand(2)); 1819 } else if (IsX86 && Name.startswith("avx512.mask.pack")) { 1820 bool IsUnsigned = Name[16] == 'u'; 1821 bool IsDW = Name[18] == 'd'; 1822 VectorType *VecTy = cast<VectorType>(CI->getType()); 1823 Intrinsic::ID IID; 1824 if (!IsUnsigned && !IsDW && VecTy->getPrimitiveSizeInBits() == 128) 1825 IID = Intrinsic::x86_sse2_packsswb_128; 1826 else if (!IsUnsigned && !IsDW && VecTy->getPrimitiveSizeInBits() == 256) 1827 IID = Intrinsic::x86_avx2_packsswb; 1828 else if (!IsUnsigned && !IsDW && VecTy->getPrimitiveSizeInBits() == 512) 1829 IID = Intrinsic::x86_avx512_packsswb_512; 1830 else if (!IsUnsigned && IsDW && VecTy->getPrimitiveSizeInBits() == 128) 1831 IID = Intrinsic::x86_sse2_packssdw_128; 1832 else if (!IsUnsigned && IsDW && VecTy->getPrimitiveSizeInBits() == 256) 1833 IID = Intrinsic::x86_avx2_packssdw; 1834 else if (!IsUnsigned && IsDW && VecTy->getPrimitiveSizeInBits() == 512) 1835 IID = Intrinsic::x86_avx512_packssdw_512; 1836 else if (IsUnsigned && !IsDW && VecTy->getPrimitiveSizeInBits() == 128) 1837 IID = Intrinsic::x86_sse2_packuswb_128; 1838 else if (IsUnsigned && !IsDW && VecTy->getPrimitiveSizeInBits() == 256) 1839 IID = Intrinsic::x86_avx2_packuswb; 1840 else if (IsUnsigned && !IsDW && VecTy->getPrimitiveSizeInBits() == 512) 1841 IID = Intrinsic::x86_avx512_packuswb_512; 1842 else if (IsUnsigned && IsDW && VecTy->getPrimitiveSizeInBits() == 128) 1843 IID = Intrinsic::x86_sse41_packusdw; 1844 else if (IsUnsigned && IsDW && VecTy->getPrimitiveSizeInBits() == 256) 1845 IID = Intrinsic::x86_avx2_packusdw; 1846 else if (IsUnsigned && IsDW && VecTy->getPrimitiveSizeInBits() == 512) 1847 IID = Intrinsic::x86_avx512_packusdw_512; 1848 else 1849 llvm_unreachable("Unexpected intrinsic"); 1850 1851 Rep = Builder.CreateCall(Intrinsic::getDeclaration(F->getParent(), IID), 1852 { CI->getArgOperand(0), CI->getArgOperand(1) }); 1853 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1854 CI->getArgOperand(2)); 1855 } else if (IsX86 && Name.startswith("avx512.mask.psll")) { 1856 bool IsImmediate = Name[16] == 'i' || 1857 (Name.size() > 18 && Name[18] == 'i'); 1858 bool IsVariable = Name[16] == 'v'; 1859 char Size = Name[16] == '.' ? Name[17] : 1860 Name[17] == '.' ? Name[18] : 1861 Name[18] == '.' ? Name[19] : 1862 Name[20]; 1863 1864 Intrinsic::ID IID; 1865 if (IsVariable && Name[17] != '.') { 1866 if (Size == 'd' && Name[17] == '2') // avx512.mask.psllv2.di 1867 IID = Intrinsic::x86_avx2_psllv_q; 1868 else if (Size == 'd' && Name[17] == '4') // avx512.mask.psllv4.di 1869 IID = Intrinsic::x86_avx2_psllv_q_256; 1870 else if (Size == 's' && Name[17] == '4') // avx512.mask.psllv4.si 1871 IID = Intrinsic::x86_avx2_psllv_d; 1872 else if (Size == 's' && Name[17] == '8') // avx512.mask.psllv8.si 1873 IID = Intrinsic::x86_avx2_psllv_d_256; 1874 else if (Size == 'h' && Name[17] == '8') // avx512.mask.psllv8.hi 1875 IID = Intrinsic::x86_avx512_psllv_w_128; 1876 else if (Size == 'h' && Name[17] == '1') // avx512.mask.psllv16.hi 1877 IID = Intrinsic::x86_avx512_psllv_w_256; 1878 else if (Name[17] == '3' && Name[18] == '2') // avx512.mask.psllv32hi 1879 IID = Intrinsic::x86_avx512_psllv_w_512; 1880 else 1881 llvm_unreachable("Unexpected size"); 1882 } else if (Name.endswith(".128")) { 1883 if (Size == 'd') // avx512.mask.psll.d.128, avx512.mask.psll.di.128 1884 IID = IsImmediate ? Intrinsic::x86_sse2_pslli_d 1885 : Intrinsic::x86_sse2_psll_d; 1886 else if (Size == 'q') // avx512.mask.psll.q.128, avx512.mask.psll.qi.128 1887 IID = IsImmediate ? Intrinsic::x86_sse2_pslli_q 1888 : Intrinsic::x86_sse2_psll_q; 1889 else if (Size == 'w') // avx512.mask.psll.w.128, avx512.mask.psll.wi.128 1890 IID = IsImmediate ? Intrinsic::x86_sse2_pslli_w 1891 : Intrinsic::x86_sse2_psll_w; 1892 else 1893 llvm_unreachable("Unexpected size"); 1894 } else if (Name.endswith(".256")) { 1895 if (Size == 'd') // avx512.mask.psll.d.256, avx512.mask.psll.di.256 1896 IID = IsImmediate ? Intrinsic::x86_avx2_pslli_d 1897 : Intrinsic::x86_avx2_psll_d; 1898 else if (Size == 'q') // avx512.mask.psll.q.256, avx512.mask.psll.qi.256 1899 IID = IsImmediate ? Intrinsic::x86_avx2_pslli_q 1900 : Intrinsic::x86_avx2_psll_q; 1901 else if (Size == 'w') // avx512.mask.psll.w.256, avx512.mask.psll.wi.256 1902 IID = IsImmediate ? Intrinsic::x86_avx2_pslli_w 1903 : Intrinsic::x86_avx2_psll_w; 1904 else 1905 llvm_unreachable("Unexpected size"); 1906 } else { 1907 if (Size == 'd') // psll.di.512, pslli.d, psll.d, psllv.d.512 1908 IID = IsImmediate ? Intrinsic::x86_avx512_pslli_d_512 : 1909 IsVariable ? Intrinsic::x86_avx512_psllv_d_512 : 1910 Intrinsic::x86_avx512_psll_d_512; 1911 else if (Size == 'q') // psll.qi.512, pslli.q, psll.q, psllv.q.512 1912 IID = IsImmediate ? Intrinsic::x86_avx512_pslli_q_512 : 1913 IsVariable ? Intrinsic::x86_avx512_psllv_q_512 : 1914 Intrinsic::x86_avx512_psll_q_512; 1915 else if (Size == 'w') // psll.wi.512, pslli.w, psll.w 1916 IID = IsImmediate ? Intrinsic::x86_avx512_pslli_w_512 1917 : Intrinsic::x86_avx512_psll_w_512; 1918 else 1919 llvm_unreachable("Unexpected size"); 1920 } 1921 1922 Rep = UpgradeX86MaskedShift(Builder, *CI, IID); 1923 } else if (IsX86 && Name.startswith("avx512.mask.psrl")) { 1924 bool IsImmediate = Name[16] == 'i' || 1925 (Name.size() > 18 && Name[18] == 'i'); 1926 bool IsVariable = Name[16] == 'v'; 1927 char Size = Name[16] == '.' ? Name[17] : 1928 Name[17] == '.' ? Name[18] : 1929 Name[18] == '.' ? Name[19] : 1930 Name[20]; 1931 1932 Intrinsic::ID IID; 1933 if (IsVariable && Name[17] != '.') { 1934 if (Size == 'd' && Name[17] == '2') // avx512.mask.psrlv2.di 1935 IID = Intrinsic::x86_avx2_psrlv_q; 1936 else if (Size == 'd' && Name[17] == '4') // avx512.mask.psrlv4.di 1937 IID = Intrinsic::x86_avx2_psrlv_q_256; 1938 else if (Size == 's' && Name[17] == '4') // avx512.mask.psrlv4.si 1939 IID = Intrinsic::x86_avx2_psrlv_d; 1940 else if (Size == 's' && Name[17] == '8') // avx512.mask.psrlv8.si 1941 IID = Intrinsic::x86_avx2_psrlv_d_256; 1942 else if (Size == 'h' && Name[17] == '8') // avx512.mask.psrlv8.hi 1943 IID = Intrinsic::x86_avx512_psrlv_w_128; 1944 else if (Size == 'h' && Name[17] == '1') // avx512.mask.psrlv16.hi 1945 IID = Intrinsic::x86_avx512_psrlv_w_256; 1946 else if (Name[17] == '3' && Name[18] == '2') // avx512.mask.psrlv32hi 1947 IID = Intrinsic::x86_avx512_psrlv_w_512; 1948 else 1949 llvm_unreachable("Unexpected size"); 1950 } else if (Name.endswith(".128")) { 1951 if (Size == 'd') // avx512.mask.psrl.d.128, avx512.mask.psrl.di.128 1952 IID = IsImmediate ? Intrinsic::x86_sse2_psrli_d 1953 : Intrinsic::x86_sse2_psrl_d; 1954 else if (Size == 'q') // avx512.mask.psrl.q.128, avx512.mask.psrl.qi.128 1955 IID = IsImmediate ? Intrinsic::x86_sse2_psrli_q 1956 : Intrinsic::x86_sse2_psrl_q; 1957 else if (Size == 'w') // avx512.mask.psrl.w.128, avx512.mask.psrl.wi.128 1958 IID = IsImmediate ? Intrinsic::x86_sse2_psrli_w 1959 : Intrinsic::x86_sse2_psrl_w; 1960 else 1961 llvm_unreachable("Unexpected size"); 1962 } else if (Name.endswith(".256")) { 1963 if (Size == 'd') // avx512.mask.psrl.d.256, avx512.mask.psrl.di.256 1964 IID = IsImmediate ? Intrinsic::x86_avx2_psrli_d 1965 : Intrinsic::x86_avx2_psrl_d; 1966 else if (Size == 'q') // avx512.mask.psrl.q.256, avx512.mask.psrl.qi.256 1967 IID = IsImmediate ? Intrinsic::x86_avx2_psrli_q 1968 : Intrinsic::x86_avx2_psrl_q; 1969 else if (Size == 'w') // avx512.mask.psrl.w.256, avx512.mask.psrl.wi.256 1970 IID = IsImmediate ? Intrinsic::x86_avx2_psrli_w 1971 : Intrinsic::x86_avx2_psrl_w; 1972 else 1973 llvm_unreachable("Unexpected size"); 1974 } else { 1975 if (Size == 'd') // psrl.di.512, psrli.d, psrl.d, psrl.d.512 1976 IID = IsImmediate ? Intrinsic::x86_avx512_psrli_d_512 : 1977 IsVariable ? Intrinsic::x86_avx512_psrlv_d_512 : 1978 Intrinsic::x86_avx512_psrl_d_512; 1979 else if (Size == 'q') // psrl.qi.512, psrli.q, psrl.q, psrl.q.512 1980 IID = IsImmediate ? Intrinsic::x86_avx512_psrli_q_512 : 1981 IsVariable ? Intrinsic::x86_avx512_psrlv_q_512 : 1982 Intrinsic::x86_avx512_psrl_q_512; 1983 else if (Size == 'w') // psrl.wi.512, psrli.w, psrl.w) 1984 IID = IsImmediate ? Intrinsic::x86_avx512_psrli_w_512 1985 : Intrinsic::x86_avx512_psrl_w_512; 1986 else 1987 llvm_unreachable("Unexpected size"); 1988 } 1989 1990 Rep = UpgradeX86MaskedShift(Builder, *CI, IID); 1991 } else if (IsX86 && Name.startswith("avx512.mask.psra")) { 1992 bool IsImmediate = Name[16] == 'i' || 1993 (Name.size() > 18 && Name[18] == 'i'); 1994 bool IsVariable = Name[16] == 'v'; 1995 char Size = Name[16] == '.' ? Name[17] : 1996 Name[17] == '.' ? Name[18] : 1997 Name[18] == '.' ? Name[19] : 1998 Name[20]; 1999 2000 Intrinsic::ID IID; 2001 if (IsVariable && Name[17] != '.') { 2002 if (Size == 's' && Name[17] == '4') // avx512.mask.psrav4.si 2003 IID = Intrinsic::x86_avx2_psrav_d; 2004 else if (Size == 's' && Name[17] == '8') // avx512.mask.psrav8.si 2005 IID = Intrinsic::x86_avx2_psrav_d_256; 2006 else if (Size == 'h' && Name[17] == '8') // avx512.mask.psrav8.hi 2007 IID = Intrinsic::x86_avx512_psrav_w_128; 2008 else if (Size == 'h' && Name[17] == '1') // avx512.mask.psrav16.hi 2009 IID = Intrinsic::x86_avx512_psrav_w_256; 2010 else if (Name[17] == '3' && Name[18] == '2') // avx512.mask.psrav32hi 2011 IID = Intrinsic::x86_avx512_psrav_w_512; 2012 else 2013 llvm_unreachable("Unexpected size"); 2014 } else if (Name.endswith(".128")) { 2015 if (Size == 'd') // avx512.mask.psra.d.128, avx512.mask.psra.di.128 2016 IID = IsImmediate ? Intrinsic::x86_sse2_psrai_d 2017 : Intrinsic::x86_sse2_psra_d; 2018 else if (Size == 'q') // avx512.mask.psra.q.128, avx512.mask.psra.qi.128 2019 IID = IsImmediate ? Intrinsic::x86_avx512_psrai_q_128 : 2020 IsVariable ? Intrinsic::x86_avx512_psrav_q_128 : 2021 Intrinsic::x86_avx512_psra_q_128; 2022 else if (Size == 'w') // avx512.mask.psra.w.128, avx512.mask.psra.wi.128 2023 IID = IsImmediate ? Intrinsic::x86_sse2_psrai_w 2024 : Intrinsic::x86_sse2_psra_w; 2025 else 2026 llvm_unreachable("Unexpected size"); 2027 } else if (Name.endswith(".256")) { 2028 if (Size == 'd') // avx512.mask.psra.d.256, avx512.mask.psra.di.256 2029 IID = IsImmediate ? Intrinsic::x86_avx2_psrai_d 2030 : Intrinsic::x86_avx2_psra_d; 2031 else if (Size == 'q') // avx512.mask.psra.q.256, avx512.mask.psra.qi.256 2032 IID = IsImmediate ? Intrinsic::x86_avx512_psrai_q_256 : 2033 IsVariable ? Intrinsic::x86_avx512_psrav_q_256 : 2034 Intrinsic::x86_avx512_psra_q_256; 2035 else if (Size == 'w') // avx512.mask.psra.w.256, avx512.mask.psra.wi.256 2036 IID = IsImmediate ? Intrinsic::x86_avx2_psrai_w 2037 : Intrinsic::x86_avx2_psra_w; 2038 else 2039 llvm_unreachable("Unexpected size"); 2040 } else { 2041 if (Size == 'd') // psra.di.512, psrai.d, psra.d, psrav.d.512 2042 IID = IsImmediate ? Intrinsic::x86_avx512_psrai_d_512 : 2043 IsVariable ? Intrinsic::x86_avx512_psrav_d_512 : 2044 Intrinsic::x86_avx512_psra_d_512; 2045 else if (Size == 'q') // psra.qi.512, psrai.q, psra.q 2046 IID = IsImmediate ? Intrinsic::x86_avx512_psrai_q_512 : 2047 IsVariable ? Intrinsic::x86_avx512_psrav_q_512 : 2048 Intrinsic::x86_avx512_psra_q_512; 2049 else if (Size == 'w') // psra.wi.512, psrai.w, psra.w 2050 IID = IsImmediate ? Intrinsic::x86_avx512_psrai_w_512 2051 : Intrinsic::x86_avx512_psra_w_512; 2052 else 2053 llvm_unreachable("Unexpected size"); 2054 } 2055 2056 Rep = UpgradeX86MaskedShift(Builder, *CI, IID); 2057 } else if (IsX86 && Name.startswith("avx512.mask.move.s")) { 2058 Rep = upgradeMaskedMove(Builder, *CI); 2059 } else if (IsX86 && Name.startswith("avx512.cvtmask2")) { 2060 Rep = UpgradeMaskToInt(Builder, *CI); 2061 } else if (IsX86 && Name.startswith("avx512.mask.vpermilvar.")) { 2062 Intrinsic::ID IID; 2063 if (Name.endswith("ps.128")) 2064 IID = Intrinsic::x86_avx_vpermilvar_ps; 2065 else if (Name.endswith("pd.128")) 2066 IID = Intrinsic::x86_avx_vpermilvar_pd; 2067 else if (Name.endswith("ps.256")) 2068 IID = Intrinsic::x86_avx_vpermilvar_ps_256; 2069 else if (Name.endswith("pd.256")) 2070 IID = Intrinsic::x86_avx_vpermilvar_pd_256; 2071 else if (Name.endswith("ps.512")) 2072 IID = Intrinsic::x86_avx512_vpermilvar_ps_512; 2073 else if (Name.endswith("pd.512")) 2074 IID = Intrinsic::x86_avx512_vpermilvar_pd_512; 2075 else 2076 llvm_unreachable("Unexpected vpermilvar intrinsic"); 2077 2078 Function *Intrin = Intrinsic::getDeclaration(F->getParent(), IID); 2079 Rep = Builder.CreateCall(Intrin, 2080 { CI->getArgOperand(0), CI->getArgOperand(1) }); 2081 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 2082 CI->getArgOperand(2)); 2083 } else if (IsX86 && Name.endswith(".movntdqa")) { 2084 Module *M = F->getParent(); 2085 MDNode *Node = MDNode::get( 2086 C, ConstantAsMetadata::get(ConstantInt::get(Type::getInt32Ty(C), 1))); 2087 2088 Value *Ptr = CI->getArgOperand(0); 2089 VectorType *VTy = cast<VectorType>(CI->getType()); 2090 2091 // Convert the type of the pointer to a pointer to the stored type. 2092 Value *BC = 2093 Builder.CreateBitCast(Ptr, PointerType::getUnqual(VTy), "cast"); 2094 LoadInst *LI = Builder.CreateAlignedLoad(BC, VTy->getBitWidth() / 8); 2095 LI->setMetadata(M->getMDKindID("nontemporal"), Node); 2096 Rep = LI; 2097 } else if (IsX86 && 2098 (Name.startswith("sse2.pavg") || Name.startswith("avx2.pavg") || 2099 Name.startswith("avx512.mask.pavg"))) { 2100 // llvm.x86.sse2.pavg.b/w, llvm.x86.avx2.pavg.b/w, 2101 // llvm.x86.avx512.mask.pavg.b/w 2102 Value *A = CI->getArgOperand(0); 2103 Value *B = CI->getArgOperand(1); 2104 VectorType *ZextType = VectorType::getExtendedElementVectorType( 2105 cast<VectorType>(A->getType())); 2106 Value *ExtendedA = Builder.CreateZExt(A, ZextType); 2107 Value *ExtendedB = Builder.CreateZExt(B, ZextType); 2108 Value *Sum = Builder.CreateAdd(ExtendedA, ExtendedB); 2109 Value *AddOne = Builder.CreateAdd(Sum, ConstantInt::get(ZextType, 1)); 2110 Value *ShiftR = Builder.CreateLShr(AddOne, ConstantInt::get(ZextType, 1)); 2111 Rep = Builder.CreateTrunc(ShiftR, A->getType()); 2112 if (CI->getNumArgOperands() > 2) { 2113 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 2114 CI->getArgOperand(2)); 2115 } 2116 } else if (IsNVVM && (Name == "abs.i" || Name == "abs.ll")) { 2117 Value *Arg = CI->getArgOperand(0); 2118 Value *Neg = Builder.CreateNeg(Arg, "neg"); 2119 Value *Cmp = Builder.CreateICmpSGE( 2120 Arg, llvm::Constant::getNullValue(Arg->getType()), "abs.cond"); 2121 Rep = Builder.CreateSelect(Cmp, Arg, Neg, "abs"); 2122 } else if (IsNVVM && (Name == "max.i" || Name == "max.ll" || 2123 Name == "max.ui" || Name == "max.ull")) { 2124 Value *Arg0 = CI->getArgOperand(0); 2125 Value *Arg1 = CI->getArgOperand(1); 2126 Value *Cmp = Name.endswith(".ui") || Name.endswith(".ull") 2127 ? Builder.CreateICmpUGE(Arg0, Arg1, "max.cond") 2128 : Builder.CreateICmpSGE(Arg0, Arg1, "max.cond"); 2129 Rep = Builder.CreateSelect(Cmp, Arg0, Arg1, "max"); 2130 } else if (IsNVVM && (Name == "min.i" || Name == "min.ll" || 2131 Name == "min.ui" || Name == "min.ull")) { 2132 Value *Arg0 = CI->getArgOperand(0); 2133 Value *Arg1 = CI->getArgOperand(1); 2134 Value *Cmp = Name.endswith(".ui") || Name.endswith(".ull") 2135 ? Builder.CreateICmpULE(Arg0, Arg1, "min.cond") 2136 : Builder.CreateICmpSLE(Arg0, Arg1, "min.cond"); 2137 Rep = Builder.CreateSelect(Cmp, Arg0, Arg1, "min"); 2138 } else if (IsNVVM && Name == "clz.ll") { 2139 // llvm.nvvm.clz.ll returns an i32, but llvm.ctlz.i64 and returns an i64. 2140 Value *Arg = CI->getArgOperand(0); 2141 Value *Ctlz = Builder.CreateCall( 2142 Intrinsic::getDeclaration(F->getParent(), Intrinsic::ctlz, 2143 {Arg->getType()}), 2144 {Arg, Builder.getFalse()}, "ctlz"); 2145 Rep = Builder.CreateTrunc(Ctlz, Builder.getInt32Ty(), "ctlz.trunc"); 2146 } else if (IsNVVM && Name == "popc.ll") { 2147 // llvm.nvvm.popc.ll returns an i32, but llvm.ctpop.i64 and returns an 2148 // i64. 2149 Value *Arg = CI->getArgOperand(0); 2150 Value *Popc = Builder.CreateCall( 2151 Intrinsic::getDeclaration(F->getParent(), Intrinsic::ctpop, 2152 {Arg->getType()}), 2153 Arg, "ctpop"); 2154 Rep = Builder.CreateTrunc(Popc, Builder.getInt32Ty(), "ctpop.trunc"); 2155 } else if (IsNVVM && Name == "h2f") { 2156 Rep = Builder.CreateCall(Intrinsic::getDeclaration( 2157 F->getParent(), Intrinsic::convert_from_fp16, 2158 {Builder.getFloatTy()}), 2159 CI->getArgOperand(0), "h2f"); 2160 } else { 2161 llvm_unreachable("Unknown function for CallInst upgrade."); 2162 } 2163 2164 if (Rep) 2165 CI->replaceAllUsesWith(Rep); 2166 CI->eraseFromParent(); 2167 return; 2168 } 2169 2170 CallInst *NewCall = nullptr; 2171 switch (NewFn->getIntrinsicID()) { 2172 default: { 2173 // Handle generic mangling change, but nothing else 2174 assert( 2175 (CI->getCalledFunction()->getName() != NewFn->getName()) && 2176 "Unknown function for CallInst upgrade and isn't just a name change"); 2177 CI->setCalledFunction(NewFn); 2178 return; 2179 } 2180 2181 case Intrinsic::arm_neon_vld1: 2182 case Intrinsic::arm_neon_vld2: 2183 case Intrinsic::arm_neon_vld3: 2184 case Intrinsic::arm_neon_vld4: 2185 case Intrinsic::arm_neon_vld2lane: 2186 case Intrinsic::arm_neon_vld3lane: 2187 case Intrinsic::arm_neon_vld4lane: 2188 case Intrinsic::arm_neon_vst1: 2189 case Intrinsic::arm_neon_vst2: 2190 case Intrinsic::arm_neon_vst3: 2191 case Intrinsic::arm_neon_vst4: 2192 case Intrinsic::arm_neon_vst2lane: 2193 case Intrinsic::arm_neon_vst3lane: 2194 case Intrinsic::arm_neon_vst4lane: { 2195 SmallVector<Value *, 4> Args(CI->arg_operands().begin(), 2196 CI->arg_operands().end()); 2197 NewCall = Builder.CreateCall(NewFn, Args); 2198 break; 2199 } 2200 2201 case Intrinsic::bitreverse: 2202 NewCall = Builder.CreateCall(NewFn, {CI->getArgOperand(0)}); 2203 break; 2204 2205 case Intrinsic::ctlz: 2206 case Intrinsic::cttz: 2207 assert(CI->getNumArgOperands() == 1 && 2208 "Mismatch between function args and call args"); 2209 NewCall = 2210 Builder.CreateCall(NewFn, {CI->getArgOperand(0), Builder.getFalse()}); 2211 break; 2212 2213 case Intrinsic::objectsize: { 2214 Value *NullIsUnknownSize = CI->getNumArgOperands() == 2 2215 ? Builder.getFalse() 2216 : CI->getArgOperand(2); 2217 NewCall = Builder.CreateCall( 2218 NewFn, {CI->getArgOperand(0), CI->getArgOperand(1), NullIsUnknownSize}); 2219 break; 2220 } 2221 2222 case Intrinsic::ctpop: 2223 NewCall = Builder.CreateCall(NewFn, {CI->getArgOperand(0)}); 2224 break; 2225 2226 case Intrinsic::convert_from_fp16: 2227 NewCall = Builder.CreateCall(NewFn, {CI->getArgOperand(0)}); 2228 break; 2229 2230 case Intrinsic::dbg_value: 2231 // Upgrade from the old version that had an extra offset argument. 2232 assert(CI->getNumArgOperands() == 4); 2233 // Drop nonzero offsets instead of attempting to upgrade them. 2234 if (auto *Offset = dyn_cast_or_null<Constant>(CI->getArgOperand(1))) 2235 if (Offset->isZeroValue()) { 2236 NewCall = Builder.CreateCall( 2237 NewFn, 2238 {CI->getArgOperand(0), CI->getArgOperand(2), CI->getArgOperand(3)}); 2239 break; 2240 } 2241 CI->eraseFromParent(); 2242 return; 2243 2244 case Intrinsic::x86_xop_vfrcz_ss: 2245 case Intrinsic::x86_xop_vfrcz_sd: 2246 NewCall = Builder.CreateCall(NewFn, {CI->getArgOperand(1)}); 2247 break; 2248 2249 case Intrinsic::x86_xop_vpermil2pd: 2250 case Intrinsic::x86_xop_vpermil2ps: 2251 case Intrinsic::x86_xop_vpermil2pd_256: 2252 case Intrinsic::x86_xop_vpermil2ps_256: { 2253 SmallVector<Value *, 4> Args(CI->arg_operands().begin(), 2254 CI->arg_operands().end()); 2255 VectorType *FltIdxTy = cast<VectorType>(Args[2]->getType()); 2256 VectorType *IntIdxTy = VectorType::getInteger(FltIdxTy); 2257 Args[2] = Builder.CreateBitCast(Args[2], IntIdxTy); 2258 NewCall = Builder.CreateCall(NewFn, Args); 2259 break; 2260 } 2261 2262 case Intrinsic::x86_sse41_ptestc: 2263 case Intrinsic::x86_sse41_ptestz: 2264 case Intrinsic::x86_sse41_ptestnzc: { 2265 // The arguments for these intrinsics used to be v4f32, and changed 2266 // to v2i64. This is purely a nop, since those are bitwise intrinsics. 2267 // So, the only thing required is a bitcast for both arguments. 2268 // First, check the arguments have the old type. 2269 Value *Arg0 = CI->getArgOperand(0); 2270 if (Arg0->getType() != VectorType::get(Type::getFloatTy(C), 4)) 2271 return; 2272 2273 // Old intrinsic, add bitcasts 2274 Value *Arg1 = CI->getArgOperand(1); 2275 2276 Type *NewVecTy = VectorType::get(Type::getInt64Ty(C), 2); 2277 2278 Value *BC0 = Builder.CreateBitCast(Arg0, NewVecTy, "cast"); 2279 Value *BC1 = Builder.CreateBitCast(Arg1, NewVecTy, "cast"); 2280 2281 NewCall = Builder.CreateCall(NewFn, {BC0, BC1}); 2282 break; 2283 } 2284 2285 case Intrinsic::x86_sse41_insertps: 2286 case Intrinsic::x86_sse41_dppd: 2287 case Intrinsic::x86_sse41_dpps: 2288 case Intrinsic::x86_sse41_mpsadbw: 2289 case Intrinsic::x86_avx_dp_ps_256: 2290 case Intrinsic::x86_avx2_mpsadbw: { 2291 // Need to truncate the last argument from i32 to i8 -- this argument models 2292 // an inherently 8-bit immediate operand to these x86 instructions. 2293 SmallVector<Value *, 4> Args(CI->arg_operands().begin(), 2294 CI->arg_operands().end()); 2295 2296 // Replace the last argument with a trunc. 2297 Args.back() = Builder.CreateTrunc(Args.back(), Type::getInt8Ty(C), "trunc"); 2298 NewCall = Builder.CreateCall(NewFn, Args); 2299 break; 2300 } 2301 2302 case Intrinsic::thread_pointer: { 2303 NewCall = Builder.CreateCall(NewFn, {}); 2304 break; 2305 } 2306 2307 case Intrinsic::invariant_start: 2308 case Intrinsic::invariant_end: 2309 case Intrinsic::masked_load: 2310 case Intrinsic::masked_store: 2311 case Intrinsic::masked_gather: 2312 case Intrinsic::masked_scatter: { 2313 SmallVector<Value *, 4> Args(CI->arg_operands().begin(), 2314 CI->arg_operands().end()); 2315 NewCall = Builder.CreateCall(NewFn, Args); 2316 break; 2317 } 2318 } 2319 assert(NewCall && "Should have either set this variable or returned through " 2320 "the default case"); 2321 std::string Name = CI->getName(); 2322 if (!Name.empty()) { 2323 CI->setName(Name + ".old"); 2324 NewCall->setName(Name); 2325 } 2326 CI->replaceAllUsesWith(NewCall); 2327 CI->eraseFromParent(); 2328 } 2329 2330 void llvm::UpgradeCallsToIntrinsic(Function *F) { 2331 assert(F && "Illegal attempt to upgrade a non-existent intrinsic."); 2332 2333 // Check if this function should be upgraded and get the replacement function 2334 // if there is one. 2335 Function *NewFn; 2336 if (UpgradeIntrinsicFunction(F, NewFn)) { 2337 // Replace all users of the old function with the new function or new 2338 // instructions. This is not a range loop because the call is deleted. 2339 for (auto UI = F->user_begin(), UE = F->user_end(); UI != UE; ) 2340 if (CallInst *CI = dyn_cast<CallInst>(*UI++)) 2341 UpgradeIntrinsicCall(CI, NewFn); 2342 2343 // Remove old function, no longer used, from the module. 2344 F->eraseFromParent(); 2345 } 2346 } 2347 2348 MDNode *llvm::UpgradeTBAANode(MDNode &MD) { 2349 // Check if the tag uses struct-path aware TBAA format. 2350 if (isa<MDNode>(MD.getOperand(0)) && MD.getNumOperands() >= 3) 2351 return &MD; 2352 2353 auto &Context = MD.getContext(); 2354 if (MD.getNumOperands() == 3) { 2355 Metadata *Elts[] = {MD.getOperand(0), MD.getOperand(1)}; 2356 MDNode *ScalarType = MDNode::get(Context, Elts); 2357 // Create a MDNode <ScalarType, ScalarType, offset 0, const> 2358 Metadata *Elts2[] = {ScalarType, ScalarType, 2359 ConstantAsMetadata::get( 2360 Constant::getNullValue(Type::getInt64Ty(Context))), 2361 MD.getOperand(2)}; 2362 return MDNode::get(Context, Elts2); 2363 } 2364 // Create a MDNode <MD, MD, offset 0> 2365 Metadata *Elts[] = {&MD, &MD, ConstantAsMetadata::get(Constant::getNullValue( 2366 Type::getInt64Ty(Context)))}; 2367 return MDNode::get(Context, Elts); 2368 } 2369 2370 Instruction *llvm::UpgradeBitCastInst(unsigned Opc, Value *V, Type *DestTy, 2371 Instruction *&Temp) { 2372 if (Opc != Instruction::BitCast) 2373 return nullptr; 2374 2375 Temp = nullptr; 2376 Type *SrcTy = V->getType(); 2377 if (SrcTy->isPtrOrPtrVectorTy() && DestTy->isPtrOrPtrVectorTy() && 2378 SrcTy->getPointerAddressSpace() != DestTy->getPointerAddressSpace()) { 2379 LLVMContext &Context = V->getContext(); 2380 2381 // We have no information about target data layout, so we assume that 2382 // the maximum pointer size is 64bit. 2383 Type *MidTy = Type::getInt64Ty(Context); 2384 Temp = CastInst::Create(Instruction::PtrToInt, V, MidTy); 2385 2386 return CastInst::Create(Instruction::IntToPtr, Temp, DestTy); 2387 } 2388 2389 return nullptr; 2390 } 2391 2392 Value *llvm::UpgradeBitCastExpr(unsigned Opc, Constant *C, Type *DestTy) { 2393 if (Opc != Instruction::BitCast) 2394 return nullptr; 2395 2396 Type *SrcTy = C->getType(); 2397 if (SrcTy->isPtrOrPtrVectorTy() && DestTy->isPtrOrPtrVectorTy() && 2398 SrcTy->getPointerAddressSpace() != DestTy->getPointerAddressSpace()) { 2399 LLVMContext &Context = C->getContext(); 2400 2401 // We have no information about target data layout, so we assume that 2402 // the maximum pointer size is 64bit. 2403 Type *MidTy = Type::getInt64Ty(Context); 2404 2405 return ConstantExpr::getIntToPtr(ConstantExpr::getPtrToInt(C, MidTy), 2406 DestTy); 2407 } 2408 2409 return nullptr; 2410 } 2411 2412 /// Check the debug info version number, if it is out-dated, drop the debug 2413 /// info. Return true if module is modified. 2414 bool llvm::UpgradeDebugInfo(Module &M) { 2415 unsigned Version = getDebugMetadataVersionFromModule(M); 2416 if (Version == DEBUG_METADATA_VERSION) { 2417 bool BrokenDebugInfo = false; 2418 if (verifyModule(M, &llvm::errs(), &BrokenDebugInfo)) 2419 report_fatal_error("Broken module found, compilation aborted!"); 2420 if (!BrokenDebugInfo) 2421 // Everything is ok. 2422 return false; 2423 else { 2424 // Diagnose malformed debug info. 2425 DiagnosticInfoIgnoringInvalidDebugMetadata Diag(M); 2426 M.getContext().diagnose(Diag); 2427 } 2428 } 2429 bool Modified = StripDebugInfo(M); 2430 if (Modified && Version != DEBUG_METADATA_VERSION) { 2431 // Diagnose a version mismatch. 2432 DiagnosticInfoDebugMetadataVersion DiagVersion(M, Version); 2433 M.getContext().diagnose(DiagVersion); 2434 } 2435 return Modified; 2436 } 2437 2438 bool llvm::UpgradeModuleFlags(Module &M) { 2439 NamedMDNode *ModFlags = M.getModuleFlagsMetadata(); 2440 if (!ModFlags) 2441 return false; 2442 2443 bool HasObjCFlag = false, HasClassProperties = false, Changed = false; 2444 for (unsigned I = 0, E = ModFlags->getNumOperands(); I != E; ++I) { 2445 MDNode *Op = ModFlags->getOperand(I); 2446 if (Op->getNumOperands() != 3) 2447 continue; 2448 MDString *ID = dyn_cast_or_null<MDString>(Op->getOperand(1)); 2449 if (!ID) 2450 continue; 2451 if (ID->getString() == "Objective-C Image Info Version") 2452 HasObjCFlag = true; 2453 if (ID->getString() == "Objective-C Class Properties") 2454 HasClassProperties = true; 2455 // Upgrade PIC/PIE Module Flags. The module flag behavior for these two 2456 // field was Error and now they are Max. 2457 if (ID->getString() == "PIC Level" || ID->getString() == "PIE Level") { 2458 if (auto *Behavior = 2459 mdconst::dyn_extract_or_null<ConstantInt>(Op->getOperand(0))) { 2460 if (Behavior->getLimitedValue() == Module::Error) { 2461 Type *Int32Ty = Type::getInt32Ty(M.getContext()); 2462 Metadata *Ops[3] = { 2463 ConstantAsMetadata::get(ConstantInt::get(Int32Ty, Module::Max)), 2464 MDString::get(M.getContext(), ID->getString()), 2465 Op->getOperand(2)}; 2466 ModFlags->setOperand(I, MDNode::get(M.getContext(), Ops)); 2467 Changed = true; 2468 } 2469 } 2470 } 2471 // Upgrade Objective-C Image Info Section. Removed the whitespce in the 2472 // section name so that llvm-lto will not complain about mismatching 2473 // module flags that is functionally the same. 2474 if (ID->getString() == "Objective-C Image Info Section") { 2475 if (auto *Value = dyn_cast_or_null<MDString>(Op->getOperand(2))) { 2476 SmallVector<StringRef, 4> ValueComp; 2477 Value->getString().split(ValueComp, " "); 2478 if (ValueComp.size() != 1) { 2479 std::string NewValue; 2480 for (auto &S : ValueComp) 2481 NewValue += S.str(); 2482 Metadata *Ops[3] = {Op->getOperand(0), Op->getOperand(1), 2483 MDString::get(M.getContext(), NewValue)}; 2484 ModFlags->setOperand(I, MDNode::get(M.getContext(), Ops)); 2485 Changed = true; 2486 } 2487 } 2488 } 2489 } 2490 2491 // "Objective-C Class Properties" is recently added for Objective-C. We 2492 // upgrade ObjC bitcodes to contain a "Objective-C Class Properties" module 2493 // flag of value 0, so we can correclty downgrade this flag when trying to 2494 // link an ObjC bitcode without this module flag with an ObjC bitcode with 2495 // this module flag. 2496 if (HasObjCFlag && !HasClassProperties) { 2497 M.addModuleFlag(llvm::Module::Override, "Objective-C Class Properties", 2498 (uint32_t)0); 2499 Changed = true; 2500 } 2501 2502 return Changed; 2503 } 2504 2505 void llvm::UpgradeSectionAttributes(Module &M) { 2506 auto TrimSpaces = [](StringRef Section) -> std::string { 2507 SmallVector<StringRef, 5> Components; 2508 Section.split(Components, ','); 2509 2510 SmallString<32> Buffer; 2511 raw_svector_ostream OS(Buffer); 2512 2513 for (auto Component : Components) 2514 OS << ',' << Component.trim(); 2515 2516 return OS.str().substr(1); 2517 }; 2518 2519 for (auto &GV : M.globals()) { 2520 if (!GV.hasSection()) 2521 continue; 2522 2523 StringRef Section = GV.getSection(); 2524 2525 if (!Section.startswith("__DATA, __objc_catlist")) 2526 continue; 2527 2528 // __DATA, __objc_catlist, regular, no_dead_strip 2529 // __DATA,__objc_catlist,regular,no_dead_strip 2530 GV.setSection(TrimSpaces(Section)); 2531 } 2532 } 2533 2534 static bool isOldLoopArgument(Metadata *MD) { 2535 auto *T = dyn_cast_or_null<MDTuple>(MD); 2536 if (!T) 2537 return false; 2538 if (T->getNumOperands() < 1) 2539 return false; 2540 auto *S = dyn_cast_or_null<MDString>(T->getOperand(0)); 2541 if (!S) 2542 return false; 2543 return S->getString().startswith("llvm.vectorizer."); 2544 } 2545 2546 static MDString *upgradeLoopTag(LLVMContext &C, StringRef OldTag) { 2547 StringRef OldPrefix = "llvm.vectorizer."; 2548 assert(OldTag.startswith(OldPrefix) && "Expected old prefix"); 2549 2550 if (OldTag == "llvm.vectorizer.unroll") 2551 return MDString::get(C, "llvm.loop.interleave.count"); 2552 2553 return MDString::get( 2554 C, (Twine("llvm.loop.vectorize.") + OldTag.drop_front(OldPrefix.size())) 2555 .str()); 2556 } 2557 2558 static Metadata *upgradeLoopArgument(Metadata *MD) { 2559 auto *T = dyn_cast_or_null<MDTuple>(MD); 2560 if (!T) 2561 return MD; 2562 if (T->getNumOperands() < 1) 2563 return MD; 2564 auto *OldTag = dyn_cast_or_null<MDString>(T->getOperand(0)); 2565 if (!OldTag) 2566 return MD; 2567 if (!OldTag->getString().startswith("llvm.vectorizer.")) 2568 return MD; 2569 2570 // This has an old tag. Upgrade it. 2571 SmallVector<Metadata *, 8> Ops; 2572 Ops.reserve(T->getNumOperands()); 2573 Ops.push_back(upgradeLoopTag(T->getContext(), OldTag->getString())); 2574 for (unsigned I = 1, E = T->getNumOperands(); I != E; ++I) 2575 Ops.push_back(T->getOperand(I)); 2576 2577 return MDTuple::get(T->getContext(), Ops); 2578 } 2579 2580 MDNode *llvm::upgradeInstructionLoopAttachment(MDNode &N) { 2581 auto *T = dyn_cast<MDTuple>(&N); 2582 if (!T) 2583 return &N; 2584 2585 if (none_of(T->operands(), isOldLoopArgument)) 2586 return &N; 2587 2588 SmallVector<Metadata *, 8> Ops; 2589 Ops.reserve(T->getNumOperands()); 2590 for (Metadata *MD : T->operands()) 2591 Ops.push_back(upgradeLoopArgument(MD)); 2592 2593 return MDTuple::get(T->getContext(), Ops); 2594 } 2595