1 //===-- AutoUpgrade.cpp - Implement auto-upgrade helper functions ---------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements the auto-upgrade helper functions. 11 // This is where deprecated IR intrinsics and other IR features are updated to 12 // current specifications. 13 // 14 //===----------------------------------------------------------------------===// 15 16 #include "llvm/IR/AutoUpgrade.h" 17 #include "llvm/ADT/StringSwitch.h" 18 #include "llvm/IR/CFG.h" 19 #include "llvm/IR/CallSite.h" 20 #include "llvm/IR/Constants.h" 21 #include "llvm/IR/DIBuilder.h" 22 #include "llvm/IR/DebugInfo.h" 23 #include "llvm/IR/DiagnosticInfo.h" 24 #include "llvm/IR/Function.h" 25 #include "llvm/IR/IRBuilder.h" 26 #include "llvm/IR/Instruction.h" 27 #include "llvm/IR/IntrinsicInst.h" 28 #include "llvm/IR/LLVMContext.h" 29 #include "llvm/IR/Module.h" 30 #include "llvm/Support/ErrorHandling.h" 31 #include "llvm/Support/Regex.h" 32 #include <cstring> 33 using namespace llvm; 34 35 static void rename(GlobalValue *GV) { GV->setName(GV->getName() + ".old"); } 36 37 // Upgrade the declarations of the SSE4.1 ptest intrinsics whose arguments have 38 // changed their type from v4f32 to v2i64. 39 static bool UpgradePTESTIntrinsic(Function* F, Intrinsic::ID IID, 40 Function *&NewFn) { 41 // Check whether this is an old version of the function, which received 42 // v4f32 arguments. 43 Type *Arg0Type = F->getFunctionType()->getParamType(0); 44 if (Arg0Type != VectorType::get(Type::getFloatTy(F->getContext()), 4)) 45 return false; 46 47 // Yes, it's old, replace it with new version. 48 rename(F); 49 NewFn = Intrinsic::getDeclaration(F->getParent(), IID); 50 return true; 51 } 52 53 // Upgrade the declarations of intrinsic functions whose 8-bit immediate mask 54 // arguments have changed their type from i32 to i8. 55 static bool UpgradeX86IntrinsicsWith8BitMask(Function *F, Intrinsic::ID IID, 56 Function *&NewFn) { 57 // Check that the last argument is an i32. 58 Type *LastArgType = F->getFunctionType()->getParamType( 59 F->getFunctionType()->getNumParams() - 1); 60 if (!LastArgType->isIntegerTy(32)) 61 return false; 62 63 // Move this function aside and map down. 64 rename(F); 65 NewFn = Intrinsic::getDeclaration(F->getParent(), IID); 66 return true; 67 } 68 69 static bool ShouldUpgradeX86Intrinsic(Function *F, StringRef Name) { 70 // All of the intrinsics matches below should be marked with which llvm 71 // version started autoupgrading them. At some point in the future we would 72 // like to use this information to remove upgrade code for some older 73 // intrinsics. It is currently undecided how we will determine that future 74 // point. 75 if (Name.startswith("sse2.pcmpeq.") || // Added in 3.1 76 Name.startswith("sse2.pcmpgt.") || // Added in 3.1 77 Name.startswith("avx2.pcmpeq.") || // Added in 3.1 78 Name.startswith("avx2.pcmpgt.") || // Added in 3.1 79 Name.startswith("avx512.mask.pcmpeq.") || // Added in 3.9 80 Name.startswith("avx512.mask.pcmpgt.") || // Added in 3.9 81 Name == "sse.add.ss" || // Added in 4.0 82 Name == "sse2.add.sd" || // Added in 4.0 83 Name == "sse.sub.ss" || // Added in 4.0 84 Name == "sse2.sub.sd" || // Added in 4.0 85 Name == "sse.mul.ss" || // Added in 4.0 86 Name == "sse2.mul.sd" || // Added in 4.0 87 Name == "sse.div.ss" || // Added in 4.0 88 Name == "sse2.div.sd" || // Added in 4.0 89 Name == "sse41.pmaxsb" || // Added in 3.9 90 Name == "sse2.pmaxs.w" || // Added in 3.9 91 Name == "sse41.pmaxsd" || // Added in 3.9 92 Name == "sse2.pmaxu.b" || // Added in 3.9 93 Name == "sse41.pmaxuw" || // Added in 3.9 94 Name == "sse41.pmaxud" || // Added in 3.9 95 Name == "sse41.pminsb" || // Added in 3.9 96 Name == "sse2.pmins.w" || // Added in 3.9 97 Name == "sse41.pminsd" || // Added in 3.9 98 Name == "sse2.pminu.b" || // Added in 3.9 99 Name == "sse41.pminuw" || // Added in 3.9 100 Name == "sse41.pminud" || // Added in 3.9 101 Name.startswith("avx512.mask.pshuf.b.") || // Added in 4.0 102 Name.startswith("avx2.pmax") || // Added in 3.9 103 Name.startswith("avx2.pmin") || // Added in 3.9 104 Name.startswith("avx512.mask.pmax") || // Added in 4.0 105 Name.startswith("avx512.mask.pmin") || // Added in 4.0 106 Name.startswith("avx2.vbroadcast") || // Added in 3.8 107 Name.startswith("avx2.pbroadcast") || // Added in 3.8 108 Name.startswith("avx.vpermil.") || // Added in 3.1 109 Name.startswith("sse2.pshuf") || // Added in 3.9 110 Name.startswith("avx512.pbroadcast") || // Added in 3.9 111 Name.startswith("avx512.mask.broadcast.s") || // Added in 3.9 112 Name.startswith("avx512.mask.movddup") || // Added in 3.9 113 Name.startswith("avx512.mask.movshdup") || // Added in 3.9 114 Name.startswith("avx512.mask.movsldup") || // Added in 3.9 115 Name.startswith("avx512.mask.pshuf.d.") || // Added in 3.9 116 Name.startswith("avx512.mask.pshufl.w.") || // Added in 3.9 117 Name.startswith("avx512.mask.pshufh.w.") || // Added in 3.9 118 Name.startswith("avx512.mask.shuf.p") || // Added in 4.0 119 Name.startswith("avx512.mask.vpermil.p") || // Added in 3.9 120 Name.startswith("avx512.mask.perm.df.") || // Added in 3.9 121 Name.startswith("avx512.mask.perm.di.") || // Added in 3.9 122 Name.startswith("avx512.mask.punpckl") || // Added in 3.9 123 Name.startswith("avx512.mask.punpckh") || // Added in 3.9 124 Name.startswith("avx512.mask.unpckl.") || // Added in 3.9 125 Name.startswith("avx512.mask.unpckh.") || // Added in 3.9 126 Name.startswith("avx512.mask.pand.") || // Added in 3.9 127 Name.startswith("avx512.mask.pandn.") || // Added in 3.9 128 Name.startswith("avx512.mask.por.") || // Added in 3.9 129 Name.startswith("avx512.mask.pxor.") || // Added in 3.9 130 Name.startswith("avx512.mask.and.") || // Added in 3.9 131 Name.startswith("avx512.mask.andn.") || // Added in 3.9 132 Name.startswith("avx512.mask.or.") || // Added in 3.9 133 Name.startswith("avx512.mask.xor.") || // Added in 3.9 134 Name.startswith("avx512.mask.padd.") || // Added in 4.0 135 Name.startswith("avx512.mask.psub.") || // Added in 4.0 136 Name.startswith("avx512.mask.pmull.") || // Added in 4.0 137 Name.startswith("avx512.mask.cvtdq2pd.") || // Added in 4.0 138 Name.startswith("avx512.mask.cvtudq2pd.") || // Added in 4.0 139 Name.startswith("avx512.mask.pmul.dq.") || // Added in 4.0 140 Name.startswith("avx512.mask.pmulu.dq.") || // Added in 4.0 141 Name.startswith("avx512.mask.packsswb.") || // Added in 5.0 142 Name.startswith("avx512.mask.packssdw.") || // Added in 5.0 143 Name.startswith("avx512.mask.packuswb.") || // Added in 5.0 144 Name.startswith("avx512.mask.packusdw.") || // Added in 5.0 145 Name == "avx512.mask.add.pd.128" || // Added in 4.0 146 Name == "avx512.mask.add.pd.256" || // Added in 4.0 147 Name == "avx512.mask.add.ps.128" || // Added in 4.0 148 Name == "avx512.mask.add.ps.256" || // Added in 4.0 149 Name == "avx512.mask.div.pd.128" || // Added in 4.0 150 Name == "avx512.mask.div.pd.256" || // Added in 4.0 151 Name == "avx512.mask.div.ps.128" || // Added in 4.0 152 Name == "avx512.mask.div.ps.256" || // Added in 4.0 153 Name == "avx512.mask.mul.pd.128" || // Added in 4.0 154 Name == "avx512.mask.mul.pd.256" || // Added in 4.0 155 Name == "avx512.mask.mul.ps.128" || // Added in 4.0 156 Name == "avx512.mask.mul.ps.256" || // Added in 4.0 157 Name == "avx512.mask.sub.pd.128" || // Added in 4.0 158 Name == "avx512.mask.sub.pd.256" || // Added in 4.0 159 Name == "avx512.mask.sub.ps.128" || // Added in 4.0 160 Name == "avx512.mask.sub.ps.256" || // Added in 4.0 161 Name == "avx512.mask.max.pd.128" || // Added in 5.0 162 Name == "avx512.mask.max.pd.256" || // Added in 5.0 163 Name == "avx512.mask.max.ps.128" || // Added in 5.0 164 Name == "avx512.mask.max.ps.256" || // Added in 5.0 165 Name == "avx512.mask.min.pd.128" || // Added in 5.0 166 Name == "avx512.mask.min.pd.256" || // Added in 5.0 167 Name == "avx512.mask.min.ps.128" || // Added in 5.0 168 Name == "avx512.mask.min.ps.256" || // Added in 5.0 169 Name.startswith("avx512.mask.vpermilvar.") || // Added in 4.0 170 Name.startswith("avx512.mask.psll.d") || // Added in 4.0 171 Name.startswith("avx512.mask.psll.q") || // Added in 4.0 172 Name.startswith("avx512.mask.psll.w") || // Added in 4.0 173 Name.startswith("avx512.mask.psra.d") || // Added in 4.0 174 Name.startswith("avx512.mask.psra.q") || // Added in 4.0 175 Name.startswith("avx512.mask.psra.w") || // Added in 4.0 176 Name.startswith("avx512.mask.psrl.d") || // Added in 4.0 177 Name.startswith("avx512.mask.psrl.q") || // Added in 4.0 178 Name.startswith("avx512.mask.psrl.w") || // Added in 4.0 179 Name.startswith("avx512.mask.pslli") || // Added in 4.0 180 Name.startswith("avx512.mask.psrai") || // Added in 4.0 181 Name.startswith("avx512.mask.psrli") || // Added in 4.0 182 Name.startswith("avx512.mask.psllv") || // Added in 4.0 183 Name.startswith("avx512.mask.psrav") || // Added in 4.0 184 Name.startswith("avx512.mask.psrlv") || // Added in 4.0 185 Name.startswith("sse41.pmovsx") || // Added in 3.8 186 Name.startswith("sse41.pmovzx") || // Added in 3.9 187 Name.startswith("avx2.pmovsx") || // Added in 3.9 188 Name.startswith("avx2.pmovzx") || // Added in 3.9 189 Name.startswith("avx512.mask.pmovsx") || // Added in 4.0 190 Name.startswith("avx512.mask.pmovzx") || // Added in 4.0 191 Name.startswith("avx512.mask.lzcnt.") || // Added in 5.0 192 Name == "sse2.cvtdq2pd" || // Added in 3.9 193 Name == "sse2.cvtps2pd" || // Added in 3.9 194 Name == "avx.cvtdq2.pd.256" || // Added in 3.9 195 Name == "avx.cvt.ps2.pd.256" || // Added in 3.9 196 Name.startswith("avx.vinsertf128.") || // Added in 3.7 197 Name == "avx2.vinserti128" || // Added in 3.7 198 Name.startswith("avx512.mask.insert") || // Added in 4.0 199 Name.startswith("avx.vextractf128.") || // Added in 3.7 200 Name == "avx2.vextracti128" || // Added in 3.7 201 Name.startswith("avx512.mask.vextract") || // Added in 4.0 202 Name.startswith("sse4a.movnt.") || // Added in 3.9 203 Name.startswith("avx.movnt.") || // Added in 3.2 204 Name.startswith("avx512.storent.") || // Added in 3.9 205 Name == "sse2.storel.dq" || // Added in 3.9 206 Name.startswith("sse.storeu.") || // Added in 3.9 207 Name.startswith("sse2.storeu.") || // Added in 3.9 208 Name.startswith("avx.storeu.") || // Added in 3.9 209 Name.startswith("avx512.mask.storeu.") || // Added in 3.9 210 Name.startswith("avx512.mask.store.p") || // Added in 3.9 211 Name.startswith("avx512.mask.store.b.") || // Added in 3.9 212 Name.startswith("avx512.mask.store.w.") || // Added in 3.9 213 Name.startswith("avx512.mask.store.d.") || // Added in 3.9 214 Name.startswith("avx512.mask.store.q.") || // Added in 3.9 215 Name.startswith("avx512.mask.loadu.") || // Added in 3.9 216 Name.startswith("avx512.mask.load.") || // Added in 3.9 217 Name == "sse42.crc32.64.8" || // Added in 3.4 218 Name.startswith("avx.vbroadcast.s") || // Added in 3.5 219 Name.startswith("avx512.mask.palignr.") || // Added in 3.9 220 Name.startswith("avx512.mask.valign.") || // Added in 4.0 221 Name.startswith("sse2.psll.dq") || // Added in 3.7 222 Name.startswith("sse2.psrl.dq") || // Added in 3.7 223 Name.startswith("avx2.psll.dq") || // Added in 3.7 224 Name.startswith("avx2.psrl.dq") || // Added in 3.7 225 Name.startswith("avx512.psll.dq") || // Added in 3.9 226 Name.startswith("avx512.psrl.dq") || // Added in 3.9 227 Name == "sse41.pblendw" || // Added in 3.7 228 Name.startswith("sse41.blendp") || // Added in 3.7 229 Name.startswith("avx.blend.p") || // Added in 3.7 230 Name == "avx2.pblendw" || // Added in 3.7 231 Name.startswith("avx2.pblendd.") || // Added in 3.7 232 Name.startswith("avx.vbroadcastf128") || // Added in 4.0 233 Name == "avx2.vbroadcasti128" || // Added in 3.7 234 Name == "xop.vpcmov" || // Added in 3.8 235 Name == "xop.vpcmov.256" || // Added in 5.0 236 Name.startswith("avx512.mask.move.s") || // Added in 4.0 237 (Name.startswith("xop.vpcom") && // Added in 3.2 238 F->arg_size() == 2)) 239 return true; 240 241 return false; 242 } 243 244 static bool UpgradeX86IntrinsicFunction(Function *F, StringRef Name, 245 Function *&NewFn) { 246 // Only handle intrinsics that start with "x86.". 247 if (!Name.startswith("x86.")) 248 return false; 249 // Remove "x86." prefix. 250 Name = Name.substr(4); 251 252 if (ShouldUpgradeX86Intrinsic(F, Name)) { 253 NewFn = nullptr; 254 return true; 255 } 256 257 // SSE4.1 ptest functions may have an old signature. 258 if (Name.startswith("sse41.ptest")) { // Added in 3.2 259 if (Name.substr(11) == "c") 260 return UpgradePTESTIntrinsic(F, Intrinsic::x86_sse41_ptestc, NewFn); 261 if (Name.substr(11) == "z") 262 return UpgradePTESTIntrinsic(F, Intrinsic::x86_sse41_ptestz, NewFn); 263 if (Name.substr(11) == "nzc") 264 return UpgradePTESTIntrinsic(F, Intrinsic::x86_sse41_ptestnzc, NewFn); 265 } 266 // Several blend and other instructions with masks used the wrong number of 267 // bits. 268 if (Name == "sse41.insertps") // Added in 3.6 269 return UpgradeX86IntrinsicsWith8BitMask(F, Intrinsic::x86_sse41_insertps, 270 NewFn); 271 if (Name == "sse41.dppd") // Added in 3.6 272 return UpgradeX86IntrinsicsWith8BitMask(F, Intrinsic::x86_sse41_dppd, 273 NewFn); 274 if (Name == "sse41.dpps") // Added in 3.6 275 return UpgradeX86IntrinsicsWith8BitMask(F, Intrinsic::x86_sse41_dpps, 276 NewFn); 277 if (Name == "sse41.mpsadbw") // Added in 3.6 278 return UpgradeX86IntrinsicsWith8BitMask(F, Intrinsic::x86_sse41_mpsadbw, 279 NewFn); 280 if (Name == "avx.dp.ps.256") // Added in 3.6 281 return UpgradeX86IntrinsicsWith8BitMask(F, Intrinsic::x86_avx_dp_ps_256, 282 NewFn); 283 if (Name == "avx2.mpsadbw") // Added in 3.6 284 return UpgradeX86IntrinsicsWith8BitMask(F, Intrinsic::x86_avx2_mpsadbw, 285 NewFn); 286 287 // frcz.ss/sd may need to have an argument dropped. Added in 3.2 288 if (Name.startswith("xop.vfrcz.ss") && F->arg_size() == 2) { 289 rename(F); 290 NewFn = Intrinsic::getDeclaration(F->getParent(), 291 Intrinsic::x86_xop_vfrcz_ss); 292 return true; 293 } 294 if (Name.startswith("xop.vfrcz.sd") && F->arg_size() == 2) { 295 rename(F); 296 NewFn = Intrinsic::getDeclaration(F->getParent(), 297 Intrinsic::x86_xop_vfrcz_sd); 298 return true; 299 } 300 // Upgrade any XOP PERMIL2 index operand still using a float/double vector. 301 if (Name.startswith("xop.vpermil2")) { // Added in 3.9 302 auto Idx = F->getFunctionType()->getParamType(2); 303 if (Idx->isFPOrFPVectorTy()) { 304 rename(F); 305 unsigned IdxSize = Idx->getPrimitiveSizeInBits(); 306 unsigned EltSize = Idx->getScalarSizeInBits(); 307 Intrinsic::ID Permil2ID; 308 if (EltSize == 64 && IdxSize == 128) 309 Permil2ID = Intrinsic::x86_xop_vpermil2pd; 310 else if (EltSize == 32 && IdxSize == 128) 311 Permil2ID = Intrinsic::x86_xop_vpermil2ps; 312 else if (EltSize == 64 && IdxSize == 256) 313 Permil2ID = Intrinsic::x86_xop_vpermil2pd_256; 314 else 315 Permil2ID = Intrinsic::x86_xop_vpermil2ps_256; 316 NewFn = Intrinsic::getDeclaration(F->getParent(), Permil2ID); 317 return true; 318 } 319 } 320 321 return false; 322 } 323 324 static bool UpgradeIntrinsicFunction1(Function *F, Function *&NewFn) { 325 assert(F && "Illegal to upgrade a non-existent Function."); 326 327 // Quickly eliminate it, if it's not a candidate. 328 StringRef Name = F->getName(); 329 if (Name.size() <= 8 || !Name.startswith("llvm.")) 330 return false; 331 Name = Name.substr(5); // Strip off "llvm." 332 333 switch (Name[0]) { 334 default: break; 335 case 'a': { 336 if (Name.startswith("arm.rbit") || Name.startswith("aarch64.rbit")) { 337 NewFn = Intrinsic::getDeclaration(F->getParent(), Intrinsic::bitreverse, 338 F->arg_begin()->getType()); 339 return true; 340 } 341 if (Name.startswith("arm.neon.vclz")) { 342 Type* args[2] = { 343 F->arg_begin()->getType(), 344 Type::getInt1Ty(F->getContext()) 345 }; 346 // Can't use Intrinsic::getDeclaration here as it adds a ".i1" to 347 // the end of the name. Change name from llvm.arm.neon.vclz.* to 348 // llvm.ctlz.* 349 FunctionType* fType = FunctionType::get(F->getReturnType(), args, false); 350 NewFn = Function::Create(fType, F->getLinkage(), 351 "llvm.ctlz." + Name.substr(14), F->getParent()); 352 return true; 353 } 354 if (Name.startswith("arm.neon.vcnt")) { 355 NewFn = Intrinsic::getDeclaration(F->getParent(), Intrinsic::ctpop, 356 F->arg_begin()->getType()); 357 return true; 358 } 359 Regex vldRegex("^arm\\.neon\\.vld([1234]|[234]lane)\\.v[a-z0-9]*$"); 360 if (vldRegex.match(Name)) { 361 auto fArgs = F->getFunctionType()->params(); 362 SmallVector<Type *, 4> Tys(fArgs.begin(), fArgs.end()); 363 // Can't use Intrinsic::getDeclaration here as the return types might 364 // then only be structurally equal. 365 FunctionType* fType = FunctionType::get(F->getReturnType(), Tys, false); 366 NewFn = Function::Create(fType, F->getLinkage(), 367 "llvm." + Name + ".p0i8", F->getParent()); 368 return true; 369 } 370 Regex vstRegex("^arm\\.neon\\.vst([1234]|[234]lane)\\.v[a-z0-9]*$"); 371 if (vstRegex.match(Name)) { 372 static const Intrinsic::ID StoreInts[] = {Intrinsic::arm_neon_vst1, 373 Intrinsic::arm_neon_vst2, 374 Intrinsic::arm_neon_vst3, 375 Intrinsic::arm_neon_vst4}; 376 377 static const Intrinsic::ID StoreLaneInts[] = { 378 Intrinsic::arm_neon_vst2lane, Intrinsic::arm_neon_vst3lane, 379 Intrinsic::arm_neon_vst4lane 380 }; 381 382 auto fArgs = F->getFunctionType()->params(); 383 Type *Tys[] = {fArgs[0], fArgs[1]}; 384 if (Name.find("lane") == StringRef::npos) 385 NewFn = Intrinsic::getDeclaration(F->getParent(), 386 StoreInts[fArgs.size() - 3], Tys); 387 else 388 NewFn = Intrinsic::getDeclaration(F->getParent(), 389 StoreLaneInts[fArgs.size() - 5], Tys); 390 return true; 391 } 392 if (Name == "aarch64.thread.pointer" || Name == "arm.thread.pointer") { 393 NewFn = Intrinsic::getDeclaration(F->getParent(), Intrinsic::thread_pointer); 394 return true; 395 } 396 break; 397 } 398 399 case 'c': { 400 if (Name.startswith("ctlz.") && F->arg_size() == 1) { 401 rename(F); 402 NewFn = Intrinsic::getDeclaration(F->getParent(), Intrinsic::ctlz, 403 F->arg_begin()->getType()); 404 return true; 405 } 406 if (Name.startswith("cttz.") && F->arg_size() == 1) { 407 rename(F); 408 NewFn = Intrinsic::getDeclaration(F->getParent(), Intrinsic::cttz, 409 F->arg_begin()->getType()); 410 return true; 411 } 412 break; 413 } 414 case 'i': { 415 if (Name.startswith("invariant.start")) { 416 auto Args = F->getFunctionType()->params(); 417 Type* ObjectPtr[1] = {Args[1]}; 418 if (F->getName() != 419 Intrinsic::getName(Intrinsic::invariant_start, ObjectPtr)) { 420 rename(F); 421 NewFn = Intrinsic::getDeclaration( 422 F->getParent(), Intrinsic::invariant_start, ObjectPtr); 423 return true; 424 } 425 } 426 if (Name.startswith("invariant.end")) { 427 auto Args = F->getFunctionType()->params(); 428 Type* ObjectPtr[1] = {Args[2]}; 429 if (F->getName() != 430 Intrinsic::getName(Intrinsic::invariant_end, ObjectPtr)) { 431 rename(F); 432 NewFn = Intrinsic::getDeclaration(F->getParent(), 433 Intrinsic::invariant_end, ObjectPtr); 434 return true; 435 } 436 } 437 break; 438 } 439 case 'm': { 440 if (Name.startswith("masked.load.")) { 441 Type *Tys[] = { F->getReturnType(), F->arg_begin()->getType() }; 442 if (F->getName() != Intrinsic::getName(Intrinsic::masked_load, Tys)) { 443 rename(F); 444 NewFn = Intrinsic::getDeclaration(F->getParent(), 445 Intrinsic::masked_load, 446 Tys); 447 return true; 448 } 449 } 450 if (Name.startswith("masked.store.")) { 451 auto Args = F->getFunctionType()->params(); 452 Type *Tys[] = { Args[0], Args[1] }; 453 if (F->getName() != Intrinsic::getName(Intrinsic::masked_store, Tys)) { 454 rename(F); 455 NewFn = Intrinsic::getDeclaration(F->getParent(), 456 Intrinsic::masked_store, 457 Tys); 458 return true; 459 } 460 } 461 break; 462 } 463 case 'n': { 464 if (Name.startswith("nvvm.")) { 465 Name = Name.substr(5); 466 467 // The following nvvm intrinsics correspond exactly to an LLVM intrinsic. 468 Intrinsic::ID IID = StringSwitch<Intrinsic::ID>(Name) 469 .Cases("brev32", "brev64", Intrinsic::bitreverse) 470 .Case("clz.i", Intrinsic::ctlz) 471 .Case("popc.i", Intrinsic::ctpop) 472 .Default(Intrinsic::not_intrinsic); 473 if (IID != Intrinsic::not_intrinsic && F->arg_size() == 1) { 474 NewFn = Intrinsic::getDeclaration(F->getParent(), IID, 475 {F->getReturnType()}); 476 return true; 477 } 478 479 // The following nvvm intrinsics correspond exactly to an LLVM idiom, but 480 // not to an intrinsic alone. We expand them in UpgradeIntrinsicCall. 481 // 482 // TODO: We could add lohi.i2d. 483 bool Expand = StringSwitch<bool>(Name) 484 .Cases("abs.i", "abs.ll", true) 485 .Cases("clz.ll", "popc.ll", "h2f", true) 486 .Cases("max.i", "max.ll", "max.ui", "max.ull", true) 487 .Cases("min.i", "min.ll", "min.ui", "min.ull", true) 488 .Default(false); 489 if (Expand) { 490 NewFn = nullptr; 491 return true; 492 } 493 } 494 } 495 case 'o': 496 // We only need to change the name to match the mangling including the 497 // address space. 498 if (Name.startswith("objectsize.")) { 499 Type *Tys[2] = { F->getReturnType(), F->arg_begin()->getType() }; 500 if (F->arg_size() == 2 || 501 F->getName() != Intrinsic::getName(Intrinsic::objectsize, Tys)) { 502 rename(F); 503 NewFn = Intrinsic::getDeclaration(F->getParent(), Intrinsic::objectsize, 504 Tys); 505 return true; 506 } 507 } 508 break; 509 510 case 's': 511 if (Name == "stackprotectorcheck") { 512 NewFn = nullptr; 513 return true; 514 } 515 break; 516 517 case 'x': 518 if (UpgradeX86IntrinsicFunction(F, Name, NewFn)) 519 return true; 520 } 521 // Remangle our intrinsic since we upgrade the mangling 522 auto Result = llvm::Intrinsic::remangleIntrinsicFunction(F); 523 if (Result != None) { 524 NewFn = Result.getValue(); 525 return true; 526 } 527 528 // This may not belong here. This function is effectively being overloaded 529 // to both detect an intrinsic which needs upgrading, and to provide the 530 // upgraded form of the intrinsic. We should perhaps have two separate 531 // functions for this. 532 return false; 533 } 534 535 bool llvm::UpgradeIntrinsicFunction(Function *F, Function *&NewFn) { 536 NewFn = nullptr; 537 bool Upgraded = UpgradeIntrinsicFunction1(F, NewFn); 538 assert(F != NewFn && "Intrinsic function upgraded to the same function"); 539 540 // Upgrade intrinsic attributes. This does not change the function. 541 if (NewFn) 542 F = NewFn; 543 if (Intrinsic::ID id = F->getIntrinsicID()) 544 F->setAttributes(Intrinsic::getAttributes(F->getContext(), id)); 545 return Upgraded; 546 } 547 548 bool llvm::UpgradeGlobalVariable(GlobalVariable *GV) { 549 // Nothing to do yet. 550 return false; 551 } 552 553 // Handles upgrading SSE2/AVX2/AVX512BW PSLLDQ intrinsics by converting them 554 // to byte shuffles. 555 static Value *UpgradeX86PSLLDQIntrinsics(IRBuilder<> &Builder, 556 Value *Op, unsigned Shift) { 557 Type *ResultTy = Op->getType(); 558 unsigned NumElts = ResultTy->getVectorNumElements() * 8; 559 560 // Bitcast from a 64-bit element type to a byte element type. 561 Type *VecTy = VectorType::get(Builder.getInt8Ty(), NumElts); 562 Op = Builder.CreateBitCast(Op, VecTy, "cast"); 563 564 // We'll be shuffling in zeroes. 565 Value *Res = Constant::getNullValue(VecTy); 566 567 // If shift is less than 16, emit a shuffle to move the bytes. Otherwise, 568 // we'll just return the zero vector. 569 if (Shift < 16) { 570 uint32_t Idxs[64]; 571 // 256/512-bit version is split into 2/4 16-byte lanes. 572 for (unsigned l = 0; l != NumElts; l += 16) 573 for (unsigned i = 0; i != 16; ++i) { 574 unsigned Idx = NumElts + i - Shift; 575 if (Idx < NumElts) 576 Idx -= NumElts - 16; // end of lane, switch operand. 577 Idxs[l + i] = Idx + l; 578 } 579 580 Res = Builder.CreateShuffleVector(Res, Op, makeArrayRef(Idxs, NumElts)); 581 } 582 583 // Bitcast back to a 64-bit element type. 584 return Builder.CreateBitCast(Res, ResultTy, "cast"); 585 } 586 587 // Handles upgrading SSE2/AVX2/AVX512BW PSRLDQ intrinsics by converting them 588 // to byte shuffles. 589 static Value *UpgradeX86PSRLDQIntrinsics(IRBuilder<> &Builder, Value *Op, 590 unsigned Shift) { 591 Type *ResultTy = Op->getType(); 592 unsigned NumElts = ResultTy->getVectorNumElements() * 8; 593 594 // Bitcast from a 64-bit element type to a byte element type. 595 Type *VecTy = VectorType::get(Builder.getInt8Ty(), NumElts); 596 Op = Builder.CreateBitCast(Op, VecTy, "cast"); 597 598 // We'll be shuffling in zeroes. 599 Value *Res = Constant::getNullValue(VecTy); 600 601 // If shift is less than 16, emit a shuffle to move the bytes. Otherwise, 602 // we'll just return the zero vector. 603 if (Shift < 16) { 604 uint32_t Idxs[64]; 605 // 256/512-bit version is split into 2/4 16-byte lanes. 606 for (unsigned l = 0; l != NumElts; l += 16) 607 for (unsigned i = 0; i != 16; ++i) { 608 unsigned Idx = i + Shift; 609 if (Idx >= 16) 610 Idx += NumElts - 16; // end of lane, switch operand. 611 Idxs[l + i] = Idx + l; 612 } 613 614 Res = Builder.CreateShuffleVector(Op, Res, makeArrayRef(Idxs, NumElts)); 615 } 616 617 // Bitcast back to a 64-bit element type. 618 return Builder.CreateBitCast(Res, ResultTy, "cast"); 619 } 620 621 static Value *getX86MaskVec(IRBuilder<> &Builder, Value *Mask, 622 unsigned NumElts) { 623 llvm::VectorType *MaskTy = llvm::VectorType::get(Builder.getInt1Ty(), 624 cast<IntegerType>(Mask->getType())->getBitWidth()); 625 Mask = Builder.CreateBitCast(Mask, MaskTy); 626 627 // If we have less than 8 elements, then the starting mask was an i8 and 628 // we need to extract down to the right number of elements. 629 if (NumElts < 8) { 630 uint32_t Indices[4]; 631 for (unsigned i = 0; i != NumElts; ++i) 632 Indices[i] = i; 633 Mask = Builder.CreateShuffleVector(Mask, Mask, 634 makeArrayRef(Indices, NumElts), 635 "extract"); 636 } 637 638 return Mask; 639 } 640 641 static Value *EmitX86Select(IRBuilder<> &Builder, Value *Mask, 642 Value *Op0, Value *Op1) { 643 // If the mask is all ones just emit the align operation. 644 if (const auto *C = dyn_cast<Constant>(Mask)) 645 if (C->isAllOnesValue()) 646 return Op0; 647 648 Mask = getX86MaskVec(Builder, Mask, Op0->getType()->getVectorNumElements()); 649 return Builder.CreateSelect(Mask, Op0, Op1); 650 } 651 652 // Handle autoupgrade for masked PALIGNR and VALIGND/Q intrinsics. 653 // PALIGNR handles large immediates by shifting while VALIGN masks the immediate 654 // so we need to handle both cases. VALIGN also doesn't have 128-bit lanes. 655 static Value *UpgradeX86ALIGNIntrinsics(IRBuilder<> &Builder, Value *Op0, 656 Value *Op1, Value *Shift, 657 Value *Passthru, Value *Mask, 658 bool IsVALIGN) { 659 unsigned ShiftVal = cast<llvm::ConstantInt>(Shift)->getZExtValue(); 660 661 unsigned NumElts = Op0->getType()->getVectorNumElements(); 662 assert((IsVALIGN || NumElts % 16 == 0) && "Illegal NumElts for PALIGNR!"); 663 assert((!IsVALIGN || NumElts <= 16) && "NumElts too large for VALIGN!"); 664 assert(isPowerOf2_32(NumElts) && "NumElts not a power of 2!"); 665 666 // Mask the immediate for VALIGN. 667 if (IsVALIGN) 668 ShiftVal &= (NumElts - 1); 669 670 // If palignr is shifting the pair of vectors more than the size of two 671 // lanes, emit zero. 672 if (ShiftVal >= 32) 673 return llvm::Constant::getNullValue(Op0->getType()); 674 675 // If palignr is shifting the pair of input vectors more than one lane, 676 // but less than two lanes, convert to shifting in zeroes. 677 if (ShiftVal > 16) { 678 ShiftVal -= 16; 679 Op1 = Op0; 680 Op0 = llvm::Constant::getNullValue(Op0->getType()); 681 } 682 683 uint32_t Indices[64]; 684 // 256-bit palignr operates on 128-bit lanes so we need to handle that 685 for (unsigned l = 0; l < NumElts; l += 16) { 686 for (unsigned i = 0; i != 16; ++i) { 687 unsigned Idx = ShiftVal + i; 688 if (!IsVALIGN && Idx >= 16) // Disable wrap for VALIGN. 689 Idx += NumElts - 16; // End of lane, switch operand. 690 Indices[l + i] = Idx + l; 691 } 692 } 693 694 Value *Align = Builder.CreateShuffleVector(Op1, Op0, 695 makeArrayRef(Indices, NumElts), 696 "palignr"); 697 698 return EmitX86Select(Builder, Mask, Align, Passthru); 699 } 700 701 static Value *UpgradeMaskedStore(IRBuilder<> &Builder, 702 Value *Ptr, Value *Data, Value *Mask, 703 bool Aligned) { 704 // Cast the pointer to the right type. 705 Ptr = Builder.CreateBitCast(Ptr, 706 llvm::PointerType::getUnqual(Data->getType())); 707 unsigned Align = 708 Aligned ? cast<VectorType>(Data->getType())->getBitWidth() / 8 : 1; 709 710 // If the mask is all ones just emit a regular store. 711 if (const auto *C = dyn_cast<Constant>(Mask)) 712 if (C->isAllOnesValue()) 713 return Builder.CreateAlignedStore(Data, Ptr, Align); 714 715 // Convert the mask from an integer type to a vector of i1. 716 unsigned NumElts = Data->getType()->getVectorNumElements(); 717 Mask = getX86MaskVec(Builder, Mask, NumElts); 718 return Builder.CreateMaskedStore(Data, Ptr, Align, Mask); 719 } 720 721 static Value *UpgradeMaskedLoad(IRBuilder<> &Builder, 722 Value *Ptr, Value *Passthru, Value *Mask, 723 bool Aligned) { 724 // Cast the pointer to the right type. 725 Ptr = Builder.CreateBitCast(Ptr, 726 llvm::PointerType::getUnqual(Passthru->getType())); 727 unsigned Align = 728 Aligned ? cast<VectorType>(Passthru->getType())->getBitWidth() / 8 : 1; 729 730 // If the mask is all ones just emit a regular store. 731 if (const auto *C = dyn_cast<Constant>(Mask)) 732 if (C->isAllOnesValue()) 733 return Builder.CreateAlignedLoad(Ptr, Align); 734 735 // Convert the mask from an integer type to a vector of i1. 736 unsigned NumElts = Passthru->getType()->getVectorNumElements(); 737 Mask = getX86MaskVec(Builder, Mask, NumElts); 738 return Builder.CreateMaskedLoad(Ptr, Align, Mask, Passthru); 739 } 740 741 static Value *upgradeIntMinMax(IRBuilder<> &Builder, CallInst &CI, 742 ICmpInst::Predicate Pred) { 743 Value *Op0 = CI.getArgOperand(0); 744 Value *Op1 = CI.getArgOperand(1); 745 Value *Cmp = Builder.CreateICmp(Pred, Op0, Op1); 746 Value *Res = Builder.CreateSelect(Cmp, Op0, Op1); 747 748 if (CI.getNumArgOperands() == 4) 749 Res = EmitX86Select(Builder, CI.getArgOperand(3), Res, CI.getArgOperand(2)); 750 751 return Res; 752 } 753 754 static Value *upgradeMaskedCompare(IRBuilder<> &Builder, CallInst &CI, 755 ICmpInst::Predicate Pred) { 756 Value *Op0 = CI.getArgOperand(0); 757 unsigned NumElts = Op0->getType()->getVectorNumElements(); 758 Value *Cmp = Builder.CreateICmp(Pred, Op0, CI.getArgOperand(1)); 759 760 Value *Mask = CI.getArgOperand(2); 761 const auto *C = dyn_cast<Constant>(Mask); 762 if (!C || !C->isAllOnesValue()) 763 Cmp = Builder.CreateAnd(Cmp, getX86MaskVec(Builder, Mask, NumElts)); 764 765 if (NumElts < 8) { 766 uint32_t Indices[8]; 767 for (unsigned i = 0; i != NumElts; ++i) 768 Indices[i] = i; 769 for (unsigned i = NumElts; i != 8; ++i) 770 Indices[i] = NumElts + i % NumElts; 771 Cmp = Builder.CreateShuffleVector(Cmp, 772 Constant::getNullValue(Cmp->getType()), 773 Indices); 774 } 775 return Builder.CreateBitCast(Cmp, IntegerType::get(CI.getContext(), 776 std::max(NumElts, 8U))); 777 } 778 779 // Replace a masked intrinsic with an older unmasked intrinsic. 780 static Value *UpgradeX86MaskedShift(IRBuilder<> &Builder, CallInst &CI, 781 Intrinsic::ID IID) { 782 Function *F = CI.getCalledFunction(); 783 Function *Intrin = Intrinsic::getDeclaration(F->getParent(), IID); 784 Value *Rep = Builder.CreateCall(Intrin, 785 { CI.getArgOperand(0), CI.getArgOperand(1) }); 786 return EmitX86Select(Builder, CI.getArgOperand(3), Rep, CI.getArgOperand(2)); 787 } 788 789 static Value* upgradeMaskedMove(IRBuilder<> &Builder, CallInst &CI) { 790 Value* A = CI.getArgOperand(0); 791 Value* B = CI.getArgOperand(1); 792 Value* Src = CI.getArgOperand(2); 793 Value* Mask = CI.getArgOperand(3); 794 795 Value* AndNode = Builder.CreateAnd(Mask, APInt(8, 1)); 796 Value* Cmp = Builder.CreateIsNotNull(AndNode); 797 Value* Extract1 = Builder.CreateExtractElement(B, (uint64_t)0); 798 Value* Extract2 = Builder.CreateExtractElement(Src, (uint64_t)0); 799 Value* Select = Builder.CreateSelect(Cmp, Extract1, Extract2); 800 return Builder.CreateInsertElement(A, Select, (uint64_t)0); 801 } 802 803 /// Upgrade a call to an old intrinsic. All argument and return casting must be 804 /// provided to seamlessly integrate with existing context. 805 void llvm::UpgradeIntrinsicCall(CallInst *CI, Function *NewFn) { 806 Function *F = CI->getCalledFunction(); 807 LLVMContext &C = CI->getContext(); 808 IRBuilder<> Builder(C); 809 Builder.SetInsertPoint(CI->getParent(), CI->getIterator()); 810 811 assert(F && "Intrinsic call is not direct?"); 812 813 if (!NewFn) { 814 // Get the Function's name. 815 StringRef Name = F->getName(); 816 817 assert(Name.startswith("llvm.") && "Intrinsic doesn't start with 'llvm.'"); 818 Name = Name.substr(5); 819 820 bool IsX86 = Name.startswith("x86."); 821 if (IsX86) 822 Name = Name.substr(4); 823 bool IsNVVM = Name.startswith("nvvm."); 824 if (IsNVVM) 825 Name = Name.substr(5); 826 827 if (IsX86 && Name.startswith("sse4a.movnt.")) { 828 Module *M = F->getParent(); 829 SmallVector<Metadata *, 1> Elts; 830 Elts.push_back( 831 ConstantAsMetadata::get(ConstantInt::get(Type::getInt32Ty(C), 1))); 832 MDNode *Node = MDNode::get(C, Elts); 833 834 Value *Arg0 = CI->getArgOperand(0); 835 Value *Arg1 = CI->getArgOperand(1); 836 837 // Nontemporal (unaligned) store of the 0'th element of the float/double 838 // vector. 839 Type *SrcEltTy = cast<VectorType>(Arg1->getType())->getElementType(); 840 PointerType *EltPtrTy = PointerType::getUnqual(SrcEltTy); 841 Value *Addr = Builder.CreateBitCast(Arg0, EltPtrTy, "cast"); 842 Value *Extract = 843 Builder.CreateExtractElement(Arg1, (uint64_t)0, "extractelement"); 844 845 StoreInst *SI = Builder.CreateAlignedStore(Extract, Addr, 1); 846 SI->setMetadata(M->getMDKindID("nontemporal"), Node); 847 848 // Remove intrinsic. 849 CI->eraseFromParent(); 850 return; 851 } 852 853 if (IsX86 && (Name.startswith("avx.movnt.") || 854 Name.startswith("avx512.storent."))) { 855 Module *M = F->getParent(); 856 SmallVector<Metadata *, 1> Elts; 857 Elts.push_back( 858 ConstantAsMetadata::get(ConstantInt::get(Type::getInt32Ty(C), 1))); 859 MDNode *Node = MDNode::get(C, Elts); 860 861 Value *Arg0 = CI->getArgOperand(0); 862 Value *Arg1 = CI->getArgOperand(1); 863 864 // Convert the type of the pointer to a pointer to the stored type. 865 Value *BC = Builder.CreateBitCast(Arg0, 866 PointerType::getUnqual(Arg1->getType()), 867 "cast"); 868 VectorType *VTy = cast<VectorType>(Arg1->getType()); 869 StoreInst *SI = Builder.CreateAlignedStore(Arg1, BC, 870 VTy->getBitWidth() / 8); 871 SI->setMetadata(M->getMDKindID("nontemporal"), Node); 872 873 // Remove intrinsic. 874 CI->eraseFromParent(); 875 return; 876 } 877 878 if (IsX86 && Name == "sse2.storel.dq") { 879 Value *Arg0 = CI->getArgOperand(0); 880 Value *Arg1 = CI->getArgOperand(1); 881 882 Type *NewVecTy = VectorType::get(Type::getInt64Ty(C), 2); 883 Value *BC0 = Builder.CreateBitCast(Arg1, NewVecTy, "cast"); 884 Value *Elt = Builder.CreateExtractElement(BC0, (uint64_t)0); 885 Value *BC = Builder.CreateBitCast(Arg0, 886 PointerType::getUnqual(Elt->getType()), 887 "cast"); 888 Builder.CreateAlignedStore(Elt, BC, 1); 889 890 // Remove intrinsic. 891 CI->eraseFromParent(); 892 return; 893 } 894 895 if (IsX86 && (Name.startswith("sse.storeu.") || 896 Name.startswith("sse2.storeu.") || 897 Name.startswith("avx.storeu."))) { 898 Value *Arg0 = CI->getArgOperand(0); 899 Value *Arg1 = CI->getArgOperand(1); 900 901 Arg0 = Builder.CreateBitCast(Arg0, 902 PointerType::getUnqual(Arg1->getType()), 903 "cast"); 904 Builder.CreateAlignedStore(Arg1, Arg0, 1); 905 906 // Remove intrinsic. 907 CI->eraseFromParent(); 908 return; 909 } 910 911 if (IsX86 && (Name.startswith("avx512.mask.store"))) { 912 // "avx512.mask.storeu." or "avx512.mask.store." 913 bool Aligned = Name[17] != 'u'; // "avx512.mask.storeu". 914 UpgradeMaskedStore(Builder, CI->getArgOperand(0), CI->getArgOperand(1), 915 CI->getArgOperand(2), Aligned); 916 917 // Remove intrinsic. 918 CI->eraseFromParent(); 919 return; 920 } 921 922 Value *Rep; 923 // Upgrade packed integer vector compare intrinsics to compare instructions. 924 if (IsX86 && (Name.startswith("sse2.pcmp") || 925 Name.startswith("avx2.pcmp"))) { 926 // "sse2.pcpmpeq." "sse2.pcmpgt." "avx2.pcmpeq." or "avx2.pcmpgt." 927 bool CmpEq = Name[9] == 'e'; 928 Rep = Builder.CreateICmp(CmpEq ? ICmpInst::ICMP_EQ : ICmpInst::ICMP_SGT, 929 CI->getArgOperand(0), CI->getArgOperand(1)); 930 Rep = Builder.CreateSExt(Rep, CI->getType(), ""); 931 } else if (IsX86 && (Name == "sse.add.ss" || Name == "sse2.add.sd")) { 932 Type *I32Ty = Type::getInt32Ty(C); 933 Value *Elt0 = Builder.CreateExtractElement(CI->getArgOperand(0), 934 ConstantInt::get(I32Ty, 0)); 935 Value *Elt1 = Builder.CreateExtractElement(CI->getArgOperand(1), 936 ConstantInt::get(I32Ty, 0)); 937 Rep = Builder.CreateInsertElement(CI->getArgOperand(0), 938 Builder.CreateFAdd(Elt0, Elt1), 939 ConstantInt::get(I32Ty, 0)); 940 } else if (IsX86 && (Name == "sse.sub.ss" || Name == "sse2.sub.sd")) { 941 Type *I32Ty = Type::getInt32Ty(C); 942 Value *Elt0 = Builder.CreateExtractElement(CI->getArgOperand(0), 943 ConstantInt::get(I32Ty, 0)); 944 Value *Elt1 = Builder.CreateExtractElement(CI->getArgOperand(1), 945 ConstantInt::get(I32Ty, 0)); 946 Rep = Builder.CreateInsertElement(CI->getArgOperand(0), 947 Builder.CreateFSub(Elt0, Elt1), 948 ConstantInt::get(I32Ty, 0)); 949 } else if (IsX86 && (Name == "sse.mul.ss" || Name == "sse2.mul.sd")) { 950 Type *I32Ty = Type::getInt32Ty(C); 951 Value *Elt0 = Builder.CreateExtractElement(CI->getArgOperand(0), 952 ConstantInt::get(I32Ty, 0)); 953 Value *Elt1 = Builder.CreateExtractElement(CI->getArgOperand(1), 954 ConstantInt::get(I32Ty, 0)); 955 Rep = Builder.CreateInsertElement(CI->getArgOperand(0), 956 Builder.CreateFMul(Elt0, Elt1), 957 ConstantInt::get(I32Ty, 0)); 958 } else if (IsX86 && (Name == "sse.div.ss" || Name == "sse2.div.sd")) { 959 Type *I32Ty = Type::getInt32Ty(C); 960 Value *Elt0 = Builder.CreateExtractElement(CI->getArgOperand(0), 961 ConstantInt::get(I32Ty, 0)); 962 Value *Elt1 = Builder.CreateExtractElement(CI->getArgOperand(1), 963 ConstantInt::get(I32Ty, 0)); 964 Rep = Builder.CreateInsertElement(CI->getArgOperand(0), 965 Builder.CreateFDiv(Elt0, Elt1), 966 ConstantInt::get(I32Ty, 0)); 967 } else if (IsX86 && Name.startswith("avx512.mask.pcmp")) { 968 // "avx512.mask.pcmpeq." or "avx512.mask.pcmpgt." 969 bool CmpEq = Name[16] == 'e'; 970 Rep = upgradeMaskedCompare(Builder, *CI, 971 CmpEq ? ICmpInst::ICMP_EQ 972 : ICmpInst::ICMP_SGT); 973 } else if (IsX86 && (Name == "sse41.pmaxsb" || 974 Name == "sse2.pmaxs.w" || 975 Name == "sse41.pmaxsd" || 976 Name.startswith("avx2.pmaxs") || 977 Name.startswith("avx512.mask.pmaxs"))) { 978 Rep = upgradeIntMinMax(Builder, *CI, ICmpInst::ICMP_SGT); 979 } else if (IsX86 && (Name == "sse2.pmaxu.b" || 980 Name == "sse41.pmaxuw" || 981 Name == "sse41.pmaxud" || 982 Name.startswith("avx2.pmaxu") || 983 Name.startswith("avx512.mask.pmaxu"))) { 984 Rep = upgradeIntMinMax(Builder, *CI, ICmpInst::ICMP_UGT); 985 } else if (IsX86 && (Name == "sse41.pminsb" || 986 Name == "sse2.pmins.w" || 987 Name == "sse41.pminsd" || 988 Name.startswith("avx2.pmins") || 989 Name.startswith("avx512.mask.pmins"))) { 990 Rep = upgradeIntMinMax(Builder, *CI, ICmpInst::ICMP_SLT); 991 } else if (IsX86 && (Name == "sse2.pminu.b" || 992 Name == "sse41.pminuw" || 993 Name == "sse41.pminud" || 994 Name.startswith("avx2.pminu") || 995 Name.startswith("avx512.mask.pminu"))) { 996 Rep = upgradeIntMinMax(Builder, *CI, ICmpInst::ICMP_ULT); 997 } else if (IsX86 && (Name == "sse2.cvtdq2pd" || 998 Name == "sse2.cvtps2pd" || 999 Name == "avx.cvtdq2.pd.256" || 1000 Name == "avx.cvt.ps2.pd.256" || 1001 Name.startswith("avx512.mask.cvtdq2pd.") || 1002 Name.startswith("avx512.mask.cvtudq2pd."))) { 1003 // Lossless i32/float to double conversion. 1004 // Extract the bottom elements if necessary and convert to double vector. 1005 Value *Src = CI->getArgOperand(0); 1006 VectorType *SrcTy = cast<VectorType>(Src->getType()); 1007 VectorType *DstTy = cast<VectorType>(CI->getType()); 1008 Rep = CI->getArgOperand(0); 1009 1010 unsigned NumDstElts = DstTy->getNumElements(); 1011 if (NumDstElts < SrcTy->getNumElements()) { 1012 assert(NumDstElts == 2 && "Unexpected vector size"); 1013 uint32_t ShuffleMask[2] = { 0, 1 }; 1014 Rep = Builder.CreateShuffleVector(Rep, UndefValue::get(SrcTy), 1015 ShuffleMask); 1016 } 1017 1018 bool SInt2Double = (StringRef::npos != Name.find("cvtdq2")); 1019 bool UInt2Double = (StringRef::npos != Name.find("cvtudq2")); 1020 if (SInt2Double) 1021 Rep = Builder.CreateSIToFP(Rep, DstTy, "cvtdq2pd"); 1022 else if (UInt2Double) 1023 Rep = Builder.CreateUIToFP(Rep, DstTy, "cvtudq2pd"); 1024 else 1025 Rep = Builder.CreateFPExt(Rep, DstTy, "cvtps2pd"); 1026 1027 if (CI->getNumArgOperands() == 3) 1028 Rep = EmitX86Select(Builder, CI->getArgOperand(2), Rep, 1029 CI->getArgOperand(1)); 1030 } else if (IsX86 && (Name.startswith("avx512.mask.loadu."))) { 1031 Rep = UpgradeMaskedLoad(Builder, CI->getArgOperand(0), 1032 CI->getArgOperand(1), CI->getArgOperand(2), 1033 /*Aligned*/false); 1034 } else if (IsX86 && (Name.startswith("avx512.mask.load."))) { 1035 Rep = UpgradeMaskedLoad(Builder, CI->getArgOperand(0), 1036 CI->getArgOperand(1),CI->getArgOperand(2), 1037 /*Aligned*/true); 1038 } else if (IsX86 && Name.startswith("xop.vpcom")) { 1039 Intrinsic::ID intID; 1040 if (Name.endswith("ub")) 1041 intID = Intrinsic::x86_xop_vpcomub; 1042 else if (Name.endswith("uw")) 1043 intID = Intrinsic::x86_xop_vpcomuw; 1044 else if (Name.endswith("ud")) 1045 intID = Intrinsic::x86_xop_vpcomud; 1046 else if (Name.endswith("uq")) 1047 intID = Intrinsic::x86_xop_vpcomuq; 1048 else if (Name.endswith("b")) 1049 intID = Intrinsic::x86_xop_vpcomb; 1050 else if (Name.endswith("w")) 1051 intID = Intrinsic::x86_xop_vpcomw; 1052 else if (Name.endswith("d")) 1053 intID = Intrinsic::x86_xop_vpcomd; 1054 else if (Name.endswith("q")) 1055 intID = Intrinsic::x86_xop_vpcomq; 1056 else 1057 llvm_unreachable("Unknown suffix"); 1058 1059 Name = Name.substr(9); // strip off "xop.vpcom" 1060 unsigned Imm; 1061 if (Name.startswith("lt")) 1062 Imm = 0; 1063 else if (Name.startswith("le")) 1064 Imm = 1; 1065 else if (Name.startswith("gt")) 1066 Imm = 2; 1067 else if (Name.startswith("ge")) 1068 Imm = 3; 1069 else if (Name.startswith("eq")) 1070 Imm = 4; 1071 else if (Name.startswith("ne")) 1072 Imm = 5; 1073 else if (Name.startswith("false")) 1074 Imm = 6; 1075 else if (Name.startswith("true")) 1076 Imm = 7; 1077 else 1078 llvm_unreachable("Unknown condition"); 1079 1080 Function *VPCOM = Intrinsic::getDeclaration(F->getParent(), intID); 1081 Rep = 1082 Builder.CreateCall(VPCOM, {CI->getArgOperand(0), CI->getArgOperand(1), 1083 Builder.getInt8(Imm)}); 1084 } else if (IsX86 && Name.startswith("xop.vpcmov")) { 1085 Value *Sel = CI->getArgOperand(2); 1086 Value *NotSel = Builder.CreateNot(Sel); 1087 Value *Sel0 = Builder.CreateAnd(CI->getArgOperand(0), Sel); 1088 Value *Sel1 = Builder.CreateAnd(CI->getArgOperand(1), NotSel); 1089 Rep = Builder.CreateOr(Sel0, Sel1); 1090 } else if (IsX86 && Name == "sse42.crc32.64.8") { 1091 Function *CRC32 = Intrinsic::getDeclaration(F->getParent(), 1092 Intrinsic::x86_sse42_crc32_32_8); 1093 Value *Trunc0 = Builder.CreateTrunc(CI->getArgOperand(0), Type::getInt32Ty(C)); 1094 Rep = Builder.CreateCall(CRC32, {Trunc0, CI->getArgOperand(1)}); 1095 Rep = Builder.CreateZExt(Rep, CI->getType(), ""); 1096 } else if (IsX86 && Name.startswith("avx.vbroadcast.s")) { 1097 // Replace broadcasts with a series of insertelements. 1098 Type *VecTy = CI->getType(); 1099 Type *EltTy = VecTy->getVectorElementType(); 1100 unsigned EltNum = VecTy->getVectorNumElements(); 1101 Value *Cast = Builder.CreateBitCast(CI->getArgOperand(0), 1102 EltTy->getPointerTo()); 1103 Value *Load = Builder.CreateLoad(EltTy, Cast); 1104 Type *I32Ty = Type::getInt32Ty(C); 1105 Rep = UndefValue::get(VecTy); 1106 for (unsigned I = 0; I < EltNum; ++I) 1107 Rep = Builder.CreateInsertElement(Rep, Load, 1108 ConstantInt::get(I32Ty, I)); 1109 } else if (IsX86 && (Name.startswith("sse41.pmovsx") || 1110 Name.startswith("sse41.pmovzx") || 1111 Name.startswith("avx2.pmovsx") || 1112 Name.startswith("avx2.pmovzx") || 1113 Name.startswith("avx512.mask.pmovsx") || 1114 Name.startswith("avx512.mask.pmovzx"))) { 1115 VectorType *SrcTy = cast<VectorType>(CI->getArgOperand(0)->getType()); 1116 VectorType *DstTy = cast<VectorType>(CI->getType()); 1117 unsigned NumDstElts = DstTy->getNumElements(); 1118 1119 // Extract a subvector of the first NumDstElts lanes and sign/zero extend. 1120 SmallVector<uint32_t, 8> ShuffleMask(NumDstElts); 1121 for (unsigned i = 0; i != NumDstElts; ++i) 1122 ShuffleMask[i] = i; 1123 1124 Value *SV = Builder.CreateShuffleVector( 1125 CI->getArgOperand(0), UndefValue::get(SrcTy), ShuffleMask); 1126 1127 bool DoSext = (StringRef::npos != Name.find("pmovsx")); 1128 Rep = DoSext ? Builder.CreateSExt(SV, DstTy) 1129 : Builder.CreateZExt(SV, DstTy); 1130 // If there are 3 arguments, it's a masked intrinsic so we need a select. 1131 if (CI->getNumArgOperands() == 3) 1132 Rep = EmitX86Select(Builder, CI->getArgOperand(2), Rep, 1133 CI->getArgOperand(1)); 1134 } else if (IsX86 && (Name.startswith("avx.vbroadcastf128") || 1135 Name == "avx2.vbroadcasti128")) { 1136 // Replace vbroadcastf128/vbroadcasti128 with a vector load+shuffle. 1137 Type *EltTy = CI->getType()->getVectorElementType(); 1138 unsigned NumSrcElts = 128 / EltTy->getPrimitiveSizeInBits(); 1139 Type *VT = VectorType::get(EltTy, NumSrcElts); 1140 Value *Op = Builder.CreatePointerCast(CI->getArgOperand(0), 1141 PointerType::getUnqual(VT)); 1142 Value *Load = Builder.CreateAlignedLoad(Op, 1); 1143 if (NumSrcElts == 2) 1144 Rep = Builder.CreateShuffleVector(Load, UndefValue::get(Load->getType()), 1145 { 0, 1, 0, 1 }); 1146 else 1147 Rep = Builder.CreateShuffleVector(Load, UndefValue::get(Load->getType()), 1148 { 0, 1, 2, 3, 0, 1, 2, 3 }); 1149 } else if (IsX86 && (Name.startswith("avx2.pbroadcast") || 1150 Name.startswith("avx2.vbroadcast") || 1151 Name.startswith("avx512.pbroadcast") || 1152 Name.startswith("avx512.mask.broadcast.s"))) { 1153 // Replace vp?broadcasts with a vector shuffle. 1154 Value *Op = CI->getArgOperand(0); 1155 unsigned NumElts = CI->getType()->getVectorNumElements(); 1156 Type *MaskTy = VectorType::get(Type::getInt32Ty(C), NumElts); 1157 Rep = Builder.CreateShuffleVector(Op, UndefValue::get(Op->getType()), 1158 Constant::getNullValue(MaskTy)); 1159 1160 if (CI->getNumArgOperands() == 3) 1161 Rep = EmitX86Select(Builder, CI->getArgOperand(2), Rep, 1162 CI->getArgOperand(1)); 1163 } else if (IsX86 && Name.startswith("avx512.mask.palignr.")) { 1164 Rep = UpgradeX86ALIGNIntrinsics(Builder, CI->getArgOperand(0), 1165 CI->getArgOperand(1), 1166 CI->getArgOperand(2), 1167 CI->getArgOperand(3), 1168 CI->getArgOperand(4), 1169 false); 1170 } else if (IsX86 && Name.startswith("avx512.mask.valign.")) { 1171 Rep = UpgradeX86ALIGNIntrinsics(Builder, CI->getArgOperand(0), 1172 CI->getArgOperand(1), 1173 CI->getArgOperand(2), 1174 CI->getArgOperand(3), 1175 CI->getArgOperand(4), 1176 true); 1177 } else if (IsX86 && (Name == "sse2.psll.dq" || 1178 Name == "avx2.psll.dq")) { 1179 // 128/256-bit shift left specified in bits. 1180 unsigned Shift = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue(); 1181 Rep = UpgradeX86PSLLDQIntrinsics(Builder, CI->getArgOperand(0), 1182 Shift / 8); // Shift is in bits. 1183 } else if (IsX86 && (Name == "sse2.psrl.dq" || 1184 Name == "avx2.psrl.dq")) { 1185 // 128/256-bit shift right specified in bits. 1186 unsigned Shift = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue(); 1187 Rep = UpgradeX86PSRLDQIntrinsics(Builder, CI->getArgOperand(0), 1188 Shift / 8); // Shift is in bits. 1189 } else if (IsX86 && (Name == "sse2.psll.dq.bs" || 1190 Name == "avx2.psll.dq.bs" || 1191 Name == "avx512.psll.dq.512")) { 1192 // 128/256/512-bit shift left specified in bytes. 1193 unsigned Shift = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue(); 1194 Rep = UpgradeX86PSLLDQIntrinsics(Builder, CI->getArgOperand(0), Shift); 1195 } else if (IsX86 && (Name == "sse2.psrl.dq.bs" || 1196 Name == "avx2.psrl.dq.bs" || 1197 Name == "avx512.psrl.dq.512")) { 1198 // 128/256/512-bit shift right specified in bytes. 1199 unsigned Shift = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue(); 1200 Rep = UpgradeX86PSRLDQIntrinsics(Builder, CI->getArgOperand(0), Shift); 1201 } else if (IsX86 && (Name == "sse41.pblendw" || 1202 Name.startswith("sse41.blendp") || 1203 Name.startswith("avx.blend.p") || 1204 Name == "avx2.pblendw" || 1205 Name.startswith("avx2.pblendd."))) { 1206 Value *Op0 = CI->getArgOperand(0); 1207 Value *Op1 = CI->getArgOperand(1); 1208 unsigned Imm = cast <ConstantInt>(CI->getArgOperand(2))->getZExtValue(); 1209 VectorType *VecTy = cast<VectorType>(CI->getType()); 1210 unsigned NumElts = VecTy->getNumElements(); 1211 1212 SmallVector<uint32_t, 16> Idxs(NumElts); 1213 for (unsigned i = 0; i != NumElts; ++i) 1214 Idxs[i] = ((Imm >> (i%8)) & 1) ? i + NumElts : i; 1215 1216 Rep = Builder.CreateShuffleVector(Op0, Op1, Idxs); 1217 } else if (IsX86 && (Name.startswith("avx.vinsertf128.") || 1218 Name == "avx2.vinserti128" || 1219 Name.startswith("avx512.mask.insert"))) { 1220 Value *Op0 = CI->getArgOperand(0); 1221 Value *Op1 = CI->getArgOperand(1); 1222 unsigned Imm = cast<ConstantInt>(CI->getArgOperand(2))->getZExtValue(); 1223 unsigned DstNumElts = CI->getType()->getVectorNumElements(); 1224 unsigned SrcNumElts = Op1->getType()->getVectorNumElements(); 1225 unsigned Scale = DstNumElts / SrcNumElts; 1226 1227 // Mask off the high bits of the immediate value; hardware ignores those. 1228 Imm = Imm % Scale; 1229 1230 // Extend the second operand into a vector the size of the destination. 1231 Value *UndefV = UndefValue::get(Op1->getType()); 1232 SmallVector<uint32_t, 8> Idxs(DstNumElts); 1233 for (unsigned i = 0; i != SrcNumElts; ++i) 1234 Idxs[i] = i; 1235 for (unsigned i = SrcNumElts; i != DstNumElts; ++i) 1236 Idxs[i] = SrcNumElts; 1237 Rep = Builder.CreateShuffleVector(Op1, UndefV, Idxs); 1238 1239 // Insert the second operand into the first operand. 1240 1241 // Note that there is no guarantee that instruction lowering will actually 1242 // produce a vinsertf128 instruction for the created shuffles. In 1243 // particular, the 0 immediate case involves no lane changes, so it can 1244 // be handled as a blend. 1245 1246 // Example of shuffle mask for 32-bit elements: 1247 // Imm = 1 <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11> 1248 // Imm = 0 <i32 8, i32 9, i32 10, i32 11, i32 4, i32 5, i32 6, i32 7 > 1249 1250 // First fill with identify mask. 1251 for (unsigned i = 0; i != DstNumElts; ++i) 1252 Idxs[i] = i; 1253 // Then replace the elements where we need to insert. 1254 for (unsigned i = 0; i != SrcNumElts; ++i) 1255 Idxs[i + Imm * SrcNumElts] = i + DstNumElts; 1256 Rep = Builder.CreateShuffleVector(Op0, Rep, Idxs); 1257 1258 // If the intrinsic has a mask operand, handle that. 1259 if (CI->getNumArgOperands() == 5) 1260 Rep = EmitX86Select(Builder, CI->getArgOperand(4), Rep, 1261 CI->getArgOperand(3)); 1262 } else if (IsX86 && (Name.startswith("avx.vextractf128.") || 1263 Name == "avx2.vextracti128" || 1264 Name.startswith("avx512.mask.vextract"))) { 1265 Value *Op0 = CI->getArgOperand(0); 1266 unsigned Imm = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue(); 1267 unsigned DstNumElts = CI->getType()->getVectorNumElements(); 1268 unsigned SrcNumElts = Op0->getType()->getVectorNumElements(); 1269 unsigned Scale = SrcNumElts / DstNumElts; 1270 1271 // Mask off the high bits of the immediate value; hardware ignores those. 1272 Imm = Imm % Scale; 1273 1274 // Get indexes for the subvector of the input vector. 1275 SmallVector<uint32_t, 8> Idxs(DstNumElts); 1276 for (unsigned i = 0; i != DstNumElts; ++i) { 1277 Idxs[i] = i + (Imm * DstNumElts); 1278 } 1279 Rep = Builder.CreateShuffleVector(Op0, Op0, Idxs); 1280 1281 // If the intrinsic has a mask operand, handle that. 1282 if (CI->getNumArgOperands() == 4) 1283 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1284 CI->getArgOperand(2)); 1285 } else if (!IsX86 && Name == "stackprotectorcheck") { 1286 Rep = nullptr; 1287 } else if (IsX86 && (Name.startswith("avx512.mask.perm.df.") || 1288 Name.startswith("avx512.mask.perm.di."))) { 1289 Value *Op0 = CI->getArgOperand(0); 1290 unsigned Imm = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue(); 1291 VectorType *VecTy = cast<VectorType>(CI->getType()); 1292 unsigned NumElts = VecTy->getNumElements(); 1293 1294 SmallVector<uint32_t, 8> Idxs(NumElts); 1295 for (unsigned i = 0; i != NumElts; ++i) 1296 Idxs[i] = (i & ~0x3) + ((Imm >> (2 * (i & 0x3))) & 3); 1297 1298 Rep = Builder.CreateShuffleVector(Op0, Op0, Idxs); 1299 1300 if (CI->getNumArgOperands() == 4) 1301 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1302 CI->getArgOperand(2)); 1303 } else if (IsX86 && (Name.startswith("avx.vpermil.") || 1304 Name == "sse2.pshuf.d" || 1305 Name.startswith("avx512.mask.vpermil.p") || 1306 Name.startswith("avx512.mask.pshuf.d."))) { 1307 Value *Op0 = CI->getArgOperand(0); 1308 unsigned Imm = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue(); 1309 VectorType *VecTy = cast<VectorType>(CI->getType()); 1310 unsigned NumElts = VecTy->getNumElements(); 1311 // Calculate the size of each index in the immediate. 1312 unsigned IdxSize = 64 / VecTy->getScalarSizeInBits(); 1313 unsigned IdxMask = ((1 << IdxSize) - 1); 1314 1315 SmallVector<uint32_t, 8> Idxs(NumElts); 1316 // Lookup the bits for this element, wrapping around the immediate every 1317 // 8-bits. Elements are grouped into sets of 2 or 4 elements so we need 1318 // to offset by the first index of each group. 1319 for (unsigned i = 0; i != NumElts; ++i) 1320 Idxs[i] = ((Imm >> ((i * IdxSize) % 8)) & IdxMask) | (i & ~IdxMask); 1321 1322 Rep = Builder.CreateShuffleVector(Op0, Op0, Idxs); 1323 1324 if (CI->getNumArgOperands() == 4) 1325 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1326 CI->getArgOperand(2)); 1327 } else if (IsX86 && (Name == "sse2.pshufl.w" || 1328 Name.startswith("avx512.mask.pshufl.w."))) { 1329 Value *Op0 = CI->getArgOperand(0); 1330 unsigned Imm = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue(); 1331 unsigned NumElts = CI->getType()->getVectorNumElements(); 1332 1333 SmallVector<uint32_t, 16> Idxs(NumElts); 1334 for (unsigned l = 0; l != NumElts; l += 8) { 1335 for (unsigned i = 0; i != 4; ++i) 1336 Idxs[i + l] = ((Imm >> (2 * i)) & 0x3) + l; 1337 for (unsigned i = 4; i != 8; ++i) 1338 Idxs[i + l] = i + l; 1339 } 1340 1341 Rep = Builder.CreateShuffleVector(Op0, Op0, Idxs); 1342 1343 if (CI->getNumArgOperands() == 4) 1344 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1345 CI->getArgOperand(2)); 1346 } else if (IsX86 && (Name == "sse2.pshufh.w" || 1347 Name.startswith("avx512.mask.pshufh.w."))) { 1348 Value *Op0 = CI->getArgOperand(0); 1349 unsigned Imm = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue(); 1350 unsigned NumElts = CI->getType()->getVectorNumElements(); 1351 1352 SmallVector<uint32_t, 16> Idxs(NumElts); 1353 for (unsigned l = 0; l != NumElts; l += 8) { 1354 for (unsigned i = 0; i != 4; ++i) 1355 Idxs[i + l] = i + l; 1356 for (unsigned i = 0; i != 4; ++i) 1357 Idxs[i + l + 4] = ((Imm >> (2 * i)) & 0x3) + 4 + l; 1358 } 1359 1360 Rep = Builder.CreateShuffleVector(Op0, Op0, Idxs); 1361 1362 if (CI->getNumArgOperands() == 4) 1363 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1364 CI->getArgOperand(2)); 1365 } else if (IsX86 && Name.startswith("avx512.mask.shuf.p")) { 1366 Value *Op0 = CI->getArgOperand(0); 1367 Value *Op1 = CI->getArgOperand(1); 1368 unsigned Imm = cast<ConstantInt>(CI->getArgOperand(2))->getZExtValue(); 1369 unsigned NumElts = CI->getType()->getVectorNumElements(); 1370 1371 unsigned NumLaneElts = 128/CI->getType()->getScalarSizeInBits(); 1372 unsigned HalfLaneElts = NumLaneElts / 2; 1373 1374 SmallVector<uint32_t, 16> Idxs(NumElts); 1375 for (unsigned i = 0; i != NumElts; ++i) { 1376 // Base index is the starting element of the lane. 1377 Idxs[i] = i - (i % NumLaneElts); 1378 // If we are half way through the lane switch to the other source. 1379 if ((i % NumLaneElts) >= HalfLaneElts) 1380 Idxs[i] += NumElts; 1381 // Now select the specific element. By adding HalfLaneElts bits from 1382 // the immediate. Wrapping around the immediate every 8-bits. 1383 Idxs[i] += (Imm >> ((i * HalfLaneElts) % 8)) & ((1 << HalfLaneElts) - 1); 1384 } 1385 1386 Rep = Builder.CreateShuffleVector(Op0, Op1, Idxs); 1387 1388 Rep = EmitX86Select(Builder, CI->getArgOperand(4), Rep, 1389 CI->getArgOperand(3)); 1390 } else if (IsX86 && (Name.startswith("avx512.mask.movddup") || 1391 Name.startswith("avx512.mask.movshdup") || 1392 Name.startswith("avx512.mask.movsldup"))) { 1393 Value *Op0 = CI->getArgOperand(0); 1394 unsigned NumElts = CI->getType()->getVectorNumElements(); 1395 unsigned NumLaneElts = 128/CI->getType()->getScalarSizeInBits(); 1396 1397 unsigned Offset = 0; 1398 if (Name.startswith("avx512.mask.movshdup.")) 1399 Offset = 1; 1400 1401 SmallVector<uint32_t, 16> Idxs(NumElts); 1402 for (unsigned l = 0; l != NumElts; l += NumLaneElts) 1403 for (unsigned i = 0; i != NumLaneElts; i += 2) { 1404 Idxs[i + l + 0] = i + l + Offset; 1405 Idxs[i + l + 1] = i + l + Offset; 1406 } 1407 1408 Rep = Builder.CreateShuffleVector(Op0, Op0, Idxs); 1409 1410 Rep = EmitX86Select(Builder, CI->getArgOperand(2), Rep, 1411 CI->getArgOperand(1)); 1412 } else if (IsX86 && (Name.startswith("avx512.mask.punpckl") || 1413 Name.startswith("avx512.mask.unpckl."))) { 1414 Value *Op0 = CI->getArgOperand(0); 1415 Value *Op1 = CI->getArgOperand(1); 1416 int NumElts = CI->getType()->getVectorNumElements(); 1417 int NumLaneElts = 128/CI->getType()->getScalarSizeInBits(); 1418 1419 SmallVector<uint32_t, 64> Idxs(NumElts); 1420 for (int l = 0; l != NumElts; l += NumLaneElts) 1421 for (int i = 0; i != NumLaneElts; ++i) 1422 Idxs[i + l] = l + (i / 2) + NumElts * (i % 2); 1423 1424 Rep = Builder.CreateShuffleVector(Op0, Op1, Idxs); 1425 1426 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1427 CI->getArgOperand(2)); 1428 } else if (IsX86 && (Name.startswith("avx512.mask.punpckh") || 1429 Name.startswith("avx512.mask.unpckh."))) { 1430 Value *Op0 = CI->getArgOperand(0); 1431 Value *Op1 = CI->getArgOperand(1); 1432 int NumElts = CI->getType()->getVectorNumElements(); 1433 int NumLaneElts = 128/CI->getType()->getScalarSizeInBits(); 1434 1435 SmallVector<uint32_t, 64> Idxs(NumElts); 1436 for (int l = 0; l != NumElts; l += NumLaneElts) 1437 for (int i = 0; i != NumLaneElts; ++i) 1438 Idxs[i + l] = (NumLaneElts / 2) + l + (i / 2) + NumElts * (i % 2); 1439 1440 Rep = Builder.CreateShuffleVector(Op0, Op1, Idxs); 1441 1442 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1443 CI->getArgOperand(2)); 1444 } else if (IsX86 && Name.startswith("avx512.mask.pand.")) { 1445 Rep = Builder.CreateAnd(CI->getArgOperand(0), CI->getArgOperand(1)); 1446 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1447 CI->getArgOperand(2)); 1448 } else if (IsX86 && Name.startswith("avx512.mask.pandn.")) { 1449 Rep = Builder.CreateAnd(Builder.CreateNot(CI->getArgOperand(0)), 1450 CI->getArgOperand(1)); 1451 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1452 CI->getArgOperand(2)); 1453 } else if (IsX86 && Name.startswith("avx512.mask.por.")) { 1454 Rep = Builder.CreateOr(CI->getArgOperand(0), CI->getArgOperand(1)); 1455 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1456 CI->getArgOperand(2)); 1457 } else if (IsX86 && Name.startswith("avx512.mask.pxor.")) { 1458 Rep = Builder.CreateXor(CI->getArgOperand(0), CI->getArgOperand(1)); 1459 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1460 CI->getArgOperand(2)); 1461 } else if (IsX86 && Name.startswith("avx512.mask.and.")) { 1462 VectorType *FTy = cast<VectorType>(CI->getType()); 1463 VectorType *ITy = VectorType::getInteger(FTy); 1464 Rep = Builder.CreateAnd(Builder.CreateBitCast(CI->getArgOperand(0), ITy), 1465 Builder.CreateBitCast(CI->getArgOperand(1), ITy)); 1466 Rep = Builder.CreateBitCast(Rep, FTy); 1467 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1468 CI->getArgOperand(2)); 1469 } else if (IsX86 && Name.startswith("avx512.mask.andn.")) { 1470 VectorType *FTy = cast<VectorType>(CI->getType()); 1471 VectorType *ITy = VectorType::getInteger(FTy); 1472 Rep = Builder.CreateNot(Builder.CreateBitCast(CI->getArgOperand(0), ITy)); 1473 Rep = Builder.CreateAnd(Rep, 1474 Builder.CreateBitCast(CI->getArgOperand(1), ITy)); 1475 Rep = Builder.CreateBitCast(Rep, FTy); 1476 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1477 CI->getArgOperand(2)); 1478 } else if (IsX86 && Name.startswith("avx512.mask.or.")) { 1479 VectorType *FTy = cast<VectorType>(CI->getType()); 1480 VectorType *ITy = VectorType::getInteger(FTy); 1481 Rep = Builder.CreateOr(Builder.CreateBitCast(CI->getArgOperand(0), ITy), 1482 Builder.CreateBitCast(CI->getArgOperand(1), ITy)); 1483 Rep = Builder.CreateBitCast(Rep, FTy); 1484 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1485 CI->getArgOperand(2)); 1486 } else if (IsX86 && Name.startswith("avx512.mask.xor.")) { 1487 VectorType *FTy = cast<VectorType>(CI->getType()); 1488 VectorType *ITy = VectorType::getInteger(FTy); 1489 Rep = Builder.CreateXor(Builder.CreateBitCast(CI->getArgOperand(0), ITy), 1490 Builder.CreateBitCast(CI->getArgOperand(1), ITy)); 1491 Rep = Builder.CreateBitCast(Rep, FTy); 1492 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1493 CI->getArgOperand(2)); 1494 } else if (IsX86 && Name.startswith("avx512.mask.padd.")) { 1495 Rep = Builder.CreateAdd(CI->getArgOperand(0), CI->getArgOperand(1)); 1496 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1497 CI->getArgOperand(2)); 1498 } else if (IsX86 && Name.startswith("avx512.mask.psub.")) { 1499 Rep = Builder.CreateSub(CI->getArgOperand(0), CI->getArgOperand(1)); 1500 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1501 CI->getArgOperand(2)); 1502 } else if (IsX86 && Name.startswith("avx512.mask.pmull.")) { 1503 Rep = Builder.CreateMul(CI->getArgOperand(0), CI->getArgOperand(1)); 1504 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1505 CI->getArgOperand(2)); 1506 } else if (IsX86 && (Name.startswith("avx512.mask.add.p"))) { 1507 Rep = Builder.CreateFAdd(CI->getArgOperand(0), CI->getArgOperand(1)); 1508 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1509 CI->getArgOperand(2)); 1510 } else if (IsX86 && Name.startswith("avx512.mask.div.p")) { 1511 Rep = Builder.CreateFDiv(CI->getArgOperand(0), CI->getArgOperand(1)); 1512 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1513 CI->getArgOperand(2)); 1514 } else if (IsX86 && Name.startswith("avx512.mask.mul.p")) { 1515 Rep = Builder.CreateFMul(CI->getArgOperand(0), CI->getArgOperand(1)); 1516 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1517 CI->getArgOperand(2)); 1518 } else if (IsX86 && Name.startswith("avx512.mask.sub.p")) { 1519 Rep = Builder.CreateFSub(CI->getArgOperand(0), CI->getArgOperand(1)); 1520 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1521 CI->getArgOperand(2)); 1522 } else if (IsX86 && Name.startswith("avx512.mask.lzcnt.")) { 1523 Rep = Builder.CreateCall(Intrinsic::getDeclaration(F->getParent(), 1524 Intrinsic::ctlz, 1525 CI->getType()), 1526 { CI->getArgOperand(0), Builder.getInt1(false) }); 1527 Rep = EmitX86Select(Builder, CI->getArgOperand(2), Rep, 1528 CI->getArgOperand(1)); 1529 } else if (IsX86 && (Name.startswith("avx512.mask.max.p") || 1530 Name.startswith("avx512.mask.min.p"))) { 1531 bool IsMin = Name[13] == 'i'; 1532 VectorType *VecTy = cast<VectorType>(CI->getType()); 1533 unsigned VecWidth = VecTy->getPrimitiveSizeInBits(); 1534 unsigned EltWidth = VecTy->getScalarSizeInBits(); 1535 Intrinsic::ID IID; 1536 if (!IsMin && VecWidth == 128 && EltWidth == 32) 1537 IID = Intrinsic::x86_sse_max_ps; 1538 else if (!IsMin && VecWidth == 128 && EltWidth == 64) 1539 IID = Intrinsic::x86_sse2_max_pd; 1540 else if (!IsMin && VecWidth == 256 && EltWidth == 32) 1541 IID = Intrinsic::x86_avx_max_ps_256; 1542 else if (!IsMin && VecWidth == 256 && EltWidth == 64) 1543 IID = Intrinsic::x86_avx_max_pd_256; 1544 else if (IsMin && VecWidth == 128 && EltWidth == 32) 1545 IID = Intrinsic::x86_sse_min_ps; 1546 else if (IsMin && VecWidth == 128 && EltWidth == 64) 1547 IID = Intrinsic::x86_sse2_min_pd; 1548 else if (IsMin && VecWidth == 256 && EltWidth == 32) 1549 IID = Intrinsic::x86_avx_min_ps_256; 1550 else if (IsMin && VecWidth == 256 && EltWidth == 64) 1551 IID = Intrinsic::x86_avx_min_pd_256; 1552 else 1553 llvm_unreachable("Unexpected intrinsic"); 1554 1555 Rep = Builder.CreateCall(Intrinsic::getDeclaration(F->getParent(), IID), 1556 { CI->getArgOperand(0), CI->getArgOperand(1) }); 1557 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1558 CI->getArgOperand(2)); 1559 } else if (IsX86 && Name.startswith("avx512.mask.pshuf.b.")) { 1560 VectorType *VecTy = cast<VectorType>(CI->getType()); 1561 Intrinsic::ID IID; 1562 if (VecTy->getPrimitiveSizeInBits() == 128) 1563 IID = Intrinsic::x86_ssse3_pshuf_b_128; 1564 else if (VecTy->getPrimitiveSizeInBits() == 256) 1565 IID = Intrinsic::x86_avx2_pshuf_b; 1566 else if (VecTy->getPrimitiveSizeInBits() == 512) 1567 IID = Intrinsic::x86_avx512_pshuf_b_512; 1568 else 1569 llvm_unreachable("Unexpected intrinsic"); 1570 1571 Rep = Builder.CreateCall(Intrinsic::getDeclaration(F->getParent(), IID), 1572 { CI->getArgOperand(0), CI->getArgOperand(1) }); 1573 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1574 CI->getArgOperand(2)); 1575 } else if (IsX86 && (Name.startswith("avx512.mask.pmul.dq.") || 1576 Name.startswith("avx512.mask.pmulu.dq."))) { 1577 bool IsUnsigned = Name[16] == 'u'; 1578 VectorType *VecTy = cast<VectorType>(CI->getType()); 1579 Intrinsic::ID IID; 1580 if (!IsUnsigned && VecTy->getPrimitiveSizeInBits() == 128) 1581 IID = Intrinsic::x86_sse41_pmuldq; 1582 else if (!IsUnsigned && VecTy->getPrimitiveSizeInBits() == 256) 1583 IID = Intrinsic::x86_avx2_pmul_dq; 1584 else if (!IsUnsigned && VecTy->getPrimitiveSizeInBits() == 512) 1585 IID = Intrinsic::x86_avx512_pmul_dq_512; 1586 else if (IsUnsigned && VecTy->getPrimitiveSizeInBits() == 128) 1587 IID = Intrinsic::x86_sse2_pmulu_dq; 1588 else if (IsUnsigned && VecTy->getPrimitiveSizeInBits() == 256) 1589 IID = Intrinsic::x86_avx2_pmulu_dq; 1590 else if (IsUnsigned && VecTy->getPrimitiveSizeInBits() == 512) 1591 IID = Intrinsic::x86_avx512_pmulu_dq_512; 1592 else 1593 llvm_unreachable("Unexpected intrinsic"); 1594 1595 Rep = Builder.CreateCall(Intrinsic::getDeclaration(F->getParent(), IID), 1596 { CI->getArgOperand(0), CI->getArgOperand(1) }); 1597 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1598 CI->getArgOperand(2)); 1599 } else if (IsX86 && Name.startswith("avx512.mask.pack")) { 1600 bool IsUnsigned = Name[16] == 'u'; 1601 bool IsDW = Name[18] == 'd'; 1602 VectorType *VecTy = cast<VectorType>(CI->getType()); 1603 Intrinsic::ID IID; 1604 if (!IsUnsigned && !IsDW && VecTy->getPrimitiveSizeInBits() == 128) 1605 IID = Intrinsic::x86_sse2_packsswb_128; 1606 else if (!IsUnsigned && !IsDW && VecTy->getPrimitiveSizeInBits() == 256) 1607 IID = Intrinsic::x86_avx2_packsswb; 1608 else if (!IsUnsigned && !IsDW && VecTy->getPrimitiveSizeInBits() == 512) 1609 IID = Intrinsic::x86_avx512_packsswb_512; 1610 else if (!IsUnsigned && IsDW && VecTy->getPrimitiveSizeInBits() == 128) 1611 IID = Intrinsic::x86_sse2_packssdw_128; 1612 else if (!IsUnsigned && IsDW && VecTy->getPrimitiveSizeInBits() == 256) 1613 IID = Intrinsic::x86_avx2_packssdw; 1614 else if (!IsUnsigned && IsDW && VecTy->getPrimitiveSizeInBits() == 512) 1615 IID = Intrinsic::x86_avx512_packssdw_512; 1616 else if (IsUnsigned && !IsDW && VecTy->getPrimitiveSizeInBits() == 128) 1617 IID = Intrinsic::x86_sse2_packuswb_128; 1618 else if (IsUnsigned && !IsDW && VecTy->getPrimitiveSizeInBits() == 256) 1619 IID = Intrinsic::x86_avx2_packuswb; 1620 else if (IsUnsigned && !IsDW && VecTy->getPrimitiveSizeInBits() == 512) 1621 IID = Intrinsic::x86_avx512_packuswb_512; 1622 else if (IsUnsigned && IsDW && VecTy->getPrimitiveSizeInBits() == 128) 1623 IID = Intrinsic::x86_sse41_packusdw; 1624 else if (IsUnsigned && IsDW && VecTy->getPrimitiveSizeInBits() == 256) 1625 IID = Intrinsic::x86_avx2_packusdw; 1626 else if (IsUnsigned && IsDW && VecTy->getPrimitiveSizeInBits() == 512) 1627 IID = Intrinsic::x86_avx512_packusdw_512; 1628 else 1629 llvm_unreachable("Unexpected intrinsic"); 1630 1631 Rep = Builder.CreateCall(Intrinsic::getDeclaration(F->getParent(), IID), 1632 { CI->getArgOperand(0), CI->getArgOperand(1) }); 1633 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1634 CI->getArgOperand(2)); 1635 } else if (IsX86 && Name.startswith("avx512.mask.psll")) { 1636 bool IsImmediate = Name[16] == 'i' || 1637 (Name.size() > 18 && Name[18] == 'i'); 1638 bool IsVariable = Name[16] == 'v'; 1639 char Size = Name[16] == '.' ? Name[17] : 1640 Name[17] == '.' ? Name[18] : 1641 Name[18] == '.' ? Name[19] : 1642 Name[20]; 1643 1644 Intrinsic::ID IID; 1645 if (IsVariable && Name[17] != '.') { 1646 if (Size == 'd' && Name[17] == '2') // avx512.mask.psllv2.di 1647 IID = Intrinsic::x86_avx2_psllv_q; 1648 else if (Size == 'd' && Name[17] == '4') // avx512.mask.psllv4.di 1649 IID = Intrinsic::x86_avx2_psllv_q_256; 1650 else if (Size == 's' && Name[17] == '4') // avx512.mask.psllv4.si 1651 IID = Intrinsic::x86_avx2_psllv_d; 1652 else if (Size == 's' && Name[17] == '8') // avx512.mask.psllv8.si 1653 IID = Intrinsic::x86_avx2_psllv_d_256; 1654 else if (Size == 'h' && Name[17] == '8') // avx512.mask.psllv8.hi 1655 IID = Intrinsic::x86_avx512_psllv_w_128; 1656 else if (Size == 'h' && Name[17] == '1') // avx512.mask.psllv16.hi 1657 IID = Intrinsic::x86_avx512_psllv_w_256; 1658 else if (Name[17] == '3' && Name[18] == '2') // avx512.mask.psllv32hi 1659 IID = Intrinsic::x86_avx512_psllv_w_512; 1660 else 1661 llvm_unreachable("Unexpected size"); 1662 } else if (Name.endswith(".128")) { 1663 if (Size == 'd') // avx512.mask.psll.d.128, avx512.mask.psll.di.128 1664 IID = IsImmediate ? Intrinsic::x86_sse2_pslli_d 1665 : Intrinsic::x86_sse2_psll_d; 1666 else if (Size == 'q') // avx512.mask.psll.q.128, avx512.mask.psll.qi.128 1667 IID = IsImmediate ? Intrinsic::x86_sse2_pslli_q 1668 : Intrinsic::x86_sse2_psll_q; 1669 else if (Size == 'w') // avx512.mask.psll.w.128, avx512.mask.psll.wi.128 1670 IID = IsImmediate ? Intrinsic::x86_sse2_pslli_w 1671 : Intrinsic::x86_sse2_psll_w; 1672 else 1673 llvm_unreachable("Unexpected size"); 1674 } else if (Name.endswith(".256")) { 1675 if (Size == 'd') // avx512.mask.psll.d.256, avx512.mask.psll.di.256 1676 IID = IsImmediate ? Intrinsic::x86_avx2_pslli_d 1677 : Intrinsic::x86_avx2_psll_d; 1678 else if (Size == 'q') // avx512.mask.psll.q.256, avx512.mask.psll.qi.256 1679 IID = IsImmediate ? Intrinsic::x86_avx2_pslli_q 1680 : Intrinsic::x86_avx2_psll_q; 1681 else if (Size == 'w') // avx512.mask.psll.w.256, avx512.mask.psll.wi.256 1682 IID = IsImmediate ? Intrinsic::x86_avx2_pslli_w 1683 : Intrinsic::x86_avx2_psll_w; 1684 else 1685 llvm_unreachable("Unexpected size"); 1686 } else { 1687 if (Size == 'd') // psll.di.512, pslli.d, psll.d, psllv.d.512 1688 IID = IsImmediate ? Intrinsic::x86_avx512_pslli_d_512 : 1689 IsVariable ? Intrinsic::x86_avx512_psllv_d_512 : 1690 Intrinsic::x86_avx512_psll_d_512; 1691 else if (Size == 'q') // psll.qi.512, pslli.q, psll.q, psllv.q.512 1692 IID = IsImmediate ? Intrinsic::x86_avx512_pslli_q_512 : 1693 IsVariable ? Intrinsic::x86_avx512_psllv_q_512 : 1694 Intrinsic::x86_avx512_psll_q_512; 1695 else if (Size == 'w') // psll.wi.512, pslli.w, psll.w 1696 IID = IsImmediate ? Intrinsic::x86_avx512_pslli_w_512 1697 : Intrinsic::x86_avx512_psll_w_512; 1698 else 1699 llvm_unreachable("Unexpected size"); 1700 } 1701 1702 Rep = UpgradeX86MaskedShift(Builder, *CI, IID); 1703 } else if (IsX86 && Name.startswith("avx512.mask.psrl")) { 1704 bool IsImmediate = Name[16] == 'i' || 1705 (Name.size() > 18 && Name[18] == 'i'); 1706 bool IsVariable = Name[16] == 'v'; 1707 char Size = Name[16] == '.' ? Name[17] : 1708 Name[17] == '.' ? Name[18] : 1709 Name[18] == '.' ? Name[19] : 1710 Name[20]; 1711 1712 Intrinsic::ID IID; 1713 if (IsVariable && Name[17] != '.') { 1714 if (Size == 'd' && Name[17] == '2') // avx512.mask.psrlv2.di 1715 IID = Intrinsic::x86_avx2_psrlv_q; 1716 else if (Size == 'd' && Name[17] == '4') // avx512.mask.psrlv4.di 1717 IID = Intrinsic::x86_avx2_psrlv_q_256; 1718 else if (Size == 's' && Name[17] == '4') // avx512.mask.psrlv4.si 1719 IID = Intrinsic::x86_avx2_psrlv_d; 1720 else if (Size == 's' && Name[17] == '8') // avx512.mask.psrlv8.si 1721 IID = Intrinsic::x86_avx2_psrlv_d_256; 1722 else if (Size == 'h' && Name[17] == '8') // avx512.mask.psrlv8.hi 1723 IID = Intrinsic::x86_avx512_psrlv_w_128; 1724 else if (Size == 'h' && Name[17] == '1') // avx512.mask.psrlv16.hi 1725 IID = Intrinsic::x86_avx512_psrlv_w_256; 1726 else if (Name[17] == '3' && Name[18] == '2') // avx512.mask.psrlv32hi 1727 IID = Intrinsic::x86_avx512_psrlv_w_512; 1728 else 1729 llvm_unreachable("Unexpected size"); 1730 } else if (Name.endswith(".128")) { 1731 if (Size == 'd') // avx512.mask.psrl.d.128, avx512.mask.psrl.di.128 1732 IID = IsImmediate ? Intrinsic::x86_sse2_psrli_d 1733 : Intrinsic::x86_sse2_psrl_d; 1734 else if (Size == 'q') // avx512.mask.psrl.q.128, avx512.mask.psrl.qi.128 1735 IID = IsImmediate ? Intrinsic::x86_sse2_psrli_q 1736 : Intrinsic::x86_sse2_psrl_q; 1737 else if (Size == 'w') // avx512.mask.psrl.w.128, avx512.mask.psrl.wi.128 1738 IID = IsImmediate ? Intrinsic::x86_sse2_psrli_w 1739 : Intrinsic::x86_sse2_psrl_w; 1740 else 1741 llvm_unreachable("Unexpected size"); 1742 } else if (Name.endswith(".256")) { 1743 if (Size == 'd') // avx512.mask.psrl.d.256, avx512.mask.psrl.di.256 1744 IID = IsImmediate ? Intrinsic::x86_avx2_psrli_d 1745 : Intrinsic::x86_avx2_psrl_d; 1746 else if (Size == 'q') // avx512.mask.psrl.q.256, avx512.mask.psrl.qi.256 1747 IID = IsImmediate ? Intrinsic::x86_avx2_psrli_q 1748 : Intrinsic::x86_avx2_psrl_q; 1749 else if (Size == 'w') // avx512.mask.psrl.w.256, avx512.mask.psrl.wi.256 1750 IID = IsImmediate ? Intrinsic::x86_avx2_psrli_w 1751 : Intrinsic::x86_avx2_psrl_w; 1752 else 1753 llvm_unreachable("Unexpected size"); 1754 } else { 1755 if (Size == 'd') // psrl.di.512, psrli.d, psrl.d, psrl.d.512 1756 IID = IsImmediate ? Intrinsic::x86_avx512_psrli_d_512 : 1757 IsVariable ? Intrinsic::x86_avx512_psrlv_d_512 : 1758 Intrinsic::x86_avx512_psrl_d_512; 1759 else if (Size == 'q') // psrl.qi.512, psrli.q, psrl.q, psrl.q.512 1760 IID = IsImmediate ? Intrinsic::x86_avx512_psrli_q_512 : 1761 IsVariable ? Intrinsic::x86_avx512_psrlv_q_512 : 1762 Intrinsic::x86_avx512_psrl_q_512; 1763 else if (Size == 'w') // psrl.wi.512, psrli.w, psrl.w) 1764 IID = IsImmediate ? Intrinsic::x86_avx512_psrli_w_512 1765 : Intrinsic::x86_avx512_psrl_w_512; 1766 else 1767 llvm_unreachable("Unexpected size"); 1768 } 1769 1770 Rep = UpgradeX86MaskedShift(Builder, *CI, IID); 1771 } else if (IsX86 && Name.startswith("avx512.mask.psra")) { 1772 bool IsImmediate = Name[16] == 'i' || 1773 (Name.size() > 18 && Name[18] == 'i'); 1774 bool IsVariable = Name[16] == 'v'; 1775 char Size = Name[16] == '.' ? Name[17] : 1776 Name[17] == '.' ? Name[18] : 1777 Name[18] == '.' ? Name[19] : 1778 Name[20]; 1779 1780 Intrinsic::ID IID; 1781 if (IsVariable && Name[17] != '.') { 1782 if (Size == 's' && Name[17] == '4') // avx512.mask.psrav4.si 1783 IID = Intrinsic::x86_avx2_psrav_d; 1784 else if (Size == 's' && Name[17] == '8') // avx512.mask.psrav8.si 1785 IID = Intrinsic::x86_avx2_psrav_d_256; 1786 else if (Size == 'h' && Name[17] == '8') // avx512.mask.psrav8.hi 1787 IID = Intrinsic::x86_avx512_psrav_w_128; 1788 else if (Size == 'h' && Name[17] == '1') // avx512.mask.psrav16.hi 1789 IID = Intrinsic::x86_avx512_psrav_w_256; 1790 else if (Name[17] == '3' && Name[18] == '2') // avx512.mask.psrav32hi 1791 IID = Intrinsic::x86_avx512_psrav_w_512; 1792 else 1793 llvm_unreachable("Unexpected size"); 1794 } else if (Name.endswith(".128")) { 1795 if (Size == 'd') // avx512.mask.psra.d.128, avx512.mask.psra.di.128 1796 IID = IsImmediate ? Intrinsic::x86_sse2_psrai_d 1797 : Intrinsic::x86_sse2_psra_d; 1798 else if (Size == 'q') // avx512.mask.psra.q.128, avx512.mask.psra.qi.128 1799 IID = IsImmediate ? Intrinsic::x86_avx512_psrai_q_128 : 1800 IsVariable ? Intrinsic::x86_avx512_psrav_q_128 : 1801 Intrinsic::x86_avx512_psra_q_128; 1802 else if (Size == 'w') // avx512.mask.psra.w.128, avx512.mask.psra.wi.128 1803 IID = IsImmediate ? Intrinsic::x86_sse2_psrai_w 1804 : Intrinsic::x86_sse2_psra_w; 1805 else 1806 llvm_unreachable("Unexpected size"); 1807 } else if (Name.endswith(".256")) { 1808 if (Size == 'd') // avx512.mask.psra.d.256, avx512.mask.psra.di.256 1809 IID = IsImmediate ? Intrinsic::x86_avx2_psrai_d 1810 : Intrinsic::x86_avx2_psra_d; 1811 else if (Size == 'q') // avx512.mask.psra.q.256, avx512.mask.psra.qi.256 1812 IID = IsImmediate ? Intrinsic::x86_avx512_psrai_q_256 : 1813 IsVariable ? Intrinsic::x86_avx512_psrav_q_256 : 1814 Intrinsic::x86_avx512_psra_q_256; 1815 else if (Size == 'w') // avx512.mask.psra.w.256, avx512.mask.psra.wi.256 1816 IID = IsImmediate ? Intrinsic::x86_avx2_psrai_w 1817 : Intrinsic::x86_avx2_psra_w; 1818 else 1819 llvm_unreachable("Unexpected size"); 1820 } else { 1821 if (Size == 'd') // psra.di.512, psrai.d, psra.d, psrav.d.512 1822 IID = IsImmediate ? Intrinsic::x86_avx512_psrai_d_512 : 1823 IsVariable ? Intrinsic::x86_avx512_psrav_d_512 : 1824 Intrinsic::x86_avx512_psra_d_512; 1825 else if (Size == 'q') // psra.qi.512, psrai.q, psra.q 1826 IID = IsImmediate ? Intrinsic::x86_avx512_psrai_q_512 : 1827 IsVariable ? Intrinsic::x86_avx512_psrav_q_512 : 1828 Intrinsic::x86_avx512_psra_q_512; 1829 else if (Size == 'w') // psra.wi.512, psrai.w, psra.w 1830 IID = IsImmediate ? Intrinsic::x86_avx512_psrai_w_512 1831 : Intrinsic::x86_avx512_psra_w_512; 1832 else 1833 llvm_unreachable("Unexpected size"); 1834 } 1835 1836 Rep = UpgradeX86MaskedShift(Builder, *CI, IID); 1837 } else if (IsX86 && Name.startswith("avx512.mask.move.s")) { 1838 Rep = upgradeMaskedMove(Builder, *CI); 1839 } else if (IsX86 && Name.startswith("avx512.mask.vpermilvar.")) { 1840 Intrinsic::ID IID; 1841 if (Name.endswith("ps.128")) 1842 IID = Intrinsic::x86_avx_vpermilvar_ps; 1843 else if (Name.endswith("pd.128")) 1844 IID = Intrinsic::x86_avx_vpermilvar_pd; 1845 else if (Name.endswith("ps.256")) 1846 IID = Intrinsic::x86_avx_vpermilvar_ps_256; 1847 else if (Name.endswith("pd.256")) 1848 IID = Intrinsic::x86_avx_vpermilvar_pd_256; 1849 else if (Name.endswith("ps.512")) 1850 IID = Intrinsic::x86_avx512_vpermilvar_ps_512; 1851 else if (Name.endswith("pd.512")) 1852 IID = Intrinsic::x86_avx512_vpermilvar_pd_512; 1853 else 1854 llvm_unreachable("Unexpected vpermilvar intrinsic"); 1855 1856 Function *Intrin = Intrinsic::getDeclaration(F->getParent(), IID); 1857 Rep = Builder.CreateCall(Intrin, 1858 { CI->getArgOperand(0), CI->getArgOperand(1) }); 1859 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1860 CI->getArgOperand(2)); 1861 } else if (IsNVVM && (Name == "abs.i" || Name == "abs.ll")) { 1862 Value *Arg = CI->getArgOperand(0); 1863 Value *Neg = Builder.CreateNeg(Arg, "neg"); 1864 Value *Cmp = Builder.CreateICmpSGE( 1865 Arg, llvm::Constant::getNullValue(Arg->getType()), "abs.cond"); 1866 Rep = Builder.CreateSelect(Cmp, Arg, Neg, "abs"); 1867 } else if (IsNVVM && (Name == "max.i" || Name == "max.ll" || 1868 Name == "max.ui" || Name == "max.ull")) { 1869 Value *Arg0 = CI->getArgOperand(0); 1870 Value *Arg1 = CI->getArgOperand(1); 1871 Value *Cmp = Name.endswith(".ui") || Name.endswith(".ull") 1872 ? Builder.CreateICmpUGE(Arg0, Arg1, "max.cond") 1873 : Builder.CreateICmpSGE(Arg0, Arg1, "max.cond"); 1874 Rep = Builder.CreateSelect(Cmp, Arg0, Arg1, "max"); 1875 } else if (IsNVVM && (Name == "min.i" || Name == "min.ll" || 1876 Name == "min.ui" || Name == "min.ull")) { 1877 Value *Arg0 = CI->getArgOperand(0); 1878 Value *Arg1 = CI->getArgOperand(1); 1879 Value *Cmp = Name.endswith(".ui") || Name.endswith(".ull") 1880 ? Builder.CreateICmpULE(Arg0, Arg1, "min.cond") 1881 : Builder.CreateICmpSLE(Arg0, Arg1, "min.cond"); 1882 Rep = Builder.CreateSelect(Cmp, Arg0, Arg1, "min"); 1883 } else if (IsNVVM && Name == "clz.ll") { 1884 // llvm.nvvm.clz.ll returns an i32, but llvm.ctlz.i64 and returns an i64. 1885 Value *Arg = CI->getArgOperand(0); 1886 Value *Ctlz = Builder.CreateCall( 1887 Intrinsic::getDeclaration(F->getParent(), Intrinsic::ctlz, 1888 {Arg->getType()}), 1889 {Arg, Builder.getFalse()}, "ctlz"); 1890 Rep = Builder.CreateTrunc(Ctlz, Builder.getInt32Ty(), "ctlz.trunc"); 1891 } else if (IsNVVM && Name == "popc.ll") { 1892 // llvm.nvvm.popc.ll returns an i32, but llvm.ctpop.i64 and returns an 1893 // i64. 1894 Value *Arg = CI->getArgOperand(0); 1895 Value *Popc = Builder.CreateCall( 1896 Intrinsic::getDeclaration(F->getParent(), Intrinsic::ctpop, 1897 {Arg->getType()}), 1898 Arg, "ctpop"); 1899 Rep = Builder.CreateTrunc(Popc, Builder.getInt32Ty(), "ctpop.trunc"); 1900 } else if (IsNVVM && Name == "h2f") { 1901 Rep = Builder.CreateCall(Intrinsic::getDeclaration( 1902 F->getParent(), Intrinsic::convert_from_fp16, 1903 {Builder.getFloatTy()}), 1904 CI->getArgOperand(0), "h2f"); 1905 } else { 1906 llvm_unreachable("Unknown function for CallInst upgrade."); 1907 } 1908 1909 if (Rep) 1910 CI->replaceAllUsesWith(Rep); 1911 CI->eraseFromParent(); 1912 return; 1913 } 1914 1915 CallInst *NewCall = nullptr; 1916 switch (NewFn->getIntrinsicID()) { 1917 default: { 1918 // Handle generic mangling change, but nothing else 1919 assert( 1920 (CI->getCalledFunction()->getName() != NewFn->getName()) && 1921 "Unknown function for CallInst upgrade and isn't just a name change"); 1922 CI->setCalledFunction(NewFn); 1923 return; 1924 } 1925 1926 case Intrinsic::arm_neon_vld1: 1927 case Intrinsic::arm_neon_vld2: 1928 case Intrinsic::arm_neon_vld3: 1929 case Intrinsic::arm_neon_vld4: 1930 case Intrinsic::arm_neon_vld2lane: 1931 case Intrinsic::arm_neon_vld3lane: 1932 case Intrinsic::arm_neon_vld4lane: 1933 case Intrinsic::arm_neon_vst1: 1934 case Intrinsic::arm_neon_vst2: 1935 case Intrinsic::arm_neon_vst3: 1936 case Intrinsic::arm_neon_vst4: 1937 case Intrinsic::arm_neon_vst2lane: 1938 case Intrinsic::arm_neon_vst3lane: 1939 case Intrinsic::arm_neon_vst4lane: { 1940 SmallVector<Value *, 4> Args(CI->arg_operands().begin(), 1941 CI->arg_operands().end()); 1942 NewCall = Builder.CreateCall(NewFn, Args); 1943 break; 1944 } 1945 1946 case Intrinsic::bitreverse: 1947 NewCall = Builder.CreateCall(NewFn, {CI->getArgOperand(0)}); 1948 break; 1949 1950 case Intrinsic::ctlz: 1951 case Intrinsic::cttz: 1952 assert(CI->getNumArgOperands() == 1 && 1953 "Mismatch between function args and call args"); 1954 NewCall = 1955 Builder.CreateCall(NewFn, {CI->getArgOperand(0), Builder.getFalse()}); 1956 break; 1957 1958 case Intrinsic::objectsize: { 1959 Value *NullIsUnknownSize = CI->getNumArgOperands() == 2 1960 ? Builder.getFalse() 1961 : CI->getArgOperand(2); 1962 NewCall = Builder.CreateCall( 1963 NewFn, {CI->getArgOperand(0), CI->getArgOperand(1), NullIsUnknownSize}); 1964 break; 1965 } 1966 1967 case Intrinsic::ctpop: 1968 NewCall = Builder.CreateCall(NewFn, {CI->getArgOperand(0)}); 1969 break; 1970 1971 case Intrinsic::convert_from_fp16: 1972 NewCall = Builder.CreateCall(NewFn, {CI->getArgOperand(0)}); 1973 break; 1974 1975 case Intrinsic::x86_xop_vfrcz_ss: 1976 case Intrinsic::x86_xop_vfrcz_sd: 1977 NewCall = Builder.CreateCall(NewFn, {CI->getArgOperand(1)}); 1978 break; 1979 1980 case Intrinsic::x86_xop_vpermil2pd: 1981 case Intrinsic::x86_xop_vpermil2ps: 1982 case Intrinsic::x86_xop_vpermil2pd_256: 1983 case Intrinsic::x86_xop_vpermil2ps_256: { 1984 SmallVector<Value *, 4> Args(CI->arg_operands().begin(), 1985 CI->arg_operands().end()); 1986 VectorType *FltIdxTy = cast<VectorType>(Args[2]->getType()); 1987 VectorType *IntIdxTy = VectorType::getInteger(FltIdxTy); 1988 Args[2] = Builder.CreateBitCast(Args[2], IntIdxTy); 1989 NewCall = Builder.CreateCall(NewFn, Args); 1990 break; 1991 } 1992 1993 case Intrinsic::x86_sse41_ptestc: 1994 case Intrinsic::x86_sse41_ptestz: 1995 case Intrinsic::x86_sse41_ptestnzc: { 1996 // The arguments for these intrinsics used to be v4f32, and changed 1997 // to v2i64. This is purely a nop, since those are bitwise intrinsics. 1998 // So, the only thing required is a bitcast for both arguments. 1999 // First, check the arguments have the old type. 2000 Value *Arg0 = CI->getArgOperand(0); 2001 if (Arg0->getType() != VectorType::get(Type::getFloatTy(C), 4)) 2002 return; 2003 2004 // Old intrinsic, add bitcasts 2005 Value *Arg1 = CI->getArgOperand(1); 2006 2007 Type *NewVecTy = VectorType::get(Type::getInt64Ty(C), 2); 2008 2009 Value *BC0 = Builder.CreateBitCast(Arg0, NewVecTy, "cast"); 2010 Value *BC1 = Builder.CreateBitCast(Arg1, NewVecTy, "cast"); 2011 2012 NewCall = Builder.CreateCall(NewFn, {BC0, BC1}); 2013 break; 2014 } 2015 2016 case Intrinsic::x86_sse41_insertps: 2017 case Intrinsic::x86_sse41_dppd: 2018 case Intrinsic::x86_sse41_dpps: 2019 case Intrinsic::x86_sse41_mpsadbw: 2020 case Intrinsic::x86_avx_dp_ps_256: 2021 case Intrinsic::x86_avx2_mpsadbw: { 2022 // Need to truncate the last argument from i32 to i8 -- this argument models 2023 // an inherently 8-bit immediate operand to these x86 instructions. 2024 SmallVector<Value *, 4> Args(CI->arg_operands().begin(), 2025 CI->arg_operands().end()); 2026 2027 // Replace the last argument with a trunc. 2028 Args.back() = Builder.CreateTrunc(Args.back(), Type::getInt8Ty(C), "trunc"); 2029 NewCall = Builder.CreateCall(NewFn, Args); 2030 break; 2031 } 2032 2033 case Intrinsic::thread_pointer: { 2034 NewCall = Builder.CreateCall(NewFn, {}); 2035 break; 2036 } 2037 2038 case Intrinsic::invariant_start: 2039 case Intrinsic::invariant_end: 2040 case Intrinsic::masked_load: 2041 case Intrinsic::masked_store: { 2042 SmallVector<Value *, 4> Args(CI->arg_operands().begin(), 2043 CI->arg_operands().end()); 2044 NewCall = Builder.CreateCall(NewFn, Args); 2045 break; 2046 } 2047 } 2048 assert(NewCall && "Should have either set this variable or returned through " 2049 "the default case"); 2050 std::string Name = CI->getName(); 2051 if (!Name.empty()) { 2052 CI->setName(Name + ".old"); 2053 NewCall->setName(Name); 2054 } 2055 CI->replaceAllUsesWith(NewCall); 2056 CI->eraseFromParent(); 2057 } 2058 2059 void llvm::UpgradeCallsToIntrinsic(Function *F) { 2060 assert(F && "Illegal attempt to upgrade a non-existent intrinsic."); 2061 2062 // Check if this function should be upgraded and get the replacement function 2063 // if there is one. 2064 Function *NewFn; 2065 if (UpgradeIntrinsicFunction(F, NewFn)) { 2066 // Replace all users of the old function with the new function or new 2067 // instructions. This is not a range loop because the call is deleted. 2068 for (auto UI = F->user_begin(), UE = F->user_end(); UI != UE; ) 2069 if (CallInst *CI = dyn_cast<CallInst>(*UI++)) 2070 UpgradeIntrinsicCall(CI, NewFn); 2071 2072 // Remove old function, no longer used, from the module. 2073 F->eraseFromParent(); 2074 } 2075 } 2076 2077 MDNode *llvm::UpgradeTBAANode(MDNode &MD) { 2078 // Check if the tag uses struct-path aware TBAA format. 2079 if (isa<MDNode>(MD.getOperand(0)) && MD.getNumOperands() >= 3) 2080 return &MD; 2081 2082 auto &Context = MD.getContext(); 2083 if (MD.getNumOperands() == 3) { 2084 Metadata *Elts[] = {MD.getOperand(0), MD.getOperand(1)}; 2085 MDNode *ScalarType = MDNode::get(Context, Elts); 2086 // Create a MDNode <ScalarType, ScalarType, offset 0, const> 2087 Metadata *Elts2[] = {ScalarType, ScalarType, 2088 ConstantAsMetadata::get( 2089 Constant::getNullValue(Type::getInt64Ty(Context))), 2090 MD.getOperand(2)}; 2091 return MDNode::get(Context, Elts2); 2092 } 2093 // Create a MDNode <MD, MD, offset 0> 2094 Metadata *Elts[] = {&MD, &MD, ConstantAsMetadata::get(Constant::getNullValue( 2095 Type::getInt64Ty(Context)))}; 2096 return MDNode::get(Context, Elts); 2097 } 2098 2099 Instruction *llvm::UpgradeBitCastInst(unsigned Opc, Value *V, Type *DestTy, 2100 Instruction *&Temp) { 2101 if (Opc != Instruction::BitCast) 2102 return nullptr; 2103 2104 Temp = nullptr; 2105 Type *SrcTy = V->getType(); 2106 if (SrcTy->isPtrOrPtrVectorTy() && DestTy->isPtrOrPtrVectorTy() && 2107 SrcTy->getPointerAddressSpace() != DestTy->getPointerAddressSpace()) { 2108 LLVMContext &Context = V->getContext(); 2109 2110 // We have no information about target data layout, so we assume that 2111 // the maximum pointer size is 64bit. 2112 Type *MidTy = Type::getInt64Ty(Context); 2113 Temp = CastInst::Create(Instruction::PtrToInt, V, MidTy); 2114 2115 return CastInst::Create(Instruction::IntToPtr, Temp, DestTy); 2116 } 2117 2118 return nullptr; 2119 } 2120 2121 Value *llvm::UpgradeBitCastExpr(unsigned Opc, Constant *C, Type *DestTy) { 2122 if (Opc != Instruction::BitCast) 2123 return nullptr; 2124 2125 Type *SrcTy = C->getType(); 2126 if (SrcTy->isPtrOrPtrVectorTy() && DestTy->isPtrOrPtrVectorTy() && 2127 SrcTy->getPointerAddressSpace() != DestTy->getPointerAddressSpace()) { 2128 LLVMContext &Context = C->getContext(); 2129 2130 // We have no information about target data layout, so we assume that 2131 // the maximum pointer size is 64bit. 2132 Type *MidTy = Type::getInt64Ty(Context); 2133 2134 return ConstantExpr::getIntToPtr(ConstantExpr::getPtrToInt(C, MidTy), 2135 DestTy); 2136 } 2137 2138 return nullptr; 2139 } 2140 2141 /// Check the debug info version number, if it is out-dated, drop the debug 2142 /// info. Return true if module is modified. 2143 bool llvm::UpgradeDebugInfo(Module &M) { 2144 unsigned Version = getDebugMetadataVersionFromModule(M); 2145 if (Version == DEBUG_METADATA_VERSION) 2146 return false; 2147 2148 bool RetCode = StripDebugInfo(M); 2149 if (RetCode) { 2150 DiagnosticInfoDebugMetadataVersion DiagVersion(M, Version); 2151 M.getContext().diagnose(DiagVersion); 2152 } 2153 return RetCode; 2154 } 2155 2156 bool llvm::UpgradeModuleFlags(Module &M) { 2157 const NamedMDNode *ModFlags = M.getModuleFlagsMetadata(); 2158 if (!ModFlags) 2159 return false; 2160 2161 bool HasObjCFlag = false, HasClassProperties = false; 2162 for (unsigned I = 0, E = ModFlags->getNumOperands(); I != E; ++I) { 2163 MDNode *Op = ModFlags->getOperand(I); 2164 if (Op->getNumOperands() < 2) 2165 continue; 2166 MDString *ID = dyn_cast_or_null<MDString>(Op->getOperand(1)); 2167 if (!ID) 2168 continue; 2169 if (ID->getString() == "Objective-C Image Info Version") 2170 HasObjCFlag = true; 2171 if (ID->getString() == "Objective-C Class Properties") 2172 HasClassProperties = true; 2173 } 2174 // "Objective-C Class Properties" is recently added for Objective-C. We 2175 // upgrade ObjC bitcodes to contain a "Objective-C Class Properties" module 2176 // flag of value 0, so we can correclty downgrade this flag when trying to 2177 // link an ObjC bitcode without this module flag with an ObjC bitcode with 2178 // this module flag. 2179 if (HasObjCFlag && !HasClassProperties) { 2180 M.addModuleFlag(llvm::Module::Override, "Objective-C Class Properties", 2181 (uint32_t)0); 2182 return true; 2183 } 2184 return false; 2185 } 2186 2187 static bool isOldLoopArgument(Metadata *MD) { 2188 auto *T = dyn_cast_or_null<MDTuple>(MD); 2189 if (!T) 2190 return false; 2191 if (T->getNumOperands() < 1) 2192 return false; 2193 auto *S = dyn_cast_or_null<MDString>(T->getOperand(0)); 2194 if (!S) 2195 return false; 2196 return S->getString().startswith("llvm.vectorizer."); 2197 } 2198 2199 static MDString *upgradeLoopTag(LLVMContext &C, StringRef OldTag) { 2200 StringRef OldPrefix = "llvm.vectorizer."; 2201 assert(OldTag.startswith(OldPrefix) && "Expected old prefix"); 2202 2203 if (OldTag == "llvm.vectorizer.unroll") 2204 return MDString::get(C, "llvm.loop.interleave.count"); 2205 2206 return MDString::get( 2207 C, (Twine("llvm.loop.vectorize.") + OldTag.drop_front(OldPrefix.size())) 2208 .str()); 2209 } 2210 2211 static Metadata *upgradeLoopArgument(Metadata *MD) { 2212 auto *T = dyn_cast_or_null<MDTuple>(MD); 2213 if (!T) 2214 return MD; 2215 if (T->getNumOperands() < 1) 2216 return MD; 2217 auto *OldTag = dyn_cast_or_null<MDString>(T->getOperand(0)); 2218 if (!OldTag) 2219 return MD; 2220 if (!OldTag->getString().startswith("llvm.vectorizer.")) 2221 return MD; 2222 2223 // This has an old tag. Upgrade it. 2224 SmallVector<Metadata *, 8> Ops; 2225 Ops.reserve(T->getNumOperands()); 2226 Ops.push_back(upgradeLoopTag(T->getContext(), OldTag->getString())); 2227 for (unsigned I = 1, E = T->getNumOperands(); I != E; ++I) 2228 Ops.push_back(T->getOperand(I)); 2229 2230 return MDTuple::get(T->getContext(), Ops); 2231 } 2232 2233 MDNode *llvm::upgradeInstructionLoopAttachment(MDNode &N) { 2234 auto *T = dyn_cast<MDTuple>(&N); 2235 if (!T) 2236 return &N; 2237 2238 if (none_of(T->operands(), isOldLoopArgument)) 2239 return &N; 2240 2241 SmallVector<Metadata *, 8> Ops; 2242 Ops.reserve(T->getNumOperands()); 2243 for (Metadata *MD : T->operands()) 2244 Ops.push_back(upgradeLoopArgument(MD)); 2245 2246 return MDTuple::get(T->getContext(), Ops); 2247 } 2248