1 //===-- AutoUpgrade.cpp - Implement auto-upgrade helper functions ---------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements the auto-upgrade helper functions. 11 // This is where deprecated IR intrinsics and other IR features are updated to 12 // current specifications. 13 // 14 //===----------------------------------------------------------------------===// 15 16 #include "llvm/IR/AutoUpgrade.h" 17 #include "llvm/ADT/StringSwitch.h" 18 #include "llvm/IR/Constants.h" 19 #include "llvm/IR/DIBuilder.h" 20 #include "llvm/IR/DebugInfo.h" 21 #include "llvm/IR/DiagnosticInfo.h" 22 #include "llvm/IR/Function.h" 23 #include "llvm/IR/IRBuilder.h" 24 #include "llvm/IR/Instruction.h" 25 #include "llvm/IR/IntrinsicInst.h" 26 #include "llvm/IR/LLVMContext.h" 27 #include "llvm/IR/Module.h" 28 #include "llvm/IR/Verifier.h" 29 #include "llvm/Support/ErrorHandling.h" 30 #include "llvm/Support/Regex.h" 31 #include <cstring> 32 using namespace llvm; 33 34 static void rename(GlobalValue *GV) { GV->setName(GV->getName() + ".old"); } 35 36 // Upgrade the declarations of the SSE4.1 ptest intrinsics whose arguments have 37 // changed their type from v4f32 to v2i64. 38 static bool UpgradePTESTIntrinsic(Function* F, Intrinsic::ID IID, 39 Function *&NewFn) { 40 // Check whether this is an old version of the function, which received 41 // v4f32 arguments. 42 Type *Arg0Type = F->getFunctionType()->getParamType(0); 43 if (Arg0Type != VectorType::get(Type::getFloatTy(F->getContext()), 4)) 44 return false; 45 46 // Yes, it's old, replace it with new version. 47 rename(F); 48 NewFn = Intrinsic::getDeclaration(F->getParent(), IID); 49 return true; 50 } 51 52 // Upgrade the declarations of intrinsic functions whose 8-bit immediate mask 53 // arguments have changed their type from i32 to i8. 54 static bool UpgradeX86IntrinsicsWith8BitMask(Function *F, Intrinsic::ID IID, 55 Function *&NewFn) { 56 // Check that the last argument is an i32. 57 Type *LastArgType = F->getFunctionType()->getParamType( 58 F->getFunctionType()->getNumParams() - 1); 59 if (!LastArgType->isIntegerTy(32)) 60 return false; 61 62 // Move this function aside and map down. 63 rename(F); 64 NewFn = Intrinsic::getDeclaration(F->getParent(), IID); 65 return true; 66 } 67 68 static bool ShouldUpgradeX86Intrinsic(Function *F, StringRef Name) { 69 // All of the intrinsics matches below should be marked with which llvm 70 // version started autoupgrading them. At some point in the future we would 71 // like to use this information to remove upgrade code for some older 72 // intrinsics. It is currently undecided how we will determine that future 73 // point. 74 if (Name=="ssse3.pabs.b.128" || // Added in 6.0 75 Name=="ssse3.pabs.w.128" || // Added in 6.0 76 Name=="ssse3.pabs.d.128" || // Added in 6.0 77 Name.startswith("avx512.mask.shuf.i") || // Added in 6.0 78 Name.startswith("avx512.mask.shuf.f") || // Added in 6.0 79 Name.startswith("avx512.kunpck") || //added in 6.0 80 Name.startswith("avx2.pabs.") || // Added in 6.0 81 Name.startswith("avx512.mask.pabs.") || // Added in 6.0 82 Name.startswith("avx512.broadcastm") || // Added in 6.0 83 Name.startswith("avx512.mask.pbroadcast") || // Added in 6.0 84 Name.startswith("sse2.pcmpeq.") || // Added in 3.1 85 Name.startswith("sse2.pcmpgt.") || // Added in 3.1 86 Name.startswith("avx2.pcmpeq.") || // Added in 3.1 87 Name.startswith("avx2.pcmpgt.") || // Added in 3.1 88 Name.startswith("avx512.mask.pcmpeq.") || // Added in 3.9 89 Name.startswith("avx512.mask.pcmpgt.") || // Added in 3.9 90 Name.startswith("avx.vperm2f128.") || // Added in 6.0 91 Name == "avx2.vperm2i128" || // Added in 6.0 92 Name == "sse.add.ss" || // Added in 4.0 93 Name == "sse2.add.sd" || // Added in 4.0 94 Name == "sse.sub.ss" || // Added in 4.0 95 Name == "sse2.sub.sd" || // Added in 4.0 96 Name == "sse.mul.ss" || // Added in 4.0 97 Name == "sse2.mul.sd" || // Added in 4.0 98 Name == "sse.div.ss" || // Added in 4.0 99 Name == "sse2.div.sd" || // Added in 4.0 100 Name == "sse41.pmaxsb" || // Added in 3.9 101 Name == "sse2.pmaxs.w" || // Added in 3.9 102 Name == "sse41.pmaxsd" || // Added in 3.9 103 Name == "sse2.pmaxu.b" || // Added in 3.9 104 Name == "sse41.pmaxuw" || // Added in 3.9 105 Name == "sse41.pmaxud" || // Added in 3.9 106 Name == "sse41.pminsb" || // Added in 3.9 107 Name == "sse2.pmins.w" || // Added in 3.9 108 Name == "sse41.pminsd" || // Added in 3.9 109 Name == "sse2.pminu.b" || // Added in 3.9 110 Name == "sse41.pminuw" || // Added in 3.9 111 Name == "sse41.pminud" || // Added in 3.9 112 Name == "avx512.kand.w" || // Added in 7.0 113 Name == "avx512.kandn.w" || // Added in 7.0 114 Name == "avx512.knot.w" || // Added in 7.0 115 Name == "avx512.kor.w" || // Added in 7.0 116 Name == "avx512.kxor.w" || // Added in 7.0 117 Name == "avx512.kxnor.w" || // Added in 7.0 118 Name.startswith("avx512.mask.pshuf.b.") || // Added in 4.0 119 Name.startswith("avx2.pmax") || // Added in 3.9 120 Name.startswith("avx2.pmin") || // Added in 3.9 121 Name.startswith("avx512.mask.pmax") || // Added in 4.0 122 Name.startswith("avx512.mask.pmin") || // Added in 4.0 123 Name.startswith("avx2.vbroadcast") || // Added in 3.8 124 Name.startswith("avx2.pbroadcast") || // Added in 3.8 125 Name.startswith("avx.vpermil.") || // Added in 3.1 126 Name.startswith("sse2.pshuf") || // Added in 3.9 127 Name.startswith("avx512.pbroadcast") || // Added in 3.9 128 Name.startswith("avx512.mask.broadcast.s") || // Added in 3.9 129 Name.startswith("avx512.mask.movddup") || // Added in 3.9 130 Name.startswith("avx512.mask.movshdup") || // Added in 3.9 131 Name.startswith("avx512.mask.movsldup") || // Added in 3.9 132 Name.startswith("avx512.mask.pshuf.d.") || // Added in 3.9 133 Name.startswith("avx512.mask.pshufl.w.") || // Added in 3.9 134 Name.startswith("avx512.mask.pshufh.w.") || // Added in 3.9 135 Name.startswith("avx512.mask.shuf.p") || // Added in 4.0 136 Name.startswith("avx512.mask.vpermil.p") || // Added in 3.9 137 Name.startswith("avx512.mask.perm.df.") || // Added in 3.9 138 Name.startswith("avx512.mask.perm.di.") || // Added in 3.9 139 Name.startswith("avx512.mask.punpckl") || // Added in 3.9 140 Name.startswith("avx512.mask.punpckh") || // Added in 3.9 141 Name.startswith("avx512.mask.unpckl.") || // Added in 3.9 142 Name.startswith("avx512.mask.unpckh.") || // Added in 3.9 143 Name.startswith("avx512.mask.pand.") || // Added in 3.9 144 Name.startswith("avx512.mask.pandn.") || // Added in 3.9 145 Name.startswith("avx512.mask.por.") || // Added in 3.9 146 Name.startswith("avx512.mask.pxor.") || // Added in 3.9 147 Name.startswith("avx512.mask.and.") || // Added in 3.9 148 Name.startswith("avx512.mask.andn.") || // Added in 3.9 149 Name.startswith("avx512.mask.or.") || // Added in 3.9 150 Name.startswith("avx512.mask.xor.") || // Added in 3.9 151 Name.startswith("avx512.mask.padd.") || // Added in 4.0 152 Name.startswith("avx512.mask.psub.") || // Added in 4.0 153 Name.startswith("avx512.mask.pmull.") || // Added in 4.0 154 Name.startswith("avx512.mask.cvtdq2pd.") || // Added in 4.0 155 Name.startswith("avx512.mask.cvtudq2pd.") || // Added in 4.0 156 Name.startswith("avx512.mask.pmul.dq.") || // Added in 4.0 157 Name.startswith("avx512.mask.pmulu.dq.") || // Added in 4.0 158 Name.startswith("avx512.mask.packsswb.") || // Added in 5.0 159 Name.startswith("avx512.mask.packssdw.") || // Added in 5.0 160 Name.startswith("avx512.mask.packuswb.") || // Added in 5.0 161 Name.startswith("avx512.mask.packusdw.") || // Added in 5.0 162 Name.startswith("avx512.mask.cmp.b") || // Added in 5.0 163 Name.startswith("avx512.mask.cmp.d") || // Added in 5.0 164 Name.startswith("avx512.mask.cmp.q") || // Added in 5.0 165 Name.startswith("avx512.mask.cmp.w") || // Added in 5.0 166 Name.startswith("avx512.mask.ucmp.") || // Added in 5.0 167 Name.startswith("avx512.cvtb2mask.") || // Added in 7.0 168 Name.startswith("avx512.cvtw2mask.") || // Added in 7.0 169 Name.startswith("avx512.cvtd2mask.") || // Added in 7.0 170 Name.startswith("avx512.cvtq2mask.") || // Added in 7.0 171 Name == "avx512.mask.add.pd.128" || // Added in 4.0 172 Name == "avx512.mask.add.pd.256" || // Added in 4.0 173 Name == "avx512.mask.add.ps.128" || // Added in 4.0 174 Name == "avx512.mask.add.ps.256" || // Added in 4.0 175 Name == "avx512.mask.div.pd.128" || // Added in 4.0 176 Name == "avx512.mask.div.pd.256" || // Added in 4.0 177 Name == "avx512.mask.div.ps.128" || // Added in 4.0 178 Name == "avx512.mask.div.ps.256" || // Added in 4.0 179 Name == "avx512.mask.mul.pd.128" || // Added in 4.0 180 Name == "avx512.mask.mul.pd.256" || // Added in 4.0 181 Name == "avx512.mask.mul.ps.128" || // Added in 4.0 182 Name == "avx512.mask.mul.ps.256" || // Added in 4.0 183 Name == "avx512.mask.sub.pd.128" || // Added in 4.0 184 Name == "avx512.mask.sub.pd.256" || // Added in 4.0 185 Name == "avx512.mask.sub.ps.128" || // Added in 4.0 186 Name == "avx512.mask.sub.ps.256" || // Added in 4.0 187 Name == "avx512.mask.max.pd.128" || // Added in 5.0 188 Name == "avx512.mask.max.pd.256" || // Added in 5.0 189 Name == "avx512.mask.max.ps.128" || // Added in 5.0 190 Name == "avx512.mask.max.ps.256" || // Added in 5.0 191 Name == "avx512.mask.min.pd.128" || // Added in 5.0 192 Name == "avx512.mask.min.pd.256" || // Added in 5.0 193 Name == "avx512.mask.min.ps.128" || // Added in 5.0 194 Name == "avx512.mask.min.ps.256" || // Added in 5.0 195 Name.startswith("avx512.mask.vpermilvar.") || // Added in 4.0 196 Name.startswith("avx512.mask.psll.d") || // Added in 4.0 197 Name.startswith("avx512.mask.psll.q") || // Added in 4.0 198 Name.startswith("avx512.mask.psll.w") || // Added in 4.0 199 Name.startswith("avx512.mask.psra.d") || // Added in 4.0 200 Name.startswith("avx512.mask.psra.q") || // Added in 4.0 201 Name.startswith("avx512.mask.psra.w") || // Added in 4.0 202 Name.startswith("avx512.mask.psrl.d") || // Added in 4.0 203 Name.startswith("avx512.mask.psrl.q") || // Added in 4.0 204 Name.startswith("avx512.mask.psrl.w") || // Added in 4.0 205 Name.startswith("avx512.mask.pslli") || // Added in 4.0 206 Name.startswith("avx512.mask.psrai") || // Added in 4.0 207 Name.startswith("avx512.mask.psrli") || // Added in 4.0 208 Name.startswith("avx512.mask.psllv") || // Added in 4.0 209 Name.startswith("avx512.mask.psrav") || // Added in 4.0 210 Name.startswith("avx512.mask.psrlv") || // Added in 4.0 211 Name.startswith("sse41.pmovsx") || // Added in 3.8 212 Name.startswith("sse41.pmovzx") || // Added in 3.9 213 Name.startswith("avx2.pmovsx") || // Added in 3.9 214 Name.startswith("avx2.pmovzx") || // Added in 3.9 215 Name.startswith("avx512.mask.pmovsx") || // Added in 4.0 216 Name.startswith("avx512.mask.pmovzx") || // Added in 4.0 217 Name.startswith("avx512.mask.lzcnt.") || // Added in 5.0 218 Name == "sse2.cvtdq2pd" || // Added in 3.9 219 Name == "sse2.cvtps2pd" || // Added in 3.9 220 Name == "avx.cvtdq2.pd.256" || // Added in 3.9 221 Name == "avx.cvt.ps2.pd.256" || // Added in 3.9 222 Name.startswith("avx.vinsertf128.") || // Added in 3.7 223 Name == "avx2.vinserti128" || // Added in 3.7 224 Name.startswith("avx512.mask.insert") || // Added in 4.0 225 Name.startswith("avx.vextractf128.") || // Added in 3.7 226 Name == "avx2.vextracti128" || // Added in 3.7 227 Name.startswith("avx512.mask.vextract") || // Added in 4.0 228 Name.startswith("sse4a.movnt.") || // Added in 3.9 229 Name.startswith("avx.movnt.") || // Added in 3.2 230 Name.startswith("avx512.storent.") || // Added in 3.9 231 Name == "sse41.movntdqa" || // Added in 5.0 232 Name == "avx2.movntdqa" || // Added in 5.0 233 Name == "avx512.movntdqa" || // Added in 5.0 234 Name == "sse2.storel.dq" || // Added in 3.9 235 Name.startswith("sse.storeu.") || // Added in 3.9 236 Name.startswith("sse2.storeu.") || // Added in 3.9 237 Name.startswith("avx.storeu.") || // Added in 3.9 238 Name.startswith("avx512.mask.storeu.") || // Added in 3.9 239 Name.startswith("avx512.mask.store.p") || // Added in 3.9 240 Name.startswith("avx512.mask.store.b.") || // Added in 3.9 241 Name.startswith("avx512.mask.store.w.") || // Added in 3.9 242 Name.startswith("avx512.mask.store.d.") || // Added in 3.9 243 Name.startswith("avx512.mask.store.q.") || // Added in 3.9 244 Name.startswith("avx512.mask.loadu.") || // Added in 3.9 245 Name.startswith("avx512.mask.load.") || // Added in 3.9 246 Name == "sse42.crc32.64.8" || // Added in 3.4 247 Name.startswith("avx.vbroadcast.s") || // Added in 3.5 248 Name.startswith("avx512.mask.palignr.") || // Added in 3.9 249 Name.startswith("avx512.mask.valign.") || // Added in 4.0 250 Name.startswith("sse2.psll.dq") || // Added in 3.7 251 Name.startswith("sse2.psrl.dq") || // Added in 3.7 252 Name.startswith("avx2.psll.dq") || // Added in 3.7 253 Name.startswith("avx2.psrl.dq") || // Added in 3.7 254 Name.startswith("avx512.psll.dq") || // Added in 3.9 255 Name.startswith("avx512.psrl.dq") || // Added in 3.9 256 Name == "sse41.pblendw" || // Added in 3.7 257 Name.startswith("sse41.blendp") || // Added in 3.7 258 Name.startswith("avx.blend.p") || // Added in 3.7 259 Name == "avx2.pblendw" || // Added in 3.7 260 Name.startswith("avx2.pblendd.") || // Added in 3.7 261 Name.startswith("avx.vbroadcastf128") || // Added in 4.0 262 Name == "avx2.vbroadcasti128" || // Added in 3.7 263 Name.startswith("avx512.mask.broadcastf") || // Added in 6.0 264 Name.startswith("avx512.mask.broadcasti") || // Added in 6.0 265 Name == "xop.vpcmov" || // Added in 3.8 266 Name == "xop.vpcmov.256" || // Added in 5.0 267 Name.startswith("avx512.mask.move.s") || // Added in 4.0 268 Name.startswith("avx512.cvtmask2") || // Added in 5.0 269 (Name.startswith("xop.vpcom") && // Added in 3.2 270 F->arg_size() == 2) || 271 Name.startswith("avx512.ptestm") || //Added in 6.0 272 Name.startswith("avx512.ptestnm") || //Added in 6.0 273 Name.startswith("sse2.pavg") || // Added in 6.0 274 Name.startswith("avx2.pavg") || // Added in 6.0 275 Name.startswith("avx512.mask.pavg")) // Added in 6.0 276 return true; 277 278 return false; 279 } 280 281 static bool UpgradeX86IntrinsicFunction(Function *F, StringRef Name, 282 Function *&NewFn) { 283 // Only handle intrinsics that start with "x86.". 284 if (!Name.startswith("x86.")) 285 return false; 286 // Remove "x86." prefix. 287 Name = Name.substr(4); 288 289 if (ShouldUpgradeX86Intrinsic(F, Name)) { 290 NewFn = nullptr; 291 return true; 292 } 293 294 // SSE4.1 ptest functions may have an old signature. 295 if (Name.startswith("sse41.ptest")) { // Added in 3.2 296 if (Name.substr(11) == "c") 297 return UpgradePTESTIntrinsic(F, Intrinsic::x86_sse41_ptestc, NewFn); 298 if (Name.substr(11) == "z") 299 return UpgradePTESTIntrinsic(F, Intrinsic::x86_sse41_ptestz, NewFn); 300 if (Name.substr(11) == "nzc") 301 return UpgradePTESTIntrinsic(F, Intrinsic::x86_sse41_ptestnzc, NewFn); 302 } 303 // Several blend and other instructions with masks used the wrong number of 304 // bits. 305 if (Name == "sse41.insertps") // Added in 3.6 306 return UpgradeX86IntrinsicsWith8BitMask(F, Intrinsic::x86_sse41_insertps, 307 NewFn); 308 if (Name == "sse41.dppd") // Added in 3.6 309 return UpgradeX86IntrinsicsWith8BitMask(F, Intrinsic::x86_sse41_dppd, 310 NewFn); 311 if (Name == "sse41.dpps") // Added in 3.6 312 return UpgradeX86IntrinsicsWith8BitMask(F, Intrinsic::x86_sse41_dpps, 313 NewFn); 314 if (Name == "sse41.mpsadbw") // Added in 3.6 315 return UpgradeX86IntrinsicsWith8BitMask(F, Intrinsic::x86_sse41_mpsadbw, 316 NewFn); 317 if (Name == "avx.dp.ps.256") // Added in 3.6 318 return UpgradeX86IntrinsicsWith8BitMask(F, Intrinsic::x86_avx_dp_ps_256, 319 NewFn); 320 if (Name == "avx2.mpsadbw") // Added in 3.6 321 return UpgradeX86IntrinsicsWith8BitMask(F, Intrinsic::x86_avx2_mpsadbw, 322 NewFn); 323 324 // frcz.ss/sd may need to have an argument dropped. Added in 3.2 325 if (Name.startswith("xop.vfrcz.ss") && F->arg_size() == 2) { 326 rename(F); 327 NewFn = Intrinsic::getDeclaration(F->getParent(), 328 Intrinsic::x86_xop_vfrcz_ss); 329 return true; 330 } 331 if (Name.startswith("xop.vfrcz.sd") && F->arg_size() == 2) { 332 rename(F); 333 NewFn = Intrinsic::getDeclaration(F->getParent(), 334 Intrinsic::x86_xop_vfrcz_sd); 335 return true; 336 } 337 // Upgrade any XOP PERMIL2 index operand still using a float/double vector. 338 if (Name.startswith("xop.vpermil2")) { // Added in 3.9 339 auto Idx = F->getFunctionType()->getParamType(2); 340 if (Idx->isFPOrFPVectorTy()) { 341 rename(F); 342 unsigned IdxSize = Idx->getPrimitiveSizeInBits(); 343 unsigned EltSize = Idx->getScalarSizeInBits(); 344 Intrinsic::ID Permil2ID; 345 if (EltSize == 64 && IdxSize == 128) 346 Permil2ID = Intrinsic::x86_xop_vpermil2pd; 347 else if (EltSize == 32 && IdxSize == 128) 348 Permil2ID = Intrinsic::x86_xop_vpermil2ps; 349 else if (EltSize == 64 && IdxSize == 256) 350 Permil2ID = Intrinsic::x86_xop_vpermil2pd_256; 351 else 352 Permil2ID = Intrinsic::x86_xop_vpermil2ps_256; 353 NewFn = Intrinsic::getDeclaration(F->getParent(), Permil2ID); 354 return true; 355 } 356 } 357 358 return false; 359 } 360 361 static bool UpgradeIntrinsicFunction1(Function *F, Function *&NewFn) { 362 assert(F && "Illegal to upgrade a non-existent Function."); 363 364 // Quickly eliminate it, if it's not a candidate. 365 StringRef Name = F->getName(); 366 if (Name.size() <= 8 || !Name.startswith("llvm.")) 367 return false; 368 Name = Name.substr(5); // Strip off "llvm." 369 370 switch (Name[0]) { 371 default: break; 372 case 'a': { 373 if (Name.startswith("arm.rbit") || Name.startswith("aarch64.rbit")) { 374 NewFn = Intrinsic::getDeclaration(F->getParent(), Intrinsic::bitreverse, 375 F->arg_begin()->getType()); 376 return true; 377 } 378 if (Name.startswith("arm.neon.vclz")) { 379 Type* args[2] = { 380 F->arg_begin()->getType(), 381 Type::getInt1Ty(F->getContext()) 382 }; 383 // Can't use Intrinsic::getDeclaration here as it adds a ".i1" to 384 // the end of the name. Change name from llvm.arm.neon.vclz.* to 385 // llvm.ctlz.* 386 FunctionType* fType = FunctionType::get(F->getReturnType(), args, false); 387 NewFn = Function::Create(fType, F->getLinkage(), 388 "llvm.ctlz." + Name.substr(14), F->getParent()); 389 return true; 390 } 391 if (Name.startswith("arm.neon.vcnt")) { 392 NewFn = Intrinsic::getDeclaration(F->getParent(), Intrinsic::ctpop, 393 F->arg_begin()->getType()); 394 return true; 395 } 396 Regex vldRegex("^arm\\.neon\\.vld([1234]|[234]lane)\\.v[a-z0-9]*$"); 397 if (vldRegex.match(Name)) { 398 auto fArgs = F->getFunctionType()->params(); 399 SmallVector<Type *, 4> Tys(fArgs.begin(), fArgs.end()); 400 // Can't use Intrinsic::getDeclaration here as the return types might 401 // then only be structurally equal. 402 FunctionType* fType = FunctionType::get(F->getReturnType(), Tys, false); 403 NewFn = Function::Create(fType, F->getLinkage(), 404 "llvm." + Name + ".p0i8", F->getParent()); 405 return true; 406 } 407 Regex vstRegex("^arm\\.neon\\.vst([1234]|[234]lane)\\.v[a-z0-9]*$"); 408 if (vstRegex.match(Name)) { 409 static const Intrinsic::ID StoreInts[] = {Intrinsic::arm_neon_vst1, 410 Intrinsic::arm_neon_vst2, 411 Intrinsic::arm_neon_vst3, 412 Intrinsic::arm_neon_vst4}; 413 414 static const Intrinsic::ID StoreLaneInts[] = { 415 Intrinsic::arm_neon_vst2lane, Intrinsic::arm_neon_vst3lane, 416 Intrinsic::arm_neon_vst4lane 417 }; 418 419 auto fArgs = F->getFunctionType()->params(); 420 Type *Tys[] = {fArgs[0], fArgs[1]}; 421 if (Name.find("lane") == StringRef::npos) 422 NewFn = Intrinsic::getDeclaration(F->getParent(), 423 StoreInts[fArgs.size() - 3], Tys); 424 else 425 NewFn = Intrinsic::getDeclaration(F->getParent(), 426 StoreLaneInts[fArgs.size() - 5], Tys); 427 return true; 428 } 429 if (Name == "aarch64.thread.pointer" || Name == "arm.thread.pointer") { 430 NewFn = Intrinsic::getDeclaration(F->getParent(), Intrinsic::thread_pointer); 431 return true; 432 } 433 break; 434 } 435 436 case 'c': { 437 if (Name.startswith("ctlz.") && F->arg_size() == 1) { 438 rename(F); 439 NewFn = Intrinsic::getDeclaration(F->getParent(), Intrinsic::ctlz, 440 F->arg_begin()->getType()); 441 return true; 442 } 443 if (Name.startswith("cttz.") && F->arg_size() == 1) { 444 rename(F); 445 NewFn = Intrinsic::getDeclaration(F->getParent(), Intrinsic::cttz, 446 F->arg_begin()->getType()); 447 return true; 448 } 449 break; 450 } 451 case 'd': { 452 if (Name == "dbg.value" && F->arg_size() == 4) { 453 rename(F); 454 NewFn = Intrinsic::getDeclaration(F->getParent(), Intrinsic::dbg_value); 455 return true; 456 } 457 break; 458 } 459 case 'i': 460 case 'l': { 461 bool IsLifetimeStart = Name.startswith("lifetime.start"); 462 if (IsLifetimeStart || Name.startswith("invariant.start")) { 463 Intrinsic::ID ID = IsLifetimeStart ? 464 Intrinsic::lifetime_start : Intrinsic::invariant_start; 465 auto Args = F->getFunctionType()->params(); 466 Type* ObjectPtr[1] = {Args[1]}; 467 if (F->getName() != Intrinsic::getName(ID, ObjectPtr)) { 468 rename(F); 469 NewFn = Intrinsic::getDeclaration(F->getParent(), ID, ObjectPtr); 470 return true; 471 } 472 } 473 474 bool IsLifetimeEnd = Name.startswith("lifetime.end"); 475 if (IsLifetimeEnd || Name.startswith("invariant.end")) { 476 Intrinsic::ID ID = IsLifetimeEnd ? 477 Intrinsic::lifetime_end : Intrinsic::invariant_end; 478 479 auto Args = F->getFunctionType()->params(); 480 Type* ObjectPtr[1] = {Args[IsLifetimeEnd ? 1 : 2]}; 481 if (F->getName() != Intrinsic::getName(ID, ObjectPtr)) { 482 rename(F); 483 NewFn = Intrinsic::getDeclaration(F->getParent(), ID, ObjectPtr); 484 return true; 485 } 486 } 487 break; 488 } 489 case 'm': { 490 if (Name.startswith("masked.load.")) { 491 Type *Tys[] = { F->getReturnType(), F->arg_begin()->getType() }; 492 if (F->getName() != Intrinsic::getName(Intrinsic::masked_load, Tys)) { 493 rename(F); 494 NewFn = Intrinsic::getDeclaration(F->getParent(), 495 Intrinsic::masked_load, 496 Tys); 497 return true; 498 } 499 } 500 if (Name.startswith("masked.store.")) { 501 auto Args = F->getFunctionType()->params(); 502 Type *Tys[] = { Args[0], Args[1] }; 503 if (F->getName() != Intrinsic::getName(Intrinsic::masked_store, Tys)) { 504 rename(F); 505 NewFn = Intrinsic::getDeclaration(F->getParent(), 506 Intrinsic::masked_store, 507 Tys); 508 return true; 509 } 510 } 511 // Renaming gather/scatter intrinsics with no address space overloading 512 // to the new overload which includes an address space 513 if (Name.startswith("masked.gather.")) { 514 Type *Tys[] = {F->getReturnType(), F->arg_begin()->getType()}; 515 if (F->getName() != Intrinsic::getName(Intrinsic::masked_gather, Tys)) { 516 rename(F); 517 NewFn = Intrinsic::getDeclaration(F->getParent(), 518 Intrinsic::masked_gather, Tys); 519 return true; 520 } 521 } 522 if (Name.startswith("masked.scatter.")) { 523 auto Args = F->getFunctionType()->params(); 524 Type *Tys[] = {Args[0], Args[1]}; 525 if (F->getName() != Intrinsic::getName(Intrinsic::masked_scatter, Tys)) { 526 rename(F); 527 NewFn = Intrinsic::getDeclaration(F->getParent(), 528 Intrinsic::masked_scatter, Tys); 529 return true; 530 } 531 } 532 // Updating the memory intrinsics (memcpy/memmove/memset) that have an 533 // alignment parameter to embedding the alignment as an attribute of 534 // the pointer args. 535 if (Name.startswith("memcpy.") && F->arg_size() == 5) { 536 rename(F); 537 // Get the types of dest, src, and len 538 ArrayRef<Type *> ParamTypes = F->getFunctionType()->params().slice(0, 3); 539 NewFn = Intrinsic::getDeclaration(F->getParent(), Intrinsic::memcpy, 540 ParamTypes); 541 return true; 542 } 543 if (Name.startswith("memmove.") && F->arg_size() == 5) { 544 rename(F); 545 // Get the types of dest, src, and len 546 ArrayRef<Type *> ParamTypes = F->getFunctionType()->params().slice(0, 3); 547 NewFn = Intrinsic::getDeclaration(F->getParent(), Intrinsic::memmove, 548 ParamTypes); 549 return true; 550 } 551 if (Name.startswith("memset.") && F->arg_size() == 5) { 552 rename(F); 553 // Get the types of dest, and len 554 const auto *FT = F->getFunctionType(); 555 Type *ParamTypes[2] = { 556 FT->getParamType(0), // Dest 557 FT->getParamType(2) // len 558 }; 559 NewFn = Intrinsic::getDeclaration(F->getParent(), Intrinsic::memset, 560 ParamTypes); 561 return true; 562 } 563 break; 564 } 565 case 'n': { 566 if (Name.startswith("nvvm.")) { 567 Name = Name.substr(5); 568 569 // The following nvvm intrinsics correspond exactly to an LLVM intrinsic. 570 Intrinsic::ID IID = StringSwitch<Intrinsic::ID>(Name) 571 .Cases("brev32", "brev64", Intrinsic::bitreverse) 572 .Case("clz.i", Intrinsic::ctlz) 573 .Case("popc.i", Intrinsic::ctpop) 574 .Default(Intrinsic::not_intrinsic); 575 if (IID != Intrinsic::not_intrinsic && F->arg_size() == 1) { 576 NewFn = Intrinsic::getDeclaration(F->getParent(), IID, 577 {F->getReturnType()}); 578 return true; 579 } 580 581 // The following nvvm intrinsics correspond exactly to an LLVM idiom, but 582 // not to an intrinsic alone. We expand them in UpgradeIntrinsicCall. 583 // 584 // TODO: We could add lohi.i2d. 585 bool Expand = StringSwitch<bool>(Name) 586 .Cases("abs.i", "abs.ll", true) 587 .Cases("clz.ll", "popc.ll", "h2f", true) 588 .Cases("max.i", "max.ll", "max.ui", "max.ull", true) 589 .Cases("min.i", "min.ll", "min.ui", "min.ull", true) 590 .Default(false); 591 if (Expand) { 592 NewFn = nullptr; 593 return true; 594 } 595 } 596 break; 597 } 598 case 'o': 599 // We only need to change the name to match the mangling including the 600 // address space. 601 if (Name.startswith("objectsize.")) { 602 Type *Tys[2] = { F->getReturnType(), F->arg_begin()->getType() }; 603 if (F->arg_size() == 2 || 604 F->getName() != Intrinsic::getName(Intrinsic::objectsize, Tys)) { 605 rename(F); 606 NewFn = Intrinsic::getDeclaration(F->getParent(), Intrinsic::objectsize, 607 Tys); 608 return true; 609 } 610 } 611 break; 612 613 case 's': 614 if (Name == "stackprotectorcheck") { 615 NewFn = nullptr; 616 return true; 617 } 618 break; 619 620 case 'x': 621 if (UpgradeX86IntrinsicFunction(F, Name, NewFn)) 622 return true; 623 } 624 // Remangle our intrinsic since we upgrade the mangling 625 auto Result = llvm::Intrinsic::remangleIntrinsicFunction(F); 626 if (Result != None) { 627 NewFn = Result.getValue(); 628 return true; 629 } 630 631 // This may not belong here. This function is effectively being overloaded 632 // to both detect an intrinsic which needs upgrading, and to provide the 633 // upgraded form of the intrinsic. We should perhaps have two separate 634 // functions for this. 635 return false; 636 } 637 638 bool llvm::UpgradeIntrinsicFunction(Function *F, Function *&NewFn) { 639 NewFn = nullptr; 640 bool Upgraded = UpgradeIntrinsicFunction1(F, NewFn); 641 assert(F != NewFn && "Intrinsic function upgraded to the same function"); 642 643 // Upgrade intrinsic attributes. This does not change the function. 644 if (NewFn) 645 F = NewFn; 646 if (Intrinsic::ID id = F->getIntrinsicID()) 647 F->setAttributes(Intrinsic::getAttributes(F->getContext(), id)); 648 return Upgraded; 649 } 650 651 bool llvm::UpgradeGlobalVariable(GlobalVariable *GV) { 652 // Nothing to do yet. 653 return false; 654 } 655 656 // Handles upgrading SSE2/AVX2/AVX512BW PSLLDQ intrinsics by converting them 657 // to byte shuffles. 658 static Value *UpgradeX86PSLLDQIntrinsics(IRBuilder<> &Builder, 659 Value *Op, unsigned Shift) { 660 Type *ResultTy = Op->getType(); 661 unsigned NumElts = ResultTy->getVectorNumElements() * 8; 662 663 // Bitcast from a 64-bit element type to a byte element type. 664 Type *VecTy = VectorType::get(Builder.getInt8Ty(), NumElts); 665 Op = Builder.CreateBitCast(Op, VecTy, "cast"); 666 667 // We'll be shuffling in zeroes. 668 Value *Res = Constant::getNullValue(VecTy); 669 670 // If shift is less than 16, emit a shuffle to move the bytes. Otherwise, 671 // we'll just return the zero vector. 672 if (Shift < 16) { 673 uint32_t Idxs[64]; 674 // 256/512-bit version is split into 2/4 16-byte lanes. 675 for (unsigned l = 0; l != NumElts; l += 16) 676 for (unsigned i = 0; i != 16; ++i) { 677 unsigned Idx = NumElts + i - Shift; 678 if (Idx < NumElts) 679 Idx -= NumElts - 16; // end of lane, switch operand. 680 Idxs[l + i] = Idx + l; 681 } 682 683 Res = Builder.CreateShuffleVector(Res, Op, makeArrayRef(Idxs, NumElts)); 684 } 685 686 // Bitcast back to a 64-bit element type. 687 return Builder.CreateBitCast(Res, ResultTy, "cast"); 688 } 689 690 // Handles upgrading SSE2/AVX2/AVX512BW PSRLDQ intrinsics by converting them 691 // to byte shuffles. 692 static Value *UpgradeX86PSRLDQIntrinsics(IRBuilder<> &Builder, Value *Op, 693 unsigned Shift) { 694 Type *ResultTy = Op->getType(); 695 unsigned NumElts = ResultTy->getVectorNumElements() * 8; 696 697 // Bitcast from a 64-bit element type to a byte element type. 698 Type *VecTy = VectorType::get(Builder.getInt8Ty(), NumElts); 699 Op = Builder.CreateBitCast(Op, VecTy, "cast"); 700 701 // We'll be shuffling in zeroes. 702 Value *Res = Constant::getNullValue(VecTy); 703 704 // If shift is less than 16, emit a shuffle to move the bytes. Otherwise, 705 // we'll just return the zero vector. 706 if (Shift < 16) { 707 uint32_t Idxs[64]; 708 // 256/512-bit version is split into 2/4 16-byte lanes. 709 for (unsigned l = 0; l != NumElts; l += 16) 710 for (unsigned i = 0; i != 16; ++i) { 711 unsigned Idx = i + Shift; 712 if (Idx >= 16) 713 Idx += NumElts - 16; // end of lane, switch operand. 714 Idxs[l + i] = Idx + l; 715 } 716 717 Res = Builder.CreateShuffleVector(Op, Res, makeArrayRef(Idxs, NumElts)); 718 } 719 720 // Bitcast back to a 64-bit element type. 721 return Builder.CreateBitCast(Res, ResultTy, "cast"); 722 } 723 724 static Value *getX86MaskVec(IRBuilder<> &Builder, Value *Mask, 725 unsigned NumElts) { 726 llvm::VectorType *MaskTy = llvm::VectorType::get(Builder.getInt1Ty(), 727 cast<IntegerType>(Mask->getType())->getBitWidth()); 728 Mask = Builder.CreateBitCast(Mask, MaskTy); 729 730 // If we have less than 8 elements, then the starting mask was an i8 and 731 // we need to extract down to the right number of elements. 732 if (NumElts < 8) { 733 uint32_t Indices[4]; 734 for (unsigned i = 0; i != NumElts; ++i) 735 Indices[i] = i; 736 Mask = Builder.CreateShuffleVector(Mask, Mask, 737 makeArrayRef(Indices, NumElts), 738 "extract"); 739 } 740 741 return Mask; 742 } 743 744 static Value *EmitX86Select(IRBuilder<> &Builder, Value *Mask, 745 Value *Op0, Value *Op1) { 746 // If the mask is all ones just emit the align operation. 747 if (const auto *C = dyn_cast<Constant>(Mask)) 748 if (C->isAllOnesValue()) 749 return Op0; 750 751 Mask = getX86MaskVec(Builder, Mask, Op0->getType()->getVectorNumElements()); 752 return Builder.CreateSelect(Mask, Op0, Op1); 753 } 754 755 // Handle autoupgrade for masked PALIGNR and VALIGND/Q intrinsics. 756 // PALIGNR handles large immediates by shifting while VALIGN masks the immediate 757 // so we need to handle both cases. VALIGN also doesn't have 128-bit lanes. 758 static Value *UpgradeX86ALIGNIntrinsics(IRBuilder<> &Builder, Value *Op0, 759 Value *Op1, Value *Shift, 760 Value *Passthru, Value *Mask, 761 bool IsVALIGN) { 762 unsigned ShiftVal = cast<llvm::ConstantInt>(Shift)->getZExtValue(); 763 764 unsigned NumElts = Op0->getType()->getVectorNumElements(); 765 assert((IsVALIGN || NumElts % 16 == 0) && "Illegal NumElts for PALIGNR!"); 766 assert((!IsVALIGN || NumElts <= 16) && "NumElts too large for VALIGN!"); 767 assert(isPowerOf2_32(NumElts) && "NumElts not a power of 2!"); 768 769 // Mask the immediate for VALIGN. 770 if (IsVALIGN) 771 ShiftVal &= (NumElts - 1); 772 773 // If palignr is shifting the pair of vectors more than the size of two 774 // lanes, emit zero. 775 if (ShiftVal >= 32) 776 return llvm::Constant::getNullValue(Op0->getType()); 777 778 // If palignr is shifting the pair of input vectors more than one lane, 779 // but less than two lanes, convert to shifting in zeroes. 780 if (ShiftVal > 16) { 781 ShiftVal -= 16; 782 Op1 = Op0; 783 Op0 = llvm::Constant::getNullValue(Op0->getType()); 784 } 785 786 uint32_t Indices[64]; 787 // 256-bit palignr operates on 128-bit lanes so we need to handle that 788 for (unsigned l = 0; l < NumElts; l += 16) { 789 for (unsigned i = 0; i != 16; ++i) { 790 unsigned Idx = ShiftVal + i; 791 if (!IsVALIGN && Idx >= 16) // Disable wrap for VALIGN. 792 Idx += NumElts - 16; // End of lane, switch operand. 793 Indices[l + i] = Idx + l; 794 } 795 } 796 797 Value *Align = Builder.CreateShuffleVector(Op1, Op0, 798 makeArrayRef(Indices, NumElts), 799 "palignr"); 800 801 return EmitX86Select(Builder, Mask, Align, Passthru); 802 } 803 804 static Value *UpgradeMaskedStore(IRBuilder<> &Builder, 805 Value *Ptr, Value *Data, Value *Mask, 806 bool Aligned) { 807 // Cast the pointer to the right type. 808 Ptr = Builder.CreateBitCast(Ptr, 809 llvm::PointerType::getUnqual(Data->getType())); 810 unsigned Align = 811 Aligned ? cast<VectorType>(Data->getType())->getBitWidth() / 8 : 1; 812 813 // If the mask is all ones just emit a regular store. 814 if (const auto *C = dyn_cast<Constant>(Mask)) 815 if (C->isAllOnesValue()) 816 return Builder.CreateAlignedStore(Data, Ptr, Align); 817 818 // Convert the mask from an integer type to a vector of i1. 819 unsigned NumElts = Data->getType()->getVectorNumElements(); 820 Mask = getX86MaskVec(Builder, Mask, NumElts); 821 return Builder.CreateMaskedStore(Data, Ptr, Align, Mask); 822 } 823 824 static Value *UpgradeMaskedLoad(IRBuilder<> &Builder, 825 Value *Ptr, Value *Passthru, Value *Mask, 826 bool Aligned) { 827 // Cast the pointer to the right type. 828 Ptr = Builder.CreateBitCast(Ptr, 829 llvm::PointerType::getUnqual(Passthru->getType())); 830 unsigned Align = 831 Aligned ? cast<VectorType>(Passthru->getType())->getBitWidth() / 8 : 1; 832 833 // If the mask is all ones just emit a regular store. 834 if (const auto *C = dyn_cast<Constant>(Mask)) 835 if (C->isAllOnesValue()) 836 return Builder.CreateAlignedLoad(Ptr, Align); 837 838 // Convert the mask from an integer type to a vector of i1. 839 unsigned NumElts = Passthru->getType()->getVectorNumElements(); 840 Mask = getX86MaskVec(Builder, Mask, NumElts); 841 return Builder.CreateMaskedLoad(Ptr, Align, Mask, Passthru); 842 } 843 844 static Value *upgradeAbs(IRBuilder<> &Builder, CallInst &CI) { 845 Value *Op0 = CI.getArgOperand(0); 846 llvm::Type *Ty = Op0->getType(); 847 Value *Zero = llvm::Constant::getNullValue(Ty); 848 Value *Cmp = Builder.CreateICmp(ICmpInst::ICMP_SGT, Op0, Zero); 849 Value *Neg = Builder.CreateNeg(Op0); 850 Value *Res = Builder.CreateSelect(Cmp, Op0, Neg); 851 852 if (CI.getNumArgOperands() == 3) 853 Res = EmitX86Select(Builder,CI.getArgOperand(2), Res, CI.getArgOperand(1)); 854 855 return Res; 856 } 857 858 static Value *upgradeIntMinMax(IRBuilder<> &Builder, CallInst &CI, 859 ICmpInst::Predicate Pred) { 860 Value *Op0 = CI.getArgOperand(0); 861 Value *Op1 = CI.getArgOperand(1); 862 Value *Cmp = Builder.CreateICmp(Pred, Op0, Op1); 863 Value *Res = Builder.CreateSelect(Cmp, Op0, Op1); 864 865 if (CI.getNumArgOperands() == 4) 866 Res = EmitX86Select(Builder, CI.getArgOperand(3), Res, CI.getArgOperand(2)); 867 868 return Res; 869 } 870 871 // Applying mask on vector of i1's and make sure result is at least 8 bits wide. 872 static Value *ApplyX86MaskOn1BitsVec(IRBuilder<> &Builder,Value *Vec, Value *Mask, 873 unsigned NumElts) { 874 if (Mask) { 875 const auto *C = dyn_cast<Constant>(Mask); 876 if (!C || !C->isAllOnesValue()) 877 Vec = Builder.CreateAnd(Vec, getX86MaskVec(Builder, Mask, NumElts)); 878 } 879 880 if (NumElts < 8) { 881 uint32_t Indices[8]; 882 for (unsigned i = 0; i != NumElts; ++i) 883 Indices[i] = i; 884 for (unsigned i = NumElts; i != 8; ++i) 885 Indices[i] = NumElts + i % NumElts; 886 Vec = Builder.CreateShuffleVector(Vec, 887 Constant::getNullValue(Vec->getType()), 888 Indices); 889 } 890 return Builder.CreateBitCast(Vec, Builder.getIntNTy(std::max(NumElts, 8U))); 891 } 892 893 static Value *upgradeMaskedCompare(IRBuilder<> &Builder, CallInst &CI, 894 unsigned CC, bool Signed) { 895 Value *Op0 = CI.getArgOperand(0); 896 unsigned NumElts = Op0->getType()->getVectorNumElements(); 897 898 Value *Cmp; 899 if (CC == 3) { 900 Cmp = Constant::getNullValue(llvm::VectorType::get(Builder.getInt1Ty(), NumElts)); 901 } else if (CC == 7) { 902 Cmp = Constant::getAllOnesValue(llvm::VectorType::get(Builder.getInt1Ty(), NumElts)); 903 } else { 904 ICmpInst::Predicate Pred; 905 switch (CC) { 906 default: llvm_unreachable("Unknown condition code"); 907 case 0: Pred = ICmpInst::ICMP_EQ; break; 908 case 1: Pred = Signed ? ICmpInst::ICMP_SLT : ICmpInst::ICMP_ULT; break; 909 case 2: Pred = Signed ? ICmpInst::ICMP_SLE : ICmpInst::ICMP_ULE; break; 910 case 4: Pred = ICmpInst::ICMP_NE; break; 911 case 5: Pred = Signed ? ICmpInst::ICMP_SGE : ICmpInst::ICMP_UGE; break; 912 case 6: Pred = Signed ? ICmpInst::ICMP_SGT : ICmpInst::ICMP_UGT; break; 913 } 914 Cmp = Builder.CreateICmp(Pred, Op0, CI.getArgOperand(1)); 915 } 916 917 Value *Mask = CI.getArgOperand(CI.getNumArgOperands() - 1); 918 919 return ApplyX86MaskOn1BitsVec(Builder, Cmp, Mask, NumElts); 920 } 921 922 // Replace a masked intrinsic with an older unmasked intrinsic. 923 static Value *UpgradeX86MaskedShift(IRBuilder<> &Builder, CallInst &CI, 924 Intrinsic::ID IID) { 925 Function *F = CI.getCalledFunction(); 926 Function *Intrin = Intrinsic::getDeclaration(F->getParent(), IID); 927 Value *Rep = Builder.CreateCall(Intrin, 928 { CI.getArgOperand(0), CI.getArgOperand(1) }); 929 return EmitX86Select(Builder, CI.getArgOperand(3), Rep, CI.getArgOperand(2)); 930 } 931 932 static Value* upgradeMaskedMove(IRBuilder<> &Builder, CallInst &CI) { 933 Value* A = CI.getArgOperand(0); 934 Value* B = CI.getArgOperand(1); 935 Value* Src = CI.getArgOperand(2); 936 Value* Mask = CI.getArgOperand(3); 937 938 Value* AndNode = Builder.CreateAnd(Mask, APInt(8, 1)); 939 Value* Cmp = Builder.CreateIsNotNull(AndNode); 940 Value* Extract1 = Builder.CreateExtractElement(B, (uint64_t)0); 941 Value* Extract2 = Builder.CreateExtractElement(Src, (uint64_t)0); 942 Value* Select = Builder.CreateSelect(Cmp, Extract1, Extract2); 943 return Builder.CreateInsertElement(A, Select, (uint64_t)0); 944 } 945 946 947 static Value* UpgradeMaskToInt(IRBuilder<> &Builder, CallInst &CI) { 948 Value* Op = CI.getArgOperand(0); 949 Type* ReturnOp = CI.getType(); 950 unsigned NumElts = CI.getType()->getVectorNumElements(); 951 Value *Mask = getX86MaskVec(Builder, Op, NumElts); 952 return Builder.CreateSExt(Mask, ReturnOp, "vpmovm2"); 953 } 954 955 /// Upgrade a call to an old intrinsic. All argument and return casting must be 956 /// provided to seamlessly integrate with existing context. 957 void llvm::UpgradeIntrinsicCall(CallInst *CI, Function *NewFn) { 958 Function *F = CI->getCalledFunction(); 959 LLVMContext &C = CI->getContext(); 960 IRBuilder<> Builder(C); 961 Builder.SetInsertPoint(CI->getParent(), CI->getIterator()); 962 963 assert(F && "Intrinsic call is not direct?"); 964 965 if (!NewFn) { 966 // Get the Function's name. 967 StringRef Name = F->getName(); 968 969 assert(Name.startswith("llvm.") && "Intrinsic doesn't start with 'llvm.'"); 970 Name = Name.substr(5); 971 972 bool IsX86 = Name.startswith("x86."); 973 if (IsX86) 974 Name = Name.substr(4); 975 bool IsNVVM = Name.startswith("nvvm."); 976 if (IsNVVM) 977 Name = Name.substr(5); 978 979 if (IsX86 && Name.startswith("sse4a.movnt.")) { 980 Module *M = F->getParent(); 981 SmallVector<Metadata *, 1> Elts; 982 Elts.push_back( 983 ConstantAsMetadata::get(ConstantInt::get(Type::getInt32Ty(C), 1))); 984 MDNode *Node = MDNode::get(C, Elts); 985 986 Value *Arg0 = CI->getArgOperand(0); 987 Value *Arg1 = CI->getArgOperand(1); 988 989 // Nontemporal (unaligned) store of the 0'th element of the float/double 990 // vector. 991 Type *SrcEltTy = cast<VectorType>(Arg1->getType())->getElementType(); 992 PointerType *EltPtrTy = PointerType::getUnqual(SrcEltTy); 993 Value *Addr = Builder.CreateBitCast(Arg0, EltPtrTy, "cast"); 994 Value *Extract = 995 Builder.CreateExtractElement(Arg1, (uint64_t)0, "extractelement"); 996 997 StoreInst *SI = Builder.CreateAlignedStore(Extract, Addr, 1); 998 SI->setMetadata(M->getMDKindID("nontemporal"), Node); 999 1000 // Remove intrinsic. 1001 CI->eraseFromParent(); 1002 return; 1003 } 1004 1005 if (IsX86 && (Name.startswith("avx.movnt.") || 1006 Name.startswith("avx512.storent."))) { 1007 Module *M = F->getParent(); 1008 SmallVector<Metadata *, 1> Elts; 1009 Elts.push_back( 1010 ConstantAsMetadata::get(ConstantInt::get(Type::getInt32Ty(C), 1))); 1011 MDNode *Node = MDNode::get(C, Elts); 1012 1013 Value *Arg0 = CI->getArgOperand(0); 1014 Value *Arg1 = CI->getArgOperand(1); 1015 1016 // Convert the type of the pointer to a pointer to the stored type. 1017 Value *BC = Builder.CreateBitCast(Arg0, 1018 PointerType::getUnqual(Arg1->getType()), 1019 "cast"); 1020 VectorType *VTy = cast<VectorType>(Arg1->getType()); 1021 StoreInst *SI = Builder.CreateAlignedStore(Arg1, BC, 1022 VTy->getBitWidth() / 8); 1023 SI->setMetadata(M->getMDKindID("nontemporal"), Node); 1024 1025 // Remove intrinsic. 1026 CI->eraseFromParent(); 1027 return; 1028 } 1029 1030 if (IsX86 && Name == "sse2.storel.dq") { 1031 Value *Arg0 = CI->getArgOperand(0); 1032 Value *Arg1 = CI->getArgOperand(1); 1033 1034 Type *NewVecTy = VectorType::get(Type::getInt64Ty(C), 2); 1035 Value *BC0 = Builder.CreateBitCast(Arg1, NewVecTy, "cast"); 1036 Value *Elt = Builder.CreateExtractElement(BC0, (uint64_t)0); 1037 Value *BC = Builder.CreateBitCast(Arg0, 1038 PointerType::getUnqual(Elt->getType()), 1039 "cast"); 1040 Builder.CreateAlignedStore(Elt, BC, 1); 1041 1042 // Remove intrinsic. 1043 CI->eraseFromParent(); 1044 return; 1045 } 1046 1047 if (IsX86 && (Name.startswith("sse.storeu.") || 1048 Name.startswith("sse2.storeu.") || 1049 Name.startswith("avx.storeu."))) { 1050 Value *Arg0 = CI->getArgOperand(0); 1051 Value *Arg1 = CI->getArgOperand(1); 1052 1053 Arg0 = Builder.CreateBitCast(Arg0, 1054 PointerType::getUnqual(Arg1->getType()), 1055 "cast"); 1056 Builder.CreateAlignedStore(Arg1, Arg0, 1); 1057 1058 // Remove intrinsic. 1059 CI->eraseFromParent(); 1060 return; 1061 } 1062 1063 if (IsX86 && (Name.startswith("avx512.mask.store"))) { 1064 // "avx512.mask.storeu." or "avx512.mask.store." 1065 bool Aligned = Name[17] != 'u'; // "avx512.mask.storeu". 1066 UpgradeMaskedStore(Builder, CI->getArgOperand(0), CI->getArgOperand(1), 1067 CI->getArgOperand(2), Aligned); 1068 1069 // Remove intrinsic. 1070 CI->eraseFromParent(); 1071 return; 1072 } 1073 1074 Value *Rep; 1075 // Upgrade packed integer vector compare intrinsics to compare instructions. 1076 if (IsX86 && (Name.startswith("sse2.pcmp") || 1077 Name.startswith("avx2.pcmp"))) { 1078 // "sse2.pcpmpeq." "sse2.pcmpgt." "avx2.pcmpeq." or "avx2.pcmpgt." 1079 bool CmpEq = Name[9] == 'e'; 1080 Rep = Builder.CreateICmp(CmpEq ? ICmpInst::ICMP_EQ : ICmpInst::ICMP_SGT, 1081 CI->getArgOperand(0), CI->getArgOperand(1)); 1082 Rep = Builder.CreateSExt(Rep, CI->getType(), ""); 1083 } else if (IsX86 && (Name.startswith("avx512.broadcastm"))) { 1084 Type *ExtTy = Type::getInt32Ty(C); 1085 if (CI->getOperand(0)->getType()->isIntegerTy(8)) 1086 ExtTy = Type::getInt64Ty(C); 1087 unsigned NumElts = CI->getType()->getPrimitiveSizeInBits() / 1088 ExtTy->getPrimitiveSizeInBits(); 1089 Rep = Builder.CreateZExt(CI->getArgOperand(0), ExtTy); 1090 Rep = Builder.CreateVectorSplat(NumElts, Rep); 1091 } else if (IsX86 && (Name.startswith("avx512.ptestm") || 1092 Name.startswith("avx512.ptestnm"))) { 1093 Value *Op0 = CI->getArgOperand(0); 1094 Value *Op1 = CI->getArgOperand(1); 1095 Value *Mask = CI->getArgOperand(2); 1096 Rep = Builder.CreateAnd(Op0, Op1); 1097 llvm::Type *Ty = Op0->getType(); 1098 Value *Zero = llvm::Constant::getNullValue(Ty); 1099 ICmpInst::Predicate Pred = 1100 Name.startswith("avx512.ptestm") ? ICmpInst::ICMP_NE : ICmpInst::ICMP_EQ; 1101 Rep = Builder.CreateICmp(Pred, Rep, Zero); 1102 unsigned NumElts = Op0->getType()->getVectorNumElements(); 1103 Rep = ApplyX86MaskOn1BitsVec(Builder, Rep, Mask, NumElts); 1104 } else if (IsX86 && (Name.startswith("avx512.mask.pbroadcast"))){ 1105 unsigned NumElts = 1106 CI->getArgOperand(1)->getType()->getVectorNumElements(); 1107 Rep = Builder.CreateVectorSplat(NumElts, CI->getArgOperand(0)); 1108 Rep = EmitX86Select(Builder, CI->getArgOperand(2), Rep, 1109 CI->getArgOperand(1)); 1110 } else if (IsX86 && (Name.startswith("avx512.kunpck"))) { 1111 unsigned NumElts = CI->getType()->getScalarSizeInBits(); 1112 Value *LHS = getX86MaskVec(Builder, CI->getArgOperand(0), NumElts); 1113 Value *RHS = getX86MaskVec(Builder, CI->getArgOperand(1), NumElts); 1114 uint32_t Indices[64]; 1115 for (unsigned i = 0; i != NumElts; ++i) 1116 Indices[i] = i; 1117 1118 // First extract half of each vector. This gives better codegen than 1119 // doing it in a single shuffle. 1120 LHS = Builder.CreateShuffleVector(LHS, LHS, 1121 makeArrayRef(Indices, NumElts / 2)); 1122 RHS = Builder.CreateShuffleVector(RHS, RHS, 1123 makeArrayRef(Indices, NumElts / 2)); 1124 // Concat the vectors. 1125 Rep = Builder.CreateShuffleVector(LHS, RHS, 1126 makeArrayRef(Indices, NumElts)); 1127 Rep = Builder.CreateBitCast(Rep, CI->getType()); 1128 } else if (IsX86 && Name == "avx512.kand.w") { 1129 Value *LHS = getX86MaskVec(Builder, CI->getArgOperand(0), 16); 1130 Value *RHS = getX86MaskVec(Builder, CI->getArgOperand(1), 16); 1131 Rep = Builder.CreateAnd(LHS, RHS); 1132 Rep = Builder.CreateBitCast(Rep, CI->getType()); 1133 } else if (IsX86 && Name == "avx512.kandn.w") { 1134 Value *LHS = getX86MaskVec(Builder, CI->getArgOperand(0), 16); 1135 Value *RHS = getX86MaskVec(Builder, CI->getArgOperand(1), 16); 1136 LHS = Builder.CreateNot(LHS); 1137 Rep = Builder.CreateAnd(LHS, RHS); 1138 Rep = Builder.CreateBitCast(Rep, CI->getType()); 1139 } else if (IsX86 && Name == "avx512.kor.w") { 1140 Value *LHS = getX86MaskVec(Builder, CI->getArgOperand(0), 16); 1141 Value *RHS = getX86MaskVec(Builder, CI->getArgOperand(1), 16); 1142 Rep = Builder.CreateOr(LHS, RHS); 1143 Rep = Builder.CreateBitCast(Rep, CI->getType()); 1144 } else if (IsX86 && Name == "avx512.kxor.w") { 1145 Value *LHS = getX86MaskVec(Builder, CI->getArgOperand(0), 16); 1146 Value *RHS = getX86MaskVec(Builder, CI->getArgOperand(1), 16); 1147 Rep = Builder.CreateXor(LHS, RHS); 1148 Rep = Builder.CreateBitCast(Rep, CI->getType()); 1149 } else if (IsX86 && Name == "avx512.kxnor.w") { 1150 Value *LHS = getX86MaskVec(Builder, CI->getArgOperand(0), 16); 1151 Value *RHS = getX86MaskVec(Builder, CI->getArgOperand(1), 16); 1152 LHS = Builder.CreateNot(LHS); 1153 Rep = Builder.CreateXor(LHS, RHS); 1154 Rep = Builder.CreateBitCast(Rep, CI->getType()); 1155 } else if (IsX86 && Name == "avx512.knot.w") { 1156 Rep = getX86MaskVec(Builder, CI->getArgOperand(0), 16); 1157 Rep = Builder.CreateNot(Rep); 1158 Rep = Builder.CreateBitCast(Rep, CI->getType()); 1159 } else if (IsX86 && (Name == "sse.add.ss" || Name == "sse2.add.sd")) { 1160 Type *I32Ty = Type::getInt32Ty(C); 1161 Value *Elt0 = Builder.CreateExtractElement(CI->getArgOperand(0), 1162 ConstantInt::get(I32Ty, 0)); 1163 Value *Elt1 = Builder.CreateExtractElement(CI->getArgOperand(1), 1164 ConstantInt::get(I32Ty, 0)); 1165 Rep = Builder.CreateInsertElement(CI->getArgOperand(0), 1166 Builder.CreateFAdd(Elt0, Elt1), 1167 ConstantInt::get(I32Ty, 0)); 1168 } else if (IsX86 && (Name == "sse.sub.ss" || Name == "sse2.sub.sd")) { 1169 Type *I32Ty = Type::getInt32Ty(C); 1170 Value *Elt0 = Builder.CreateExtractElement(CI->getArgOperand(0), 1171 ConstantInt::get(I32Ty, 0)); 1172 Value *Elt1 = Builder.CreateExtractElement(CI->getArgOperand(1), 1173 ConstantInt::get(I32Ty, 0)); 1174 Rep = Builder.CreateInsertElement(CI->getArgOperand(0), 1175 Builder.CreateFSub(Elt0, Elt1), 1176 ConstantInt::get(I32Ty, 0)); 1177 } else if (IsX86 && (Name == "sse.mul.ss" || Name == "sse2.mul.sd")) { 1178 Type *I32Ty = Type::getInt32Ty(C); 1179 Value *Elt0 = Builder.CreateExtractElement(CI->getArgOperand(0), 1180 ConstantInt::get(I32Ty, 0)); 1181 Value *Elt1 = Builder.CreateExtractElement(CI->getArgOperand(1), 1182 ConstantInt::get(I32Ty, 0)); 1183 Rep = Builder.CreateInsertElement(CI->getArgOperand(0), 1184 Builder.CreateFMul(Elt0, Elt1), 1185 ConstantInt::get(I32Ty, 0)); 1186 } else if (IsX86 && (Name == "sse.div.ss" || Name == "sse2.div.sd")) { 1187 Type *I32Ty = Type::getInt32Ty(C); 1188 Value *Elt0 = Builder.CreateExtractElement(CI->getArgOperand(0), 1189 ConstantInt::get(I32Ty, 0)); 1190 Value *Elt1 = Builder.CreateExtractElement(CI->getArgOperand(1), 1191 ConstantInt::get(I32Ty, 0)); 1192 Rep = Builder.CreateInsertElement(CI->getArgOperand(0), 1193 Builder.CreateFDiv(Elt0, Elt1), 1194 ConstantInt::get(I32Ty, 0)); 1195 } else if (IsX86 && Name.startswith("avx512.mask.pcmp")) { 1196 // "avx512.mask.pcmpeq." or "avx512.mask.pcmpgt." 1197 bool CmpEq = Name[16] == 'e'; 1198 Rep = upgradeMaskedCompare(Builder, *CI, CmpEq ? 0 : 6, true); 1199 } else if (IsX86 && Name.startswith("avx512.mask.cmp")) { 1200 unsigned Imm = cast<ConstantInt>(CI->getArgOperand(2))->getZExtValue(); 1201 Rep = upgradeMaskedCompare(Builder, *CI, Imm, true); 1202 } else if (IsX86 && Name.startswith("avx512.mask.ucmp")) { 1203 unsigned Imm = cast<ConstantInt>(CI->getArgOperand(2))->getZExtValue(); 1204 Rep = upgradeMaskedCompare(Builder, *CI, Imm, false); 1205 } else if (IsX86 && (Name.startswith("avx512.cvtb2mask.") || 1206 Name.startswith("avx512.cvtw2mask.") || 1207 Name.startswith("avx512.cvtd2mask.") || 1208 Name.startswith("avx512.cvtq2mask."))) { 1209 Value *Op = CI->getArgOperand(0); 1210 Value *Zero = llvm::Constant::getNullValue(Op->getType()); 1211 Rep = Builder.CreateICmp(ICmpInst::ICMP_SLT, Op, Zero); 1212 Rep = ApplyX86MaskOn1BitsVec(Builder, Rep, nullptr, 1213 Op->getType()->getVectorNumElements()); 1214 } else if(IsX86 && (Name == "ssse3.pabs.b.128" || 1215 Name == "ssse3.pabs.w.128" || 1216 Name == "ssse3.pabs.d.128" || 1217 Name.startswith("avx2.pabs") || 1218 Name.startswith("avx512.mask.pabs"))) { 1219 Rep = upgradeAbs(Builder, *CI); 1220 } else if (IsX86 && (Name == "sse41.pmaxsb" || 1221 Name == "sse2.pmaxs.w" || 1222 Name == "sse41.pmaxsd" || 1223 Name.startswith("avx2.pmaxs") || 1224 Name.startswith("avx512.mask.pmaxs"))) { 1225 Rep = upgradeIntMinMax(Builder, *CI, ICmpInst::ICMP_SGT); 1226 } else if (IsX86 && (Name == "sse2.pmaxu.b" || 1227 Name == "sse41.pmaxuw" || 1228 Name == "sse41.pmaxud" || 1229 Name.startswith("avx2.pmaxu") || 1230 Name.startswith("avx512.mask.pmaxu"))) { 1231 Rep = upgradeIntMinMax(Builder, *CI, ICmpInst::ICMP_UGT); 1232 } else if (IsX86 && (Name == "sse41.pminsb" || 1233 Name == "sse2.pmins.w" || 1234 Name == "sse41.pminsd" || 1235 Name.startswith("avx2.pmins") || 1236 Name.startswith("avx512.mask.pmins"))) { 1237 Rep = upgradeIntMinMax(Builder, *CI, ICmpInst::ICMP_SLT); 1238 } else if (IsX86 && (Name == "sse2.pminu.b" || 1239 Name == "sse41.pminuw" || 1240 Name == "sse41.pminud" || 1241 Name.startswith("avx2.pminu") || 1242 Name.startswith("avx512.mask.pminu"))) { 1243 Rep = upgradeIntMinMax(Builder, *CI, ICmpInst::ICMP_ULT); 1244 } else if (IsX86 && (Name == "sse2.cvtdq2pd" || 1245 Name == "sse2.cvtps2pd" || 1246 Name == "avx.cvtdq2.pd.256" || 1247 Name == "avx.cvt.ps2.pd.256" || 1248 Name.startswith("avx512.mask.cvtdq2pd.") || 1249 Name.startswith("avx512.mask.cvtudq2pd."))) { 1250 // Lossless i32/float to double conversion. 1251 // Extract the bottom elements if necessary and convert to double vector. 1252 Value *Src = CI->getArgOperand(0); 1253 VectorType *SrcTy = cast<VectorType>(Src->getType()); 1254 VectorType *DstTy = cast<VectorType>(CI->getType()); 1255 Rep = CI->getArgOperand(0); 1256 1257 unsigned NumDstElts = DstTy->getNumElements(); 1258 if (NumDstElts < SrcTy->getNumElements()) { 1259 assert(NumDstElts == 2 && "Unexpected vector size"); 1260 uint32_t ShuffleMask[2] = { 0, 1 }; 1261 Rep = Builder.CreateShuffleVector(Rep, UndefValue::get(SrcTy), 1262 ShuffleMask); 1263 } 1264 1265 bool SInt2Double = (StringRef::npos != Name.find("cvtdq2")); 1266 bool UInt2Double = (StringRef::npos != Name.find("cvtudq2")); 1267 if (SInt2Double) 1268 Rep = Builder.CreateSIToFP(Rep, DstTy, "cvtdq2pd"); 1269 else if (UInt2Double) 1270 Rep = Builder.CreateUIToFP(Rep, DstTy, "cvtudq2pd"); 1271 else 1272 Rep = Builder.CreateFPExt(Rep, DstTy, "cvtps2pd"); 1273 1274 if (CI->getNumArgOperands() == 3) 1275 Rep = EmitX86Select(Builder, CI->getArgOperand(2), Rep, 1276 CI->getArgOperand(1)); 1277 } else if (IsX86 && (Name.startswith("avx512.mask.loadu."))) { 1278 Rep = UpgradeMaskedLoad(Builder, CI->getArgOperand(0), 1279 CI->getArgOperand(1), CI->getArgOperand(2), 1280 /*Aligned*/false); 1281 } else if (IsX86 && (Name.startswith("avx512.mask.load."))) { 1282 Rep = UpgradeMaskedLoad(Builder, CI->getArgOperand(0), 1283 CI->getArgOperand(1),CI->getArgOperand(2), 1284 /*Aligned*/true); 1285 } else if (IsX86 && Name.startswith("xop.vpcom")) { 1286 Intrinsic::ID intID; 1287 if (Name.endswith("ub")) 1288 intID = Intrinsic::x86_xop_vpcomub; 1289 else if (Name.endswith("uw")) 1290 intID = Intrinsic::x86_xop_vpcomuw; 1291 else if (Name.endswith("ud")) 1292 intID = Intrinsic::x86_xop_vpcomud; 1293 else if (Name.endswith("uq")) 1294 intID = Intrinsic::x86_xop_vpcomuq; 1295 else if (Name.endswith("b")) 1296 intID = Intrinsic::x86_xop_vpcomb; 1297 else if (Name.endswith("w")) 1298 intID = Intrinsic::x86_xop_vpcomw; 1299 else if (Name.endswith("d")) 1300 intID = Intrinsic::x86_xop_vpcomd; 1301 else if (Name.endswith("q")) 1302 intID = Intrinsic::x86_xop_vpcomq; 1303 else 1304 llvm_unreachable("Unknown suffix"); 1305 1306 Name = Name.substr(9); // strip off "xop.vpcom" 1307 unsigned Imm; 1308 if (Name.startswith("lt")) 1309 Imm = 0; 1310 else if (Name.startswith("le")) 1311 Imm = 1; 1312 else if (Name.startswith("gt")) 1313 Imm = 2; 1314 else if (Name.startswith("ge")) 1315 Imm = 3; 1316 else if (Name.startswith("eq")) 1317 Imm = 4; 1318 else if (Name.startswith("ne")) 1319 Imm = 5; 1320 else if (Name.startswith("false")) 1321 Imm = 6; 1322 else if (Name.startswith("true")) 1323 Imm = 7; 1324 else 1325 llvm_unreachable("Unknown condition"); 1326 1327 Function *VPCOM = Intrinsic::getDeclaration(F->getParent(), intID); 1328 Rep = 1329 Builder.CreateCall(VPCOM, {CI->getArgOperand(0), CI->getArgOperand(1), 1330 Builder.getInt8(Imm)}); 1331 } else if (IsX86 && Name.startswith("xop.vpcmov")) { 1332 Value *Sel = CI->getArgOperand(2); 1333 Value *NotSel = Builder.CreateNot(Sel); 1334 Value *Sel0 = Builder.CreateAnd(CI->getArgOperand(0), Sel); 1335 Value *Sel1 = Builder.CreateAnd(CI->getArgOperand(1), NotSel); 1336 Rep = Builder.CreateOr(Sel0, Sel1); 1337 } else if (IsX86 && Name == "sse42.crc32.64.8") { 1338 Function *CRC32 = Intrinsic::getDeclaration(F->getParent(), 1339 Intrinsic::x86_sse42_crc32_32_8); 1340 Value *Trunc0 = Builder.CreateTrunc(CI->getArgOperand(0), Type::getInt32Ty(C)); 1341 Rep = Builder.CreateCall(CRC32, {Trunc0, CI->getArgOperand(1)}); 1342 Rep = Builder.CreateZExt(Rep, CI->getType(), ""); 1343 } else if (IsX86 && Name.startswith("avx.vbroadcast.s")) { 1344 // Replace broadcasts with a series of insertelements. 1345 Type *VecTy = CI->getType(); 1346 Type *EltTy = VecTy->getVectorElementType(); 1347 unsigned EltNum = VecTy->getVectorNumElements(); 1348 Value *Cast = Builder.CreateBitCast(CI->getArgOperand(0), 1349 EltTy->getPointerTo()); 1350 Value *Load = Builder.CreateLoad(EltTy, Cast); 1351 Type *I32Ty = Type::getInt32Ty(C); 1352 Rep = UndefValue::get(VecTy); 1353 for (unsigned I = 0; I < EltNum; ++I) 1354 Rep = Builder.CreateInsertElement(Rep, Load, 1355 ConstantInt::get(I32Ty, I)); 1356 } else if (IsX86 && (Name.startswith("sse41.pmovsx") || 1357 Name.startswith("sse41.pmovzx") || 1358 Name.startswith("avx2.pmovsx") || 1359 Name.startswith("avx2.pmovzx") || 1360 Name.startswith("avx512.mask.pmovsx") || 1361 Name.startswith("avx512.mask.pmovzx"))) { 1362 VectorType *SrcTy = cast<VectorType>(CI->getArgOperand(0)->getType()); 1363 VectorType *DstTy = cast<VectorType>(CI->getType()); 1364 unsigned NumDstElts = DstTy->getNumElements(); 1365 1366 // Extract a subvector of the first NumDstElts lanes and sign/zero extend. 1367 SmallVector<uint32_t, 8> ShuffleMask(NumDstElts); 1368 for (unsigned i = 0; i != NumDstElts; ++i) 1369 ShuffleMask[i] = i; 1370 1371 Value *SV = Builder.CreateShuffleVector( 1372 CI->getArgOperand(0), UndefValue::get(SrcTy), ShuffleMask); 1373 1374 bool DoSext = (StringRef::npos != Name.find("pmovsx")); 1375 Rep = DoSext ? Builder.CreateSExt(SV, DstTy) 1376 : Builder.CreateZExt(SV, DstTy); 1377 // If there are 3 arguments, it's a masked intrinsic so we need a select. 1378 if (CI->getNumArgOperands() == 3) 1379 Rep = EmitX86Select(Builder, CI->getArgOperand(2), Rep, 1380 CI->getArgOperand(1)); 1381 } else if (IsX86 && (Name.startswith("avx.vbroadcastf128") || 1382 Name == "avx2.vbroadcasti128")) { 1383 // Replace vbroadcastf128/vbroadcasti128 with a vector load+shuffle. 1384 Type *EltTy = CI->getType()->getVectorElementType(); 1385 unsigned NumSrcElts = 128 / EltTy->getPrimitiveSizeInBits(); 1386 Type *VT = VectorType::get(EltTy, NumSrcElts); 1387 Value *Op = Builder.CreatePointerCast(CI->getArgOperand(0), 1388 PointerType::getUnqual(VT)); 1389 Value *Load = Builder.CreateAlignedLoad(Op, 1); 1390 if (NumSrcElts == 2) 1391 Rep = Builder.CreateShuffleVector(Load, UndefValue::get(Load->getType()), 1392 { 0, 1, 0, 1 }); 1393 else 1394 Rep = Builder.CreateShuffleVector(Load, UndefValue::get(Load->getType()), 1395 { 0, 1, 2, 3, 0, 1, 2, 3 }); 1396 } else if (IsX86 && (Name.startswith("avx512.mask.shuf.i") || 1397 Name.startswith("avx512.mask.shuf.f"))) { 1398 unsigned Imm = cast<ConstantInt>(CI->getArgOperand(2))->getZExtValue(); 1399 Type *VT = CI->getType(); 1400 unsigned NumLanes = VT->getPrimitiveSizeInBits() / 128; 1401 unsigned NumElementsInLane = 128 / VT->getScalarSizeInBits(); 1402 unsigned ControlBitsMask = NumLanes - 1; 1403 unsigned NumControlBits = NumLanes / 2; 1404 SmallVector<uint32_t, 8> ShuffleMask(0); 1405 1406 for (unsigned l = 0; l != NumLanes; ++l) { 1407 unsigned LaneMask = (Imm >> (l * NumControlBits)) & ControlBitsMask; 1408 // We actually need the other source. 1409 if (l >= NumLanes / 2) 1410 LaneMask += NumLanes; 1411 for (unsigned i = 0; i != NumElementsInLane; ++i) 1412 ShuffleMask.push_back(LaneMask * NumElementsInLane + i); 1413 } 1414 Rep = Builder.CreateShuffleVector(CI->getArgOperand(0), 1415 CI->getArgOperand(1), ShuffleMask); 1416 Rep = EmitX86Select(Builder, CI->getArgOperand(4), Rep, 1417 CI->getArgOperand(3)); 1418 }else if (IsX86 && (Name.startswith("avx512.mask.broadcastf") || 1419 Name.startswith("avx512.mask.broadcasti"))) { 1420 unsigned NumSrcElts = 1421 CI->getArgOperand(0)->getType()->getVectorNumElements(); 1422 unsigned NumDstElts = CI->getType()->getVectorNumElements(); 1423 1424 SmallVector<uint32_t, 8> ShuffleMask(NumDstElts); 1425 for (unsigned i = 0; i != NumDstElts; ++i) 1426 ShuffleMask[i] = i % NumSrcElts; 1427 1428 Rep = Builder.CreateShuffleVector(CI->getArgOperand(0), 1429 CI->getArgOperand(0), 1430 ShuffleMask); 1431 Rep = EmitX86Select(Builder, CI->getArgOperand(2), Rep, 1432 CI->getArgOperand(1)); 1433 } else if (IsX86 && (Name.startswith("avx2.pbroadcast") || 1434 Name.startswith("avx2.vbroadcast") || 1435 Name.startswith("avx512.pbroadcast") || 1436 Name.startswith("avx512.mask.broadcast.s"))) { 1437 // Replace vp?broadcasts with a vector shuffle. 1438 Value *Op = CI->getArgOperand(0); 1439 unsigned NumElts = CI->getType()->getVectorNumElements(); 1440 Type *MaskTy = VectorType::get(Type::getInt32Ty(C), NumElts); 1441 Rep = Builder.CreateShuffleVector(Op, UndefValue::get(Op->getType()), 1442 Constant::getNullValue(MaskTy)); 1443 1444 if (CI->getNumArgOperands() == 3) 1445 Rep = EmitX86Select(Builder, CI->getArgOperand(2), Rep, 1446 CI->getArgOperand(1)); 1447 } else if (IsX86 && Name.startswith("avx512.mask.palignr.")) { 1448 Rep = UpgradeX86ALIGNIntrinsics(Builder, CI->getArgOperand(0), 1449 CI->getArgOperand(1), 1450 CI->getArgOperand(2), 1451 CI->getArgOperand(3), 1452 CI->getArgOperand(4), 1453 false); 1454 } else if (IsX86 && Name.startswith("avx512.mask.valign.")) { 1455 Rep = UpgradeX86ALIGNIntrinsics(Builder, CI->getArgOperand(0), 1456 CI->getArgOperand(1), 1457 CI->getArgOperand(2), 1458 CI->getArgOperand(3), 1459 CI->getArgOperand(4), 1460 true); 1461 } else if (IsX86 && (Name == "sse2.psll.dq" || 1462 Name == "avx2.psll.dq")) { 1463 // 128/256-bit shift left specified in bits. 1464 unsigned Shift = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue(); 1465 Rep = UpgradeX86PSLLDQIntrinsics(Builder, CI->getArgOperand(0), 1466 Shift / 8); // Shift is in bits. 1467 } else if (IsX86 && (Name == "sse2.psrl.dq" || 1468 Name == "avx2.psrl.dq")) { 1469 // 128/256-bit shift right specified in bits. 1470 unsigned Shift = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue(); 1471 Rep = UpgradeX86PSRLDQIntrinsics(Builder, CI->getArgOperand(0), 1472 Shift / 8); // Shift is in bits. 1473 } else if (IsX86 && (Name == "sse2.psll.dq.bs" || 1474 Name == "avx2.psll.dq.bs" || 1475 Name == "avx512.psll.dq.512")) { 1476 // 128/256/512-bit shift left specified in bytes. 1477 unsigned Shift = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue(); 1478 Rep = UpgradeX86PSLLDQIntrinsics(Builder, CI->getArgOperand(0), Shift); 1479 } else if (IsX86 && (Name == "sse2.psrl.dq.bs" || 1480 Name == "avx2.psrl.dq.bs" || 1481 Name == "avx512.psrl.dq.512")) { 1482 // 128/256/512-bit shift right specified in bytes. 1483 unsigned Shift = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue(); 1484 Rep = UpgradeX86PSRLDQIntrinsics(Builder, CI->getArgOperand(0), Shift); 1485 } else if (IsX86 && (Name == "sse41.pblendw" || 1486 Name.startswith("sse41.blendp") || 1487 Name.startswith("avx.blend.p") || 1488 Name == "avx2.pblendw" || 1489 Name.startswith("avx2.pblendd."))) { 1490 Value *Op0 = CI->getArgOperand(0); 1491 Value *Op1 = CI->getArgOperand(1); 1492 unsigned Imm = cast <ConstantInt>(CI->getArgOperand(2))->getZExtValue(); 1493 VectorType *VecTy = cast<VectorType>(CI->getType()); 1494 unsigned NumElts = VecTy->getNumElements(); 1495 1496 SmallVector<uint32_t, 16> Idxs(NumElts); 1497 for (unsigned i = 0; i != NumElts; ++i) 1498 Idxs[i] = ((Imm >> (i%8)) & 1) ? i + NumElts : i; 1499 1500 Rep = Builder.CreateShuffleVector(Op0, Op1, Idxs); 1501 } else if (IsX86 && (Name.startswith("avx.vinsertf128.") || 1502 Name == "avx2.vinserti128" || 1503 Name.startswith("avx512.mask.insert"))) { 1504 Value *Op0 = CI->getArgOperand(0); 1505 Value *Op1 = CI->getArgOperand(1); 1506 unsigned Imm = cast<ConstantInt>(CI->getArgOperand(2))->getZExtValue(); 1507 unsigned DstNumElts = CI->getType()->getVectorNumElements(); 1508 unsigned SrcNumElts = Op1->getType()->getVectorNumElements(); 1509 unsigned Scale = DstNumElts / SrcNumElts; 1510 1511 // Mask off the high bits of the immediate value; hardware ignores those. 1512 Imm = Imm % Scale; 1513 1514 // Extend the second operand into a vector the size of the destination. 1515 Value *UndefV = UndefValue::get(Op1->getType()); 1516 SmallVector<uint32_t, 8> Idxs(DstNumElts); 1517 for (unsigned i = 0; i != SrcNumElts; ++i) 1518 Idxs[i] = i; 1519 for (unsigned i = SrcNumElts; i != DstNumElts; ++i) 1520 Idxs[i] = SrcNumElts; 1521 Rep = Builder.CreateShuffleVector(Op1, UndefV, Idxs); 1522 1523 // Insert the second operand into the first operand. 1524 1525 // Note that there is no guarantee that instruction lowering will actually 1526 // produce a vinsertf128 instruction for the created shuffles. In 1527 // particular, the 0 immediate case involves no lane changes, so it can 1528 // be handled as a blend. 1529 1530 // Example of shuffle mask for 32-bit elements: 1531 // Imm = 1 <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11> 1532 // Imm = 0 <i32 8, i32 9, i32 10, i32 11, i32 4, i32 5, i32 6, i32 7 > 1533 1534 // First fill with identify mask. 1535 for (unsigned i = 0; i != DstNumElts; ++i) 1536 Idxs[i] = i; 1537 // Then replace the elements where we need to insert. 1538 for (unsigned i = 0; i != SrcNumElts; ++i) 1539 Idxs[i + Imm * SrcNumElts] = i + DstNumElts; 1540 Rep = Builder.CreateShuffleVector(Op0, Rep, Idxs); 1541 1542 // If the intrinsic has a mask operand, handle that. 1543 if (CI->getNumArgOperands() == 5) 1544 Rep = EmitX86Select(Builder, CI->getArgOperand(4), Rep, 1545 CI->getArgOperand(3)); 1546 } else if (IsX86 && (Name.startswith("avx.vextractf128.") || 1547 Name == "avx2.vextracti128" || 1548 Name.startswith("avx512.mask.vextract"))) { 1549 Value *Op0 = CI->getArgOperand(0); 1550 unsigned Imm = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue(); 1551 unsigned DstNumElts = CI->getType()->getVectorNumElements(); 1552 unsigned SrcNumElts = Op0->getType()->getVectorNumElements(); 1553 unsigned Scale = SrcNumElts / DstNumElts; 1554 1555 // Mask off the high bits of the immediate value; hardware ignores those. 1556 Imm = Imm % Scale; 1557 1558 // Get indexes for the subvector of the input vector. 1559 SmallVector<uint32_t, 8> Idxs(DstNumElts); 1560 for (unsigned i = 0; i != DstNumElts; ++i) { 1561 Idxs[i] = i + (Imm * DstNumElts); 1562 } 1563 Rep = Builder.CreateShuffleVector(Op0, Op0, Idxs); 1564 1565 // If the intrinsic has a mask operand, handle that. 1566 if (CI->getNumArgOperands() == 4) 1567 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1568 CI->getArgOperand(2)); 1569 } else if (!IsX86 && Name == "stackprotectorcheck") { 1570 Rep = nullptr; 1571 } else if (IsX86 && (Name.startswith("avx512.mask.perm.df.") || 1572 Name.startswith("avx512.mask.perm.di."))) { 1573 Value *Op0 = CI->getArgOperand(0); 1574 unsigned Imm = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue(); 1575 VectorType *VecTy = cast<VectorType>(CI->getType()); 1576 unsigned NumElts = VecTy->getNumElements(); 1577 1578 SmallVector<uint32_t, 8> Idxs(NumElts); 1579 for (unsigned i = 0; i != NumElts; ++i) 1580 Idxs[i] = (i & ~0x3) + ((Imm >> (2 * (i & 0x3))) & 3); 1581 1582 Rep = Builder.CreateShuffleVector(Op0, Op0, Idxs); 1583 1584 if (CI->getNumArgOperands() == 4) 1585 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1586 CI->getArgOperand(2)); 1587 } else if (IsX86 && (Name.startswith("avx.vperm2f128.") || 1588 Name == "avx2.vperm2i128")) { 1589 // The immediate permute control byte looks like this: 1590 // [1:0] - select 128 bits from sources for low half of destination 1591 // [2] - ignore 1592 // [3] - zero low half of destination 1593 // [5:4] - select 128 bits from sources for high half of destination 1594 // [6] - ignore 1595 // [7] - zero high half of destination 1596 1597 uint8_t Imm = cast<ConstantInt>(CI->getArgOperand(2))->getZExtValue(); 1598 1599 unsigned NumElts = CI->getType()->getVectorNumElements(); 1600 unsigned HalfSize = NumElts / 2; 1601 SmallVector<uint32_t, 8> ShuffleMask(NumElts); 1602 1603 // Determine which operand(s) are actually in use for this instruction. 1604 Value *V0 = (Imm & 0x02) ? CI->getArgOperand(1) : CI->getArgOperand(0); 1605 Value *V1 = (Imm & 0x20) ? CI->getArgOperand(1) : CI->getArgOperand(0); 1606 1607 // If needed, replace operands based on zero mask. 1608 V0 = (Imm & 0x08) ? ConstantAggregateZero::get(CI->getType()) : V0; 1609 V1 = (Imm & 0x80) ? ConstantAggregateZero::get(CI->getType()) : V1; 1610 1611 // Permute low half of result. 1612 unsigned StartIndex = (Imm & 0x01) ? HalfSize : 0; 1613 for (unsigned i = 0; i < HalfSize; ++i) 1614 ShuffleMask[i] = StartIndex + i; 1615 1616 // Permute high half of result. 1617 StartIndex = (Imm & 0x10) ? HalfSize : 0; 1618 for (unsigned i = 0; i < HalfSize; ++i) 1619 ShuffleMask[i + HalfSize] = NumElts + StartIndex + i; 1620 1621 Rep = Builder.CreateShuffleVector(V0, V1, ShuffleMask); 1622 1623 } else if (IsX86 && (Name.startswith("avx.vpermil.") || 1624 Name == "sse2.pshuf.d" || 1625 Name.startswith("avx512.mask.vpermil.p") || 1626 Name.startswith("avx512.mask.pshuf.d."))) { 1627 Value *Op0 = CI->getArgOperand(0); 1628 unsigned Imm = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue(); 1629 VectorType *VecTy = cast<VectorType>(CI->getType()); 1630 unsigned NumElts = VecTy->getNumElements(); 1631 // Calculate the size of each index in the immediate. 1632 unsigned IdxSize = 64 / VecTy->getScalarSizeInBits(); 1633 unsigned IdxMask = ((1 << IdxSize) - 1); 1634 1635 SmallVector<uint32_t, 8> Idxs(NumElts); 1636 // Lookup the bits for this element, wrapping around the immediate every 1637 // 8-bits. Elements are grouped into sets of 2 or 4 elements so we need 1638 // to offset by the first index of each group. 1639 for (unsigned i = 0; i != NumElts; ++i) 1640 Idxs[i] = ((Imm >> ((i * IdxSize) % 8)) & IdxMask) | (i & ~IdxMask); 1641 1642 Rep = Builder.CreateShuffleVector(Op0, Op0, Idxs); 1643 1644 if (CI->getNumArgOperands() == 4) 1645 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1646 CI->getArgOperand(2)); 1647 } else if (IsX86 && (Name == "sse2.pshufl.w" || 1648 Name.startswith("avx512.mask.pshufl.w."))) { 1649 Value *Op0 = CI->getArgOperand(0); 1650 unsigned Imm = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue(); 1651 unsigned NumElts = CI->getType()->getVectorNumElements(); 1652 1653 SmallVector<uint32_t, 16> Idxs(NumElts); 1654 for (unsigned l = 0; l != NumElts; l += 8) { 1655 for (unsigned i = 0; i != 4; ++i) 1656 Idxs[i + l] = ((Imm >> (2 * i)) & 0x3) + l; 1657 for (unsigned i = 4; i != 8; ++i) 1658 Idxs[i + l] = i + l; 1659 } 1660 1661 Rep = Builder.CreateShuffleVector(Op0, Op0, Idxs); 1662 1663 if (CI->getNumArgOperands() == 4) 1664 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1665 CI->getArgOperand(2)); 1666 } else if (IsX86 && (Name == "sse2.pshufh.w" || 1667 Name.startswith("avx512.mask.pshufh.w."))) { 1668 Value *Op0 = CI->getArgOperand(0); 1669 unsigned Imm = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue(); 1670 unsigned NumElts = CI->getType()->getVectorNumElements(); 1671 1672 SmallVector<uint32_t, 16> Idxs(NumElts); 1673 for (unsigned l = 0; l != NumElts; l += 8) { 1674 for (unsigned i = 0; i != 4; ++i) 1675 Idxs[i + l] = i + l; 1676 for (unsigned i = 0; i != 4; ++i) 1677 Idxs[i + l + 4] = ((Imm >> (2 * i)) & 0x3) + 4 + l; 1678 } 1679 1680 Rep = Builder.CreateShuffleVector(Op0, Op0, Idxs); 1681 1682 if (CI->getNumArgOperands() == 4) 1683 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1684 CI->getArgOperand(2)); 1685 } else if (IsX86 && Name.startswith("avx512.mask.shuf.p")) { 1686 Value *Op0 = CI->getArgOperand(0); 1687 Value *Op1 = CI->getArgOperand(1); 1688 unsigned Imm = cast<ConstantInt>(CI->getArgOperand(2))->getZExtValue(); 1689 unsigned NumElts = CI->getType()->getVectorNumElements(); 1690 1691 unsigned NumLaneElts = 128/CI->getType()->getScalarSizeInBits(); 1692 unsigned HalfLaneElts = NumLaneElts / 2; 1693 1694 SmallVector<uint32_t, 16> Idxs(NumElts); 1695 for (unsigned i = 0; i != NumElts; ++i) { 1696 // Base index is the starting element of the lane. 1697 Idxs[i] = i - (i % NumLaneElts); 1698 // If we are half way through the lane switch to the other source. 1699 if ((i % NumLaneElts) >= HalfLaneElts) 1700 Idxs[i] += NumElts; 1701 // Now select the specific element. By adding HalfLaneElts bits from 1702 // the immediate. Wrapping around the immediate every 8-bits. 1703 Idxs[i] += (Imm >> ((i * HalfLaneElts) % 8)) & ((1 << HalfLaneElts) - 1); 1704 } 1705 1706 Rep = Builder.CreateShuffleVector(Op0, Op1, Idxs); 1707 1708 Rep = EmitX86Select(Builder, CI->getArgOperand(4), Rep, 1709 CI->getArgOperand(3)); 1710 } else if (IsX86 && (Name.startswith("avx512.mask.movddup") || 1711 Name.startswith("avx512.mask.movshdup") || 1712 Name.startswith("avx512.mask.movsldup"))) { 1713 Value *Op0 = CI->getArgOperand(0); 1714 unsigned NumElts = CI->getType()->getVectorNumElements(); 1715 unsigned NumLaneElts = 128/CI->getType()->getScalarSizeInBits(); 1716 1717 unsigned Offset = 0; 1718 if (Name.startswith("avx512.mask.movshdup.")) 1719 Offset = 1; 1720 1721 SmallVector<uint32_t, 16> Idxs(NumElts); 1722 for (unsigned l = 0; l != NumElts; l += NumLaneElts) 1723 for (unsigned i = 0; i != NumLaneElts; i += 2) { 1724 Idxs[i + l + 0] = i + l + Offset; 1725 Idxs[i + l + 1] = i + l + Offset; 1726 } 1727 1728 Rep = Builder.CreateShuffleVector(Op0, Op0, Idxs); 1729 1730 Rep = EmitX86Select(Builder, CI->getArgOperand(2), Rep, 1731 CI->getArgOperand(1)); 1732 } else if (IsX86 && (Name.startswith("avx512.mask.punpckl") || 1733 Name.startswith("avx512.mask.unpckl."))) { 1734 Value *Op0 = CI->getArgOperand(0); 1735 Value *Op1 = CI->getArgOperand(1); 1736 int NumElts = CI->getType()->getVectorNumElements(); 1737 int NumLaneElts = 128/CI->getType()->getScalarSizeInBits(); 1738 1739 SmallVector<uint32_t, 64> Idxs(NumElts); 1740 for (int l = 0; l != NumElts; l += NumLaneElts) 1741 for (int i = 0; i != NumLaneElts; ++i) 1742 Idxs[i + l] = l + (i / 2) + NumElts * (i % 2); 1743 1744 Rep = Builder.CreateShuffleVector(Op0, Op1, Idxs); 1745 1746 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1747 CI->getArgOperand(2)); 1748 } else if (IsX86 && (Name.startswith("avx512.mask.punpckh") || 1749 Name.startswith("avx512.mask.unpckh."))) { 1750 Value *Op0 = CI->getArgOperand(0); 1751 Value *Op1 = CI->getArgOperand(1); 1752 int NumElts = CI->getType()->getVectorNumElements(); 1753 int NumLaneElts = 128/CI->getType()->getScalarSizeInBits(); 1754 1755 SmallVector<uint32_t, 64> Idxs(NumElts); 1756 for (int l = 0; l != NumElts; l += NumLaneElts) 1757 for (int i = 0; i != NumLaneElts; ++i) 1758 Idxs[i + l] = (NumLaneElts / 2) + l + (i / 2) + NumElts * (i % 2); 1759 1760 Rep = Builder.CreateShuffleVector(Op0, Op1, Idxs); 1761 1762 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1763 CI->getArgOperand(2)); 1764 } else if (IsX86 && Name.startswith("avx512.mask.pand.")) { 1765 Rep = Builder.CreateAnd(CI->getArgOperand(0), CI->getArgOperand(1)); 1766 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1767 CI->getArgOperand(2)); 1768 } else if (IsX86 && Name.startswith("avx512.mask.pandn.")) { 1769 Rep = Builder.CreateAnd(Builder.CreateNot(CI->getArgOperand(0)), 1770 CI->getArgOperand(1)); 1771 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1772 CI->getArgOperand(2)); 1773 } else if (IsX86 && Name.startswith("avx512.mask.por.")) { 1774 Rep = Builder.CreateOr(CI->getArgOperand(0), CI->getArgOperand(1)); 1775 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1776 CI->getArgOperand(2)); 1777 } else if (IsX86 && Name.startswith("avx512.mask.pxor.")) { 1778 Rep = Builder.CreateXor(CI->getArgOperand(0), CI->getArgOperand(1)); 1779 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1780 CI->getArgOperand(2)); 1781 } else if (IsX86 && Name.startswith("avx512.mask.and.")) { 1782 VectorType *FTy = cast<VectorType>(CI->getType()); 1783 VectorType *ITy = VectorType::getInteger(FTy); 1784 Rep = Builder.CreateAnd(Builder.CreateBitCast(CI->getArgOperand(0), ITy), 1785 Builder.CreateBitCast(CI->getArgOperand(1), ITy)); 1786 Rep = Builder.CreateBitCast(Rep, FTy); 1787 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1788 CI->getArgOperand(2)); 1789 } else if (IsX86 && Name.startswith("avx512.mask.andn.")) { 1790 VectorType *FTy = cast<VectorType>(CI->getType()); 1791 VectorType *ITy = VectorType::getInteger(FTy); 1792 Rep = Builder.CreateNot(Builder.CreateBitCast(CI->getArgOperand(0), ITy)); 1793 Rep = Builder.CreateAnd(Rep, 1794 Builder.CreateBitCast(CI->getArgOperand(1), ITy)); 1795 Rep = Builder.CreateBitCast(Rep, FTy); 1796 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1797 CI->getArgOperand(2)); 1798 } else if (IsX86 && Name.startswith("avx512.mask.or.")) { 1799 VectorType *FTy = cast<VectorType>(CI->getType()); 1800 VectorType *ITy = VectorType::getInteger(FTy); 1801 Rep = Builder.CreateOr(Builder.CreateBitCast(CI->getArgOperand(0), ITy), 1802 Builder.CreateBitCast(CI->getArgOperand(1), ITy)); 1803 Rep = Builder.CreateBitCast(Rep, FTy); 1804 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1805 CI->getArgOperand(2)); 1806 } else if (IsX86 && Name.startswith("avx512.mask.xor.")) { 1807 VectorType *FTy = cast<VectorType>(CI->getType()); 1808 VectorType *ITy = VectorType::getInteger(FTy); 1809 Rep = Builder.CreateXor(Builder.CreateBitCast(CI->getArgOperand(0), ITy), 1810 Builder.CreateBitCast(CI->getArgOperand(1), ITy)); 1811 Rep = Builder.CreateBitCast(Rep, FTy); 1812 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1813 CI->getArgOperand(2)); 1814 } else if (IsX86 && Name.startswith("avx512.mask.padd.")) { 1815 Rep = Builder.CreateAdd(CI->getArgOperand(0), CI->getArgOperand(1)); 1816 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1817 CI->getArgOperand(2)); 1818 } else if (IsX86 && Name.startswith("avx512.mask.psub.")) { 1819 Rep = Builder.CreateSub(CI->getArgOperand(0), CI->getArgOperand(1)); 1820 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1821 CI->getArgOperand(2)); 1822 } else if (IsX86 && Name.startswith("avx512.mask.pmull.")) { 1823 Rep = Builder.CreateMul(CI->getArgOperand(0), CI->getArgOperand(1)); 1824 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1825 CI->getArgOperand(2)); 1826 } else if (IsX86 && (Name.startswith("avx512.mask.add.p"))) { 1827 Rep = Builder.CreateFAdd(CI->getArgOperand(0), CI->getArgOperand(1)); 1828 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1829 CI->getArgOperand(2)); 1830 } else if (IsX86 && Name.startswith("avx512.mask.div.p")) { 1831 Rep = Builder.CreateFDiv(CI->getArgOperand(0), CI->getArgOperand(1)); 1832 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1833 CI->getArgOperand(2)); 1834 } else if (IsX86 && Name.startswith("avx512.mask.mul.p")) { 1835 Rep = Builder.CreateFMul(CI->getArgOperand(0), CI->getArgOperand(1)); 1836 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1837 CI->getArgOperand(2)); 1838 } else if (IsX86 && Name.startswith("avx512.mask.sub.p")) { 1839 Rep = Builder.CreateFSub(CI->getArgOperand(0), CI->getArgOperand(1)); 1840 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1841 CI->getArgOperand(2)); 1842 } else if (IsX86 && Name.startswith("avx512.mask.lzcnt.")) { 1843 Rep = Builder.CreateCall(Intrinsic::getDeclaration(F->getParent(), 1844 Intrinsic::ctlz, 1845 CI->getType()), 1846 { CI->getArgOperand(0), Builder.getInt1(false) }); 1847 Rep = EmitX86Select(Builder, CI->getArgOperand(2), Rep, 1848 CI->getArgOperand(1)); 1849 } else if (IsX86 && (Name.startswith("avx512.mask.max.p") || 1850 Name.startswith("avx512.mask.min.p"))) { 1851 bool IsMin = Name[13] == 'i'; 1852 VectorType *VecTy = cast<VectorType>(CI->getType()); 1853 unsigned VecWidth = VecTy->getPrimitiveSizeInBits(); 1854 unsigned EltWidth = VecTy->getScalarSizeInBits(); 1855 Intrinsic::ID IID; 1856 if (!IsMin && VecWidth == 128 && EltWidth == 32) 1857 IID = Intrinsic::x86_sse_max_ps; 1858 else if (!IsMin && VecWidth == 128 && EltWidth == 64) 1859 IID = Intrinsic::x86_sse2_max_pd; 1860 else if (!IsMin && VecWidth == 256 && EltWidth == 32) 1861 IID = Intrinsic::x86_avx_max_ps_256; 1862 else if (!IsMin && VecWidth == 256 && EltWidth == 64) 1863 IID = Intrinsic::x86_avx_max_pd_256; 1864 else if (IsMin && VecWidth == 128 && EltWidth == 32) 1865 IID = Intrinsic::x86_sse_min_ps; 1866 else if (IsMin && VecWidth == 128 && EltWidth == 64) 1867 IID = Intrinsic::x86_sse2_min_pd; 1868 else if (IsMin && VecWidth == 256 && EltWidth == 32) 1869 IID = Intrinsic::x86_avx_min_ps_256; 1870 else if (IsMin && VecWidth == 256 && EltWidth == 64) 1871 IID = Intrinsic::x86_avx_min_pd_256; 1872 else 1873 llvm_unreachable("Unexpected intrinsic"); 1874 1875 Rep = Builder.CreateCall(Intrinsic::getDeclaration(F->getParent(), IID), 1876 { CI->getArgOperand(0), CI->getArgOperand(1) }); 1877 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1878 CI->getArgOperand(2)); 1879 } else if (IsX86 && Name.startswith("avx512.mask.pshuf.b.")) { 1880 VectorType *VecTy = cast<VectorType>(CI->getType()); 1881 Intrinsic::ID IID; 1882 if (VecTy->getPrimitiveSizeInBits() == 128) 1883 IID = Intrinsic::x86_ssse3_pshuf_b_128; 1884 else if (VecTy->getPrimitiveSizeInBits() == 256) 1885 IID = Intrinsic::x86_avx2_pshuf_b; 1886 else if (VecTy->getPrimitiveSizeInBits() == 512) 1887 IID = Intrinsic::x86_avx512_pshuf_b_512; 1888 else 1889 llvm_unreachable("Unexpected intrinsic"); 1890 1891 Rep = Builder.CreateCall(Intrinsic::getDeclaration(F->getParent(), IID), 1892 { CI->getArgOperand(0), CI->getArgOperand(1) }); 1893 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1894 CI->getArgOperand(2)); 1895 } else if (IsX86 && (Name.startswith("avx512.mask.pmul.dq.") || 1896 Name.startswith("avx512.mask.pmulu.dq."))) { 1897 bool IsUnsigned = Name[16] == 'u'; 1898 VectorType *VecTy = cast<VectorType>(CI->getType()); 1899 Intrinsic::ID IID; 1900 if (!IsUnsigned && VecTy->getPrimitiveSizeInBits() == 128) 1901 IID = Intrinsic::x86_sse41_pmuldq; 1902 else if (!IsUnsigned && VecTy->getPrimitiveSizeInBits() == 256) 1903 IID = Intrinsic::x86_avx2_pmul_dq; 1904 else if (!IsUnsigned && VecTy->getPrimitiveSizeInBits() == 512) 1905 IID = Intrinsic::x86_avx512_pmul_dq_512; 1906 else if (IsUnsigned && VecTy->getPrimitiveSizeInBits() == 128) 1907 IID = Intrinsic::x86_sse2_pmulu_dq; 1908 else if (IsUnsigned && VecTy->getPrimitiveSizeInBits() == 256) 1909 IID = Intrinsic::x86_avx2_pmulu_dq; 1910 else if (IsUnsigned && VecTy->getPrimitiveSizeInBits() == 512) 1911 IID = Intrinsic::x86_avx512_pmulu_dq_512; 1912 else 1913 llvm_unreachable("Unexpected intrinsic"); 1914 1915 Rep = Builder.CreateCall(Intrinsic::getDeclaration(F->getParent(), IID), 1916 { CI->getArgOperand(0), CI->getArgOperand(1) }); 1917 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1918 CI->getArgOperand(2)); 1919 } else if (IsX86 && Name.startswith("avx512.mask.pack")) { 1920 bool IsUnsigned = Name[16] == 'u'; 1921 bool IsDW = Name[18] == 'd'; 1922 VectorType *VecTy = cast<VectorType>(CI->getType()); 1923 Intrinsic::ID IID; 1924 if (!IsUnsigned && !IsDW && VecTy->getPrimitiveSizeInBits() == 128) 1925 IID = Intrinsic::x86_sse2_packsswb_128; 1926 else if (!IsUnsigned && !IsDW && VecTy->getPrimitiveSizeInBits() == 256) 1927 IID = Intrinsic::x86_avx2_packsswb; 1928 else if (!IsUnsigned && !IsDW && VecTy->getPrimitiveSizeInBits() == 512) 1929 IID = Intrinsic::x86_avx512_packsswb_512; 1930 else if (!IsUnsigned && IsDW && VecTy->getPrimitiveSizeInBits() == 128) 1931 IID = Intrinsic::x86_sse2_packssdw_128; 1932 else if (!IsUnsigned && IsDW && VecTy->getPrimitiveSizeInBits() == 256) 1933 IID = Intrinsic::x86_avx2_packssdw; 1934 else if (!IsUnsigned && IsDW && VecTy->getPrimitiveSizeInBits() == 512) 1935 IID = Intrinsic::x86_avx512_packssdw_512; 1936 else if (IsUnsigned && !IsDW && VecTy->getPrimitiveSizeInBits() == 128) 1937 IID = Intrinsic::x86_sse2_packuswb_128; 1938 else if (IsUnsigned && !IsDW && VecTy->getPrimitiveSizeInBits() == 256) 1939 IID = Intrinsic::x86_avx2_packuswb; 1940 else if (IsUnsigned && !IsDW && VecTy->getPrimitiveSizeInBits() == 512) 1941 IID = Intrinsic::x86_avx512_packuswb_512; 1942 else if (IsUnsigned && IsDW && VecTy->getPrimitiveSizeInBits() == 128) 1943 IID = Intrinsic::x86_sse41_packusdw; 1944 else if (IsUnsigned && IsDW && VecTy->getPrimitiveSizeInBits() == 256) 1945 IID = Intrinsic::x86_avx2_packusdw; 1946 else if (IsUnsigned && IsDW && VecTy->getPrimitiveSizeInBits() == 512) 1947 IID = Intrinsic::x86_avx512_packusdw_512; 1948 else 1949 llvm_unreachable("Unexpected intrinsic"); 1950 1951 Rep = Builder.CreateCall(Intrinsic::getDeclaration(F->getParent(), IID), 1952 { CI->getArgOperand(0), CI->getArgOperand(1) }); 1953 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1954 CI->getArgOperand(2)); 1955 } else if (IsX86 && Name.startswith("avx512.mask.psll")) { 1956 bool IsImmediate = Name[16] == 'i' || 1957 (Name.size() > 18 && Name[18] == 'i'); 1958 bool IsVariable = Name[16] == 'v'; 1959 char Size = Name[16] == '.' ? Name[17] : 1960 Name[17] == '.' ? Name[18] : 1961 Name[18] == '.' ? Name[19] : 1962 Name[20]; 1963 1964 Intrinsic::ID IID; 1965 if (IsVariable && Name[17] != '.') { 1966 if (Size == 'd' && Name[17] == '2') // avx512.mask.psllv2.di 1967 IID = Intrinsic::x86_avx2_psllv_q; 1968 else if (Size == 'd' && Name[17] == '4') // avx512.mask.psllv4.di 1969 IID = Intrinsic::x86_avx2_psllv_q_256; 1970 else if (Size == 's' && Name[17] == '4') // avx512.mask.psllv4.si 1971 IID = Intrinsic::x86_avx2_psllv_d; 1972 else if (Size == 's' && Name[17] == '8') // avx512.mask.psllv8.si 1973 IID = Intrinsic::x86_avx2_psllv_d_256; 1974 else if (Size == 'h' && Name[17] == '8') // avx512.mask.psllv8.hi 1975 IID = Intrinsic::x86_avx512_psllv_w_128; 1976 else if (Size == 'h' && Name[17] == '1') // avx512.mask.psllv16.hi 1977 IID = Intrinsic::x86_avx512_psllv_w_256; 1978 else if (Name[17] == '3' && Name[18] == '2') // avx512.mask.psllv32hi 1979 IID = Intrinsic::x86_avx512_psllv_w_512; 1980 else 1981 llvm_unreachable("Unexpected size"); 1982 } else if (Name.endswith(".128")) { 1983 if (Size == 'd') // avx512.mask.psll.d.128, avx512.mask.psll.di.128 1984 IID = IsImmediate ? Intrinsic::x86_sse2_pslli_d 1985 : Intrinsic::x86_sse2_psll_d; 1986 else if (Size == 'q') // avx512.mask.psll.q.128, avx512.mask.psll.qi.128 1987 IID = IsImmediate ? Intrinsic::x86_sse2_pslli_q 1988 : Intrinsic::x86_sse2_psll_q; 1989 else if (Size == 'w') // avx512.mask.psll.w.128, avx512.mask.psll.wi.128 1990 IID = IsImmediate ? Intrinsic::x86_sse2_pslli_w 1991 : Intrinsic::x86_sse2_psll_w; 1992 else 1993 llvm_unreachable("Unexpected size"); 1994 } else if (Name.endswith(".256")) { 1995 if (Size == 'd') // avx512.mask.psll.d.256, avx512.mask.psll.di.256 1996 IID = IsImmediate ? Intrinsic::x86_avx2_pslli_d 1997 : Intrinsic::x86_avx2_psll_d; 1998 else if (Size == 'q') // avx512.mask.psll.q.256, avx512.mask.psll.qi.256 1999 IID = IsImmediate ? Intrinsic::x86_avx2_pslli_q 2000 : Intrinsic::x86_avx2_psll_q; 2001 else if (Size == 'w') // avx512.mask.psll.w.256, avx512.mask.psll.wi.256 2002 IID = IsImmediate ? Intrinsic::x86_avx2_pslli_w 2003 : Intrinsic::x86_avx2_psll_w; 2004 else 2005 llvm_unreachable("Unexpected size"); 2006 } else { 2007 if (Size == 'd') // psll.di.512, pslli.d, psll.d, psllv.d.512 2008 IID = IsImmediate ? Intrinsic::x86_avx512_pslli_d_512 : 2009 IsVariable ? Intrinsic::x86_avx512_psllv_d_512 : 2010 Intrinsic::x86_avx512_psll_d_512; 2011 else if (Size == 'q') // psll.qi.512, pslli.q, psll.q, psllv.q.512 2012 IID = IsImmediate ? Intrinsic::x86_avx512_pslli_q_512 : 2013 IsVariable ? Intrinsic::x86_avx512_psllv_q_512 : 2014 Intrinsic::x86_avx512_psll_q_512; 2015 else if (Size == 'w') // psll.wi.512, pslli.w, psll.w 2016 IID = IsImmediate ? Intrinsic::x86_avx512_pslli_w_512 2017 : Intrinsic::x86_avx512_psll_w_512; 2018 else 2019 llvm_unreachable("Unexpected size"); 2020 } 2021 2022 Rep = UpgradeX86MaskedShift(Builder, *CI, IID); 2023 } else if (IsX86 && Name.startswith("avx512.mask.psrl")) { 2024 bool IsImmediate = Name[16] == 'i' || 2025 (Name.size() > 18 && Name[18] == 'i'); 2026 bool IsVariable = Name[16] == 'v'; 2027 char Size = Name[16] == '.' ? Name[17] : 2028 Name[17] == '.' ? Name[18] : 2029 Name[18] == '.' ? Name[19] : 2030 Name[20]; 2031 2032 Intrinsic::ID IID; 2033 if (IsVariable && Name[17] != '.') { 2034 if (Size == 'd' && Name[17] == '2') // avx512.mask.psrlv2.di 2035 IID = Intrinsic::x86_avx2_psrlv_q; 2036 else if (Size == 'd' && Name[17] == '4') // avx512.mask.psrlv4.di 2037 IID = Intrinsic::x86_avx2_psrlv_q_256; 2038 else if (Size == 's' && Name[17] == '4') // avx512.mask.psrlv4.si 2039 IID = Intrinsic::x86_avx2_psrlv_d; 2040 else if (Size == 's' && Name[17] == '8') // avx512.mask.psrlv8.si 2041 IID = Intrinsic::x86_avx2_psrlv_d_256; 2042 else if (Size == 'h' && Name[17] == '8') // avx512.mask.psrlv8.hi 2043 IID = Intrinsic::x86_avx512_psrlv_w_128; 2044 else if (Size == 'h' && Name[17] == '1') // avx512.mask.psrlv16.hi 2045 IID = Intrinsic::x86_avx512_psrlv_w_256; 2046 else if (Name[17] == '3' && Name[18] == '2') // avx512.mask.psrlv32hi 2047 IID = Intrinsic::x86_avx512_psrlv_w_512; 2048 else 2049 llvm_unreachable("Unexpected size"); 2050 } else if (Name.endswith(".128")) { 2051 if (Size == 'd') // avx512.mask.psrl.d.128, avx512.mask.psrl.di.128 2052 IID = IsImmediate ? Intrinsic::x86_sse2_psrli_d 2053 : Intrinsic::x86_sse2_psrl_d; 2054 else if (Size == 'q') // avx512.mask.psrl.q.128, avx512.mask.psrl.qi.128 2055 IID = IsImmediate ? Intrinsic::x86_sse2_psrli_q 2056 : Intrinsic::x86_sse2_psrl_q; 2057 else if (Size == 'w') // avx512.mask.psrl.w.128, avx512.mask.psrl.wi.128 2058 IID = IsImmediate ? Intrinsic::x86_sse2_psrli_w 2059 : Intrinsic::x86_sse2_psrl_w; 2060 else 2061 llvm_unreachable("Unexpected size"); 2062 } else if (Name.endswith(".256")) { 2063 if (Size == 'd') // avx512.mask.psrl.d.256, avx512.mask.psrl.di.256 2064 IID = IsImmediate ? Intrinsic::x86_avx2_psrli_d 2065 : Intrinsic::x86_avx2_psrl_d; 2066 else if (Size == 'q') // avx512.mask.psrl.q.256, avx512.mask.psrl.qi.256 2067 IID = IsImmediate ? Intrinsic::x86_avx2_psrli_q 2068 : Intrinsic::x86_avx2_psrl_q; 2069 else if (Size == 'w') // avx512.mask.psrl.w.256, avx512.mask.psrl.wi.256 2070 IID = IsImmediate ? Intrinsic::x86_avx2_psrli_w 2071 : Intrinsic::x86_avx2_psrl_w; 2072 else 2073 llvm_unreachable("Unexpected size"); 2074 } else { 2075 if (Size == 'd') // psrl.di.512, psrli.d, psrl.d, psrl.d.512 2076 IID = IsImmediate ? Intrinsic::x86_avx512_psrli_d_512 : 2077 IsVariable ? Intrinsic::x86_avx512_psrlv_d_512 : 2078 Intrinsic::x86_avx512_psrl_d_512; 2079 else if (Size == 'q') // psrl.qi.512, psrli.q, psrl.q, psrl.q.512 2080 IID = IsImmediate ? Intrinsic::x86_avx512_psrli_q_512 : 2081 IsVariable ? Intrinsic::x86_avx512_psrlv_q_512 : 2082 Intrinsic::x86_avx512_psrl_q_512; 2083 else if (Size == 'w') // psrl.wi.512, psrli.w, psrl.w) 2084 IID = IsImmediate ? Intrinsic::x86_avx512_psrli_w_512 2085 : Intrinsic::x86_avx512_psrl_w_512; 2086 else 2087 llvm_unreachable("Unexpected size"); 2088 } 2089 2090 Rep = UpgradeX86MaskedShift(Builder, *CI, IID); 2091 } else if (IsX86 && Name.startswith("avx512.mask.psra")) { 2092 bool IsImmediate = Name[16] == 'i' || 2093 (Name.size() > 18 && Name[18] == 'i'); 2094 bool IsVariable = Name[16] == 'v'; 2095 char Size = Name[16] == '.' ? Name[17] : 2096 Name[17] == '.' ? Name[18] : 2097 Name[18] == '.' ? Name[19] : 2098 Name[20]; 2099 2100 Intrinsic::ID IID; 2101 if (IsVariable && Name[17] != '.') { 2102 if (Size == 's' && Name[17] == '4') // avx512.mask.psrav4.si 2103 IID = Intrinsic::x86_avx2_psrav_d; 2104 else if (Size == 's' && Name[17] == '8') // avx512.mask.psrav8.si 2105 IID = Intrinsic::x86_avx2_psrav_d_256; 2106 else if (Size == 'h' && Name[17] == '8') // avx512.mask.psrav8.hi 2107 IID = Intrinsic::x86_avx512_psrav_w_128; 2108 else if (Size == 'h' && Name[17] == '1') // avx512.mask.psrav16.hi 2109 IID = Intrinsic::x86_avx512_psrav_w_256; 2110 else if (Name[17] == '3' && Name[18] == '2') // avx512.mask.psrav32hi 2111 IID = Intrinsic::x86_avx512_psrav_w_512; 2112 else 2113 llvm_unreachable("Unexpected size"); 2114 } else if (Name.endswith(".128")) { 2115 if (Size == 'd') // avx512.mask.psra.d.128, avx512.mask.psra.di.128 2116 IID = IsImmediate ? Intrinsic::x86_sse2_psrai_d 2117 : Intrinsic::x86_sse2_psra_d; 2118 else if (Size == 'q') // avx512.mask.psra.q.128, avx512.mask.psra.qi.128 2119 IID = IsImmediate ? Intrinsic::x86_avx512_psrai_q_128 : 2120 IsVariable ? Intrinsic::x86_avx512_psrav_q_128 : 2121 Intrinsic::x86_avx512_psra_q_128; 2122 else if (Size == 'w') // avx512.mask.psra.w.128, avx512.mask.psra.wi.128 2123 IID = IsImmediate ? Intrinsic::x86_sse2_psrai_w 2124 : Intrinsic::x86_sse2_psra_w; 2125 else 2126 llvm_unreachable("Unexpected size"); 2127 } else if (Name.endswith(".256")) { 2128 if (Size == 'd') // avx512.mask.psra.d.256, avx512.mask.psra.di.256 2129 IID = IsImmediate ? Intrinsic::x86_avx2_psrai_d 2130 : Intrinsic::x86_avx2_psra_d; 2131 else if (Size == 'q') // avx512.mask.psra.q.256, avx512.mask.psra.qi.256 2132 IID = IsImmediate ? Intrinsic::x86_avx512_psrai_q_256 : 2133 IsVariable ? Intrinsic::x86_avx512_psrav_q_256 : 2134 Intrinsic::x86_avx512_psra_q_256; 2135 else if (Size == 'w') // avx512.mask.psra.w.256, avx512.mask.psra.wi.256 2136 IID = IsImmediate ? Intrinsic::x86_avx2_psrai_w 2137 : Intrinsic::x86_avx2_psra_w; 2138 else 2139 llvm_unreachable("Unexpected size"); 2140 } else { 2141 if (Size == 'd') // psra.di.512, psrai.d, psra.d, psrav.d.512 2142 IID = IsImmediate ? Intrinsic::x86_avx512_psrai_d_512 : 2143 IsVariable ? Intrinsic::x86_avx512_psrav_d_512 : 2144 Intrinsic::x86_avx512_psra_d_512; 2145 else if (Size == 'q') // psra.qi.512, psrai.q, psra.q 2146 IID = IsImmediate ? Intrinsic::x86_avx512_psrai_q_512 : 2147 IsVariable ? Intrinsic::x86_avx512_psrav_q_512 : 2148 Intrinsic::x86_avx512_psra_q_512; 2149 else if (Size == 'w') // psra.wi.512, psrai.w, psra.w 2150 IID = IsImmediate ? Intrinsic::x86_avx512_psrai_w_512 2151 : Intrinsic::x86_avx512_psra_w_512; 2152 else 2153 llvm_unreachable("Unexpected size"); 2154 } 2155 2156 Rep = UpgradeX86MaskedShift(Builder, *CI, IID); 2157 } else if (IsX86 && Name.startswith("avx512.mask.move.s")) { 2158 Rep = upgradeMaskedMove(Builder, *CI); 2159 } else if (IsX86 && Name.startswith("avx512.cvtmask2")) { 2160 Rep = UpgradeMaskToInt(Builder, *CI); 2161 } else if (IsX86 && Name.startswith("avx512.mask.vpermilvar.")) { 2162 Intrinsic::ID IID; 2163 if (Name.endswith("ps.128")) 2164 IID = Intrinsic::x86_avx_vpermilvar_ps; 2165 else if (Name.endswith("pd.128")) 2166 IID = Intrinsic::x86_avx_vpermilvar_pd; 2167 else if (Name.endswith("ps.256")) 2168 IID = Intrinsic::x86_avx_vpermilvar_ps_256; 2169 else if (Name.endswith("pd.256")) 2170 IID = Intrinsic::x86_avx_vpermilvar_pd_256; 2171 else if (Name.endswith("ps.512")) 2172 IID = Intrinsic::x86_avx512_vpermilvar_ps_512; 2173 else if (Name.endswith("pd.512")) 2174 IID = Intrinsic::x86_avx512_vpermilvar_pd_512; 2175 else 2176 llvm_unreachable("Unexpected vpermilvar intrinsic"); 2177 2178 Function *Intrin = Intrinsic::getDeclaration(F->getParent(), IID); 2179 Rep = Builder.CreateCall(Intrin, 2180 { CI->getArgOperand(0), CI->getArgOperand(1) }); 2181 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 2182 CI->getArgOperand(2)); 2183 } else if (IsX86 && Name.endswith(".movntdqa")) { 2184 Module *M = F->getParent(); 2185 MDNode *Node = MDNode::get( 2186 C, ConstantAsMetadata::get(ConstantInt::get(Type::getInt32Ty(C), 1))); 2187 2188 Value *Ptr = CI->getArgOperand(0); 2189 VectorType *VTy = cast<VectorType>(CI->getType()); 2190 2191 // Convert the type of the pointer to a pointer to the stored type. 2192 Value *BC = 2193 Builder.CreateBitCast(Ptr, PointerType::getUnqual(VTy), "cast"); 2194 LoadInst *LI = Builder.CreateAlignedLoad(BC, VTy->getBitWidth() / 8); 2195 LI->setMetadata(M->getMDKindID("nontemporal"), Node); 2196 Rep = LI; 2197 } else if (IsX86 && 2198 (Name.startswith("sse2.pavg") || Name.startswith("avx2.pavg") || 2199 Name.startswith("avx512.mask.pavg"))) { 2200 // llvm.x86.sse2.pavg.b/w, llvm.x86.avx2.pavg.b/w, 2201 // llvm.x86.avx512.mask.pavg.b/w 2202 Value *A = CI->getArgOperand(0); 2203 Value *B = CI->getArgOperand(1); 2204 VectorType *ZextType = VectorType::getExtendedElementVectorType( 2205 cast<VectorType>(A->getType())); 2206 Value *ExtendedA = Builder.CreateZExt(A, ZextType); 2207 Value *ExtendedB = Builder.CreateZExt(B, ZextType); 2208 Value *Sum = Builder.CreateAdd(ExtendedA, ExtendedB); 2209 Value *AddOne = Builder.CreateAdd(Sum, ConstantInt::get(ZextType, 1)); 2210 Value *ShiftR = Builder.CreateLShr(AddOne, ConstantInt::get(ZextType, 1)); 2211 Rep = Builder.CreateTrunc(ShiftR, A->getType()); 2212 if (CI->getNumArgOperands() > 2) { 2213 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 2214 CI->getArgOperand(2)); 2215 } 2216 } else if (IsNVVM && (Name == "abs.i" || Name == "abs.ll")) { 2217 Value *Arg = CI->getArgOperand(0); 2218 Value *Neg = Builder.CreateNeg(Arg, "neg"); 2219 Value *Cmp = Builder.CreateICmpSGE( 2220 Arg, llvm::Constant::getNullValue(Arg->getType()), "abs.cond"); 2221 Rep = Builder.CreateSelect(Cmp, Arg, Neg, "abs"); 2222 } else if (IsNVVM && (Name == "max.i" || Name == "max.ll" || 2223 Name == "max.ui" || Name == "max.ull")) { 2224 Value *Arg0 = CI->getArgOperand(0); 2225 Value *Arg1 = CI->getArgOperand(1); 2226 Value *Cmp = Name.endswith(".ui") || Name.endswith(".ull") 2227 ? Builder.CreateICmpUGE(Arg0, Arg1, "max.cond") 2228 : Builder.CreateICmpSGE(Arg0, Arg1, "max.cond"); 2229 Rep = Builder.CreateSelect(Cmp, Arg0, Arg1, "max"); 2230 } else if (IsNVVM && (Name == "min.i" || Name == "min.ll" || 2231 Name == "min.ui" || Name == "min.ull")) { 2232 Value *Arg0 = CI->getArgOperand(0); 2233 Value *Arg1 = CI->getArgOperand(1); 2234 Value *Cmp = Name.endswith(".ui") || Name.endswith(".ull") 2235 ? Builder.CreateICmpULE(Arg0, Arg1, "min.cond") 2236 : Builder.CreateICmpSLE(Arg0, Arg1, "min.cond"); 2237 Rep = Builder.CreateSelect(Cmp, Arg0, Arg1, "min"); 2238 } else if (IsNVVM && Name == "clz.ll") { 2239 // llvm.nvvm.clz.ll returns an i32, but llvm.ctlz.i64 and returns an i64. 2240 Value *Arg = CI->getArgOperand(0); 2241 Value *Ctlz = Builder.CreateCall( 2242 Intrinsic::getDeclaration(F->getParent(), Intrinsic::ctlz, 2243 {Arg->getType()}), 2244 {Arg, Builder.getFalse()}, "ctlz"); 2245 Rep = Builder.CreateTrunc(Ctlz, Builder.getInt32Ty(), "ctlz.trunc"); 2246 } else if (IsNVVM && Name == "popc.ll") { 2247 // llvm.nvvm.popc.ll returns an i32, but llvm.ctpop.i64 and returns an 2248 // i64. 2249 Value *Arg = CI->getArgOperand(0); 2250 Value *Popc = Builder.CreateCall( 2251 Intrinsic::getDeclaration(F->getParent(), Intrinsic::ctpop, 2252 {Arg->getType()}), 2253 Arg, "ctpop"); 2254 Rep = Builder.CreateTrunc(Popc, Builder.getInt32Ty(), "ctpop.trunc"); 2255 } else if (IsNVVM && Name == "h2f") { 2256 Rep = Builder.CreateCall(Intrinsic::getDeclaration( 2257 F->getParent(), Intrinsic::convert_from_fp16, 2258 {Builder.getFloatTy()}), 2259 CI->getArgOperand(0), "h2f"); 2260 } else { 2261 llvm_unreachable("Unknown function for CallInst upgrade."); 2262 } 2263 2264 if (Rep) 2265 CI->replaceAllUsesWith(Rep); 2266 CI->eraseFromParent(); 2267 return; 2268 } 2269 2270 const auto &DefaultCase = [&NewFn, &CI]() -> void { 2271 // Handle generic mangling change, but nothing else 2272 assert( 2273 (CI->getCalledFunction()->getName() != NewFn->getName()) && 2274 "Unknown function for CallInst upgrade and isn't just a name change"); 2275 CI->setCalledFunction(NewFn); 2276 }; 2277 CallInst *NewCall = nullptr; 2278 switch (NewFn->getIntrinsicID()) { 2279 default: { 2280 DefaultCase(); 2281 return; 2282 } 2283 2284 case Intrinsic::arm_neon_vld1: 2285 case Intrinsic::arm_neon_vld2: 2286 case Intrinsic::arm_neon_vld3: 2287 case Intrinsic::arm_neon_vld4: 2288 case Intrinsic::arm_neon_vld2lane: 2289 case Intrinsic::arm_neon_vld3lane: 2290 case Intrinsic::arm_neon_vld4lane: 2291 case Intrinsic::arm_neon_vst1: 2292 case Intrinsic::arm_neon_vst2: 2293 case Intrinsic::arm_neon_vst3: 2294 case Intrinsic::arm_neon_vst4: 2295 case Intrinsic::arm_neon_vst2lane: 2296 case Intrinsic::arm_neon_vst3lane: 2297 case Intrinsic::arm_neon_vst4lane: { 2298 SmallVector<Value *, 4> Args(CI->arg_operands().begin(), 2299 CI->arg_operands().end()); 2300 NewCall = Builder.CreateCall(NewFn, Args); 2301 break; 2302 } 2303 2304 case Intrinsic::bitreverse: 2305 NewCall = Builder.CreateCall(NewFn, {CI->getArgOperand(0)}); 2306 break; 2307 2308 case Intrinsic::ctlz: 2309 case Intrinsic::cttz: 2310 assert(CI->getNumArgOperands() == 1 && 2311 "Mismatch between function args and call args"); 2312 NewCall = 2313 Builder.CreateCall(NewFn, {CI->getArgOperand(0), Builder.getFalse()}); 2314 break; 2315 2316 case Intrinsic::objectsize: { 2317 Value *NullIsUnknownSize = CI->getNumArgOperands() == 2 2318 ? Builder.getFalse() 2319 : CI->getArgOperand(2); 2320 NewCall = Builder.CreateCall( 2321 NewFn, {CI->getArgOperand(0), CI->getArgOperand(1), NullIsUnknownSize}); 2322 break; 2323 } 2324 2325 case Intrinsic::ctpop: 2326 NewCall = Builder.CreateCall(NewFn, {CI->getArgOperand(0)}); 2327 break; 2328 2329 case Intrinsic::convert_from_fp16: 2330 NewCall = Builder.CreateCall(NewFn, {CI->getArgOperand(0)}); 2331 break; 2332 2333 case Intrinsic::dbg_value: 2334 // Upgrade from the old version that had an extra offset argument. 2335 assert(CI->getNumArgOperands() == 4); 2336 // Drop nonzero offsets instead of attempting to upgrade them. 2337 if (auto *Offset = dyn_cast_or_null<Constant>(CI->getArgOperand(1))) 2338 if (Offset->isZeroValue()) { 2339 NewCall = Builder.CreateCall( 2340 NewFn, 2341 {CI->getArgOperand(0), CI->getArgOperand(2), CI->getArgOperand(3)}); 2342 break; 2343 } 2344 CI->eraseFromParent(); 2345 return; 2346 2347 case Intrinsic::x86_xop_vfrcz_ss: 2348 case Intrinsic::x86_xop_vfrcz_sd: 2349 NewCall = Builder.CreateCall(NewFn, {CI->getArgOperand(1)}); 2350 break; 2351 2352 case Intrinsic::x86_xop_vpermil2pd: 2353 case Intrinsic::x86_xop_vpermil2ps: 2354 case Intrinsic::x86_xop_vpermil2pd_256: 2355 case Intrinsic::x86_xop_vpermil2ps_256: { 2356 SmallVector<Value *, 4> Args(CI->arg_operands().begin(), 2357 CI->arg_operands().end()); 2358 VectorType *FltIdxTy = cast<VectorType>(Args[2]->getType()); 2359 VectorType *IntIdxTy = VectorType::getInteger(FltIdxTy); 2360 Args[2] = Builder.CreateBitCast(Args[2], IntIdxTy); 2361 NewCall = Builder.CreateCall(NewFn, Args); 2362 break; 2363 } 2364 2365 case Intrinsic::x86_sse41_ptestc: 2366 case Intrinsic::x86_sse41_ptestz: 2367 case Intrinsic::x86_sse41_ptestnzc: { 2368 // The arguments for these intrinsics used to be v4f32, and changed 2369 // to v2i64. This is purely a nop, since those are bitwise intrinsics. 2370 // So, the only thing required is a bitcast for both arguments. 2371 // First, check the arguments have the old type. 2372 Value *Arg0 = CI->getArgOperand(0); 2373 if (Arg0->getType() != VectorType::get(Type::getFloatTy(C), 4)) 2374 return; 2375 2376 // Old intrinsic, add bitcasts 2377 Value *Arg1 = CI->getArgOperand(1); 2378 2379 Type *NewVecTy = VectorType::get(Type::getInt64Ty(C), 2); 2380 2381 Value *BC0 = Builder.CreateBitCast(Arg0, NewVecTy, "cast"); 2382 Value *BC1 = Builder.CreateBitCast(Arg1, NewVecTy, "cast"); 2383 2384 NewCall = Builder.CreateCall(NewFn, {BC0, BC1}); 2385 break; 2386 } 2387 2388 case Intrinsic::x86_sse41_insertps: 2389 case Intrinsic::x86_sse41_dppd: 2390 case Intrinsic::x86_sse41_dpps: 2391 case Intrinsic::x86_sse41_mpsadbw: 2392 case Intrinsic::x86_avx_dp_ps_256: 2393 case Intrinsic::x86_avx2_mpsadbw: { 2394 // Need to truncate the last argument from i32 to i8 -- this argument models 2395 // an inherently 8-bit immediate operand to these x86 instructions. 2396 SmallVector<Value *, 4> Args(CI->arg_operands().begin(), 2397 CI->arg_operands().end()); 2398 2399 // Replace the last argument with a trunc. 2400 Args.back() = Builder.CreateTrunc(Args.back(), Type::getInt8Ty(C), "trunc"); 2401 NewCall = Builder.CreateCall(NewFn, Args); 2402 break; 2403 } 2404 2405 case Intrinsic::thread_pointer: { 2406 NewCall = Builder.CreateCall(NewFn, {}); 2407 break; 2408 } 2409 2410 case Intrinsic::invariant_start: 2411 case Intrinsic::invariant_end: 2412 case Intrinsic::masked_load: 2413 case Intrinsic::masked_store: 2414 case Intrinsic::masked_gather: 2415 case Intrinsic::masked_scatter: { 2416 SmallVector<Value *, 4> Args(CI->arg_operands().begin(), 2417 CI->arg_operands().end()); 2418 NewCall = Builder.CreateCall(NewFn, Args); 2419 break; 2420 } 2421 2422 case Intrinsic::memcpy: 2423 case Intrinsic::memmove: 2424 case Intrinsic::memset: { 2425 // We have to make sure that the call signature is what we're expecting. 2426 // We only want to change the old signatures by removing the alignment arg: 2427 // @llvm.mem[cpy|move]...(i8*, i8*, i[32|i64], i32, i1) 2428 // -> @llvm.mem[cpy|move]...(i8*, i8*, i[32|i64], i1) 2429 // @llvm.memset...(i8*, i8, i[32|64], i32, i1) 2430 // -> @llvm.memset...(i8*, i8, i[32|64], i1) 2431 // Note: i8*'s in the above can be any pointer type 2432 if (CI->getNumArgOperands() != 5) { 2433 DefaultCase(); 2434 return; 2435 } 2436 // Remove alignment argument (3), and add alignment attributes to the 2437 // dest/src pointers. 2438 Value *Args[4] = {CI->getArgOperand(0), CI->getArgOperand(1), 2439 CI->getArgOperand(2), CI->getArgOperand(4)}; 2440 NewCall = Builder.CreateCall(NewFn, Args); 2441 auto *MemCI = cast<MemIntrinsic>(NewCall); 2442 // All mem intrinsics support dest alignment. 2443 const ConstantInt *Align = cast<ConstantInt>(CI->getArgOperand(3)); 2444 MemCI->setDestAlignment(Align->getZExtValue()); 2445 // Memcpy/Memmove also support source alignment. 2446 if (auto *MTI = dyn_cast<MemTransferInst>(MemCI)) 2447 MTI->setSourceAlignment(Align->getZExtValue()); 2448 break; 2449 } 2450 } 2451 assert(NewCall && "Should have either set this variable or returned through " 2452 "the default case"); 2453 std::string Name = CI->getName(); 2454 if (!Name.empty()) { 2455 CI->setName(Name + ".old"); 2456 NewCall->setName(Name); 2457 } 2458 CI->replaceAllUsesWith(NewCall); 2459 CI->eraseFromParent(); 2460 } 2461 2462 void llvm::UpgradeCallsToIntrinsic(Function *F) { 2463 assert(F && "Illegal attempt to upgrade a non-existent intrinsic."); 2464 2465 // Check if this function should be upgraded and get the replacement function 2466 // if there is one. 2467 Function *NewFn; 2468 if (UpgradeIntrinsicFunction(F, NewFn)) { 2469 // Replace all users of the old function with the new function or new 2470 // instructions. This is not a range loop because the call is deleted. 2471 for (auto UI = F->user_begin(), UE = F->user_end(); UI != UE; ) 2472 if (CallInst *CI = dyn_cast<CallInst>(*UI++)) 2473 UpgradeIntrinsicCall(CI, NewFn); 2474 2475 // Remove old function, no longer used, from the module. 2476 F->eraseFromParent(); 2477 } 2478 } 2479 2480 MDNode *llvm::UpgradeTBAANode(MDNode &MD) { 2481 // Check if the tag uses struct-path aware TBAA format. 2482 if (isa<MDNode>(MD.getOperand(0)) && MD.getNumOperands() >= 3) 2483 return &MD; 2484 2485 auto &Context = MD.getContext(); 2486 if (MD.getNumOperands() == 3) { 2487 Metadata *Elts[] = {MD.getOperand(0), MD.getOperand(1)}; 2488 MDNode *ScalarType = MDNode::get(Context, Elts); 2489 // Create a MDNode <ScalarType, ScalarType, offset 0, const> 2490 Metadata *Elts2[] = {ScalarType, ScalarType, 2491 ConstantAsMetadata::get( 2492 Constant::getNullValue(Type::getInt64Ty(Context))), 2493 MD.getOperand(2)}; 2494 return MDNode::get(Context, Elts2); 2495 } 2496 // Create a MDNode <MD, MD, offset 0> 2497 Metadata *Elts[] = {&MD, &MD, ConstantAsMetadata::get(Constant::getNullValue( 2498 Type::getInt64Ty(Context)))}; 2499 return MDNode::get(Context, Elts); 2500 } 2501 2502 Instruction *llvm::UpgradeBitCastInst(unsigned Opc, Value *V, Type *DestTy, 2503 Instruction *&Temp) { 2504 if (Opc != Instruction::BitCast) 2505 return nullptr; 2506 2507 Temp = nullptr; 2508 Type *SrcTy = V->getType(); 2509 if (SrcTy->isPtrOrPtrVectorTy() && DestTy->isPtrOrPtrVectorTy() && 2510 SrcTy->getPointerAddressSpace() != DestTy->getPointerAddressSpace()) { 2511 LLVMContext &Context = V->getContext(); 2512 2513 // We have no information about target data layout, so we assume that 2514 // the maximum pointer size is 64bit. 2515 Type *MidTy = Type::getInt64Ty(Context); 2516 Temp = CastInst::Create(Instruction::PtrToInt, V, MidTy); 2517 2518 return CastInst::Create(Instruction::IntToPtr, Temp, DestTy); 2519 } 2520 2521 return nullptr; 2522 } 2523 2524 Value *llvm::UpgradeBitCastExpr(unsigned Opc, Constant *C, Type *DestTy) { 2525 if (Opc != Instruction::BitCast) 2526 return nullptr; 2527 2528 Type *SrcTy = C->getType(); 2529 if (SrcTy->isPtrOrPtrVectorTy() && DestTy->isPtrOrPtrVectorTy() && 2530 SrcTy->getPointerAddressSpace() != DestTy->getPointerAddressSpace()) { 2531 LLVMContext &Context = C->getContext(); 2532 2533 // We have no information about target data layout, so we assume that 2534 // the maximum pointer size is 64bit. 2535 Type *MidTy = Type::getInt64Ty(Context); 2536 2537 return ConstantExpr::getIntToPtr(ConstantExpr::getPtrToInt(C, MidTy), 2538 DestTy); 2539 } 2540 2541 return nullptr; 2542 } 2543 2544 /// Check the debug info version number, if it is out-dated, drop the debug 2545 /// info. Return true if module is modified. 2546 bool llvm::UpgradeDebugInfo(Module &M) { 2547 unsigned Version = getDebugMetadataVersionFromModule(M); 2548 if (Version == DEBUG_METADATA_VERSION) { 2549 bool BrokenDebugInfo = false; 2550 if (verifyModule(M, &llvm::errs(), &BrokenDebugInfo)) 2551 report_fatal_error("Broken module found, compilation aborted!"); 2552 if (!BrokenDebugInfo) 2553 // Everything is ok. 2554 return false; 2555 else { 2556 // Diagnose malformed debug info. 2557 DiagnosticInfoIgnoringInvalidDebugMetadata Diag(M); 2558 M.getContext().diagnose(Diag); 2559 } 2560 } 2561 bool Modified = StripDebugInfo(M); 2562 if (Modified && Version != DEBUG_METADATA_VERSION) { 2563 // Diagnose a version mismatch. 2564 DiagnosticInfoDebugMetadataVersion DiagVersion(M, Version); 2565 M.getContext().diagnose(DiagVersion); 2566 } 2567 return Modified; 2568 } 2569 2570 bool llvm::UpgradeModuleFlags(Module &M) { 2571 NamedMDNode *ModFlags = M.getModuleFlagsMetadata(); 2572 if (!ModFlags) 2573 return false; 2574 2575 bool HasObjCFlag = false, HasClassProperties = false, Changed = false; 2576 for (unsigned I = 0, E = ModFlags->getNumOperands(); I != E; ++I) { 2577 MDNode *Op = ModFlags->getOperand(I); 2578 if (Op->getNumOperands() != 3) 2579 continue; 2580 MDString *ID = dyn_cast_or_null<MDString>(Op->getOperand(1)); 2581 if (!ID) 2582 continue; 2583 if (ID->getString() == "Objective-C Image Info Version") 2584 HasObjCFlag = true; 2585 if (ID->getString() == "Objective-C Class Properties") 2586 HasClassProperties = true; 2587 // Upgrade PIC/PIE Module Flags. The module flag behavior for these two 2588 // field was Error and now they are Max. 2589 if (ID->getString() == "PIC Level" || ID->getString() == "PIE Level") { 2590 if (auto *Behavior = 2591 mdconst::dyn_extract_or_null<ConstantInt>(Op->getOperand(0))) { 2592 if (Behavior->getLimitedValue() == Module::Error) { 2593 Type *Int32Ty = Type::getInt32Ty(M.getContext()); 2594 Metadata *Ops[3] = { 2595 ConstantAsMetadata::get(ConstantInt::get(Int32Ty, Module::Max)), 2596 MDString::get(M.getContext(), ID->getString()), 2597 Op->getOperand(2)}; 2598 ModFlags->setOperand(I, MDNode::get(M.getContext(), Ops)); 2599 Changed = true; 2600 } 2601 } 2602 } 2603 // Upgrade Objective-C Image Info Section. Removed the whitespce in the 2604 // section name so that llvm-lto will not complain about mismatching 2605 // module flags that is functionally the same. 2606 if (ID->getString() == "Objective-C Image Info Section") { 2607 if (auto *Value = dyn_cast_or_null<MDString>(Op->getOperand(2))) { 2608 SmallVector<StringRef, 4> ValueComp; 2609 Value->getString().split(ValueComp, " "); 2610 if (ValueComp.size() != 1) { 2611 std::string NewValue; 2612 for (auto &S : ValueComp) 2613 NewValue += S.str(); 2614 Metadata *Ops[3] = {Op->getOperand(0), Op->getOperand(1), 2615 MDString::get(M.getContext(), NewValue)}; 2616 ModFlags->setOperand(I, MDNode::get(M.getContext(), Ops)); 2617 Changed = true; 2618 } 2619 } 2620 } 2621 } 2622 2623 // "Objective-C Class Properties" is recently added for Objective-C. We 2624 // upgrade ObjC bitcodes to contain a "Objective-C Class Properties" module 2625 // flag of value 0, so we can correclty downgrade this flag when trying to 2626 // link an ObjC bitcode without this module flag with an ObjC bitcode with 2627 // this module flag. 2628 if (HasObjCFlag && !HasClassProperties) { 2629 M.addModuleFlag(llvm::Module::Override, "Objective-C Class Properties", 2630 (uint32_t)0); 2631 Changed = true; 2632 } 2633 2634 return Changed; 2635 } 2636 2637 void llvm::UpgradeSectionAttributes(Module &M) { 2638 auto TrimSpaces = [](StringRef Section) -> std::string { 2639 SmallVector<StringRef, 5> Components; 2640 Section.split(Components, ','); 2641 2642 SmallString<32> Buffer; 2643 raw_svector_ostream OS(Buffer); 2644 2645 for (auto Component : Components) 2646 OS << ',' << Component.trim(); 2647 2648 return OS.str().substr(1); 2649 }; 2650 2651 for (auto &GV : M.globals()) { 2652 if (!GV.hasSection()) 2653 continue; 2654 2655 StringRef Section = GV.getSection(); 2656 2657 if (!Section.startswith("__DATA, __objc_catlist")) 2658 continue; 2659 2660 // __DATA, __objc_catlist, regular, no_dead_strip 2661 // __DATA,__objc_catlist,regular,no_dead_strip 2662 GV.setSection(TrimSpaces(Section)); 2663 } 2664 } 2665 2666 static bool isOldLoopArgument(Metadata *MD) { 2667 auto *T = dyn_cast_or_null<MDTuple>(MD); 2668 if (!T) 2669 return false; 2670 if (T->getNumOperands() < 1) 2671 return false; 2672 auto *S = dyn_cast_or_null<MDString>(T->getOperand(0)); 2673 if (!S) 2674 return false; 2675 return S->getString().startswith("llvm.vectorizer."); 2676 } 2677 2678 static MDString *upgradeLoopTag(LLVMContext &C, StringRef OldTag) { 2679 StringRef OldPrefix = "llvm.vectorizer."; 2680 assert(OldTag.startswith(OldPrefix) && "Expected old prefix"); 2681 2682 if (OldTag == "llvm.vectorizer.unroll") 2683 return MDString::get(C, "llvm.loop.interleave.count"); 2684 2685 return MDString::get( 2686 C, (Twine("llvm.loop.vectorize.") + OldTag.drop_front(OldPrefix.size())) 2687 .str()); 2688 } 2689 2690 static Metadata *upgradeLoopArgument(Metadata *MD) { 2691 auto *T = dyn_cast_or_null<MDTuple>(MD); 2692 if (!T) 2693 return MD; 2694 if (T->getNumOperands() < 1) 2695 return MD; 2696 auto *OldTag = dyn_cast_or_null<MDString>(T->getOperand(0)); 2697 if (!OldTag) 2698 return MD; 2699 if (!OldTag->getString().startswith("llvm.vectorizer.")) 2700 return MD; 2701 2702 // This has an old tag. Upgrade it. 2703 SmallVector<Metadata *, 8> Ops; 2704 Ops.reserve(T->getNumOperands()); 2705 Ops.push_back(upgradeLoopTag(T->getContext(), OldTag->getString())); 2706 for (unsigned I = 1, E = T->getNumOperands(); I != E; ++I) 2707 Ops.push_back(T->getOperand(I)); 2708 2709 return MDTuple::get(T->getContext(), Ops); 2710 } 2711 2712 MDNode *llvm::upgradeInstructionLoopAttachment(MDNode &N) { 2713 auto *T = dyn_cast<MDTuple>(&N); 2714 if (!T) 2715 return &N; 2716 2717 if (none_of(T->operands(), isOldLoopArgument)) 2718 return &N; 2719 2720 SmallVector<Metadata *, 8> Ops; 2721 Ops.reserve(T->getNumOperands()); 2722 for (Metadata *MD : T->operands()) 2723 Ops.push_back(upgradeLoopArgument(MD)); 2724 2725 return MDTuple::get(T->getContext(), Ops); 2726 } 2727