1 //===-- AutoUpgrade.cpp - Implement auto-upgrade helper functions ---------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements the auto-upgrade helper functions. 11 // This is where deprecated IR intrinsics and other IR features are updated to 12 // current specifications. 13 // 14 //===----------------------------------------------------------------------===// 15 16 #include "llvm/IR/AutoUpgrade.h" 17 #include "llvm/ADT/StringSwitch.h" 18 #include "llvm/IR/CFG.h" 19 #include "llvm/IR/CallSite.h" 20 #include "llvm/IR/Constants.h" 21 #include "llvm/IR/DIBuilder.h" 22 #include "llvm/IR/DebugInfo.h" 23 #include "llvm/IR/DiagnosticInfo.h" 24 #include "llvm/IR/Function.h" 25 #include "llvm/IR/IRBuilder.h" 26 #include "llvm/IR/Instruction.h" 27 #include "llvm/IR/IntrinsicInst.h" 28 #include "llvm/IR/LLVMContext.h" 29 #include "llvm/IR/Module.h" 30 #include "llvm/Support/ErrorHandling.h" 31 #include "llvm/Support/Regex.h" 32 #include <cstring> 33 using namespace llvm; 34 35 static void rename(GlobalValue *GV) { GV->setName(GV->getName() + ".old"); } 36 37 // Upgrade the declarations of the SSE4.1 ptest intrinsics whose arguments have 38 // changed their type from v4f32 to v2i64. 39 static bool UpgradePTESTIntrinsic(Function* F, Intrinsic::ID IID, 40 Function *&NewFn) { 41 // Check whether this is an old version of the function, which received 42 // v4f32 arguments. 43 Type *Arg0Type = F->getFunctionType()->getParamType(0); 44 if (Arg0Type != VectorType::get(Type::getFloatTy(F->getContext()), 4)) 45 return false; 46 47 // Yes, it's old, replace it with new version. 48 rename(F); 49 NewFn = Intrinsic::getDeclaration(F->getParent(), IID); 50 return true; 51 } 52 53 // Upgrade the declarations of intrinsic functions whose 8-bit immediate mask 54 // arguments have changed their type from i32 to i8. 55 static bool UpgradeX86IntrinsicsWith8BitMask(Function *F, Intrinsic::ID IID, 56 Function *&NewFn) { 57 // Check that the last argument is an i32. 58 Type *LastArgType = F->getFunctionType()->getParamType( 59 F->getFunctionType()->getNumParams() - 1); 60 if (!LastArgType->isIntegerTy(32)) 61 return false; 62 63 // Move this function aside and map down. 64 rename(F); 65 NewFn = Intrinsic::getDeclaration(F->getParent(), IID); 66 return true; 67 } 68 69 static bool ShouldUpgradeX86Intrinsic(Function *F, StringRef Name) { 70 // All of the intrinsics matches below should be marked with which llvm 71 // version started autoupgrading them. At some point in the future we would 72 // like to use this information to remove upgrade code for some older 73 // intrinsics. It is currently undecided how we will determine that future 74 // point. 75 if (Name.startswith("sse2.pcmpeq.") || // Added in 3.1 76 Name.startswith("sse2.pcmpgt.") || // Added in 3.1 77 Name.startswith("avx2.pcmpeq.") || // Added in 3.1 78 Name.startswith("avx2.pcmpgt.") || // Added in 3.1 79 Name.startswith("avx512.mask.pcmpeq.") || // Added in 3.9 80 Name.startswith("avx512.mask.pcmpgt.") || // Added in 3.9 81 Name == "sse.add.ss" || // Added in 4.0 82 Name == "sse2.add.sd" || // Added in 4.0 83 Name == "sse.sub.ss" || // Added in 4.0 84 Name == "sse2.sub.sd" || // Added in 4.0 85 Name == "sse.mul.ss" || // Added in 4.0 86 Name == "sse2.mul.sd" || // Added in 4.0 87 Name == "sse.div.ss" || // Added in 4.0 88 Name == "sse2.div.sd" || // Added in 4.0 89 Name == "sse41.pmaxsb" || // Added in 3.9 90 Name == "sse2.pmaxs.w" || // Added in 3.9 91 Name == "sse41.pmaxsd" || // Added in 3.9 92 Name == "sse2.pmaxu.b" || // Added in 3.9 93 Name == "sse41.pmaxuw" || // Added in 3.9 94 Name == "sse41.pmaxud" || // Added in 3.9 95 Name == "sse41.pminsb" || // Added in 3.9 96 Name == "sse2.pmins.w" || // Added in 3.9 97 Name == "sse41.pminsd" || // Added in 3.9 98 Name == "sse2.pminu.b" || // Added in 3.9 99 Name == "sse41.pminuw" || // Added in 3.9 100 Name == "sse41.pminud" || // Added in 3.9 101 Name.startswith("avx512.mask.pshuf.b.") || // Added in 4.0 102 Name.startswith("avx2.pmax") || // Added in 3.9 103 Name.startswith("avx2.pmin") || // Added in 3.9 104 Name.startswith("avx512.mask.pmax") || // Added in 4.0 105 Name.startswith("avx512.mask.pmin") || // Added in 4.0 106 Name.startswith("avx2.vbroadcast") || // Added in 3.8 107 Name.startswith("avx2.pbroadcast") || // Added in 3.8 108 Name.startswith("avx.vpermil.") || // Added in 3.1 109 Name.startswith("sse2.pshuf") || // Added in 3.9 110 Name.startswith("avx512.pbroadcast") || // Added in 3.9 111 Name.startswith("avx512.mask.broadcast.s") || // Added in 3.9 112 Name.startswith("avx512.mask.movddup") || // Added in 3.9 113 Name.startswith("avx512.mask.movshdup") || // Added in 3.9 114 Name.startswith("avx512.mask.movsldup") || // Added in 3.9 115 Name.startswith("avx512.mask.pshuf.d.") || // Added in 3.9 116 Name.startswith("avx512.mask.pshufl.w.") || // Added in 3.9 117 Name.startswith("avx512.mask.pshufh.w.") || // Added in 3.9 118 Name.startswith("avx512.mask.shuf.p") || // Added in 4.0 119 Name.startswith("avx512.mask.vpermil.p") || // Added in 3.9 120 Name.startswith("avx512.mask.perm.df.") || // Added in 3.9 121 Name.startswith("avx512.mask.perm.di.") || // Added in 3.9 122 Name.startswith("avx512.mask.punpckl") || // Added in 3.9 123 Name.startswith("avx512.mask.punpckh") || // Added in 3.9 124 Name.startswith("avx512.mask.unpckl.") || // Added in 3.9 125 Name.startswith("avx512.mask.unpckh.") || // Added in 3.9 126 Name.startswith("avx512.mask.pand.") || // Added in 3.9 127 Name.startswith("avx512.mask.pandn.") || // Added in 3.9 128 Name.startswith("avx512.mask.por.") || // Added in 3.9 129 Name.startswith("avx512.mask.pxor.") || // Added in 3.9 130 Name.startswith("avx512.mask.and.") || // Added in 3.9 131 Name.startswith("avx512.mask.andn.") || // Added in 3.9 132 Name.startswith("avx512.mask.or.") || // Added in 3.9 133 Name.startswith("avx512.mask.xor.") || // Added in 3.9 134 Name.startswith("avx512.mask.padd.") || // Added in 4.0 135 Name.startswith("avx512.mask.psub.") || // Added in 4.0 136 Name.startswith("avx512.mask.pmull.") || // Added in 4.0 137 Name.startswith("avx512.mask.cvtdq2pd.") || // Added in 4.0 138 Name.startswith("avx512.mask.cvtudq2pd.") || // Added in 4.0 139 Name.startswith("avx512.mask.pmul.dq.") || // Added in 4.0 140 Name.startswith("avx512.mask.pmulu.dq.") || // Added in 4.0 141 Name.startswith("avx512.mask.packsswb.") || // Added in 5.0 142 Name.startswith("avx512.mask.packssdw.") || // Added in 5.0 143 Name.startswith("avx512.mask.packuswb.") || // Added in 5.0 144 Name.startswith("avx512.mask.packusdw.") || // Added in 5.0 145 Name.startswith("avx512.mask.cmp.b") || // Added in 5.0 146 Name.startswith("avx512.mask.cmp.d") || // Added in 5.0 147 Name.startswith("avx512.mask.cmp.q") || // Added in 5.0 148 Name.startswith("avx512.mask.cmp.w") || // Added in 5.0 149 Name.startswith("avx512.mask.ucmp.") || // Added in 5.0 150 Name == "avx512.mask.add.pd.128" || // Added in 4.0 151 Name == "avx512.mask.add.pd.256" || // Added in 4.0 152 Name == "avx512.mask.add.ps.128" || // Added in 4.0 153 Name == "avx512.mask.add.ps.256" || // Added in 4.0 154 Name == "avx512.mask.div.pd.128" || // Added in 4.0 155 Name == "avx512.mask.div.pd.256" || // Added in 4.0 156 Name == "avx512.mask.div.ps.128" || // Added in 4.0 157 Name == "avx512.mask.div.ps.256" || // Added in 4.0 158 Name == "avx512.mask.mul.pd.128" || // Added in 4.0 159 Name == "avx512.mask.mul.pd.256" || // Added in 4.0 160 Name == "avx512.mask.mul.ps.128" || // Added in 4.0 161 Name == "avx512.mask.mul.ps.256" || // Added in 4.0 162 Name == "avx512.mask.sub.pd.128" || // Added in 4.0 163 Name == "avx512.mask.sub.pd.256" || // Added in 4.0 164 Name == "avx512.mask.sub.ps.128" || // Added in 4.0 165 Name == "avx512.mask.sub.ps.256" || // Added in 4.0 166 Name == "avx512.mask.max.pd.128" || // Added in 5.0 167 Name == "avx512.mask.max.pd.256" || // Added in 5.0 168 Name == "avx512.mask.max.ps.128" || // Added in 5.0 169 Name == "avx512.mask.max.ps.256" || // Added in 5.0 170 Name == "avx512.mask.min.pd.128" || // Added in 5.0 171 Name == "avx512.mask.min.pd.256" || // Added in 5.0 172 Name == "avx512.mask.min.ps.128" || // Added in 5.0 173 Name == "avx512.mask.min.ps.256" || // Added in 5.0 174 Name.startswith("avx512.mask.vpermilvar.") || // Added in 4.0 175 Name.startswith("avx512.mask.psll.d") || // Added in 4.0 176 Name.startswith("avx512.mask.psll.q") || // Added in 4.0 177 Name.startswith("avx512.mask.psll.w") || // Added in 4.0 178 Name.startswith("avx512.mask.psra.d") || // Added in 4.0 179 Name.startswith("avx512.mask.psra.q") || // Added in 4.0 180 Name.startswith("avx512.mask.psra.w") || // Added in 4.0 181 Name.startswith("avx512.mask.psrl.d") || // Added in 4.0 182 Name.startswith("avx512.mask.psrl.q") || // Added in 4.0 183 Name.startswith("avx512.mask.psrl.w") || // Added in 4.0 184 Name.startswith("avx512.mask.pslli") || // Added in 4.0 185 Name.startswith("avx512.mask.psrai") || // Added in 4.0 186 Name.startswith("avx512.mask.psrli") || // Added in 4.0 187 Name.startswith("avx512.mask.psllv") || // Added in 4.0 188 Name.startswith("avx512.mask.psrav") || // Added in 4.0 189 Name.startswith("avx512.mask.psrlv") || // Added in 4.0 190 Name.startswith("sse41.pmovsx") || // Added in 3.8 191 Name.startswith("sse41.pmovzx") || // Added in 3.9 192 Name.startswith("avx2.pmovsx") || // Added in 3.9 193 Name.startswith("avx2.pmovzx") || // Added in 3.9 194 Name.startswith("avx512.mask.pmovsx") || // Added in 4.0 195 Name.startswith("avx512.mask.pmovzx") || // Added in 4.0 196 Name.startswith("avx512.mask.lzcnt.") || // Added in 5.0 197 Name == "sse2.cvtdq2pd" || // Added in 3.9 198 Name == "sse2.cvtps2pd" || // Added in 3.9 199 Name == "avx.cvtdq2.pd.256" || // Added in 3.9 200 Name == "avx.cvt.ps2.pd.256" || // Added in 3.9 201 Name.startswith("avx.vinsertf128.") || // Added in 3.7 202 Name == "avx2.vinserti128" || // Added in 3.7 203 Name.startswith("avx512.mask.insert") || // Added in 4.0 204 Name.startswith("avx.vextractf128.") || // Added in 3.7 205 Name == "avx2.vextracti128" || // Added in 3.7 206 Name.startswith("avx512.mask.vextract") || // Added in 4.0 207 Name.startswith("sse4a.movnt.") || // Added in 3.9 208 Name.startswith("avx.movnt.") || // Added in 3.2 209 Name.startswith("avx512.storent.") || // Added in 3.9 210 Name == "sse41.movntdqa" || // Added in 5.0 211 Name == "avx2.movntdqa" || // Added in 5.0 212 Name == "avx512.movntdqa" || // Added in 5.0 213 Name == "sse2.storel.dq" || // Added in 3.9 214 Name.startswith("sse.storeu.") || // Added in 3.9 215 Name.startswith("sse2.storeu.") || // Added in 3.9 216 Name.startswith("avx.storeu.") || // Added in 3.9 217 Name.startswith("avx512.mask.storeu.") || // Added in 3.9 218 Name.startswith("avx512.mask.store.p") || // Added in 3.9 219 Name.startswith("avx512.mask.store.b.") || // Added in 3.9 220 Name.startswith("avx512.mask.store.w.") || // Added in 3.9 221 Name.startswith("avx512.mask.store.d.") || // Added in 3.9 222 Name.startswith("avx512.mask.store.q.") || // Added in 3.9 223 Name.startswith("avx512.mask.loadu.") || // Added in 3.9 224 Name.startswith("avx512.mask.load.") || // Added in 3.9 225 Name == "sse42.crc32.64.8" || // Added in 3.4 226 Name.startswith("avx.vbroadcast.s") || // Added in 3.5 227 Name.startswith("avx512.mask.palignr.") || // Added in 3.9 228 Name.startswith("avx512.mask.valign.") || // Added in 4.0 229 Name.startswith("sse2.psll.dq") || // Added in 3.7 230 Name.startswith("sse2.psrl.dq") || // Added in 3.7 231 Name.startswith("avx2.psll.dq") || // Added in 3.7 232 Name.startswith("avx2.psrl.dq") || // Added in 3.7 233 Name.startswith("avx512.psll.dq") || // Added in 3.9 234 Name.startswith("avx512.psrl.dq") || // Added in 3.9 235 Name == "sse41.pblendw" || // Added in 3.7 236 Name.startswith("sse41.blendp") || // Added in 3.7 237 Name.startswith("avx.blend.p") || // Added in 3.7 238 Name == "avx2.pblendw" || // Added in 3.7 239 Name.startswith("avx2.pblendd.") || // Added in 3.7 240 Name.startswith("avx.vbroadcastf128") || // Added in 4.0 241 Name == "avx2.vbroadcasti128" || // Added in 3.7 242 Name == "xop.vpcmov" || // Added in 3.8 243 Name == "xop.vpcmov.256" || // Added in 5.0 244 Name.startswith("avx512.mask.move.s") || // Added in 4.0 245 Name.startswith("avx512.cvtmask2") || // Added in 5.0 246 (Name.startswith("xop.vpcom") && // Added in 3.2 247 F->arg_size() == 2)) 248 return true; 249 250 return false; 251 } 252 253 static bool UpgradeX86IntrinsicFunction(Function *F, StringRef Name, 254 Function *&NewFn) { 255 // Only handle intrinsics that start with "x86.". 256 if (!Name.startswith("x86.")) 257 return false; 258 // Remove "x86." prefix. 259 Name = Name.substr(4); 260 261 if (ShouldUpgradeX86Intrinsic(F, Name)) { 262 NewFn = nullptr; 263 return true; 264 } 265 266 // SSE4.1 ptest functions may have an old signature. 267 if (Name.startswith("sse41.ptest")) { // Added in 3.2 268 if (Name.substr(11) == "c") 269 return UpgradePTESTIntrinsic(F, Intrinsic::x86_sse41_ptestc, NewFn); 270 if (Name.substr(11) == "z") 271 return UpgradePTESTIntrinsic(F, Intrinsic::x86_sse41_ptestz, NewFn); 272 if (Name.substr(11) == "nzc") 273 return UpgradePTESTIntrinsic(F, Intrinsic::x86_sse41_ptestnzc, NewFn); 274 } 275 // Several blend and other instructions with masks used the wrong number of 276 // bits. 277 if (Name == "sse41.insertps") // Added in 3.6 278 return UpgradeX86IntrinsicsWith8BitMask(F, Intrinsic::x86_sse41_insertps, 279 NewFn); 280 if (Name == "sse41.dppd") // Added in 3.6 281 return UpgradeX86IntrinsicsWith8BitMask(F, Intrinsic::x86_sse41_dppd, 282 NewFn); 283 if (Name == "sse41.dpps") // Added in 3.6 284 return UpgradeX86IntrinsicsWith8BitMask(F, Intrinsic::x86_sse41_dpps, 285 NewFn); 286 if (Name == "sse41.mpsadbw") // Added in 3.6 287 return UpgradeX86IntrinsicsWith8BitMask(F, Intrinsic::x86_sse41_mpsadbw, 288 NewFn); 289 if (Name == "avx.dp.ps.256") // Added in 3.6 290 return UpgradeX86IntrinsicsWith8BitMask(F, Intrinsic::x86_avx_dp_ps_256, 291 NewFn); 292 if (Name == "avx2.mpsadbw") // Added in 3.6 293 return UpgradeX86IntrinsicsWith8BitMask(F, Intrinsic::x86_avx2_mpsadbw, 294 NewFn); 295 296 // frcz.ss/sd may need to have an argument dropped. Added in 3.2 297 if (Name.startswith("xop.vfrcz.ss") && F->arg_size() == 2) { 298 rename(F); 299 NewFn = Intrinsic::getDeclaration(F->getParent(), 300 Intrinsic::x86_xop_vfrcz_ss); 301 return true; 302 } 303 if (Name.startswith("xop.vfrcz.sd") && F->arg_size() == 2) { 304 rename(F); 305 NewFn = Intrinsic::getDeclaration(F->getParent(), 306 Intrinsic::x86_xop_vfrcz_sd); 307 return true; 308 } 309 // Upgrade any XOP PERMIL2 index operand still using a float/double vector. 310 if (Name.startswith("xop.vpermil2")) { // Added in 3.9 311 auto Idx = F->getFunctionType()->getParamType(2); 312 if (Idx->isFPOrFPVectorTy()) { 313 rename(F); 314 unsigned IdxSize = Idx->getPrimitiveSizeInBits(); 315 unsigned EltSize = Idx->getScalarSizeInBits(); 316 Intrinsic::ID Permil2ID; 317 if (EltSize == 64 && IdxSize == 128) 318 Permil2ID = Intrinsic::x86_xop_vpermil2pd; 319 else if (EltSize == 32 && IdxSize == 128) 320 Permil2ID = Intrinsic::x86_xop_vpermil2ps; 321 else if (EltSize == 64 && IdxSize == 256) 322 Permil2ID = Intrinsic::x86_xop_vpermil2pd_256; 323 else 324 Permil2ID = Intrinsic::x86_xop_vpermil2ps_256; 325 NewFn = Intrinsic::getDeclaration(F->getParent(), Permil2ID); 326 return true; 327 } 328 } 329 330 return false; 331 } 332 333 static bool UpgradeIntrinsicFunction1(Function *F, Function *&NewFn) { 334 assert(F && "Illegal to upgrade a non-existent Function."); 335 336 // Quickly eliminate it, if it's not a candidate. 337 StringRef Name = F->getName(); 338 if (Name.size() <= 8 || !Name.startswith("llvm.")) 339 return false; 340 Name = Name.substr(5); // Strip off "llvm." 341 342 switch (Name[0]) { 343 default: break; 344 case 'a': { 345 if (Name.startswith("arm.rbit") || Name.startswith("aarch64.rbit")) { 346 NewFn = Intrinsic::getDeclaration(F->getParent(), Intrinsic::bitreverse, 347 F->arg_begin()->getType()); 348 return true; 349 } 350 if (Name.startswith("arm.neon.vclz")) { 351 Type* args[2] = { 352 F->arg_begin()->getType(), 353 Type::getInt1Ty(F->getContext()) 354 }; 355 // Can't use Intrinsic::getDeclaration here as it adds a ".i1" to 356 // the end of the name. Change name from llvm.arm.neon.vclz.* to 357 // llvm.ctlz.* 358 FunctionType* fType = FunctionType::get(F->getReturnType(), args, false); 359 NewFn = Function::Create(fType, F->getLinkage(), 360 "llvm.ctlz." + Name.substr(14), F->getParent()); 361 return true; 362 } 363 if (Name.startswith("arm.neon.vcnt")) { 364 NewFn = Intrinsic::getDeclaration(F->getParent(), Intrinsic::ctpop, 365 F->arg_begin()->getType()); 366 return true; 367 } 368 Regex vldRegex("^arm\\.neon\\.vld([1234]|[234]lane)\\.v[a-z0-9]*$"); 369 if (vldRegex.match(Name)) { 370 auto fArgs = F->getFunctionType()->params(); 371 SmallVector<Type *, 4> Tys(fArgs.begin(), fArgs.end()); 372 // Can't use Intrinsic::getDeclaration here as the return types might 373 // then only be structurally equal. 374 FunctionType* fType = FunctionType::get(F->getReturnType(), Tys, false); 375 NewFn = Function::Create(fType, F->getLinkage(), 376 "llvm." + Name + ".p0i8", F->getParent()); 377 return true; 378 } 379 Regex vstRegex("^arm\\.neon\\.vst([1234]|[234]lane)\\.v[a-z0-9]*$"); 380 if (vstRegex.match(Name)) { 381 static const Intrinsic::ID StoreInts[] = {Intrinsic::arm_neon_vst1, 382 Intrinsic::arm_neon_vst2, 383 Intrinsic::arm_neon_vst3, 384 Intrinsic::arm_neon_vst4}; 385 386 static const Intrinsic::ID StoreLaneInts[] = { 387 Intrinsic::arm_neon_vst2lane, Intrinsic::arm_neon_vst3lane, 388 Intrinsic::arm_neon_vst4lane 389 }; 390 391 auto fArgs = F->getFunctionType()->params(); 392 Type *Tys[] = {fArgs[0], fArgs[1]}; 393 if (Name.find("lane") == StringRef::npos) 394 NewFn = Intrinsic::getDeclaration(F->getParent(), 395 StoreInts[fArgs.size() - 3], Tys); 396 else 397 NewFn = Intrinsic::getDeclaration(F->getParent(), 398 StoreLaneInts[fArgs.size() - 5], Tys); 399 return true; 400 } 401 if (Name == "aarch64.thread.pointer" || Name == "arm.thread.pointer") { 402 NewFn = Intrinsic::getDeclaration(F->getParent(), Intrinsic::thread_pointer); 403 return true; 404 } 405 break; 406 } 407 408 case 'c': { 409 if (Name.startswith("ctlz.") && F->arg_size() == 1) { 410 rename(F); 411 NewFn = Intrinsic::getDeclaration(F->getParent(), Intrinsic::ctlz, 412 F->arg_begin()->getType()); 413 return true; 414 } 415 if (Name.startswith("cttz.") && F->arg_size() == 1) { 416 rename(F); 417 NewFn = Intrinsic::getDeclaration(F->getParent(), Intrinsic::cttz, 418 F->arg_begin()->getType()); 419 return true; 420 } 421 break; 422 } 423 case 'd': { 424 if (Name == "dbg.value" && F->arg_size() == 4) { 425 rename(F); 426 NewFn = Intrinsic::getDeclaration(F->getParent(), Intrinsic::dbg_value); 427 return true; 428 } 429 break; 430 } 431 case 'i': 432 case 'l': { 433 bool IsLifetimeStart = Name.startswith("lifetime.start"); 434 if (IsLifetimeStart || Name.startswith("invariant.start")) { 435 Intrinsic::ID ID = IsLifetimeStart ? 436 Intrinsic::lifetime_start : Intrinsic::invariant_start; 437 auto Args = F->getFunctionType()->params(); 438 Type* ObjectPtr[1] = {Args[1]}; 439 if (F->getName() != Intrinsic::getName(ID, ObjectPtr)) { 440 rename(F); 441 NewFn = Intrinsic::getDeclaration(F->getParent(), ID, ObjectPtr); 442 return true; 443 } 444 } 445 446 bool IsLifetimeEnd = Name.startswith("lifetime.end"); 447 if (IsLifetimeEnd || Name.startswith("invariant.end")) { 448 Intrinsic::ID ID = IsLifetimeEnd ? 449 Intrinsic::lifetime_end : Intrinsic::invariant_end; 450 451 auto Args = F->getFunctionType()->params(); 452 Type* ObjectPtr[1] = {Args[IsLifetimeEnd ? 1 : 2]}; 453 if (F->getName() != Intrinsic::getName(ID, ObjectPtr)) { 454 rename(F); 455 NewFn = Intrinsic::getDeclaration(F->getParent(), ID, ObjectPtr); 456 return true; 457 } 458 } 459 break; 460 } 461 case 'm': { 462 if (Name.startswith("masked.load.")) { 463 Type *Tys[] = { F->getReturnType(), F->arg_begin()->getType() }; 464 if (F->getName() != Intrinsic::getName(Intrinsic::masked_load, Tys)) { 465 rename(F); 466 NewFn = Intrinsic::getDeclaration(F->getParent(), 467 Intrinsic::masked_load, 468 Tys); 469 return true; 470 } 471 } 472 if (Name.startswith("masked.store.")) { 473 auto Args = F->getFunctionType()->params(); 474 Type *Tys[] = { Args[0], Args[1] }; 475 if (F->getName() != Intrinsic::getName(Intrinsic::masked_store, Tys)) { 476 rename(F); 477 NewFn = Intrinsic::getDeclaration(F->getParent(), 478 Intrinsic::masked_store, 479 Tys); 480 return true; 481 } 482 } 483 // Renaming gather/scatter intrinsics with no address space overloading 484 // to the new overload which includes an address space 485 if (Name.startswith("masked.gather.")) { 486 Type *Tys[] = {F->getReturnType(), F->arg_begin()->getType()}; 487 if (F->getName() != Intrinsic::getName(Intrinsic::masked_gather, Tys)) { 488 rename(F); 489 NewFn = Intrinsic::getDeclaration(F->getParent(), 490 Intrinsic::masked_gather, Tys); 491 return true; 492 } 493 } 494 if (Name.startswith("masked.scatter.")) { 495 auto Args = F->getFunctionType()->params(); 496 Type *Tys[] = {Args[0], Args[1]}; 497 if (F->getName() != Intrinsic::getName(Intrinsic::masked_scatter, Tys)) { 498 rename(F); 499 NewFn = Intrinsic::getDeclaration(F->getParent(), 500 Intrinsic::masked_scatter, Tys); 501 return true; 502 } 503 } 504 break; 505 } 506 case 'n': { 507 if (Name.startswith("nvvm.")) { 508 Name = Name.substr(5); 509 510 // The following nvvm intrinsics correspond exactly to an LLVM intrinsic. 511 Intrinsic::ID IID = StringSwitch<Intrinsic::ID>(Name) 512 .Cases("brev32", "brev64", Intrinsic::bitreverse) 513 .Case("clz.i", Intrinsic::ctlz) 514 .Case("popc.i", Intrinsic::ctpop) 515 .Default(Intrinsic::not_intrinsic); 516 if (IID != Intrinsic::not_intrinsic && F->arg_size() == 1) { 517 NewFn = Intrinsic::getDeclaration(F->getParent(), IID, 518 {F->getReturnType()}); 519 return true; 520 } 521 522 // The following nvvm intrinsics correspond exactly to an LLVM idiom, but 523 // not to an intrinsic alone. We expand them in UpgradeIntrinsicCall. 524 // 525 // TODO: We could add lohi.i2d. 526 bool Expand = StringSwitch<bool>(Name) 527 .Cases("abs.i", "abs.ll", true) 528 .Cases("clz.ll", "popc.ll", "h2f", true) 529 .Cases("max.i", "max.ll", "max.ui", "max.ull", true) 530 .Cases("min.i", "min.ll", "min.ui", "min.ull", true) 531 .Default(false); 532 if (Expand) { 533 NewFn = nullptr; 534 return true; 535 } 536 } 537 break; 538 } 539 case 'o': 540 // We only need to change the name to match the mangling including the 541 // address space. 542 if (Name.startswith("objectsize.")) { 543 Type *Tys[2] = { F->getReturnType(), F->arg_begin()->getType() }; 544 if (F->arg_size() == 2 || 545 F->getName() != Intrinsic::getName(Intrinsic::objectsize, Tys)) { 546 rename(F); 547 NewFn = Intrinsic::getDeclaration(F->getParent(), Intrinsic::objectsize, 548 Tys); 549 return true; 550 } 551 } 552 break; 553 554 case 's': 555 if (Name == "stackprotectorcheck") { 556 NewFn = nullptr; 557 return true; 558 } 559 break; 560 561 case 'x': 562 if (UpgradeX86IntrinsicFunction(F, Name, NewFn)) 563 return true; 564 } 565 // Remangle our intrinsic since we upgrade the mangling 566 auto Result = llvm::Intrinsic::remangleIntrinsicFunction(F); 567 if (Result != None) { 568 NewFn = Result.getValue(); 569 return true; 570 } 571 572 // This may not belong here. This function is effectively being overloaded 573 // to both detect an intrinsic which needs upgrading, and to provide the 574 // upgraded form of the intrinsic. We should perhaps have two separate 575 // functions for this. 576 return false; 577 } 578 579 bool llvm::UpgradeIntrinsicFunction(Function *F, Function *&NewFn) { 580 NewFn = nullptr; 581 bool Upgraded = UpgradeIntrinsicFunction1(F, NewFn); 582 assert(F != NewFn && "Intrinsic function upgraded to the same function"); 583 584 // Upgrade intrinsic attributes. This does not change the function. 585 if (NewFn) 586 F = NewFn; 587 if (Intrinsic::ID id = F->getIntrinsicID()) 588 F->setAttributes(Intrinsic::getAttributes(F->getContext(), id)); 589 return Upgraded; 590 } 591 592 bool llvm::UpgradeGlobalVariable(GlobalVariable *GV) { 593 // Nothing to do yet. 594 return false; 595 } 596 597 // Handles upgrading SSE2/AVX2/AVX512BW PSLLDQ intrinsics by converting them 598 // to byte shuffles. 599 static Value *UpgradeX86PSLLDQIntrinsics(IRBuilder<> &Builder, 600 Value *Op, unsigned Shift) { 601 Type *ResultTy = Op->getType(); 602 unsigned NumElts = ResultTy->getVectorNumElements() * 8; 603 604 // Bitcast from a 64-bit element type to a byte element type. 605 Type *VecTy = VectorType::get(Builder.getInt8Ty(), NumElts); 606 Op = Builder.CreateBitCast(Op, VecTy, "cast"); 607 608 // We'll be shuffling in zeroes. 609 Value *Res = Constant::getNullValue(VecTy); 610 611 // If shift is less than 16, emit a shuffle to move the bytes. Otherwise, 612 // we'll just return the zero vector. 613 if (Shift < 16) { 614 uint32_t Idxs[64]; 615 // 256/512-bit version is split into 2/4 16-byte lanes. 616 for (unsigned l = 0; l != NumElts; l += 16) 617 for (unsigned i = 0; i != 16; ++i) { 618 unsigned Idx = NumElts + i - Shift; 619 if (Idx < NumElts) 620 Idx -= NumElts - 16; // end of lane, switch operand. 621 Idxs[l + i] = Idx + l; 622 } 623 624 Res = Builder.CreateShuffleVector(Res, Op, makeArrayRef(Idxs, NumElts)); 625 } 626 627 // Bitcast back to a 64-bit element type. 628 return Builder.CreateBitCast(Res, ResultTy, "cast"); 629 } 630 631 // Handles upgrading SSE2/AVX2/AVX512BW PSRLDQ intrinsics by converting them 632 // to byte shuffles. 633 static Value *UpgradeX86PSRLDQIntrinsics(IRBuilder<> &Builder, Value *Op, 634 unsigned Shift) { 635 Type *ResultTy = Op->getType(); 636 unsigned NumElts = ResultTy->getVectorNumElements() * 8; 637 638 // Bitcast from a 64-bit element type to a byte element type. 639 Type *VecTy = VectorType::get(Builder.getInt8Ty(), NumElts); 640 Op = Builder.CreateBitCast(Op, VecTy, "cast"); 641 642 // We'll be shuffling in zeroes. 643 Value *Res = Constant::getNullValue(VecTy); 644 645 // If shift is less than 16, emit a shuffle to move the bytes. Otherwise, 646 // we'll just return the zero vector. 647 if (Shift < 16) { 648 uint32_t Idxs[64]; 649 // 256/512-bit version is split into 2/4 16-byte lanes. 650 for (unsigned l = 0; l != NumElts; l += 16) 651 for (unsigned i = 0; i != 16; ++i) { 652 unsigned Idx = i + Shift; 653 if (Idx >= 16) 654 Idx += NumElts - 16; // end of lane, switch operand. 655 Idxs[l + i] = Idx + l; 656 } 657 658 Res = Builder.CreateShuffleVector(Op, Res, makeArrayRef(Idxs, NumElts)); 659 } 660 661 // Bitcast back to a 64-bit element type. 662 return Builder.CreateBitCast(Res, ResultTy, "cast"); 663 } 664 665 static Value *getX86MaskVec(IRBuilder<> &Builder, Value *Mask, 666 unsigned NumElts) { 667 llvm::VectorType *MaskTy = llvm::VectorType::get(Builder.getInt1Ty(), 668 cast<IntegerType>(Mask->getType())->getBitWidth()); 669 Mask = Builder.CreateBitCast(Mask, MaskTy); 670 671 // If we have less than 8 elements, then the starting mask was an i8 and 672 // we need to extract down to the right number of elements. 673 if (NumElts < 8) { 674 uint32_t Indices[4]; 675 for (unsigned i = 0; i != NumElts; ++i) 676 Indices[i] = i; 677 Mask = Builder.CreateShuffleVector(Mask, Mask, 678 makeArrayRef(Indices, NumElts), 679 "extract"); 680 } 681 682 return Mask; 683 } 684 685 static Value *EmitX86Select(IRBuilder<> &Builder, Value *Mask, 686 Value *Op0, Value *Op1) { 687 // If the mask is all ones just emit the align operation. 688 if (const auto *C = dyn_cast<Constant>(Mask)) 689 if (C->isAllOnesValue()) 690 return Op0; 691 692 Mask = getX86MaskVec(Builder, Mask, Op0->getType()->getVectorNumElements()); 693 return Builder.CreateSelect(Mask, Op0, Op1); 694 } 695 696 // Handle autoupgrade for masked PALIGNR and VALIGND/Q intrinsics. 697 // PALIGNR handles large immediates by shifting while VALIGN masks the immediate 698 // so we need to handle both cases. VALIGN also doesn't have 128-bit lanes. 699 static Value *UpgradeX86ALIGNIntrinsics(IRBuilder<> &Builder, Value *Op0, 700 Value *Op1, Value *Shift, 701 Value *Passthru, Value *Mask, 702 bool IsVALIGN) { 703 unsigned ShiftVal = cast<llvm::ConstantInt>(Shift)->getZExtValue(); 704 705 unsigned NumElts = Op0->getType()->getVectorNumElements(); 706 assert((IsVALIGN || NumElts % 16 == 0) && "Illegal NumElts for PALIGNR!"); 707 assert((!IsVALIGN || NumElts <= 16) && "NumElts too large for VALIGN!"); 708 assert(isPowerOf2_32(NumElts) && "NumElts not a power of 2!"); 709 710 // Mask the immediate for VALIGN. 711 if (IsVALIGN) 712 ShiftVal &= (NumElts - 1); 713 714 // If palignr is shifting the pair of vectors more than the size of two 715 // lanes, emit zero. 716 if (ShiftVal >= 32) 717 return llvm::Constant::getNullValue(Op0->getType()); 718 719 // If palignr is shifting the pair of input vectors more than one lane, 720 // but less than two lanes, convert to shifting in zeroes. 721 if (ShiftVal > 16) { 722 ShiftVal -= 16; 723 Op1 = Op0; 724 Op0 = llvm::Constant::getNullValue(Op0->getType()); 725 } 726 727 uint32_t Indices[64]; 728 // 256-bit palignr operates on 128-bit lanes so we need to handle that 729 for (unsigned l = 0; l < NumElts; l += 16) { 730 for (unsigned i = 0; i != 16; ++i) { 731 unsigned Idx = ShiftVal + i; 732 if (!IsVALIGN && Idx >= 16) // Disable wrap for VALIGN. 733 Idx += NumElts - 16; // End of lane, switch operand. 734 Indices[l + i] = Idx + l; 735 } 736 } 737 738 Value *Align = Builder.CreateShuffleVector(Op1, Op0, 739 makeArrayRef(Indices, NumElts), 740 "palignr"); 741 742 return EmitX86Select(Builder, Mask, Align, Passthru); 743 } 744 745 static Value *UpgradeMaskedStore(IRBuilder<> &Builder, 746 Value *Ptr, Value *Data, Value *Mask, 747 bool Aligned) { 748 // Cast the pointer to the right type. 749 Ptr = Builder.CreateBitCast(Ptr, 750 llvm::PointerType::getUnqual(Data->getType())); 751 unsigned Align = 752 Aligned ? cast<VectorType>(Data->getType())->getBitWidth() / 8 : 1; 753 754 // If the mask is all ones just emit a regular store. 755 if (const auto *C = dyn_cast<Constant>(Mask)) 756 if (C->isAllOnesValue()) 757 return Builder.CreateAlignedStore(Data, Ptr, Align); 758 759 // Convert the mask from an integer type to a vector of i1. 760 unsigned NumElts = Data->getType()->getVectorNumElements(); 761 Mask = getX86MaskVec(Builder, Mask, NumElts); 762 return Builder.CreateMaskedStore(Data, Ptr, Align, Mask); 763 } 764 765 static Value *UpgradeMaskedLoad(IRBuilder<> &Builder, 766 Value *Ptr, Value *Passthru, Value *Mask, 767 bool Aligned) { 768 // Cast the pointer to the right type. 769 Ptr = Builder.CreateBitCast(Ptr, 770 llvm::PointerType::getUnqual(Passthru->getType())); 771 unsigned Align = 772 Aligned ? cast<VectorType>(Passthru->getType())->getBitWidth() / 8 : 1; 773 774 // If the mask is all ones just emit a regular store. 775 if (const auto *C = dyn_cast<Constant>(Mask)) 776 if (C->isAllOnesValue()) 777 return Builder.CreateAlignedLoad(Ptr, Align); 778 779 // Convert the mask from an integer type to a vector of i1. 780 unsigned NumElts = Passthru->getType()->getVectorNumElements(); 781 Mask = getX86MaskVec(Builder, Mask, NumElts); 782 return Builder.CreateMaskedLoad(Ptr, Align, Mask, Passthru); 783 } 784 785 static Value *upgradeIntMinMax(IRBuilder<> &Builder, CallInst &CI, 786 ICmpInst::Predicate Pred) { 787 Value *Op0 = CI.getArgOperand(0); 788 Value *Op1 = CI.getArgOperand(1); 789 Value *Cmp = Builder.CreateICmp(Pred, Op0, Op1); 790 Value *Res = Builder.CreateSelect(Cmp, Op0, Op1); 791 792 if (CI.getNumArgOperands() == 4) 793 Res = EmitX86Select(Builder, CI.getArgOperand(3), Res, CI.getArgOperand(2)); 794 795 return Res; 796 } 797 798 static Value *upgradeMaskedCompare(IRBuilder<> &Builder, CallInst &CI, 799 unsigned CC, bool Signed) { 800 Value *Op0 = CI.getArgOperand(0); 801 unsigned NumElts = Op0->getType()->getVectorNumElements(); 802 803 Value *Cmp; 804 if (CC == 3) { 805 Cmp = Constant::getNullValue(llvm::VectorType::get(Builder.getInt1Ty(), NumElts)); 806 } else if (CC == 7) { 807 Cmp = Constant::getAllOnesValue(llvm::VectorType::get(Builder.getInt1Ty(), NumElts)); 808 } else { 809 ICmpInst::Predicate Pred; 810 switch (CC) { 811 default: llvm_unreachable("Unknown condition code"); 812 case 0: Pred = ICmpInst::ICMP_EQ; break; 813 case 1: Pred = Signed ? ICmpInst::ICMP_SLT : ICmpInst::ICMP_ULT; break; 814 case 2: Pred = Signed ? ICmpInst::ICMP_SLE : ICmpInst::ICMP_ULE; break; 815 case 4: Pred = ICmpInst::ICMP_NE; break; 816 case 5: Pred = Signed ? ICmpInst::ICMP_SGE : ICmpInst::ICMP_UGE; break; 817 case 6: Pred = Signed ? ICmpInst::ICMP_SGT : ICmpInst::ICMP_UGT; break; 818 } 819 Cmp = Builder.CreateICmp(Pred, Op0, CI.getArgOperand(1)); 820 } 821 822 Value *Mask = CI.getArgOperand(CI.getNumArgOperands() - 1); 823 const auto *C = dyn_cast<Constant>(Mask); 824 if (!C || !C->isAllOnesValue()) 825 Cmp = Builder.CreateAnd(Cmp, getX86MaskVec(Builder, Mask, NumElts)); 826 827 if (NumElts < 8) { 828 uint32_t Indices[8]; 829 for (unsigned i = 0; i != NumElts; ++i) 830 Indices[i] = i; 831 for (unsigned i = NumElts; i != 8; ++i) 832 Indices[i] = NumElts + i % NumElts; 833 Cmp = Builder.CreateShuffleVector(Cmp, 834 Constant::getNullValue(Cmp->getType()), 835 Indices); 836 } 837 return Builder.CreateBitCast(Cmp, IntegerType::get(CI.getContext(), 838 std::max(NumElts, 8U))); 839 } 840 841 // Replace a masked intrinsic with an older unmasked intrinsic. 842 static Value *UpgradeX86MaskedShift(IRBuilder<> &Builder, CallInst &CI, 843 Intrinsic::ID IID) { 844 Function *F = CI.getCalledFunction(); 845 Function *Intrin = Intrinsic::getDeclaration(F->getParent(), IID); 846 Value *Rep = Builder.CreateCall(Intrin, 847 { CI.getArgOperand(0), CI.getArgOperand(1) }); 848 return EmitX86Select(Builder, CI.getArgOperand(3), Rep, CI.getArgOperand(2)); 849 } 850 851 static Value* upgradeMaskedMove(IRBuilder<> &Builder, CallInst &CI) { 852 Value* A = CI.getArgOperand(0); 853 Value* B = CI.getArgOperand(1); 854 Value* Src = CI.getArgOperand(2); 855 Value* Mask = CI.getArgOperand(3); 856 857 Value* AndNode = Builder.CreateAnd(Mask, APInt(8, 1)); 858 Value* Cmp = Builder.CreateIsNotNull(AndNode); 859 Value* Extract1 = Builder.CreateExtractElement(B, (uint64_t)0); 860 Value* Extract2 = Builder.CreateExtractElement(Src, (uint64_t)0); 861 Value* Select = Builder.CreateSelect(Cmp, Extract1, Extract2); 862 return Builder.CreateInsertElement(A, Select, (uint64_t)0); 863 } 864 865 866 static Value* UpgradeMaskToInt(IRBuilder<> &Builder, CallInst &CI) { 867 Value* Op = CI.getArgOperand(0); 868 Type* ReturnOp = CI.getType(); 869 unsigned NumElts = CI.getType()->getVectorNumElements(); 870 Value *Mask = getX86MaskVec(Builder, Op, NumElts); 871 return Builder.CreateSExt(Mask, ReturnOp, "vpmovm2"); 872 } 873 874 /// Upgrade a call to an old intrinsic. All argument and return casting must be 875 /// provided to seamlessly integrate with existing context. 876 void llvm::UpgradeIntrinsicCall(CallInst *CI, Function *NewFn) { 877 Function *F = CI->getCalledFunction(); 878 LLVMContext &C = CI->getContext(); 879 IRBuilder<> Builder(C); 880 Builder.SetInsertPoint(CI->getParent(), CI->getIterator()); 881 882 assert(F && "Intrinsic call is not direct?"); 883 884 if (!NewFn) { 885 // Get the Function's name. 886 StringRef Name = F->getName(); 887 888 assert(Name.startswith("llvm.") && "Intrinsic doesn't start with 'llvm.'"); 889 Name = Name.substr(5); 890 891 bool IsX86 = Name.startswith("x86."); 892 if (IsX86) 893 Name = Name.substr(4); 894 bool IsNVVM = Name.startswith("nvvm."); 895 if (IsNVVM) 896 Name = Name.substr(5); 897 898 if (IsX86 && Name.startswith("sse4a.movnt.")) { 899 Module *M = F->getParent(); 900 SmallVector<Metadata *, 1> Elts; 901 Elts.push_back( 902 ConstantAsMetadata::get(ConstantInt::get(Type::getInt32Ty(C), 1))); 903 MDNode *Node = MDNode::get(C, Elts); 904 905 Value *Arg0 = CI->getArgOperand(0); 906 Value *Arg1 = CI->getArgOperand(1); 907 908 // Nontemporal (unaligned) store of the 0'th element of the float/double 909 // vector. 910 Type *SrcEltTy = cast<VectorType>(Arg1->getType())->getElementType(); 911 PointerType *EltPtrTy = PointerType::getUnqual(SrcEltTy); 912 Value *Addr = Builder.CreateBitCast(Arg0, EltPtrTy, "cast"); 913 Value *Extract = 914 Builder.CreateExtractElement(Arg1, (uint64_t)0, "extractelement"); 915 916 StoreInst *SI = Builder.CreateAlignedStore(Extract, Addr, 1); 917 SI->setMetadata(M->getMDKindID("nontemporal"), Node); 918 919 // Remove intrinsic. 920 CI->eraseFromParent(); 921 return; 922 } 923 924 if (IsX86 && (Name.startswith("avx.movnt.") || 925 Name.startswith("avx512.storent."))) { 926 Module *M = F->getParent(); 927 SmallVector<Metadata *, 1> Elts; 928 Elts.push_back( 929 ConstantAsMetadata::get(ConstantInt::get(Type::getInt32Ty(C), 1))); 930 MDNode *Node = MDNode::get(C, Elts); 931 932 Value *Arg0 = CI->getArgOperand(0); 933 Value *Arg1 = CI->getArgOperand(1); 934 935 // Convert the type of the pointer to a pointer to the stored type. 936 Value *BC = Builder.CreateBitCast(Arg0, 937 PointerType::getUnqual(Arg1->getType()), 938 "cast"); 939 VectorType *VTy = cast<VectorType>(Arg1->getType()); 940 StoreInst *SI = Builder.CreateAlignedStore(Arg1, BC, 941 VTy->getBitWidth() / 8); 942 SI->setMetadata(M->getMDKindID("nontemporal"), Node); 943 944 // Remove intrinsic. 945 CI->eraseFromParent(); 946 return; 947 } 948 949 if (IsX86 && Name == "sse2.storel.dq") { 950 Value *Arg0 = CI->getArgOperand(0); 951 Value *Arg1 = CI->getArgOperand(1); 952 953 Type *NewVecTy = VectorType::get(Type::getInt64Ty(C), 2); 954 Value *BC0 = Builder.CreateBitCast(Arg1, NewVecTy, "cast"); 955 Value *Elt = Builder.CreateExtractElement(BC0, (uint64_t)0); 956 Value *BC = Builder.CreateBitCast(Arg0, 957 PointerType::getUnqual(Elt->getType()), 958 "cast"); 959 Builder.CreateAlignedStore(Elt, BC, 1); 960 961 // Remove intrinsic. 962 CI->eraseFromParent(); 963 return; 964 } 965 966 if (IsX86 && (Name.startswith("sse.storeu.") || 967 Name.startswith("sse2.storeu.") || 968 Name.startswith("avx.storeu."))) { 969 Value *Arg0 = CI->getArgOperand(0); 970 Value *Arg1 = CI->getArgOperand(1); 971 972 Arg0 = Builder.CreateBitCast(Arg0, 973 PointerType::getUnqual(Arg1->getType()), 974 "cast"); 975 Builder.CreateAlignedStore(Arg1, Arg0, 1); 976 977 // Remove intrinsic. 978 CI->eraseFromParent(); 979 return; 980 } 981 982 if (IsX86 && (Name.startswith("avx512.mask.store"))) { 983 // "avx512.mask.storeu." or "avx512.mask.store." 984 bool Aligned = Name[17] != 'u'; // "avx512.mask.storeu". 985 UpgradeMaskedStore(Builder, CI->getArgOperand(0), CI->getArgOperand(1), 986 CI->getArgOperand(2), Aligned); 987 988 // Remove intrinsic. 989 CI->eraseFromParent(); 990 return; 991 } 992 993 Value *Rep; 994 // Upgrade packed integer vector compare intrinsics to compare instructions. 995 if (IsX86 && (Name.startswith("sse2.pcmp") || 996 Name.startswith("avx2.pcmp"))) { 997 // "sse2.pcpmpeq." "sse2.pcmpgt." "avx2.pcmpeq." or "avx2.pcmpgt." 998 bool CmpEq = Name[9] == 'e'; 999 Rep = Builder.CreateICmp(CmpEq ? ICmpInst::ICMP_EQ : ICmpInst::ICMP_SGT, 1000 CI->getArgOperand(0), CI->getArgOperand(1)); 1001 Rep = Builder.CreateSExt(Rep, CI->getType(), ""); 1002 } else if (IsX86 && (Name == "sse.add.ss" || Name == "sse2.add.sd")) { 1003 Type *I32Ty = Type::getInt32Ty(C); 1004 Value *Elt0 = Builder.CreateExtractElement(CI->getArgOperand(0), 1005 ConstantInt::get(I32Ty, 0)); 1006 Value *Elt1 = Builder.CreateExtractElement(CI->getArgOperand(1), 1007 ConstantInt::get(I32Ty, 0)); 1008 Rep = Builder.CreateInsertElement(CI->getArgOperand(0), 1009 Builder.CreateFAdd(Elt0, Elt1), 1010 ConstantInt::get(I32Ty, 0)); 1011 } else if (IsX86 && (Name == "sse.sub.ss" || Name == "sse2.sub.sd")) { 1012 Type *I32Ty = Type::getInt32Ty(C); 1013 Value *Elt0 = Builder.CreateExtractElement(CI->getArgOperand(0), 1014 ConstantInt::get(I32Ty, 0)); 1015 Value *Elt1 = Builder.CreateExtractElement(CI->getArgOperand(1), 1016 ConstantInt::get(I32Ty, 0)); 1017 Rep = Builder.CreateInsertElement(CI->getArgOperand(0), 1018 Builder.CreateFSub(Elt0, Elt1), 1019 ConstantInt::get(I32Ty, 0)); 1020 } else if (IsX86 && (Name == "sse.mul.ss" || Name == "sse2.mul.sd")) { 1021 Type *I32Ty = Type::getInt32Ty(C); 1022 Value *Elt0 = Builder.CreateExtractElement(CI->getArgOperand(0), 1023 ConstantInt::get(I32Ty, 0)); 1024 Value *Elt1 = Builder.CreateExtractElement(CI->getArgOperand(1), 1025 ConstantInt::get(I32Ty, 0)); 1026 Rep = Builder.CreateInsertElement(CI->getArgOperand(0), 1027 Builder.CreateFMul(Elt0, Elt1), 1028 ConstantInt::get(I32Ty, 0)); 1029 } else if (IsX86 && (Name == "sse.div.ss" || Name == "sse2.div.sd")) { 1030 Type *I32Ty = Type::getInt32Ty(C); 1031 Value *Elt0 = Builder.CreateExtractElement(CI->getArgOperand(0), 1032 ConstantInt::get(I32Ty, 0)); 1033 Value *Elt1 = Builder.CreateExtractElement(CI->getArgOperand(1), 1034 ConstantInt::get(I32Ty, 0)); 1035 Rep = Builder.CreateInsertElement(CI->getArgOperand(0), 1036 Builder.CreateFDiv(Elt0, Elt1), 1037 ConstantInt::get(I32Ty, 0)); 1038 } else if (IsX86 && Name.startswith("avx512.mask.pcmp")) { 1039 // "avx512.mask.pcmpeq." or "avx512.mask.pcmpgt." 1040 bool CmpEq = Name[16] == 'e'; 1041 Rep = upgradeMaskedCompare(Builder, *CI, CmpEq ? 0 : 6, true); 1042 } else if (IsX86 && Name.startswith("avx512.mask.cmp")) { 1043 unsigned Imm = cast<ConstantInt>(CI->getArgOperand(2))->getZExtValue(); 1044 Rep = upgradeMaskedCompare(Builder, *CI, Imm, true); 1045 } else if (IsX86 && Name.startswith("avx512.mask.ucmp")) { 1046 unsigned Imm = cast<ConstantInt>(CI->getArgOperand(2))->getZExtValue(); 1047 Rep = upgradeMaskedCompare(Builder, *CI, Imm, false); 1048 } else if (IsX86 && (Name == "sse41.pmaxsb" || 1049 Name == "sse2.pmaxs.w" || 1050 Name == "sse41.pmaxsd" || 1051 Name.startswith("avx2.pmaxs") || 1052 Name.startswith("avx512.mask.pmaxs"))) { 1053 Rep = upgradeIntMinMax(Builder, *CI, ICmpInst::ICMP_SGT); 1054 } else if (IsX86 && (Name == "sse2.pmaxu.b" || 1055 Name == "sse41.pmaxuw" || 1056 Name == "sse41.pmaxud" || 1057 Name.startswith("avx2.pmaxu") || 1058 Name.startswith("avx512.mask.pmaxu"))) { 1059 Rep = upgradeIntMinMax(Builder, *CI, ICmpInst::ICMP_UGT); 1060 } else if (IsX86 && (Name == "sse41.pminsb" || 1061 Name == "sse2.pmins.w" || 1062 Name == "sse41.pminsd" || 1063 Name.startswith("avx2.pmins") || 1064 Name.startswith("avx512.mask.pmins"))) { 1065 Rep = upgradeIntMinMax(Builder, *CI, ICmpInst::ICMP_SLT); 1066 } else if (IsX86 && (Name == "sse2.pminu.b" || 1067 Name == "sse41.pminuw" || 1068 Name == "sse41.pminud" || 1069 Name.startswith("avx2.pminu") || 1070 Name.startswith("avx512.mask.pminu"))) { 1071 Rep = upgradeIntMinMax(Builder, *CI, ICmpInst::ICMP_ULT); 1072 } else if (IsX86 && (Name == "sse2.cvtdq2pd" || 1073 Name == "sse2.cvtps2pd" || 1074 Name == "avx.cvtdq2.pd.256" || 1075 Name == "avx.cvt.ps2.pd.256" || 1076 Name.startswith("avx512.mask.cvtdq2pd.") || 1077 Name.startswith("avx512.mask.cvtudq2pd."))) { 1078 // Lossless i32/float to double conversion. 1079 // Extract the bottom elements if necessary and convert to double vector. 1080 Value *Src = CI->getArgOperand(0); 1081 VectorType *SrcTy = cast<VectorType>(Src->getType()); 1082 VectorType *DstTy = cast<VectorType>(CI->getType()); 1083 Rep = CI->getArgOperand(0); 1084 1085 unsigned NumDstElts = DstTy->getNumElements(); 1086 if (NumDstElts < SrcTy->getNumElements()) { 1087 assert(NumDstElts == 2 && "Unexpected vector size"); 1088 uint32_t ShuffleMask[2] = { 0, 1 }; 1089 Rep = Builder.CreateShuffleVector(Rep, UndefValue::get(SrcTy), 1090 ShuffleMask); 1091 } 1092 1093 bool SInt2Double = (StringRef::npos != Name.find("cvtdq2")); 1094 bool UInt2Double = (StringRef::npos != Name.find("cvtudq2")); 1095 if (SInt2Double) 1096 Rep = Builder.CreateSIToFP(Rep, DstTy, "cvtdq2pd"); 1097 else if (UInt2Double) 1098 Rep = Builder.CreateUIToFP(Rep, DstTy, "cvtudq2pd"); 1099 else 1100 Rep = Builder.CreateFPExt(Rep, DstTy, "cvtps2pd"); 1101 1102 if (CI->getNumArgOperands() == 3) 1103 Rep = EmitX86Select(Builder, CI->getArgOperand(2), Rep, 1104 CI->getArgOperand(1)); 1105 } else if (IsX86 && (Name.startswith("avx512.mask.loadu."))) { 1106 Rep = UpgradeMaskedLoad(Builder, CI->getArgOperand(0), 1107 CI->getArgOperand(1), CI->getArgOperand(2), 1108 /*Aligned*/false); 1109 } else if (IsX86 && (Name.startswith("avx512.mask.load."))) { 1110 Rep = UpgradeMaskedLoad(Builder, CI->getArgOperand(0), 1111 CI->getArgOperand(1),CI->getArgOperand(2), 1112 /*Aligned*/true); 1113 } else if (IsX86 && Name.startswith("xop.vpcom")) { 1114 Intrinsic::ID intID; 1115 if (Name.endswith("ub")) 1116 intID = Intrinsic::x86_xop_vpcomub; 1117 else if (Name.endswith("uw")) 1118 intID = Intrinsic::x86_xop_vpcomuw; 1119 else if (Name.endswith("ud")) 1120 intID = Intrinsic::x86_xop_vpcomud; 1121 else if (Name.endswith("uq")) 1122 intID = Intrinsic::x86_xop_vpcomuq; 1123 else if (Name.endswith("b")) 1124 intID = Intrinsic::x86_xop_vpcomb; 1125 else if (Name.endswith("w")) 1126 intID = Intrinsic::x86_xop_vpcomw; 1127 else if (Name.endswith("d")) 1128 intID = Intrinsic::x86_xop_vpcomd; 1129 else if (Name.endswith("q")) 1130 intID = Intrinsic::x86_xop_vpcomq; 1131 else 1132 llvm_unreachable("Unknown suffix"); 1133 1134 Name = Name.substr(9); // strip off "xop.vpcom" 1135 unsigned Imm; 1136 if (Name.startswith("lt")) 1137 Imm = 0; 1138 else if (Name.startswith("le")) 1139 Imm = 1; 1140 else if (Name.startswith("gt")) 1141 Imm = 2; 1142 else if (Name.startswith("ge")) 1143 Imm = 3; 1144 else if (Name.startswith("eq")) 1145 Imm = 4; 1146 else if (Name.startswith("ne")) 1147 Imm = 5; 1148 else if (Name.startswith("false")) 1149 Imm = 6; 1150 else if (Name.startswith("true")) 1151 Imm = 7; 1152 else 1153 llvm_unreachable("Unknown condition"); 1154 1155 Function *VPCOM = Intrinsic::getDeclaration(F->getParent(), intID); 1156 Rep = 1157 Builder.CreateCall(VPCOM, {CI->getArgOperand(0), CI->getArgOperand(1), 1158 Builder.getInt8(Imm)}); 1159 } else if (IsX86 && Name.startswith("xop.vpcmov")) { 1160 Value *Sel = CI->getArgOperand(2); 1161 Value *NotSel = Builder.CreateNot(Sel); 1162 Value *Sel0 = Builder.CreateAnd(CI->getArgOperand(0), Sel); 1163 Value *Sel1 = Builder.CreateAnd(CI->getArgOperand(1), NotSel); 1164 Rep = Builder.CreateOr(Sel0, Sel1); 1165 } else if (IsX86 && Name == "sse42.crc32.64.8") { 1166 Function *CRC32 = Intrinsic::getDeclaration(F->getParent(), 1167 Intrinsic::x86_sse42_crc32_32_8); 1168 Value *Trunc0 = Builder.CreateTrunc(CI->getArgOperand(0), Type::getInt32Ty(C)); 1169 Rep = Builder.CreateCall(CRC32, {Trunc0, CI->getArgOperand(1)}); 1170 Rep = Builder.CreateZExt(Rep, CI->getType(), ""); 1171 } else if (IsX86 && Name.startswith("avx.vbroadcast.s")) { 1172 // Replace broadcasts with a series of insertelements. 1173 Type *VecTy = CI->getType(); 1174 Type *EltTy = VecTy->getVectorElementType(); 1175 unsigned EltNum = VecTy->getVectorNumElements(); 1176 Value *Cast = Builder.CreateBitCast(CI->getArgOperand(0), 1177 EltTy->getPointerTo()); 1178 Value *Load = Builder.CreateLoad(EltTy, Cast); 1179 Type *I32Ty = Type::getInt32Ty(C); 1180 Rep = UndefValue::get(VecTy); 1181 for (unsigned I = 0; I < EltNum; ++I) 1182 Rep = Builder.CreateInsertElement(Rep, Load, 1183 ConstantInt::get(I32Ty, I)); 1184 } else if (IsX86 && (Name.startswith("sse41.pmovsx") || 1185 Name.startswith("sse41.pmovzx") || 1186 Name.startswith("avx2.pmovsx") || 1187 Name.startswith("avx2.pmovzx") || 1188 Name.startswith("avx512.mask.pmovsx") || 1189 Name.startswith("avx512.mask.pmovzx"))) { 1190 VectorType *SrcTy = cast<VectorType>(CI->getArgOperand(0)->getType()); 1191 VectorType *DstTy = cast<VectorType>(CI->getType()); 1192 unsigned NumDstElts = DstTy->getNumElements(); 1193 1194 // Extract a subvector of the first NumDstElts lanes and sign/zero extend. 1195 SmallVector<uint32_t, 8> ShuffleMask(NumDstElts); 1196 for (unsigned i = 0; i != NumDstElts; ++i) 1197 ShuffleMask[i] = i; 1198 1199 Value *SV = Builder.CreateShuffleVector( 1200 CI->getArgOperand(0), UndefValue::get(SrcTy), ShuffleMask); 1201 1202 bool DoSext = (StringRef::npos != Name.find("pmovsx")); 1203 Rep = DoSext ? Builder.CreateSExt(SV, DstTy) 1204 : Builder.CreateZExt(SV, DstTy); 1205 // If there are 3 arguments, it's a masked intrinsic so we need a select. 1206 if (CI->getNumArgOperands() == 3) 1207 Rep = EmitX86Select(Builder, CI->getArgOperand(2), Rep, 1208 CI->getArgOperand(1)); 1209 } else if (IsX86 && (Name.startswith("avx.vbroadcastf128") || 1210 Name == "avx2.vbroadcasti128")) { 1211 // Replace vbroadcastf128/vbroadcasti128 with a vector load+shuffle. 1212 Type *EltTy = CI->getType()->getVectorElementType(); 1213 unsigned NumSrcElts = 128 / EltTy->getPrimitiveSizeInBits(); 1214 Type *VT = VectorType::get(EltTy, NumSrcElts); 1215 Value *Op = Builder.CreatePointerCast(CI->getArgOperand(0), 1216 PointerType::getUnqual(VT)); 1217 Value *Load = Builder.CreateAlignedLoad(Op, 1); 1218 if (NumSrcElts == 2) 1219 Rep = Builder.CreateShuffleVector(Load, UndefValue::get(Load->getType()), 1220 { 0, 1, 0, 1 }); 1221 else 1222 Rep = Builder.CreateShuffleVector(Load, UndefValue::get(Load->getType()), 1223 { 0, 1, 2, 3, 0, 1, 2, 3 }); 1224 } else if (IsX86 && (Name.startswith("avx2.pbroadcast") || 1225 Name.startswith("avx2.vbroadcast") || 1226 Name.startswith("avx512.pbroadcast") || 1227 Name.startswith("avx512.mask.broadcast.s"))) { 1228 // Replace vp?broadcasts with a vector shuffle. 1229 Value *Op = CI->getArgOperand(0); 1230 unsigned NumElts = CI->getType()->getVectorNumElements(); 1231 Type *MaskTy = VectorType::get(Type::getInt32Ty(C), NumElts); 1232 Rep = Builder.CreateShuffleVector(Op, UndefValue::get(Op->getType()), 1233 Constant::getNullValue(MaskTy)); 1234 1235 if (CI->getNumArgOperands() == 3) 1236 Rep = EmitX86Select(Builder, CI->getArgOperand(2), Rep, 1237 CI->getArgOperand(1)); 1238 } else if (IsX86 && Name.startswith("avx512.mask.palignr.")) { 1239 Rep = UpgradeX86ALIGNIntrinsics(Builder, CI->getArgOperand(0), 1240 CI->getArgOperand(1), 1241 CI->getArgOperand(2), 1242 CI->getArgOperand(3), 1243 CI->getArgOperand(4), 1244 false); 1245 } else if (IsX86 && Name.startswith("avx512.mask.valign.")) { 1246 Rep = UpgradeX86ALIGNIntrinsics(Builder, CI->getArgOperand(0), 1247 CI->getArgOperand(1), 1248 CI->getArgOperand(2), 1249 CI->getArgOperand(3), 1250 CI->getArgOperand(4), 1251 true); 1252 } else if (IsX86 && (Name == "sse2.psll.dq" || 1253 Name == "avx2.psll.dq")) { 1254 // 128/256-bit shift left specified in bits. 1255 unsigned Shift = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue(); 1256 Rep = UpgradeX86PSLLDQIntrinsics(Builder, CI->getArgOperand(0), 1257 Shift / 8); // Shift is in bits. 1258 } else if (IsX86 && (Name == "sse2.psrl.dq" || 1259 Name == "avx2.psrl.dq")) { 1260 // 128/256-bit shift right specified in bits. 1261 unsigned Shift = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue(); 1262 Rep = UpgradeX86PSRLDQIntrinsics(Builder, CI->getArgOperand(0), 1263 Shift / 8); // Shift is in bits. 1264 } else if (IsX86 && (Name == "sse2.psll.dq.bs" || 1265 Name == "avx2.psll.dq.bs" || 1266 Name == "avx512.psll.dq.512")) { 1267 // 128/256/512-bit shift left specified in bytes. 1268 unsigned Shift = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue(); 1269 Rep = UpgradeX86PSLLDQIntrinsics(Builder, CI->getArgOperand(0), Shift); 1270 } else if (IsX86 && (Name == "sse2.psrl.dq.bs" || 1271 Name == "avx2.psrl.dq.bs" || 1272 Name == "avx512.psrl.dq.512")) { 1273 // 128/256/512-bit shift right specified in bytes. 1274 unsigned Shift = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue(); 1275 Rep = UpgradeX86PSRLDQIntrinsics(Builder, CI->getArgOperand(0), Shift); 1276 } else if (IsX86 && (Name == "sse41.pblendw" || 1277 Name.startswith("sse41.blendp") || 1278 Name.startswith("avx.blend.p") || 1279 Name == "avx2.pblendw" || 1280 Name.startswith("avx2.pblendd."))) { 1281 Value *Op0 = CI->getArgOperand(0); 1282 Value *Op1 = CI->getArgOperand(1); 1283 unsigned Imm = cast <ConstantInt>(CI->getArgOperand(2))->getZExtValue(); 1284 VectorType *VecTy = cast<VectorType>(CI->getType()); 1285 unsigned NumElts = VecTy->getNumElements(); 1286 1287 SmallVector<uint32_t, 16> Idxs(NumElts); 1288 for (unsigned i = 0; i != NumElts; ++i) 1289 Idxs[i] = ((Imm >> (i%8)) & 1) ? i + NumElts : i; 1290 1291 Rep = Builder.CreateShuffleVector(Op0, Op1, Idxs); 1292 } else if (IsX86 && (Name.startswith("avx.vinsertf128.") || 1293 Name == "avx2.vinserti128" || 1294 Name.startswith("avx512.mask.insert"))) { 1295 Value *Op0 = CI->getArgOperand(0); 1296 Value *Op1 = CI->getArgOperand(1); 1297 unsigned Imm = cast<ConstantInt>(CI->getArgOperand(2))->getZExtValue(); 1298 unsigned DstNumElts = CI->getType()->getVectorNumElements(); 1299 unsigned SrcNumElts = Op1->getType()->getVectorNumElements(); 1300 unsigned Scale = DstNumElts / SrcNumElts; 1301 1302 // Mask off the high bits of the immediate value; hardware ignores those. 1303 Imm = Imm % Scale; 1304 1305 // Extend the second operand into a vector the size of the destination. 1306 Value *UndefV = UndefValue::get(Op1->getType()); 1307 SmallVector<uint32_t, 8> Idxs(DstNumElts); 1308 for (unsigned i = 0; i != SrcNumElts; ++i) 1309 Idxs[i] = i; 1310 for (unsigned i = SrcNumElts; i != DstNumElts; ++i) 1311 Idxs[i] = SrcNumElts; 1312 Rep = Builder.CreateShuffleVector(Op1, UndefV, Idxs); 1313 1314 // Insert the second operand into the first operand. 1315 1316 // Note that there is no guarantee that instruction lowering will actually 1317 // produce a vinsertf128 instruction for the created shuffles. In 1318 // particular, the 0 immediate case involves no lane changes, so it can 1319 // be handled as a blend. 1320 1321 // Example of shuffle mask for 32-bit elements: 1322 // Imm = 1 <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11> 1323 // Imm = 0 <i32 8, i32 9, i32 10, i32 11, i32 4, i32 5, i32 6, i32 7 > 1324 1325 // First fill with identify mask. 1326 for (unsigned i = 0; i != DstNumElts; ++i) 1327 Idxs[i] = i; 1328 // Then replace the elements where we need to insert. 1329 for (unsigned i = 0; i != SrcNumElts; ++i) 1330 Idxs[i + Imm * SrcNumElts] = i + DstNumElts; 1331 Rep = Builder.CreateShuffleVector(Op0, Rep, Idxs); 1332 1333 // If the intrinsic has a mask operand, handle that. 1334 if (CI->getNumArgOperands() == 5) 1335 Rep = EmitX86Select(Builder, CI->getArgOperand(4), Rep, 1336 CI->getArgOperand(3)); 1337 } else if (IsX86 && (Name.startswith("avx.vextractf128.") || 1338 Name == "avx2.vextracti128" || 1339 Name.startswith("avx512.mask.vextract"))) { 1340 Value *Op0 = CI->getArgOperand(0); 1341 unsigned Imm = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue(); 1342 unsigned DstNumElts = CI->getType()->getVectorNumElements(); 1343 unsigned SrcNumElts = Op0->getType()->getVectorNumElements(); 1344 unsigned Scale = SrcNumElts / DstNumElts; 1345 1346 // Mask off the high bits of the immediate value; hardware ignores those. 1347 Imm = Imm % Scale; 1348 1349 // Get indexes for the subvector of the input vector. 1350 SmallVector<uint32_t, 8> Idxs(DstNumElts); 1351 for (unsigned i = 0; i != DstNumElts; ++i) { 1352 Idxs[i] = i + (Imm * DstNumElts); 1353 } 1354 Rep = Builder.CreateShuffleVector(Op0, Op0, Idxs); 1355 1356 // If the intrinsic has a mask operand, handle that. 1357 if (CI->getNumArgOperands() == 4) 1358 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1359 CI->getArgOperand(2)); 1360 } else if (!IsX86 && Name == "stackprotectorcheck") { 1361 Rep = nullptr; 1362 } else if (IsX86 && (Name.startswith("avx512.mask.perm.df.") || 1363 Name.startswith("avx512.mask.perm.di."))) { 1364 Value *Op0 = CI->getArgOperand(0); 1365 unsigned Imm = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue(); 1366 VectorType *VecTy = cast<VectorType>(CI->getType()); 1367 unsigned NumElts = VecTy->getNumElements(); 1368 1369 SmallVector<uint32_t, 8> Idxs(NumElts); 1370 for (unsigned i = 0; i != NumElts; ++i) 1371 Idxs[i] = (i & ~0x3) + ((Imm >> (2 * (i & 0x3))) & 3); 1372 1373 Rep = Builder.CreateShuffleVector(Op0, Op0, Idxs); 1374 1375 if (CI->getNumArgOperands() == 4) 1376 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1377 CI->getArgOperand(2)); 1378 } else if (IsX86 && (Name.startswith("avx.vpermil.") || 1379 Name == "sse2.pshuf.d" || 1380 Name.startswith("avx512.mask.vpermil.p") || 1381 Name.startswith("avx512.mask.pshuf.d."))) { 1382 Value *Op0 = CI->getArgOperand(0); 1383 unsigned Imm = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue(); 1384 VectorType *VecTy = cast<VectorType>(CI->getType()); 1385 unsigned NumElts = VecTy->getNumElements(); 1386 // Calculate the size of each index in the immediate. 1387 unsigned IdxSize = 64 / VecTy->getScalarSizeInBits(); 1388 unsigned IdxMask = ((1 << IdxSize) - 1); 1389 1390 SmallVector<uint32_t, 8> Idxs(NumElts); 1391 // Lookup the bits for this element, wrapping around the immediate every 1392 // 8-bits. Elements are grouped into sets of 2 or 4 elements so we need 1393 // to offset by the first index of each group. 1394 for (unsigned i = 0; i != NumElts; ++i) 1395 Idxs[i] = ((Imm >> ((i * IdxSize) % 8)) & IdxMask) | (i & ~IdxMask); 1396 1397 Rep = Builder.CreateShuffleVector(Op0, Op0, Idxs); 1398 1399 if (CI->getNumArgOperands() == 4) 1400 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1401 CI->getArgOperand(2)); 1402 } else if (IsX86 && (Name == "sse2.pshufl.w" || 1403 Name.startswith("avx512.mask.pshufl.w."))) { 1404 Value *Op0 = CI->getArgOperand(0); 1405 unsigned Imm = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue(); 1406 unsigned NumElts = CI->getType()->getVectorNumElements(); 1407 1408 SmallVector<uint32_t, 16> Idxs(NumElts); 1409 for (unsigned l = 0; l != NumElts; l += 8) { 1410 for (unsigned i = 0; i != 4; ++i) 1411 Idxs[i + l] = ((Imm >> (2 * i)) & 0x3) + l; 1412 for (unsigned i = 4; i != 8; ++i) 1413 Idxs[i + l] = i + l; 1414 } 1415 1416 Rep = Builder.CreateShuffleVector(Op0, Op0, Idxs); 1417 1418 if (CI->getNumArgOperands() == 4) 1419 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1420 CI->getArgOperand(2)); 1421 } else if (IsX86 && (Name == "sse2.pshufh.w" || 1422 Name.startswith("avx512.mask.pshufh.w."))) { 1423 Value *Op0 = CI->getArgOperand(0); 1424 unsigned Imm = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue(); 1425 unsigned NumElts = CI->getType()->getVectorNumElements(); 1426 1427 SmallVector<uint32_t, 16> Idxs(NumElts); 1428 for (unsigned l = 0; l != NumElts; l += 8) { 1429 for (unsigned i = 0; i != 4; ++i) 1430 Idxs[i + l] = i + l; 1431 for (unsigned i = 0; i != 4; ++i) 1432 Idxs[i + l + 4] = ((Imm >> (2 * i)) & 0x3) + 4 + l; 1433 } 1434 1435 Rep = Builder.CreateShuffleVector(Op0, Op0, Idxs); 1436 1437 if (CI->getNumArgOperands() == 4) 1438 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1439 CI->getArgOperand(2)); 1440 } else if (IsX86 && Name.startswith("avx512.mask.shuf.p")) { 1441 Value *Op0 = CI->getArgOperand(0); 1442 Value *Op1 = CI->getArgOperand(1); 1443 unsigned Imm = cast<ConstantInt>(CI->getArgOperand(2))->getZExtValue(); 1444 unsigned NumElts = CI->getType()->getVectorNumElements(); 1445 1446 unsigned NumLaneElts = 128/CI->getType()->getScalarSizeInBits(); 1447 unsigned HalfLaneElts = NumLaneElts / 2; 1448 1449 SmallVector<uint32_t, 16> Idxs(NumElts); 1450 for (unsigned i = 0; i != NumElts; ++i) { 1451 // Base index is the starting element of the lane. 1452 Idxs[i] = i - (i % NumLaneElts); 1453 // If we are half way through the lane switch to the other source. 1454 if ((i % NumLaneElts) >= HalfLaneElts) 1455 Idxs[i] += NumElts; 1456 // Now select the specific element. By adding HalfLaneElts bits from 1457 // the immediate. Wrapping around the immediate every 8-bits. 1458 Idxs[i] += (Imm >> ((i * HalfLaneElts) % 8)) & ((1 << HalfLaneElts) - 1); 1459 } 1460 1461 Rep = Builder.CreateShuffleVector(Op0, Op1, Idxs); 1462 1463 Rep = EmitX86Select(Builder, CI->getArgOperand(4), Rep, 1464 CI->getArgOperand(3)); 1465 } else if (IsX86 && (Name.startswith("avx512.mask.movddup") || 1466 Name.startswith("avx512.mask.movshdup") || 1467 Name.startswith("avx512.mask.movsldup"))) { 1468 Value *Op0 = CI->getArgOperand(0); 1469 unsigned NumElts = CI->getType()->getVectorNumElements(); 1470 unsigned NumLaneElts = 128/CI->getType()->getScalarSizeInBits(); 1471 1472 unsigned Offset = 0; 1473 if (Name.startswith("avx512.mask.movshdup.")) 1474 Offset = 1; 1475 1476 SmallVector<uint32_t, 16> Idxs(NumElts); 1477 for (unsigned l = 0; l != NumElts; l += NumLaneElts) 1478 for (unsigned i = 0; i != NumLaneElts; i += 2) { 1479 Idxs[i + l + 0] = i + l + Offset; 1480 Idxs[i + l + 1] = i + l + Offset; 1481 } 1482 1483 Rep = Builder.CreateShuffleVector(Op0, Op0, Idxs); 1484 1485 Rep = EmitX86Select(Builder, CI->getArgOperand(2), Rep, 1486 CI->getArgOperand(1)); 1487 } else if (IsX86 && (Name.startswith("avx512.mask.punpckl") || 1488 Name.startswith("avx512.mask.unpckl."))) { 1489 Value *Op0 = CI->getArgOperand(0); 1490 Value *Op1 = CI->getArgOperand(1); 1491 int NumElts = CI->getType()->getVectorNumElements(); 1492 int NumLaneElts = 128/CI->getType()->getScalarSizeInBits(); 1493 1494 SmallVector<uint32_t, 64> Idxs(NumElts); 1495 for (int l = 0; l != NumElts; l += NumLaneElts) 1496 for (int i = 0; i != NumLaneElts; ++i) 1497 Idxs[i + l] = l + (i / 2) + NumElts * (i % 2); 1498 1499 Rep = Builder.CreateShuffleVector(Op0, Op1, Idxs); 1500 1501 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1502 CI->getArgOperand(2)); 1503 } else if (IsX86 && (Name.startswith("avx512.mask.punpckh") || 1504 Name.startswith("avx512.mask.unpckh."))) { 1505 Value *Op0 = CI->getArgOperand(0); 1506 Value *Op1 = CI->getArgOperand(1); 1507 int NumElts = CI->getType()->getVectorNumElements(); 1508 int NumLaneElts = 128/CI->getType()->getScalarSizeInBits(); 1509 1510 SmallVector<uint32_t, 64> Idxs(NumElts); 1511 for (int l = 0; l != NumElts; l += NumLaneElts) 1512 for (int i = 0; i != NumLaneElts; ++i) 1513 Idxs[i + l] = (NumLaneElts / 2) + l + (i / 2) + NumElts * (i % 2); 1514 1515 Rep = Builder.CreateShuffleVector(Op0, Op1, Idxs); 1516 1517 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1518 CI->getArgOperand(2)); 1519 } else if (IsX86 && Name.startswith("avx512.mask.pand.")) { 1520 Rep = Builder.CreateAnd(CI->getArgOperand(0), CI->getArgOperand(1)); 1521 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1522 CI->getArgOperand(2)); 1523 } else if (IsX86 && Name.startswith("avx512.mask.pandn.")) { 1524 Rep = Builder.CreateAnd(Builder.CreateNot(CI->getArgOperand(0)), 1525 CI->getArgOperand(1)); 1526 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1527 CI->getArgOperand(2)); 1528 } else if (IsX86 && Name.startswith("avx512.mask.por.")) { 1529 Rep = Builder.CreateOr(CI->getArgOperand(0), CI->getArgOperand(1)); 1530 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1531 CI->getArgOperand(2)); 1532 } else if (IsX86 && Name.startswith("avx512.mask.pxor.")) { 1533 Rep = Builder.CreateXor(CI->getArgOperand(0), CI->getArgOperand(1)); 1534 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1535 CI->getArgOperand(2)); 1536 } else if (IsX86 && Name.startswith("avx512.mask.and.")) { 1537 VectorType *FTy = cast<VectorType>(CI->getType()); 1538 VectorType *ITy = VectorType::getInteger(FTy); 1539 Rep = Builder.CreateAnd(Builder.CreateBitCast(CI->getArgOperand(0), ITy), 1540 Builder.CreateBitCast(CI->getArgOperand(1), ITy)); 1541 Rep = Builder.CreateBitCast(Rep, FTy); 1542 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1543 CI->getArgOperand(2)); 1544 } else if (IsX86 && Name.startswith("avx512.mask.andn.")) { 1545 VectorType *FTy = cast<VectorType>(CI->getType()); 1546 VectorType *ITy = VectorType::getInteger(FTy); 1547 Rep = Builder.CreateNot(Builder.CreateBitCast(CI->getArgOperand(0), ITy)); 1548 Rep = Builder.CreateAnd(Rep, 1549 Builder.CreateBitCast(CI->getArgOperand(1), ITy)); 1550 Rep = Builder.CreateBitCast(Rep, FTy); 1551 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1552 CI->getArgOperand(2)); 1553 } else if (IsX86 && Name.startswith("avx512.mask.or.")) { 1554 VectorType *FTy = cast<VectorType>(CI->getType()); 1555 VectorType *ITy = VectorType::getInteger(FTy); 1556 Rep = Builder.CreateOr(Builder.CreateBitCast(CI->getArgOperand(0), ITy), 1557 Builder.CreateBitCast(CI->getArgOperand(1), ITy)); 1558 Rep = Builder.CreateBitCast(Rep, FTy); 1559 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1560 CI->getArgOperand(2)); 1561 } else if (IsX86 && Name.startswith("avx512.mask.xor.")) { 1562 VectorType *FTy = cast<VectorType>(CI->getType()); 1563 VectorType *ITy = VectorType::getInteger(FTy); 1564 Rep = Builder.CreateXor(Builder.CreateBitCast(CI->getArgOperand(0), ITy), 1565 Builder.CreateBitCast(CI->getArgOperand(1), ITy)); 1566 Rep = Builder.CreateBitCast(Rep, FTy); 1567 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1568 CI->getArgOperand(2)); 1569 } else if (IsX86 && Name.startswith("avx512.mask.padd.")) { 1570 Rep = Builder.CreateAdd(CI->getArgOperand(0), CI->getArgOperand(1)); 1571 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1572 CI->getArgOperand(2)); 1573 } else if (IsX86 && Name.startswith("avx512.mask.psub.")) { 1574 Rep = Builder.CreateSub(CI->getArgOperand(0), CI->getArgOperand(1)); 1575 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1576 CI->getArgOperand(2)); 1577 } else if (IsX86 && Name.startswith("avx512.mask.pmull.")) { 1578 Rep = Builder.CreateMul(CI->getArgOperand(0), CI->getArgOperand(1)); 1579 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1580 CI->getArgOperand(2)); 1581 } else if (IsX86 && (Name.startswith("avx512.mask.add.p"))) { 1582 Rep = Builder.CreateFAdd(CI->getArgOperand(0), CI->getArgOperand(1)); 1583 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1584 CI->getArgOperand(2)); 1585 } else if (IsX86 && Name.startswith("avx512.mask.div.p")) { 1586 Rep = Builder.CreateFDiv(CI->getArgOperand(0), CI->getArgOperand(1)); 1587 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1588 CI->getArgOperand(2)); 1589 } else if (IsX86 && Name.startswith("avx512.mask.mul.p")) { 1590 Rep = Builder.CreateFMul(CI->getArgOperand(0), CI->getArgOperand(1)); 1591 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1592 CI->getArgOperand(2)); 1593 } else if (IsX86 && Name.startswith("avx512.mask.sub.p")) { 1594 Rep = Builder.CreateFSub(CI->getArgOperand(0), CI->getArgOperand(1)); 1595 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1596 CI->getArgOperand(2)); 1597 } else if (IsX86 && Name.startswith("avx512.mask.lzcnt.")) { 1598 Rep = Builder.CreateCall(Intrinsic::getDeclaration(F->getParent(), 1599 Intrinsic::ctlz, 1600 CI->getType()), 1601 { CI->getArgOperand(0), Builder.getInt1(false) }); 1602 Rep = EmitX86Select(Builder, CI->getArgOperand(2), Rep, 1603 CI->getArgOperand(1)); 1604 } else if (IsX86 && (Name.startswith("avx512.mask.max.p") || 1605 Name.startswith("avx512.mask.min.p"))) { 1606 bool IsMin = Name[13] == 'i'; 1607 VectorType *VecTy = cast<VectorType>(CI->getType()); 1608 unsigned VecWidth = VecTy->getPrimitiveSizeInBits(); 1609 unsigned EltWidth = VecTy->getScalarSizeInBits(); 1610 Intrinsic::ID IID; 1611 if (!IsMin && VecWidth == 128 && EltWidth == 32) 1612 IID = Intrinsic::x86_sse_max_ps; 1613 else if (!IsMin && VecWidth == 128 && EltWidth == 64) 1614 IID = Intrinsic::x86_sse2_max_pd; 1615 else if (!IsMin && VecWidth == 256 && EltWidth == 32) 1616 IID = Intrinsic::x86_avx_max_ps_256; 1617 else if (!IsMin && VecWidth == 256 && EltWidth == 64) 1618 IID = Intrinsic::x86_avx_max_pd_256; 1619 else if (IsMin && VecWidth == 128 && EltWidth == 32) 1620 IID = Intrinsic::x86_sse_min_ps; 1621 else if (IsMin && VecWidth == 128 && EltWidth == 64) 1622 IID = Intrinsic::x86_sse2_min_pd; 1623 else if (IsMin && VecWidth == 256 && EltWidth == 32) 1624 IID = Intrinsic::x86_avx_min_ps_256; 1625 else if (IsMin && VecWidth == 256 && EltWidth == 64) 1626 IID = Intrinsic::x86_avx_min_pd_256; 1627 else 1628 llvm_unreachable("Unexpected intrinsic"); 1629 1630 Rep = Builder.CreateCall(Intrinsic::getDeclaration(F->getParent(), IID), 1631 { CI->getArgOperand(0), CI->getArgOperand(1) }); 1632 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1633 CI->getArgOperand(2)); 1634 } else if (IsX86 && Name.startswith("avx512.mask.pshuf.b.")) { 1635 VectorType *VecTy = cast<VectorType>(CI->getType()); 1636 Intrinsic::ID IID; 1637 if (VecTy->getPrimitiveSizeInBits() == 128) 1638 IID = Intrinsic::x86_ssse3_pshuf_b_128; 1639 else if (VecTy->getPrimitiveSizeInBits() == 256) 1640 IID = Intrinsic::x86_avx2_pshuf_b; 1641 else if (VecTy->getPrimitiveSizeInBits() == 512) 1642 IID = Intrinsic::x86_avx512_pshuf_b_512; 1643 else 1644 llvm_unreachable("Unexpected intrinsic"); 1645 1646 Rep = Builder.CreateCall(Intrinsic::getDeclaration(F->getParent(), IID), 1647 { CI->getArgOperand(0), CI->getArgOperand(1) }); 1648 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1649 CI->getArgOperand(2)); 1650 } else if (IsX86 && (Name.startswith("avx512.mask.pmul.dq.") || 1651 Name.startswith("avx512.mask.pmulu.dq."))) { 1652 bool IsUnsigned = Name[16] == 'u'; 1653 VectorType *VecTy = cast<VectorType>(CI->getType()); 1654 Intrinsic::ID IID; 1655 if (!IsUnsigned && VecTy->getPrimitiveSizeInBits() == 128) 1656 IID = Intrinsic::x86_sse41_pmuldq; 1657 else if (!IsUnsigned && VecTy->getPrimitiveSizeInBits() == 256) 1658 IID = Intrinsic::x86_avx2_pmul_dq; 1659 else if (!IsUnsigned && VecTy->getPrimitiveSizeInBits() == 512) 1660 IID = Intrinsic::x86_avx512_pmul_dq_512; 1661 else if (IsUnsigned && VecTy->getPrimitiveSizeInBits() == 128) 1662 IID = Intrinsic::x86_sse2_pmulu_dq; 1663 else if (IsUnsigned && VecTy->getPrimitiveSizeInBits() == 256) 1664 IID = Intrinsic::x86_avx2_pmulu_dq; 1665 else if (IsUnsigned && VecTy->getPrimitiveSizeInBits() == 512) 1666 IID = Intrinsic::x86_avx512_pmulu_dq_512; 1667 else 1668 llvm_unreachable("Unexpected intrinsic"); 1669 1670 Rep = Builder.CreateCall(Intrinsic::getDeclaration(F->getParent(), IID), 1671 { CI->getArgOperand(0), CI->getArgOperand(1) }); 1672 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1673 CI->getArgOperand(2)); 1674 } else if (IsX86 && Name.startswith("avx512.mask.pack")) { 1675 bool IsUnsigned = Name[16] == 'u'; 1676 bool IsDW = Name[18] == 'd'; 1677 VectorType *VecTy = cast<VectorType>(CI->getType()); 1678 Intrinsic::ID IID; 1679 if (!IsUnsigned && !IsDW && VecTy->getPrimitiveSizeInBits() == 128) 1680 IID = Intrinsic::x86_sse2_packsswb_128; 1681 else if (!IsUnsigned && !IsDW && VecTy->getPrimitiveSizeInBits() == 256) 1682 IID = Intrinsic::x86_avx2_packsswb; 1683 else if (!IsUnsigned && !IsDW && VecTy->getPrimitiveSizeInBits() == 512) 1684 IID = Intrinsic::x86_avx512_packsswb_512; 1685 else if (!IsUnsigned && IsDW && VecTy->getPrimitiveSizeInBits() == 128) 1686 IID = Intrinsic::x86_sse2_packssdw_128; 1687 else if (!IsUnsigned && IsDW && VecTy->getPrimitiveSizeInBits() == 256) 1688 IID = Intrinsic::x86_avx2_packssdw; 1689 else if (!IsUnsigned && IsDW && VecTy->getPrimitiveSizeInBits() == 512) 1690 IID = Intrinsic::x86_avx512_packssdw_512; 1691 else if (IsUnsigned && !IsDW && VecTy->getPrimitiveSizeInBits() == 128) 1692 IID = Intrinsic::x86_sse2_packuswb_128; 1693 else if (IsUnsigned && !IsDW && VecTy->getPrimitiveSizeInBits() == 256) 1694 IID = Intrinsic::x86_avx2_packuswb; 1695 else if (IsUnsigned && !IsDW && VecTy->getPrimitiveSizeInBits() == 512) 1696 IID = Intrinsic::x86_avx512_packuswb_512; 1697 else if (IsUnsigned && IsDW && VecTy->getPrimitiveSizeInBits() == 128) 1698 IID = Intrinsic::x86_sse41_packusdw; 1699 else if (IsUnsigned && IsDW && VecTy->getPrimitiveSizeInBits() == 256) 1700 IID = Intrinsic::x86_avx2_packusdw; 1701 else if (IsUnsigned && IsDW && VecTy->getPrimitiveSizeInBits() == 512) 1702 IID = Intrinsic::x86_avx512_packusdw_512; 1703 else 1704 llvm_unreachable("Unexpected intrinsic"); 1705 1706 Rep = Builder.CreateCall(Intrinsic::getDeclaration(F->getParent(), IID), 1707 { CI->getArgOperand(0), CI->getArgOperand(1) }); 1708 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1709 CI->getArgOperand(2)); 1710 } else if (IsX86 && Name.startswith("avx512.mask.psll")) { 1711 bool IsImmediate = Name[16] == 'i' || 1712 (Name.size() > 18 && Name[18] == 'i'); 1713 bool IsVariable = Name[16] == 'v'; 1714 char Size = Name[16] == '.' ? Name[17] : 1715 Name[17] == '.' ? Name[18] : 1716 Name[18] == '.' ? Name[19] : 1717 Name[20]; 1718 1719 Intrinsic::ID IID; 1720 if (IsVariable && Name[17] != '.') { 1721 if (Size == 'd' && Name[17] == '2') // avx512.mask.psllv2.di 1722 IID = Intrinsic::x86_avx2_psllv_q; 1723 else if (Size == 'd' && Name[17] == '4') // avx512.mask.psllv4.di 1724 IID = Intrinsic::x86_avx2_psllv_q_256; 1725 else if (Size == 's' && Name[17] == '4') // avx512.mask.psllv4.si 1726 IID = Intrinsic::x86_avx2_psllv_d; 1727 else if (Size == 's' && Name[17] == '8') // avx512.mask.psllv8.si 1728 IID = Intrinsic::x86_avx2_psllv_d_256; 1729 else if (Size == 'h' && Name[17] == '8') // avx512.mask.psllv8.hi 1730 IID = Intrinsic::x86_avx512_psllv_w_128; 1731 else if (Size == 'h' && Name[17] == '1') // avx512.mask.psllv16.hi 1732 IID = Intrinsic::x86_avx512_psllv_w_256; 1733 else if (Name[17] == '3' && Name[18] == '2') // avx512.mask.psllv32hi 1734 IID = Intrinsic::x86_avx512_psllv_w_512; 1735 else 1736 llvm_unreachable("Unexpected size"); 1737 } else if (Name.endswith(".128")) { 1738 if (Size == 'd') // avx512.mask.psll.d.128, avx512.mask.psll.di.128 1739 IID = IsImmediate ? Intrinsic::x86_sse2_pslli_d 1740 : Intrinsic::x86_sse2_psll_d; 1741 else if (Size == 'q') // avx512.mask.psll.q.128, avx512.mask.psll.qi.128 1742 IID = IsImmediate ? Intrinsic::x86_sse2_pslli_q 1743 : Intrinsic::x86_sse2_psll_q; 1744 else if (Size == 'w') // avx512.mask.psll.w.128, avx512.mask.psll.wi.128 1745 IID = IsImmediate ? Intrinsic::x86_sse2_pslli_w 1746 : Intrinsic::x86_sse2_psll_w; 1747 else 1748 llvm_unreachable("Unexpected size"); 1749 } else if (Name.endswith(".256")) { 1750 if (Size == 'd') // avx512.mask.psll.d.256, avx512.mask.psll.di.256 1751 IID = IsImmediate ? Intrinsic::x86_avx2_pslli_d 1752 : Intrinsic::x86_avx2_psll_d; 1753 else if (Size == 'q') // avx512.mask.psll.q.256, avx512.mask.psll.qi.256 1754 IID = IsImmediate ? Intrinsic::x86_avx2_pslli_q 1755 : Intrinsic::x86_avx2_psll_q; 1756 else if (Size == 'w') // avx512.mask.psll.w.256, avx512.mask.psll.wi.256 1757 IID = IsImmediate ? Intrinsic::x86_avx2_pslli_w 1758 : Intrinsic::x86_avx2_psll_w; 1759 else 1760 llvm_unreachable("Unexpected size"); 1761 } else { 1762 if (Size == 'd') // psll.di.512, pslli.d, psll.d, psllv.d.512 1763 IID = IsImmediate ? Intrinsic::x86_avx512_pslli_d_512 : 1764 IsVariable ? Intrinsic::x86_avx512_psllv_d_512 : 1765 Intrinsic::x86_avx512_psll_d_512; 1766 else if (Size == 'q') // psll.qi.512, pslli.q, psll.q, psllv.q.512 1767 IID = IsImmediate ? Intrinsic::x86_avx512_pslli_q_512 : 1768 IsVariable ? Intrinsic::x86_avx512_psllv_q_512 : 1769 Intrinsic::x86_avx512_psll_q_512; 1770 else if (Size == 'w') // psll.wi.512, pslli.w, psll.w 1771 IID = IsImmediate ? Intrinsic::x86_avx512_pslli_w_512 1772 : Intrinsic::x86_avx512_psll_w_512; 1773 else 1774 llvm_unreachable("Unexpected size"); 1775 } 1776 1777 Rep = UpgradeX86MaskedShift(Builder, *CI, IID); 1778 } else if (IsX86 && Name.startswith("avx512.mask.psrl")) { 1779 bool IsImmediate = Name[16] == 'i' || 1780 (Name.size() > 18 && Name[18] == 'i'); 1781 bool IsVariable = Name[16] == 'v'; 1782 char Size = Name[16] == '.' ? Name[17] : 1783 Name[17] == '.' ? Name[18] : 1784 Name[18] == '.' ? Name[19] : 1785 Name[20]; 1786 1787 Intrinsic::ID IID; 1788 if (IsVariable && Name[17] != '.') { 1789 if (Size == 'd' && Name[17] == '2') // avx512.mask.psrlv2.di 1790 IID = Intrinsic::x86_avx2_psrlv_q; 1791 else if (Size == 'd' && Name[17] == '4') // avx512.mask.psrlv4.di 1792 IID = Intrinsic::x86_avx2_psrlv_q_256; 1793 else if (Size == 's' && Name[17] == '4') // avx512.mask.psrlv4.si 1794 IID = Intrinsic::x86_avx2_psrlv_d; 1795 else if (Size == 's' && Name[17] == '8') // avx512.mask.psrlv8.si 1796 IID = Intrinsic::x86_avx2_psrlv_d_256; 1797 else if (Size == 'h' && Name[17] == '8') // avx512.mask.psrlv8.hi 1798 IID = Intrinsic::x86_avx512_psrlv_w_128; 1799 else if (Size == 'h' && Name[17] == '1') // avx512.mask.psrlv16.hi 1800 IID = Intrinsic::x86_avx512_psrlv_w_256; 1801 else if (Name[17] == '3' && Name[18] == '2') // avx512.mask.psrlv32hi 1802 IID = Intrinsic::x86_avx512_psrlv_w_512; 1803 else 1804 llvm_unreachable("Unexpected size"); 1805 } else if (Name.endswith(".128")) { 1806 if (Size == 'd') // avx512.mask.psrl.d.128, avx512.mask.psrl.di.128 1807 IID = IsImmediate ? Intrinsic::x86_sse2_psrli_d 1808 : Intrinsic::x86_sse2_psrl_d; 1809 else if (Size == 'q') // avx512.mask.psrl.q.128, avx512.mask.psrl.qi.128 1810 IID = IsImmediate ? Intrinsic::x86_sse2_psrli_q 1811 : Intrinsic::x86_sse2_psrl_q; 1812 else if (Size == 'w') // avx512.mask.psrl.w.128, avx512.mask.psrl.wi.128 1813 IID = IsImmediate ? Intrinsic::x86_sse2_psrli_w 1814 : Intrinsic::x86_sse2_psrl_w; 1815 else 1816 llvm_unreachable("Unexpected size"); 1817 } else if (Name.endswith(".256")) { 1818 if (Size == 'd') // avx512.mask.psrl.d.256, avx512.mask.psrl.di.256 1819 IID = IsImmediate ? Intrinsic::x86_avx2_psrli_d 1820 : Intrinsic::x86_avx2_psrl_d; 1821 else if (Size == 'q') // avx512.mask.psrl.q.256, avx512.mask.psrl.qi.256 1822 IID = IsImmediate ? Intrinsic::x86_avx2_psrli_q 1823 : Intrinsic::x86_avx2_psrl_q; 1824 else if (Size == 'w') // avx512.mask.psrl.w.256, avx512.mask.psrl.wi.256 1825 IID = IsImmediate ? Intrinsic::x86_avx2_psrli_w 1826 : Intrinsic::x86_avx2_psrl_w; 1827 else 1828 llvm_unreachable("Unexpected size"); 1829 } else { 1830 if (Size == 'd') // psrl.di.512, psrli.d, psrl.d, psrl.d.512 1831 IID = IsImmediate ? Intrinsic::x86_avx512_psrli_d_512 : 1832 IsVariable ? Intrinsic::x86_avx512_psrlv_d_512 : 1833 Intrinsic::x86_avx512_psrl_d_512; 1834 else if (Size == 'q') // psrl.qi.512, psrli.q, psrl.q, psrl.q.512 1835 IID = IsImmediate ? Intrinsic::x86_avx512_psrli_q_512 : 1836 IsVariable ? Intrinsic::x86_avx512_psrlv_q_512 : 1837 Intrinsic::x86_avx512_psrl_q_512; 1838 else if (Size == 'w') // psrl.wi.512, psrli.w, psrl.w) 1839 IID = IsImmediate ? Intrinsic::x86_avx512_psrli_w_512 1840 : Intrinsic::x86_avx512_psrl_w_512; 1841 else 1842 llvm_unreachable("Unexpected size"); 1843 } 1844 1845 Rep = UpgradeX86MaskedShift(Builder, *CI, IID); 1846 } else if (IsX86 && Name.startswith("avx512.mask.psra")) { 1847 bool IsImmediate = Name[16] == 'i' || 1848 (Name.size() > 18 && Name[18] == 'i'); 1849 bool IsVariable = Name[16] == 'v'; 1850 char Size = Name[16] == '.' ? Name[17] : 1851 Name[17] == '.' ? Name[18] : 1852 Name[18] == '.' ? Name[19] : 1853 Name[20]; 1854 1855 Intrinsic::ID IID; 1856 if (IsVariable && Name[17] != '.') { 1857 if (Size == 's' && Name[17] == '4') // avx512.mask.psrav4.si 1858 IID = Intrinsic::x86_avx2_psrav_d; 1859 else if (Size == 's' && Name[17] == '8') // avx512.mask.psrav8.si 1860 IID = Intrinsic::x86_avx2_psrav_d_256; 1861 else if (Size == 'h' && Name[17] == '8') // avx512.mask.psrav8.hi 1862 IID = Intrinsic::x86_avx512_psrav_w_128; 1863 else if (Size == 'h' && Name[17] == '1') // avx512.mask.psrav16.hi 1864 IID = Intrinsic::x86_avx512_psrav_w_256; 1865 else if (Name[17] == '3' && Name[18] == '2') // avx512.mask.psrav32hi 1866 IID = Intrinsic::x86_avx512_psrav_w_512; 1867 else 1868 llvm_unreachable("Unexpected size"); 1869 } else if (Name.endswith(".128")) { 1870 if (Size == 'd') // avx512.mask.psra.d.128, avx512.mask.psra.di.128 1871 IID = IsImmediate ? Intrinsic::x86_sse2_psrai_d 1872 : Intrinsic::x86_sse2_psra_d; 1873 else if (Size == 'q') // avx512.mask.psra.q.128, avx512.mask.psra.qi.128 1874 IID = IsImmediate ? Intrinsic::x86_avx512_psrai_q_128 : 1875 IsVariable ? Intrinsic::x86_avx512_psrav_q_128 : 1876 Intrinsic::x86_avx512_psra_q_128; 1877 else if (Size == 'w') // avx512.mask.psra.w.128, avx512.mask.psra.wi.128 1878 IID = IsImmediate ? Intrinsic::x86_sse2_psrai_w 1879 : Intrinsic::x86_sse2_psra_w; 1880 else 1881 llvm_unreachable("Unexpected size"); 1882 } else if (Name.endswith(".256")) { 1883 if (Size == 'd') // avx512.mask.psra.d.256, avx512.mask.psra.di.256 1884 IID = IsImmediate ? Intrinsic::x86_avx2_psrai_d 1885 : Intrinsic::x86_avx2_psra_d; 1886 else if (Size == 'q') // avx512.mask.psra.q.256, avx512.mask.psra.qi.256 1887 IID = IsImmediate ? Intrinsic::x86_avx512_psrai_q_256 : 1888 IsVariable ? Intrinsic::x86_avx512_psrav_q_256 : 1889 Intrinsic::x86_avx512_psra_q_256; 1890 else if (Size == 'w') // avx512.mask.psra.w.256, avx512.mask.psra.wi.256 1891 IID = IsImmediate ? Intrinsic::x86_avx2_psrai_w 1892 : Intrinsic::x86_avx2_psra_w; 1893 else 1894 llvm_unreachable("Unexpected size"); 1895 } else { 1896 if (Size == 'd') // psra.di.512, psrai.d, psra.d, psrav.d.512 1897 IID = IsImmediate ? Intrinsic::x86_avx512_psrai_d_512 : 1898 IsVariable ? Intrinsic::x86_avx512_psrav_d_512 : 1899 Intrinsic::x86_avx512_psra_d_512; 1900 else if (Size == 'q') // psra.qi.512, psrai.q, psra.q 1901 IID = IsImmediate ? Intrinsic::x86_avx512_psrai_q_512 : 1902 IsVariable ? Intrinsic::x86_avx512_psrav_q_512 : 1903 Intrinsic::x86_avx512_psra_q_512; 1904 else if (Size == 'w') // psra.wi.512, psrai.w, psra.w 1905 IID = IsImmediate ? Intrinsic::x86_avx512_psrai_w_512 1906 : Intrinsic::x86_avx512_psra_w_512; 1907 else 1908 llvm_unreachable("Unexpected size"); 1909 } 1910 1911 Rep = UpgradeX86MaskedShift(Builder, *CI, IID); 1912 } else if (IsX86 && Name.startswith("avx512.mask.move.s")) { 1913 Rep = upgradeMaskedMove(Builder, *CI); 1914 } else if (IsX86 && Name.startswith("avx512.cvtmask2")) { 1915 Rep = UpgradeMaskToInt(Builder, *CI); 1916 } else if (IsX86 && Name.startswith("avx512.mask.vpermilvar.")) { 1917 Intrinsic::ID IID; 1918 if (Name.endswith("ps.128")) 1919 IID = Intrinsic::x86_avx_vpermilvar_ps; 1920 else if (Name.endswith("pd.128")) 1921 IID = Intrinsic::x86_avx_vpermilvar_pd; 1922 else if (Name.endswith("ps.256")) 1923 IID = Intrinsic::x86_avx_vpermilvar_ps_256; 1924 else if (Name.endswith("pd.256")) 1925 IID = Intrinsic::x86_avx_vpermilvar_pd_256; 1926 else if (Name.endswith("ps.512")) 1927 IID = Intrinsic::x86_avx512_vpermilvar_ps_512; 1928 else if (Name.endswith("pd.512")) 1929 IID = Intrinsic::x86_avx512_vpermilvar_pd_512; 1930 else 1931 llvm_unreachable("Unexpected vpermilvar intrinsic"); 1932 1933 Function *Intrin = Intrinsic::getDeclaration(F->getParent(), IID); 1934 Rep = Builder.CreateCall(Intrin, 1935 { CI->getArgOperand(0), CI->getArgOperand(1) }); 1936 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1937 CI->getArgOperand(2)); 1938 } else if (IsX86 && Name.endswith(".movntdqa")) { 1939 Module *M = F->getParent(); 1940 MDNode *Node = MDNode::get( 1941 C, ConstantAsMetadata::get(ConstantInt::get(Type::getInt32Ty(C), 1))); 1942 1943 Value *Ptr = CI->getArgOperand(0); 1944 VectorType *VTy = cast<VectorType>(CI->getType()); 1945 1946 // Convert the type of the pointer to a pointer to the stored type. 1947 Value *BC = 1948 Builder.CreateBitCast(Ptr, PointerType::getUnqual(VTy), "cast"); 1949 LoadInst *LI = Builder.CreateAlignedLoad(BC, VTy->getBitWidth() / 8); 1950 LI->setMetadata(M->getMDKindID("nontemporal"), Node); 1951 Rep = LI; 1952 } else if (IsNVVM && (Name == "abs.i" || Name == "abs.ll")) { 1953 Value *Arg = CI->getArgOperand(0); 1954 Value *Neg = Builder.CreateNeg(Arg, "neg"); 1955 Value *Cmp = Builder.CreateICmpSGE( 1956 Arg, llvm::Constant::getNullValue(Arg->getType()), "abs.cond"); 1957 Rep = Builder.CreateSelect(Cmp, Arg, Neg, "abs"); 1958 } else if (IsNVVM && (Name == "max.i" || Name == "max.ll" || 1959 Name == "max.ui" || Name == "max.ull")) { 1960 Value *Arg0 = CI->getArgOperand(0); 1961 Value *Arg1 = CI->getArgOperand(1); 1962 Value *Cmp = Name.endswith(".ui") || Name.endswith(".ull") 1963 ? Builder.CreateICmpUGE(Arg0, Arg1, "max.cond") 1964 : Builder.CreateICmpSGE(Arg0, Arg1, "max.cond"); 1965 Rep = Builder.CreateSelect(Cmp, Arg0, Arg1, "max"); 1966 } else if (IsNVVM && (Name == "min.i" || Name == "min.ll" || 1967 Name == "min.ui" || Name == "min.ull")) { 1968 Value *Arg0 = CI->getArgOperand(0); 1969 Value *Arg1 = CI->getArgOperand(1); 1970 Value *Cmp = Name.endswith(".ui") || Name.endswith(".ull") 1971 ? Builder.CreateICmpULE(Arg0, Arg1, "min.cond") 1972 : Builder.CreateICmpSLE(Arg0, Arg1, "min.cond"); 1973 Rep = Builder.CreateSelect(Cmp, Arg0, Arg1, "min"); 1974 } else if (IsNVVM && Name == "clz.ll") { 1975 // llvm.nvvm.clz.ll returns an i32, but llvm.ctlz.i64 and returns an i64. 1976 Value *Arg = CI->getArgOperand(0); 1977 Value *Ctlz = Builder.CreateCall( 1978 Intrinsic::getDeclaration(F->getParent(), Intrinsic::ctlz, 1979 {Arg->getType()}), 1980 {Arg, Builder.getFalse()}, "ctlz"); 1981 Rep = Builder.CreateTrunc(Ctlz, Builder.getInt32Ty(), "ctlz.trunc"); 1982 } else if (IsNVVM && Name == "popc.ll") { 1983 // llvm.nvvm.popc.ll returns an i32, but llvm.ctpop.i64 and returns an 1984 // i64. 1985 Value *Arg = CI->getArgOperand(0); 1986 Value *Popc = Builder.CreateCall( 1987 Intrinsic::getDeclaration(F->getParent(), Intrinsic::ctpop, 1988 {Arg->getType()}), 1989 Arg, "ctpop"); 1990 Rep = Builder.CreateTrunc(Popc, Builder.getInt32Ty(), "ctpop.trunc"); 1991 } else if (IsNVVM && Name == "h2f") { 1992 Rep = Builder.CreateCall(Intrinsic::getDeclaration( 1993 F->getParent(), Intrinsic::convert_from_fp16, 1994 {Builder.getFloatTy()}), 1995 CI->getArgOperand(0), "h2f"); 1996 } else { 1997 llvm_unreachable("Unknown function for CallInst upgrade."); 1998 } 1999 2000 if (Rep) 2001 CI->replaceAllUsesWith(Rep); 2002 CI->eraseFromParent(); 2003 return; 2004 } 2005 2006 CallInst *NewCall = nullptr; 2007 switch (NewFn->getIntrinsicID()) { 2008 default: { 2009 // Handle generic mangling change, but nothing else 2010 assert( 2011 (CI->getCalledFunction()->getName() != NewFn->getName()) && 2012 "Unknown function for CallInst upgrade and isn't just a name change"); 2013 CI->setCalledFunction(NewFn); 2014 return; 2015 } 2016 2017 case Intrinsic::arm_neon_vld1: 2018 case Intrinsic::arm_neon_vld2: 2019 case Intrinsic::arm_neon_vld3: 2020 case Intrinsic::arm_neon_vld4: 2021 case Intrinsic::arm_neon_vld2lane: 2022 case Intrinsic::arm_neon_vld3lane: 2023 case Intrinsic::arm_neon_vld4lane: 2024 case Intrinsic::arm_neon_vst1: 2025 case Intrinsic::arm_neon_vst2: 2026 case Intrinsic::arm_neon_vst3: 2027 case Intrinsic::arm_neon_vst4: 2028 case Intrinsic::arm_neon_vst2lane: 2029 case Intrinsic::arm_neon_vst3lane: 2030 case Intrinsic::arm_neon_vst4lane: { 2031 SmallVector<Value *, 4> Args(CI->arg_operands().begin(), 2032 CI->arg_operands().end()); 2033 NewCall = Builder.CreateCall(NewFn, Args); 2034 break; 2035 } 2036 2037 case Intrinsic::bitreverse: 2038 NewCall = Builder.CreateCall(NewFn, {CI->getArgOperand(0)}); 2039 break; 2040 2041 case Intrinsic::ctlz: 2042 case Intrinsic::cttz: 2043 assert(CI->getNumArgOperands() == 1 && 2044 "Mismatch between function args and call args"); 2045 NewCall = 2046 Builder.CreateCall(NewFn, {CI->getArgOperand(0), Builder.getFalse()}); 2047 break; 2048 2049 case Intrinsic::objectsize: { 2050 Value *NullIsUnknownSize = CI->getNumArgOperands() == 2 2051 ? Builder.getFalse() 2052 : CI->getArgOperand(2); 2053 NewCall = Builder.CreateCall( 2054 NewFn, {CI->getArgOperand(0), CI->getArgOperand(1), NullIsUnknownSize}); 2055 break; 2056 } 2057 2058 case Intrinsic::ctpop: 2059 NewCall = Builder.CreateCall(NewFn, {CI->getArgOperand(0)}); 2060 break; 2061 2062 case Intrinsic::convert_from_fp16: 2063 NewCall = Builder.CreateCall(NewFn, {CI->getArgOperand(0)}); 2064 break; 2065 2066 case Intrinsic::dbg_value: 2067 // Upgrade from the old version that had an extra offset argument. 2068 assert(CI->getNumArgOperands() == 4); 2069 // Drop nonzero offsets instead of attempting to upgrade them. 2070 if (auto *Offset = dyn_cast_or_null<Constant>(CI->getArgOperand(1))) 2071 if (Offset->isZeroValue()) { 2072 NewCall = Builder.CreateCall( 2073 NewFn, 2074 {CI->getArgOperand(0), CI->getArgOperand(2), CI->getArgOperand(3)}); 2075 break; 2076 } 2077 CI->eraseFromParent(); 2078 return; 2079 2080 case Intrinsic::x86_xop_vfrcz_ss: 2081 case Intrinsic::x86_xop_vfrcz_sd: 2082 NewCall = Builder.CreateCall(NewFn, {CI->getArgOperand(1)}); 2083 break; 2084 2085 case Intrinsic::x86_xop_vpermil2pd: 2086 case Intrinsic::x86_xop_vpermil2ps: 2087 case Intrinsic::x86_xop_vpermil2pd_256: 2088 case Intrinsic::x86_xop_vpermil2ps_256: { 2089 SmallVector<Value *, 4> Args(CI->arg_operands().begin(), 2090 CI->arg_operands().end()); 2091 VectorType *FltIdxTy = cast<VectorType>(Args[2]->getType()); 2092 VectorType *IntIdxTy = VectorType::getInteger(FltIdxTy); 2093 Args[2] = Builder.CreateBitCast(Args[2], IntIdxTy); 2094 NewCall = Builder.CreateCall(NewFn, Args); 2095 break; 2096 } 2097 2098 case Intrinsic::x86_sse41_ptestc: 2099 case Intrinsic::x86_sse41_ptestz: 2100 case Intrinsic::x86_sse41_ptestnzc: { 2101 // The arguments for these intrinsics used to be v4f32, and changed 2102 // to v2i64. This is purely a nop, since those are bitwise intrinsics. 2103 // So, the only thing required is a bitcast for both arguments. 2104 // First, check the arguments have the old type. 2105 Value *Arg0 = CI->getArgOperand(0); 2106 if (Arg0->getType() != VectorType::get(Type::getFloatTy(C), 4)) 2107 return; 2108 2109 // Old intrinsic, add bitcasts 2110 Value *Arg1 = CI->getArgOperand(1); 2111 2112 Type *NewVecTy = VectorType::get(Type::getInt64Ty(C), 2); 2113 2114 Value *BC0 = Builder.CreateBitCast(Arg0, NewVecTy, "cast"); 2115 Value *BC1 = Builder.CreateBitCast(Arg1, NewVecTy, "cast"); 2116 2117 NewCall = Builder.CreateCall(NewFn, {BC0, BC1}); 2118 break; 2119 } 2120 2121 case Intrinsic::x86_sse41_insertps: 2122 case Intrinsic::x86_sse41_dppd: 2123 case Intrinsic::x86_sse41_dpps: 2124 case Intrinsic::x86_sse41_mpsadbw: 2125 case Intrinsic::x86_avx_dp_ps_256: 2126 case Intrinsic::x86_avx2_mpsadbw: { 2127 // Need to truncate the last argument from i32 to i8 -- this argument models 2128 // an inherently 8-bit immediate operand to these x86 instructions. 2129 SmallVector<Value *, 4> Args(CI->arg_operands().begin(), 2130 CI->arg_operands().end()); 2131 2132 // Replace the last argument with a trunc. 2133 Args.back() = Builder.CreateTrunc(Args.back(), Type::getInt8Ty(C), "trunc"); 2134 NewCall = Builder.CreateCall(NewFn, Args); 2135 break; 2136 } 2137 2138 case Intrinsic::thread_pointer: { 2139 NewCall = Builder.CreateCall(NewFn, {}); 2140 break; 2141 } 2142 2143 case Intrinsic::invariant_start: 2144 case Intrinsic::invariant_end: 2145 case Intrinsic::masked_load: 2146 case Intrinsic::masked_store: 2147 case Intrinsic::masked_gather: 2148 case Intrinsic::masked_scatter: { 2149 SmallVector<Value *, 4> Args(CI->arg_operands().begin(), 2150 CI->arg_operands().end()); 2151 NewCall = Builder.CreateCall(NewFn, Args); 2152 break; 2153 } 2154 } 2155 assert(NewCall && "Should have either set this variable or returned through " 2156 "the default case"); 2157 std::string Name = CI->getName(); 2158 if (!Name.empty()) { 2159 CI->setName(Name + ".old"); 2160 NewCall->setName(Name); 2161 } 2162 CI->replaceAllUsesWith(NewCall); 2163 CI->eraseFromParent(); 2164 } 2165 2166 void llvm::UpgradeCallsToIntrinsic(Function *F) { 2167 assert(F && "Illegal attempt to upgrade a non-existent intrinsic."); 2168 2169 // Check if this function should be upgraded and get the replacement function 2170 // if there is one. 2171 Function *NewFn; 2172 if (UpgradeIntrinsicFunction(F, NewFn)) { 2173 // Replace all users of the old function with the new function or new 2174 // instructions. This is not a range loop because the call is deleted. 2175 for (auto UI = F->user_begin(), UE = F->user_end(); UI != UE; ) 2176 if (CallInst *CI = dyn_cast<CallInst>(*UI++)) 2177 UpgradeIntrinsicCall(CI, NewFn); 2178 2179 // Remove old function, no longer used, from the module. 2180 F->eraseFromParent(); 2181 } 2182 } 2183 2184 MDNode *llvm::UpgradeTBAANode(MDNode &MD) { 2185 // Check if the tag uses struct-path aware TBAA format. 2186 if (isa<MDNode>(MD.getOperand(0)) && MD.getNumOperands() >= 3) 2187 return &MD; 2188 2189 auto &Context = MD.getContext(); 2190 if (MD.getNumOperands() == 3) { 2191 Metadata *Elts[] = {MD.getOperand(0), MD.getOperand(1)}; 2192 MDNode *ScalarType = MDNode::get(Context, Elts); 2193 // Create a MDNode <ScalarType, ScalarType, offset 0, const> 2194 Metadata *Elts2[] = {ScalarType, ScalarType, 2195 ConstantAsMetadata::get( 2196 Constant::getNullValue(Type::getInt64Ty(Context))), 2197 MD.getOperand(2)}; 2198 return MDNode::get(Context, Elts2); 2199 } 2200 // Create a MDNode <MD, MD, offset 0> 2201 Metadata *Elts[] = {&MD, &MD, ConstantAsMetadata::get(Constant::getNullValue( 2202 Type::getInt64Ty(Context)))}; 2203 return MDNode::get(Context, Elts); 2204 } 2205 2206 Instruction *llvm::UpgradeBitCastInst(unsigned Opc, Value *V, Type *DestTy, 2207 Instruction *&Temp) { 2208 if (Opc != Instruction::BitCast) 2209 return nullptr; 2210 2211 Temp = nullptr; 2212 Type *SrcTy = V->getType(); 2213 if (SrcTy->isPtrOrPtrVectorTy() && DestTy->isPtrOrPtrVectorTy() && 2214 SrcTy->getPointerAddressSpace() != DestTy->getPointerAddressSpace()) { 2215 LLVMContext &Context = V->getContext(); 2216 2217 // We have no information about target data layout, so we assume that 2218 // the maximum pointer size is 64bit. 2219 Type *MidTy = Type::getInt64Ty(Context); 2220 Temp = CastInst::Create(Instruction::PtrToInt, V, MidTy); 2221 2222 return CastInst::Create(Instruction::IntToPtr, Temp, DestTy); 2223 } 2224 2225 return nullptr; 2226 } 2227 2228 Value *llvm::UpgradeBitCastExpr(unsigned Opc, Constant *C, Type *DestTy) { 2229 if (Opc != Instruction::BitCast) 2230 return nullptr; 2231 2232 Type *SrcTy = C->getType(); 2233 if (SrcTy->isPtrOrPtrVectorTy() && DestTy->isPtrOrPtrVectorTy() && 2234 SrcTy->getPointerAddressSpace() != DestTy->getPointerAddressSpace()) { 2235 LLVMContext &Context = C->getContext(); 2236 2237 // We have no information about target data layout, so we assume that 2238 // the maximum pointer size is 64bit. 2239 Type *MidTy = Type::getInt64Ty(Context); 2240 2241 return ConstantExpr::getIntToPtr(ConstantExpr::getPtrToInt(C, MidTy), 2242 DestTy); 2243 } 2244 2245 return nullptr; 2246 } 2247 2248 /// Check the debug info version number, if it is out-dated, drop the debug 2249 /// info. Return true if module is modified. 2250 bool llvm::UpgradeDebugInfo(Module &M) { 2251 unsigned Version = getDebugMetadataVersionFromModule(M); 2252 if (Version == DEBUG_METADATA_VERSION) 2253 return false; 2254 2255 bool RetCode = StripDebugInfo(M); 2256 if (RetCode) { 2257 DiagnosticInfoDebugMetadataVersion DiagVersion(M, Version); 2258 M.getContext().diagnose(DiagVersion); 2259 } 2260 return RetCode; 2261 } 2262 2263 bool llvm::UpgradeModuleFlags(Module &M) { 2264 const NamedMDNode *ModFlags = M.getModuleFlagsMetadata(); 2265 if (!ModFlags) 2266 return false; 2267 2268 bool HasObjCFlag = false, HasClassProperties = false; 2269 for (unsigned I = 0, E = ModFlags->getNumOperands(); I != E; ++I) { 2270 MDNode *Op = ModFlags->getOperand(I); 2271 if (Op->getNumOperands() < 2) 2272 continue; 2273 MDString *ID = dyn_cast_or_null<MDString>(Op->getOperand(1)); 2274 if (!ID) 2275 continue; 2276 if (ID->getString() == "Objective-C Image Info Version") 2277 HasObjCFlag = true; 2278 if (ID->getString() == "Objective-C Class Properties") 2279 HasClassProperties = true; 2280 } 2281 // "Objective-C Class Properties" is recently added for Objective-C. We 2282 // upgrade ObjC bitcodes to contain a "Objective-C Class Properties" module 2283 // flag of value 0, so we can correclty downgrade this flag when trying to 2284 // link an ObjC bitcode without this module flag with an ObjC bitcode with 2285 // this module flag. 2286 if (HasObjCFlag && !HasClassProperties) { 2287 M.addModuleFlag(llvm::Module::Override, "Objective-C Class Properties", 2288 (uint32_t)0); 2289 return true; 2290 } 2291 return false; 2292 } 2293 2294 static bool isOldLoopArgument(Metadata *MD) { 2295 auto *T = dyn_cast_or_null<MDTuple>(MD); 2296 if (!T) 2297 return false; 2298 if (T->getNumOperands() < 1) 2299 return false; 2300 auto *S = dyn_cast_or_null<MDString>(T->getOperand(0)); 2301 if (!S) 2302 return false; 2303 return S->getString().startswith("llvm.vectorizer."); 2304 } 2305 2306 static MDString *upgradeLoopTag(LLVMContext &C, StringRef OldTag) { 2307 StringRef OldPrefix = "llvm.vectorizer."; 2308 assert(OldTag.startswith(OldPrefix) && "Expected old prefix"); 2309 2310 if (OldTag == "llvm.vectorizer.unroll") 2311 return MDString::get(C, "llvm.loop.interleave.count"); 2312 2313 return MDString::get( 2314 C, (Twine("llvm.loop.vectorize.") + OldTag.drop_front(OldPrefix.size())) 2315 .str()); 2316 } 2317 2318 static Metadata *upgradeLoopArgument(Metadata *MD) { 2319 auto *T = dyn_cast_or_null<MDTuple>(MD); 2320 if (!T) 2321 return MD; 2322 if (T->getNumOperands() < 1) 2323 return MD; 2324 auto *OldTag = dyn_cast_or_null<MDString>(T->getOperand(0)); 2325 if (!OldTag) 2326 return MD; 2327 if (!OldTag->getString().startswith("llvm.vectorizer.")) 2328 return MD; 2329 2330 // This has an old tag. Upgrade it. 2331 SmallVector<Metadata *, 8> Ops; 2332 Ops.reserve(T->getNumOperands()); 2333 Ops.push_back(upgradeLoopTag(T->getContext(), OldTag->getString())); 2334 for (unsigned I = 1, E = T->getNumOperands(); I != E; ++I) 2335 Ops.push_back(T->getOperand(I)); 2336 2337 return MDTuple::get(T->getContext(), Ops); 2338 } 2339 2340 MDNode *llvm::upgradeInstructionLoopAttachment(MDNode &N) { 2341 auto *T = dyn_cast<MDTuple>(&N); 2342 if (!T) 2343 return &N; 2344 2345 if (none_of(T->operands(), isOldLoopArgument)) 2346 return &N; 2347 2348 SmallVector<Metadata *, 8> Ops; 2349 Ops.reserve(T->getNumOperands()); 2350 for (Metadata *MD : T->operands()) 2351 Ops.push_back(upgradeLoopArgument(MD)); 2352 2353 return MDTuple::get(T->getContext(), Ops); 2354 } 2355