1 //===-- AutoUpgrade.cpp - Implement auto-upgrade helper functions ---------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements the auto-upgrade helper functions. 11 // This is where deprecated IR intrinsics and other IR features are updated to 12 // current specifications. 13 // 14 //===----------------------------------------------------------------------===// 15 16 #include "llvm/IR/AutoUpgrade.h" 17 #include "llvm/ADT/StringSwitch.h" 18 #include "llvm/IR/Constants.h" 19 #include "llvm/IR/DIBuilder.h" 20 #include "llvm/IR/DebugInfo.h" 21 #include "llvm/IR/DiagnosticInfo.h" 22 #include "llvm/IR/Function.h" 23 #include "llvm/IR/IRBuilder.h" 24 #include "llvm/IR/Instruction.h" 25 #include "llvm/IR/IntrinsicInst.h" 26 #include "llvm/IR/LLVMContext.h" 27 #include "llvm/IR/Module.h" 28 #include "llvm/IR/Verifier.h" 29 #include "llvm/Support/ErrorHandling.h" 30 #include "llvm/Support/Regex.h" 31 #include <cstring> 32 using namespace llvm; 33 34 static void rename(GlobalValue *GV) { GV->setName(GV->getName() + ".old"); } 35 36 // Upgrade the declarations of the SSE4.1 ptest intrinsics whose arguments have 37 // changed their type from v4f32 to v2i64. 38 static bool UpgradePTESTIntrinsic(Function* F, Intrinsic::ID IID, 39 Function *&NewFn) { 40 // Check whether this is an old version of the function, which received 41 // v4f32 arguments. 42 Type *Arg0Type = F->getFunctionType()->getParamType(0); 43 if (Arg0Type != VectorType::get(Type::getFloatTy(F->getContext()), 4)) 44 return false; 45 46 // Yes, it's old, replace it with new version. 47 rename(F); 48 NewFn = Intrinsic::getDeclaration(F->getParent(), IID); 49 return true; 50 } 51 52 // Upgrade the declarations of intrinsic functions whose 8-bit immediate mask 53 // arguments have changed their type from i32 to i8. 54 static bool UpgradeX86IntrinsicsWith8BitMask(Function *F, Intrinsic::ID IID, 55 Function *&NewFn) { 56 // Check that the last argument is an i32. 57 Type *LastArgType = F->getFunctionType()->getParamType( 58 F->getFunctionType()->getNumParams() - 1); 59 if (!LastArgType->isIntegerTy(32)) 60 return false; 61 62 // Move this function aside and map down. 63 rename(F); 64 NewFn = Intrinsic::getDeclaration(F->getParent(), IID); 65 return true; 66 } 67 68 // Upgrade the declaration of fp compare intrinsics that change return type 69 // from scalar to vXi1 mask. 70 static bool UpgradeX86MaskedFPCompare(Function *F, Intrinsic::ID IID, 71 Function *&NewFn) { 72 // Check if the return type is a vector. 73 if (F->getReturnType()->isVectorTy()) 74 return false; 75 76 rename(F); 77 NewFn = Intrinsic::getDeclaration(F->getParent(), IID); 78 return true; 79 } 80 81 static bool ShouldUpgradeX86Intrinsic(Function *F, StringRef Name) { 82 // All of the intrinsics matches below should be marked with which llvm 83 // version started autoupgrading them. At some point in the future we would 84 // like to use this information to remove upgrade code for some older 85 // intrinsics. It is currently undecided how we will determine that future 86 // point. 87 if (Name.startswith("sse2.padds") || // Added in 7.0 88 Name.startswith("sse2.paddus") || // Added in 7.0 89 Name.startswith("sse2.psubs") || // Added in 7.0 90 Name.startswith("sse2.psubus") || // Added in 7.0 91 Name.startswith("avx2.padds") || // Added in 7.0 92 Name.startswith("avx2.paddus") || // Added in 7.0 93 Name.startswith("avx2.psubs") || // Added in 7.0 94 Name.startswith("avx2.psubus") || // Added in 7.0 95 Name.startswith("avx512.mask.padds") || // Added in 7.0 96 Name.startswith("avx512.mask.paddus") || // Added in 7.0 97 Name.startswith("avx512.mask.psubs") || // Added in 7.0 98 Name.startswith("avx512.mask.psubus") || // Added in 7.0 99 Name=="ssse3.pabs.b.128" || // Added in 6.0 100 Name=="ssse3.pabs.w.128" || // Added in 6.0 101 Name=="ssse3.pabs.d.128" || // Added in 6.0 102 Name.startswith("avx512.mask.shuf.i") || // Added in 6.0 103 Name.startswith("avx512.mask.shuf.f") || // Added in 6.0 104 Name.startswith("avx512.kunpck") || //added in 6.0 105 Name.startswith("avx2.pabs.") || // Added in 6.0 106 Name.startswith("avx512.mask.pabs.") || // Added in 6.0 107 Name.startswith("avx512.broadcastm") || // Added in 6.0 108 Name.startswith("avx512.mask.pbroadcast") || // Added in 6.0 109 Name.startswith("sse2.pcmpeq.") || // Added in 3.1 110 Name.startswith("sse2.pcmpgt.") || // Added in 3.1 111 Name.startswith("avx2.pcmpeq.") || // Added in 3.1 112 Name.startswith("avx2.pcmpgt.") || // Added in 3.1 113 Name.startswith("avx512.mask.pcmpeq.") || // Added in 3.9 114 Name.startswith("avx512.mask.pcmpgt.") || // Added in 3.9 115 Name.startswith("avx.vperm2f128.") || // Added in 6.0 116 Name == "avx2.vperm2i128" || // Added in 6.0 117 Name == "sse.add.ss" || // Added in 4.0 118 Name == "sse2.add.sd" || // Added in 4.0 119 Name == "sse.sub.ss" || // Added in 4.0 120 Name == "sse2.sub.sd" || // Added in 4.0 121 Name == "sse.mul.ss" || // Added in 4.0 122 Name == "sse2.mul.sd" || // Added in 4.0 123 Name == "sse.div.ss" || // Added in 4.0 124 Name == "sse2.div.sd" || // Added in 4.0 125 Name == "sse41.pmaxsb" || // Added in 3.9 126 Name == "sse2.pmaxs.w" || // Added in 3.9 127 Name == "sse41.pmaxsd" || // Added in 3.9 128 Name == "sse2.pmaxu.b" || // Added in 3.9 129 Name == "sse41.pmaxuw" || // Added in 3.9 130 Name == "sse41.pmaxud" || // Added in 3.9 131 Name == "sse41.pminsb" || // Added in 3.9 132 Name == "sse2.pmins.w" || // Added in 3.9 133 Name == "sse41.pminsd" || // Added in 3.9 134 Name == "sse2.pminu.b" || // Added in 3.9 135 Name == "sse41.pminuw" || // Added in 3.9 136 Name == "sse41.pminud" || // Added in 3.9 137 Name == "avx512.kand.w" || // Added in 7.0 138 Name == "avx512.kandn.w" || // Added in 7.0 139 Name == "avx512.knot.w" || // Added in 7.0 140 Name == "avx512.kor.w" || // Added in 7.0 141 Name == "avx512.kxor.w" || // Added in 7.0 142 Name == "avx512.kxnor.w" || // Added in 7.0 143 Name == "avx512.kortestc.w" || // Added in 7.0 144 Name == "avx512.kortestz.w" || // Added in 7.0 145 Name.startswith("avx512.mask.pshuf.b.") || // Added in 4.0 146 Name.startswith("avx2.pmax") || // Added in 3.9 147 Name.startswith("avx2.pmin") || // Added in 3.9 148 Name.startswith("avx512.mask.pmax") || // Added in 4.0 149 Name.startswith("avx512.mask.pmin") || // Added in 4.0 150 Name.startswith("avx2.vbroadcast") || // Added in 3.8 151 Name.startswith("avx2.pbroadcast") || // Added in 3.8 152 Name.startswith("avx.vpermil.") || // Added in 3.1 153 Name.startswith("sse2.pshuf") || // Added in 3.9 154 Name.startswith("avx512.pbroadcast") || // Added in 3.9 155 Name.startswith("avx512.mask.broadcast.s") || // Added in 3.9 156 Name.startswith("avx512.mask.movddup") || // Added in 3.9 157 Name.startswith("avx512.mask.movshdup") || // Added in 3.9 158 Name.startswith("avx512.mask.movsldup") || // Added in 3.9 159 Name.startswith("avx512.mask.pshuf.d.") || // Added in 3.9 160 Name.startswith("avx512.mask.pshufl.w.") || // Added in 3.9 161 Name.startswith("avx512.mask.pshufh.w.") || // Added in 3.9 162 Name.startswith("avx512.mask.shuf.p") || // Added in 4.0 163 Name.startswith("avx512.mask.vpermil.p") || // Added in 3.9 164 Name.startswith("avx512.mask.perm.df.") || // Added in 3.9 165 Name.startswith("avx512.mask.perm.di.") || // Added in 3.9 166 Name.startswith("avx512.mask.punpckl") || // Added in 3.9 167 Name.startswith("avx512.mask.punpckh") || // Added in 3.9 168 Name.startswith("avx512.mask.unpckl.") || // Added in 3.9 169 Name.startswith("avx512.mask.unpckh.") || // Added in 3.9 170 Name.startswith("avx512.mask.pand.") || // Added in 3.9 171 Name.startswith("avx512.mask.pandn.") || // Added in 3.9 172 Name.startswith("avx512.mask.por.") || // Added in 3.9 173 Name.startswith("avx512.mask.pxor.") || // Added in 3.9 174 Name.startswith("avx512.mask.and.") || // Added in 3.9 175 Name.startswith("avx512.mask.andn.") || // Added in 3.9 176 Name.startswith("avx512.mask.or.") || // Added in 3.9 177 Name.startswith("avx512.mask.xor.") || // Added in 3.9 178 Name.startswith("avx512.mask.padd.") || // Added in 4.0 179 Name.startswith("avx512.mask.psub.") || // Added in 4.0 180 Name.startswith("avx512.mask.pmull.") || // Added in 4.0 181 Name.startswith("avx512.mask.cvtdq2pd.") || // Added in 4.0 182 Name.startswith("avx512.mask.cvtudq2pd.") || // Added in 4.0 183 Name == "sse2.pmulu.dq" || // Added in 7.0 184 Name == "sse41.pmuldq" || // Added in 7.0 185 Name == "avx2.pmulu.dq" || // Added in 7.0 186 Name == "avx2.pmul.dq" || // Added in 7.0 187 Name == "avx512.pmulu.dq.512" || // Added in 7.0 188 Name == "avx512.pmul.dq.512" || // Added in 7.0 189 Name.startswith("avx512.mask.pmul.dq.") || // Added in 4.0 190 Name.startswith("avx512.mask.pmulu.dq.") || // Added in 4.0 191 Name.startswith("avx512.mask.pmul.hr.sw.") || // Added in 7.0 192 Name.startswith("avx512.mask.pmulh.w.") || // Added in 7.0 193 Name.startswith("avx512.mask.pmulhu.w.") || // Added in 7.0 194 Name.startswith("avx512.mask.pmaddw.d.") || // Added in 7.0 195 Name.startswith("avx512.mask.pmaddubs.w.") || // Added in 7.0 196 Name.startswith("avx512.mask.packsswb.") || // Added in 5.0 197 Name.startswith("avx512.mask.packssdw.") || // Added in 5.0 198 Name.startswith("avx512.mask.packuswb.") || // Added in 5.0 199 Name.startswith("avx512.mask.packusdw.") || // Added in 5.0 200 Name.startswith("avx512.mask.cmp.b") || // Added in 5.0 201 Name.startswith("avx512.mask.cmp.d") || // Added in 5.0 202 Name.startswith("avx512.mask.cmp.q") || // Added in 5.0 203 Name.startswith("avx512.mask.cmp.w") || // Added in 5.0 204 Name.startswith("avx512.mask.ucmp.") || // Added in 5.0 205 Name.startswith("avx512.cvtb2mask.") || // Added in 7.0 206 Name.startswith("avx512.cvtw2mask.") || // Added in 7.0 207 Name.startswith("avx512.cvtd2mask.") || // Added in 7.0 208 Name.startswith("avx512.cvtq2mask.") || // Added in 7.0 209 Name == "avx512.mask.add.pd.128" || // Added in 4.0 210 Name == "avx512.mask.add.pd.256" || // Added in 4.0 211 Name == "avx512.mask.add.ps.128" || // Added in 4.0 212 Name == "avx512.mask.add.ps.256" || // Added in 4.0 213 Name == "avx512.mask.div.pd.128" || // Added in 4.0 214 Name == "avx512.mask.div.pd.256" || // Added in 4.0 215 Name == "avx512.mask.div.ps.128" || // Added in 4.0 216 Name == "avx512.mask.div.ps.256" || // Added in 4.0 217 Name == "avx512.mask.mul.pd.128" || // Added in 4.0 218 Name == "avx512.mask.mul.pd.256" || // Added in 4.0 219 Name == "avx512.mask.mul.ps.128" || // Added in 4.0 220 Name == "avx512.mask.mul.ps.256" || // Added in 4.0 221 Name == "avx512.mask.sub.pd.128" || // Added in 4.0 222 Name == "avx512.mask.sub.pd.256" || // Added in 4.0 223 Name == "avx512.mask.sub.ps.128" || // Added in 4.0 224 Name == "avx512.mask.sub.ps.256" || // Added in 4.0 225 Name == "avx512.mask.max.pd.128" || // Added in 5.0 226 Name == "avx512.mask.max.pd.256" || // Added in 5.0 227 Name == "avx512.mask.max.ps.128" || // Added in 5.0 228 Name == "avx512.mask.max.ps.256" || // Added in 5.0 229 Name == "avx512.mask.min.pd.128" || // Added in 5.0 230 Name == "avx512.mask.min.pd.256" || // Added in 5.0 231 Name == "avx512.mask.min.ps.128" || // Added in 5.0 232 Name == "avx512.mask.min.ps.256" || // Added in 5.0 233 Name.startswith("avx512.mask.vpermilvar.") || // Added in 4.0 234 Name.startswith("avx512.mask.psll.d") || // Added in 4.0 235 Name.startswith("avx512.mask.psll.q") || // Added in 4.0 236 Name.startswith("avx512.mask.psll.w") || // Added in 4.0 237 Name.startswith("avx512.mask.psra.d") || // Added in 4.0 238 Name.startswith("avx512.mask.psra.q") || // Added in 4.0 239 Name.startswith("avx512.mask.psra.w") || // Added in 4.0 240 Name.startswith("avx512.mask.psrl.d") || // Added in 4.0 241 Name.startswith("avx512.mask.psrl.q") || // Added in 4.0 242 Name.startswith("avx512.mask.psrl.w") || // Added in 4.0 243 Name.startswith("avx512.mask.pslli") || // Added in 4.0 244 Name.startswith("avx512.mask.psrai") || // Added in 4.0 245 Name.startswith("avx512.mask.psrli") || // Added in 4.0 246 Name.startswith("avx512.mask.psllv") || // Added in 4.0 247 Name.startswith("avx512.mask.psrav") || // Added in 4.0 248 Name.startswith("avx512.mask.psrlv") || // Added in 4.0 249 Name.startswith("sse41.pmovsx") || // Added in 3.8 250 Name.startswith("sse41.pmovzx") || // Added in 3.9 251 Name.startswith("avx2.pmovsx") || // Added in 3.9 252 Name.startswith("avx2.pmovzx") || // Added in 3.9 253 Name.startswith("avx512.mask.pmovsx") || // Added in 4.0 254 Name.startswith("avx512.mask.pmovzx") || // Added in 4.0 255 Name.startswith("avx512.mask.lzcnt.") || // Added in 5.0 256 Name == "sse2.cvtdq2pd" || // Added in 3.9 257 Name == "sse2.cvtps2pd" || // Added in 3.9 258 Name == "avx.cvtdq2.pd.256" || // Added in 3.9 259 Name == "avx.cvt.ps2.pd.256" || // Added in 3.9 260 Name.startswith("avx.vinsertf128.") || // Added in 3.7 261 Name == "avx2.vinserti128" || // Added in 3.7 262 Name.startswith("avx512.mask.insert") || // Added in 4.0 263 Name.startswith("avx.vextractf128.") || // Added in 3.7 264 Name == "avx2.vextracti128" || // Added in 3.7 265 Name.startswith("avx512.mask.vextract") || // Added in 4.0 266 Name.startswith("sse4a.movnt.") || // Added in 3.9 267 Name.startswith("avx.movnt.") || // Added in 3.2 268 Name.startswith("avx512.storent.") || // Added in 3.9 269 Name == "sse41.movntdqa" || // Added in 5.0 270 Name == "avx2.movntdqa" || // Added in 5.0 271 Name == "avx512.movntdqa" || // Added in 5.0 272 Name == "sse2.storel.dq" || // Added in 3.9 273 Name.startswith("sse.storeu.") || // Added in 3.9 274 Name.startswith("sse2.storeu.") || // Added in 3.9 275 Name.startswith("avx.storeu.") || // Added in 3.9 276 Name.startswith("avx512.mask.storeu.") || // Added in 3.9 277 Name.startswith("avx512.mask.store.p") || // Added in 3.9 278 Name.startswith("avx512.mask.store.b.") || // Added in 3.9 279 Name.startswith("avx512.mask.store.w.") || // Added in 3.9 280 Name.startswith("avx512.mask.store.d.") || // Added in 3.9 281 Name.startswith("avx512.mask.store.q.") || // Added in 3.9 282 Name.startswith("avx512.mask.loadu.") || // Added in 3.9 283 Name.startswith("avx512.mask.load.") || // Added in 3.9 284 Name == "sse42.crc32.64.8" || // Added in 3.4 285 Name.startswith("avx.vbroadcast.s") || // Added in 3.5 286 Name.startswith("avx512.mask.palignr.") || // Added in 3.9 287 Name.startswith("avx512.mask.valign.") || // Added in 4.0 288 Name.startswith("sse2.psll.dq") || // Added in 3.7 289 Name.startswith("sse2.psrl.dq") || // Added in 3.7 290 Name.startswith("avx2.psll.dq") || // Added in 3.7 291 Name.startswith("avx2.psrl.dq") || // Added in 3.7 292 Name.startswith("avx512.psll.dq") || // Added in 3.9 293 Name.startswith("avx512.psrl.dq") || // Added in 3.9 294 Name == "sse41.pblendw" || // Added in 3.7 295 Name.startswith("sse41.blendp") || // Added in 3.7 296 Name.startswith("avx.blend.p") || // Added in 3.7 297 Name == "avx2.pblendw" || // Added in 3.7 298 Name.startswith("avx2.pblendd.") || // Added in 3.7 299 Name.startswith("avx.vbroadcastf128") || // Added in 4.0 300 Name == "avx2.vbroadcasti128" || // Added in 3.7 301 Name.startswith("avx512.mask.broadcastf") || // Added in 6.0 302 Name.startswith("avx512.mask.broadcasti") || // Added in 6.0 303 Name == "xop.vpcmov" || // Added in 3.8 304 Name == "xop.vpcmov.256" || // Added in 5.0 305 Name.startswith("avx512.mask.move.s") || // Added in 4.0 306 Name.startswith("avx512.cvtmask2") || // Added in 5.0 307 (Name.startswith("xop.vpcom") && // Added in 3.2 308 F->arg_size() == 2) || 309 Name.startswith("avx512.ptestm") || //Added in 6.0 310 Name.startswith("avx512.ptestnm") || //Added in 6.0 311 Name.startswith("sse2.pavg") || // Added in 6.0 312 Name.startswith("avx2.pavg") || // Added in 6.0 313 Name.startswith("avx512.mask.pavg")) // Added in 6.0 314 return true; 315 316 return false; 317 } 318 319 static bool UpgradeX86IntrinsicFunction(Function *F, StringRef Name, 320 Function *&NewFn) { 321 // Only handle intrinsics that start with "x86.". 322 if (!Name.startswith("x86.")) 323 return false; 324 // Remove "x86." prefix. 325 Name = Name.substr(4); 326 327 if (ShouldUpgradeX86Intrinsic(F, Name)) { 328 NewFn = nullptr; 329 return true; 330 } 331 332 // SSE4.1 ptest functions may have an old signature. 333 if (Name.startswith("sse41.ptest")) { // Added in 3.2 334 if (Name.substr(11) == "c") 335 return UpgradePTESTIntrinsic(F, Intrinsic::x86_sse41_ptestc, NewFn); 336 if (Name.substr(11) == "z") 337 return UpgradePTESTIntrinsic(F, Intrinsic::x86_sse41_ptestz, NewFn); 338 if (Name.substr(11) == "nzc") 339 return UpgradePTESTIntrinsic(F, Intrinsic::x86_sse41_ptestnzc, NewFn); 340 } 341 // Several blend and other instructions with masks used the wrong number of 342 // bits. 343 if (Name == "sse41.insertps") // Added in 3.6 344 return UpgradeX86IntrinsicsWith8BitMask(F, Intrinsic::x86_sse41_insertps, 345 NewFn); 346 if (Name == "sse41.dppd") // Added in 3.6 347 return UpgradeX86IntrinsicsWith8BitMask(F, Intrinsic::x86_sse41_dppd, 348 NewFn); 349 if (Name == "sse41.dpps") // Added in 3.6 350 return UpgradeX86IntrinsicsWith8BitMask(F, Intrinsic::x86_sse41_dpps, 351 NewFn); 352 if (Name == "sse41.mpsadbw") // Added in 3.6 353 return UpgradeX86IntrinsicsWith8BitMask(F, Intrinsic::x86_sse41_mpsadbw, 354 NewFn); 355 if (Name == "avx.dp.ps.256") // Added in 3.6 356 return UpgradeX86IntrinsicsWith8BitMask(F, Intrinsic::x86_avx_dp_ps_256, 357 NewFn); 358 if (Name == "avx2.mpsadbw") // Added in 3.6 359 return UpgradeX86IntrinsicsWith8BitMask(F, Intrinsic::x86_avx2_mpsadbw, 360 NewFn); 361 if (Name == "avx512.mask.cmp.pd.128") // Added in 7.0 362 return UpgradeX86MaskedFPCompare(F, Intrinsic::x86_avx512_mask_cmp_pd_128, 363 NewFn); 364 if (Name == "avx512.mask.cmp.pd.256") // Added in 7.0 365 return UpgradeX86MaskedFPCompare(F, Intrinsic::x86_avx512_mask_cmp_pd_256, 366 NewFn); 367 if (Name == "avx512.mask.cmp.pd.512") // Added in 7.0 368 return UpgradeX86MaskedFPCompare(F, Intrinsic::x86_avx512_mask_cmp_pd_512, 369 NewFn); 370 if (Name == "avx512.mask.cmp.ps.128") // Added in 7.0 371 return UpgradeX86MaskedFPCompare(F, Intrinsic::x86_avx512_mask_cmp_ps_128, 372 NewFn); 373 if (Name == "avx512.mask.cmp.ps.256") // Added in 7.0 374 return UpgradeX86MaskedFPCompare(F, Intrinsic::x86_avx512_mask_cmp_ps_256, 375 NewFn); 376 if (Name == "avx512.mask.cmp.ps.512") // Added in 7.0 377 return UpgradeX86MaskedFPCompare(F, Intrinsic::x86_avx512_mask_cmp_ps_512, 378 NewFn); 379 380 // frcz.ss/sd may need to have an argument dropped. Added in 3.2 381 if (Name.startswith("xop.vfrcz.ss") && F->arg_size() == 2) { 382 rename(F); 383 NewFn = Intrinsic::getDeclaration(F->getParent(), 384 Intrinsic::x86_xop_vfrcz_ss); 385 return true; 386 } 387 if (Name.startswith("xop.vfrcz.sd") && F->arg_size() == 2) { 388 rename(F); 389 NewFn = Intrinsic::getDeclaration(F->getParent(), 390 Intrinsic::x86_xop_vfrcz_sd); 391 return true; 392 } 393 // Upgrade any XOP PERMIL2 index operand still using a float/double vector. 394 if (Name.startswith("xop.vpermil2")) { // Added in 3.9 395 auto Idx = F->getFunctionType()->getParamType(2); 396 if (Idx->isFPOrFPVectorTy()) { 397 rename(F); 398 unsigned IdxSize = Idx->getPrimitiveSizeInBits(); 399 unsigned EltSize = Idx->getScalarSizeInBits(); 400 Intrinsic::ID Permil2ID; 401 if (EltSize == 64 && IdxSize == 128) 402 Permil2ID = Intrinsic::x86_xop_vpermil2pd; 403 else if (EltSize == 32 && IdxSize == 128) 404 Permil2ID = Intrinsic::x86_xop_vpermil2ps; 405 else if (EltSize == 64 && IdxSize == 256) 406 Permil2ID = Intrinsic::x86_xop_vpermil2pd_256; 407 else 408 Permil2ID = Intrinsic::x86_xop_vpermil2ps_256; 409 NewFn = Intrinsic::getDeclaration(F->getParent(), Permil2ID); 410 return true; 411 } 412 } 413 414 return false; 415 } 416 417 static bool UpgradeIntrinsicFunction1(Function *F, Function *&NewFn) { 418 assert(F && "Illegal to upgrade a non-existent Function."); 419 420 // Quickly eliminate it, if it's not a candidate. 421 StringRef Name = F->getName(); 422 if (Name.size() <= 8 || !Name.startswith("llvm.")) 423 return false; 424 Name = Name.substr(5); // Strip off "llvm." 425 426 switch (Name[0]) { 427 default: break; 428 case 'a': { 429 if (Name.startswith("arm.rbit") || Name.startswith("aarch64.rbit")) { 430 NewFn = Intrinsic::getDeclaration(F->getParent(), Intrinsic::bitreverse, 431 F->arg_begin()->getType()); 432 return true; 433 } 434 if (Name.startswith("arm.neon.vclz")) { 435 Type* args[2] = { 436 F->arg_begin()->getType(), 437 Type::getInt1Ty(F->getContext()) 438 }; 439 // Can't use Intrinsic::getDeclaration here as it adds a ".i1" to 440 // the end of the name. Change name from llvm.arm.neon.vclz.* to 441 // llvm.ctlz.* 442 FunctionType* fType = FunctionType::get(F->getReturnType(), args, false); 443 NewFn = Function::Create(fType, F->getLinkage(), 444 "llvm.ctlz." + Name.substr(14), F->getParent()); 445 return true; 446 } 447 if (Name.startswith("arm.neon.vcnt")) { 448 NewFn = Intrinsic::getDeclaration(F->getParent(), Intrinsic::ctpop, 449 F->arg_begin()->getType()); 450 return true; 451 } 452 Regex vldRegex("^arm\\.neon\\.vld([1234]|[234]lane)\\.v[a-z0-9]*$"); 453 if (vldRegex.match(Name)) { 454 auto fArgs = F->getFunctionType()->params(); 455 SmallVector<Type *, 4> Tys(fArgs.begin(), fArgs.end()); 456 // Can't use Intrinsic::getDeclaration here as the return types might 457 // then only be structurally equal. 458 FunctionType* fType = FunctionType::get(F->getReturnType(), Tys, false); 459 NewFn = Function::Create(fType, F->getLinkage(), 460 "llvm." + Name + ".p0i8", F->getParent()); 461 return true; 462 } 463 Regex vstRegex("^arm\\.neon\\.vst([1234]|[234]lane)\\.v[a-z0-9]*$"); 464 if (vstRegex.match(Name)) { 465 static const Intrinsic::ID StoreInts[] = {Intrinsic::arm_neon_vst1, 466 Intrinsic::arm_neon_vst2, 467 Intrinsic::arm_neon_vst3, 468 Intrinsic::arm_neon_vst4}; 469 470 static const Intrinsic::ID StoreLaneInts[] = { 471 Intrinsic::arm_neon_vst2lane, Intrinsic::arm_neon_vst3lane, 472 Intrinsic::arm_neon_vst4lane 473 }; 474 475 auto fArgs = F->getFunctionType()->params(); 476 Type *Tys[] = {fArgs[0], fArgs[1]}; 477 if (Name.find("lane") == StringRef::npos) 478 NewFn = Intrinsic::getDeclaration(F->getParent(), 479 StoreInts[fArgs.size() - 3], Tys); 480 else 481 NewFn = Intrinsic::getDeclaration(F->getParent(), 482 StoreLaneInts[fArgs.size() - 5], Tys); 483 return true; 484 } 485 if (Name == "aarch64.thread.pointer" || Name == "arm.thread.pointer") { 486 NewFn = Intrinsic::getDeclaration(F->getParent(), Intrinsic::thread_pointer); 487 return true; 488 } 489 break; 490 } 491 492 case 'c': { 493 if (Name.startswith("ctlz.") && F->arg_size() == 1) { 494 rename(F); 495 NewFn = Intrinsic::getDeclaration(F->getParent(), Intrinsic::ctlz, 496 F->arg_begin()->getType()); 497 return true; 498 } 499 if (Name.startswith("cttz.") && F->arg_size() == 1) { 500 rename(F); 501 NewFn = Intrinsic::getDeclaration(F->getParent(), Intrinsic::cttz, 502 F->arg_begin()->getType()); 503 return true; 504 } 505 break; 506 } 507 case 'd': { 508 if (Name == "dbg.value" && F->arg_size() == 4) { 509 rename(F); 510 NewFn = Intrinsic::getDeclaration(F->getParent(), Intrinsic::dbg_value); 511 return true; 512 } 513 break; 514 } 515 case 'i': 516 case 'l': { 517 bool IsLifetimeStart = Name.startswith("lifetime.start"); 518 if (IsLifetimeStart || Name.startswith("invariant.start")) { 519 Intrinsic::ID ID = IsLifetimeStart ? 520 Intrinsic::lifetime_start : Intrinsic::invariant_start; 521 auto Args = F->getFunctionType()->params(); 522 Type* ObjectPtr[1] = {Args[1]}; 523 if (F->getName() != Intrinsic::getName(ID, ObjectPtr)) { 524 rename(F); 525 NewFn = Intrinsic::getDeclaration(F->getParent(), ID, ObjectPtr); 526 return true; 527 } 528 } 529 530 bool IsLifetimeEnd = Name.startswith("lifetime.end"); 531 if (IsLifetimeEnd || Name.startswith("invariant.end")) { 532 Intrinsic::ID ID = IsLifetimeEnd ? 533 Intrinsic::lifetime_end : Intrinsic::invariant_end; 534 535 auto Args = F->getFunctionType()->params(); 536 Type* ObjectPtr[1] = {Args[IsLifetimeEnd ? 1 : 2]}; 537 if (F->getName() != Intrinsic::getName(ID, ObjectPtr)) { 538 rename(F); 539 NewFn = Intrinsic::getDeclaration(F->getParent(), ID, ObjectPtr); 540 return true; 541 } 542 } 543 break; 544 } 545 case 'm': { 546 if (Name.startswith("masked.load.")) { 547 Type *Tys[] = { F->getReturnType(), F->arg_begin()->getType() }; 548 if (F->getName() != Intrinsic::getName(Intrinsic::masked_load, Tys)) { 549 rename(F); 550 NewFn = Intrinsic::getDeclaration(F->getParent(), 551 Intrinsic::masked_load, 552 Tys); 553 return true; 554 } 555 } 556 if (Name.startswith("masked.store.")) { 557 auto Args = F->getFunctionType()->params(); 558 Type *Tys[] = { Args[0], Args[1] }; 559 if (F->getName() != Intrinsic::getName(Intrinsic::masked_store, Tys)) { 560 rename(F); 561 NewFn = Intrinsic::getDeclaration(F->getParent(), 562 Intrinsic::masked_store, 563 Tys); 564 return true; 565 } 566 } 567 // Renaming gather/scatter intrinsics with no address space overloading 568 // to the new overload which includes an address space 569 if (Name.startswith("masked.gather.")) { 570 Type *Tys[] = {F->getReturnType(), F->arg_begin()->getType()}; 571 if (F->getName() != Intrinsic::getName(Intrinsic::masked_gather, Tys)) { 572 rename(F); 573 NewFn = Intrinsic::getDeclaration(F->getParent(), 574 Intrinsic::masked_gather, Tys); 575 return true; 576 } 577 } 578 if (Name.startswith("masked.scatter.")) { 579 auto Args = F->getFunctionType()->params(); 580 Type *Tys[] = {Args[0], Args[1]}; 581 if (F->getName() != Intrinsic::getName(Intrinsic::masked_scatter, Tys)) { 582 rename(F); 583 NewFn = Intrinsic::getDeclaration(F->getParent(), 584 Intrinsic::masked_scatter, Tys); 585 return true; 586 } 587 } 588 // Updating the memory intrinsics (memcpy/memmove/memset) that have an 589 // alignment parameter to embedding the alignment as an attribute of 590 // the pointer args. 591 if (Name.startswith("memcpy.") && F->arg_size() == 5) { 592 rename(F); 593 // Get the types of dest, src, and len 594 ArrayRef<Type *> ParamTypes = F->getFunctionType()->params().slice(0, 3); 595 NewFn = Intrinsic::getDeclaration(F->getParent(), Intrinsic::memcpy, 596 ParamTypes); 597 return true; 598 } 599 if (Name.startswith("memmove.") && F->arg_size() == 5) { 600 rename(F); 601 // Get the types of dest, src, and len 602 ArrayRef<Type *> ParamTypes = F->getFunctionType()->params().slice(0, 3); 603 NewFn = Intrinsic::getDeclaration(F->getParent(), Intrinsic::memmove, 604 ParamTypes); 605 return true; 606 } 607 if (Name.startswith("memset.") && F->arg_size() == 5) { 608 rename(F); 609 // Get the types of dest, and len 610 const auto *FT = F->getFunctionType(); 611 Type *ParamTypes[2] = { 612 FT->getParamType(0), // Dest 613 FT->getParamType(2) // len 614 }; 615 NewFn = Intrinsic::getDeclaration(F->getParent(), Intrinsic::memset, 616 ParamTypes); 617 return true; 618 } 619 break; 620 } 621 case 'n': { 622 if (Name.startswith("nvvm.")) { 623 Name = Name.substr(5); 624 625 // The following nvvm intrinsics correspond exactly to an LLVM intrinsic. 626 Intrinsic::ID IID = StringSwitch<Intrinsic::ID>(Name) 627 .Cases("brev32", "brev64", Intrinsic::bitreverse) 628 .Case("clz.i", Intrinsic::ctlz) 629 .Case("popc.i", Intrinsic::ctpop) 630 .Default(Intrinsic::not_intrinsic); 631 if (IID != Intrinsic::not_intrinsic && F->arg_size() == 1) { 632 NewFn = Intrinsic::getDeclaration(F->getParent(), IID, 633 {F->getReturnType()}); 634 return true; 635 } 636 637 // The following nvvm intrinsics correspond exactly to an LLVM idiom, but 638 // not to an intrinsic alone. We expand them in UpgradeIntrinsicCall. 639 // 640 // TODO: We could add lohi.i2d. 641 bool Expand = StringSwitch<bool>(Name) 642 .Cases("abs.i", "abs.ll", true) 643 .Cases("clz.ll", "popc.ll", "h2f", true) 644 .Cases("max.i", "max.ll", "max.ui", "max.ull", true) 645 .Cases("min.i", "min.ll", "min.ui", "min.ull", true) 646 .Default(false); 647 if (Expand) { 648 NewFn = nullptr; 649 return true; 650 } 651 } 652 break; 653 } 654 case 'o': 655 // We only need to change the name to match the mangling including the 656 // address space. 657 if (Name.startswith("objectsize.")) { 658 Type *Tys[2] = { F->getReturnType(), F->arg_begin()->getType() }; 659 if (F->arg_size() == 2 || 660 F->getName() != Intrinsic::getName(Intrinsic::objectsize, Tys)) { 661 rename(F); 662 NewFn = Intrinsic::getDeclaration(F->getParent(), Intrinsic::objectsize, 663 Tys); 664 return true; 665 } 666 } 667 break; 668 669 case 's': 670 if (Name == "stackprotectorcheck") { 671 NewFn = nullptr; 672 return true; 673 } 674 break; 675 676 case 'x': 677 if (UpgradeX86IntrinsicFunction(F, Name, NewFn)) 678 return true; 679 } 680 // Remangle our intrinsic since we upgrade the mangling 681 auto Result = llvm::Intrinsic::remangleIntrinsicFunction(F); 682 if (Result != None) { 683 NewFn = Result.getValue(); 684 return true; 685 } 686 687 // This may not belong here. This function is effectively being overloaded 688 // to both detect an intrinsic which needs upgrading, and to provide the 689 // upgraded form of the intrinsic. We should perhaps have two separate 690 // functions for this. 691 return false; 692 } 693 694 bool llvm::UpgradeIntrinsicFunction(Function *F, Function *&NewFn) { 695 NewFn = nullptr; 696 bool Upgraded = UpgradeIntrinsicFunction1(F, NewFn); 697 assert(F != NewFn && "Intrinsic function upgraded to the same function"); 698 699 // Upgrade intrinsic attributes. This does not change the function. 700 if (NewFn) 701 F = NewFn; 702 if (Intrinsic::ID id = F->getIntrinsicID()) 703 F->setAttributes(Intrinsic::getAttributes(F->getContext(), id)); 704 return Upgraded; 705 } 706 707 bool llvm::UpgradeGlobalVariable(GlobalVariable *GV) { 708 // Nothing to do yet. 709 return false; 710 } 711 712 // Handles upgrading SSE2/AVX2/AVX512BW PSLLDQ intrinsics by converting them 713 // to byte shuffles. 714 static Value *UpgradeX86PSLLDQIntrinsics(IRBuilder<> &Builder, 715 Value *Op, unsigned Shift) { 716 Type *ResultTy = Op->getType(); 717 unsigned NumElts = ResultTy->getVectorNumElements() * 8; 718 719 // Bitcast from a 64-bit element type to a byte element type. 720 Type *VecTy = VectorType::get(Builder.getInt8Ty(), NumElts); 721 Op = Builder.CreateBitCast(Op, VecTy, "cast"); 722 723 // We'll be shuffling in zeroes. 724 Value *Res = Constant::getNullValue(VecTy); 725 726 // If shift is less than 16, emit a shuffle to move the bytes. Otherwise, 727 // we'll just return the zero vector. 728 if (Shift < 16) { 729 uint32_t Idxs[64]; 730 // 256/512-bit version is split into 2/4 16-byte lanes. 731 for (unsigned l = 0; l != NumElts; l += 16) 732 for (unsigned i = 0; i != 16; ++i) { 733 unsigned Idx = NumElts + i - Shift; 734 if (Idx < NumElts) 735 Idx -= NumElts - 16; // end of lane, switch operand. 736 Idxs[l + i] = Idx + l; 737 } 738 739 Res = Builder.CreateShuffleVector(Res, Op, makeArrayRef(Idxs, NumElts)); 740 } 741 742 // Bitcast back to a 64-bit element type. 743 return Builder.CreateBitCast(Res, ResultTy, "cast"); 744 } 745 746 // Handles upgrading SSE2/AVX2/AVX512BW PSRLDQ intrinsics by converting them 747 // to byte shuffles. 748 static Value *UpgradeX86PSRLDQIntrinsics(IRBuilder<> &Builder, Value *Op, 749 unsigned Shift) { 750 Type *ResultTy = Op->getType(); 751 unsigned NumElts = ResultTy->getVectorNumElements() * 8; 752 753 // Bitcast from a 64-bit element type to a byte element type. 754 Type *VecTy = VectorType::get(Builder.getInt8Ty(), NumElts); 755 Op = Builder.CreateBitCast(Op, VecTy, "cast"); 756 757 // We'll be shuffling in zeroes. 758 Value *Res = Constant::getNullValue(VecTy); 759 760 // If shift is less than 16, emit a shuffle to move the bytes. Otherwise, 761 // we'll just return the zero vector. 762 if (Shift < 16) { 763 uint32_t Idxs[64]; 764 // 256/512-bit version is split into 2/4 16-byte lanes. 765 for (unsigned l = 0; l != NumElts; l += 16) 766 for (unsigned i = 0; i != 16; ++i) { 767 unsigned Idx = i + Shift; 768 if (Idx >= 16) 769 Idx += NumElts - 16; // end of lane, switch operand. 770 Idxs[l + i] = Idx + l; 771 } 772 773 Res = Builder.CreateShuffleVector(Op, Res, makeArrayRef(Idxs, NumElts)); 774 } 775 776 // Bitcast back to a 64-bit element type. 777 return Builder.CreateBitCast(Res, ResultTy, "cast"); 778 } 779 780 static Value *getX86MaskVec(IRBuilder<> &Builder, Value *Mask, 781 unsigned NumElts) { 782 llvm::VectorType *MaskTy = llvm::VectorType::get(Builder.getInt1Ty(), 783 cast<IntegerType>(Mask->getType())->getBitWidth()); 784 Mask = Builder.CreateBitCast(Mask, MaskTy); 785 786 // If we have less than 8 elements, then the starting mask was an i8 and 787 // we need to extract down to the right number of elements. 788 if (NumElts < 8) { 789 uint32_t Indices[4]; 790 for (unsigned i = 0; i != NumElts; ++i) 791 Indices[i] = i; 792 Mask = Builder.CreateShuffleVector(Mask, Mask, 793 makeArrayRef(Indices, NumElts), 794 "extract"); 795 } 796 797 return Mask; 798 } 799 800 static Value *EmitX86Select(IRBuilder<> &Builder, Value *Mask, 801 Value *Op0, Value *Op1) { 802 // If the mask is all ones just emit the align operation. 803 if (const auto *C = dyn_cast<Constant>(Mask)) 804 if (C->isAllOnesValue()) 805 return Op0; 806 807 Mask = getX86MaskVec(Builder, Mask, Op0->getType()->getVectorNumElements()); 808 return Builder.CreateSelect(Mask, Op0, Op1); 809 } 810 811 // Handle autoupgrade for masked PALIGNR and VALIGND/Q intrinsics. 812 // PALIGNR handles large immediates by shifting while VALIGN masks the immediate 813 // so we need to handle both cases. VALIGN also doesn't have 128-bit lanes. 814 static Value *UpgradeX86ALIGNIntrinsics(IRBuilder<> &Builder, Value *Op0, 815 Value *Op1, Value *Shift, 816 Value *Passthru, Value *Mask, 817 bool IsVALIGN) { 818 unsigned ShiftVal = cast<llvm::ConstantInt>(Shift)->getZExtValue(); 819 820 unsigned NumElts = Op0->getType()->getVectorNumElements(); 821 assert((IsVALIGN || NumElts % 16 == 0) && "Illegal NumElts for PALIGNR!"); 822 assert((!IsVALIGN || NumElts <= 16) && "NumElts too large for VALIGN!"); 823 assert(isPowerOf2_32(NumElts) && "NumElts not a power of 2!"); 824 825 // Mask the immediate for VALIGN. 826 if (IsVALIGN) 827 ShiftVal &= (NumElts - 1); 828 829 // If palignr is shifting the pair of vectors more than the size of two 830 // lanes, emit zero. 831 if (ShiftVal >= 32) 832 return llvm::Constant::getNullValue(Op0->getType()); 833 834 // If palignr is shifting the pair of input vectors more than one lane, 835 // but less than two lanes, convert to shifting in zeroes. 836 if (ShiftVal > 16) { 837 ShiftVal -= 16; 838 Op1 = Op0; 839 Op0 = llvm::Constant::getNullValue(Op0->getType()); 840 } 841 842 uint32_t Indices[64]; 843 // 256-bit palignr operates on 128-bit lanes so we need to handle that 844 for (unsigned l = 0; l < NumElts; l += 16) { 845 for (unsigned i = 0; i != 16; ++i) { 846 unsigned Idx = ShiftVal + i; 847 if (!IsVALIGN && Idx >= 16) // Disable wrap for VALIGN. 848 Idx += NumElts - 16; // End of lane, switch operand. 849 Indices[l + i] = Idx + l; 850 } 851 } 852 853 Value *Align = Builder.CreateShuffleVector(Op1, Op0, 854 makeArrayRef(Indices, NumElts), 855 "palignr"); 856 857 return EmitX86Select(Builder, Mask, Align, Passthru); 858 } 859 860 static Value *UpgradeX86AddSubSatIntrinsics(IRBuilder<> &Builder, CallInst &CI, 861 bool IsSigned, bool IsAddition) { 862 // Get elements. 863 Value *Op0 = CI.getArgOperand(0); 864 Value *Op1 = CI.getArgOperand(1); 865 866 // Extend elements. 867 Type *ResultType = CI.getType(); 868 unsigned NumElts = ResultType->getVectorNumElements(); 869 870 Value *Res; 871 if (!IsAddition && !IsSigned) { 872 Value *ICmp = Builder.CreateICmp(ICmpInst::ICMP_UGT, Op0, Op1); 873 Value *Select = Builder.CreateSelect(ICmp, Op0, Op1); 874 Res = Builder.CreateSub(Select, Op1); 875 } else { 876 Type *EltType = ResultType->getVectorElementType(); 877 Type *ExtEltType = EltType == Builder.getInt8Ty() ? Builder.getInt16Ty() 878 : Builder.getInt32Ty(); 879 Type *ExtVT = VectorType::get(ExtEltType, NumElts); 880 Op0 = IsSigned ? Builder.CreateSExt(Op0, ExtVT) 881 : Builder.CreateZExt(Op0, ExtVT); 882 Op1 = IsSigned ? Builder.CreateSExt(Op1, ExtVT) 883 : Builder.CreateZExt(Op1, ExtVT); 884 885 // Perform addition/substraction. 886 Res = IsAddition ? Builder.CreateAdd(Op0, Op1) 887 : Builder.CreateSub(Op0, Op1); 888 889 // Create a vector of maximum values of not extended type 890 // (if overflow occurs, it will be saturated to that value). 891 unsigned EltSizeInBits = EltType->getPrimitiveSizeInBits(); 892 APInt MaxInt = IsSigned ? APInt::getSignedMaxValue(EltSizeInBits) 893 : APInt::getMaxValue(EltSizeInBits); 894 Value *MaxVec = ConstantInt::get(ResultType, MaxInt); 895 // Extend so that it can be compared to result of add/sub. 896 MaxVec = IsSigned ? Builder.CreateSExt(MaxVec, ExtVT) 897 : Builder.CreateZExt(MaxVec, ExtVT); 898 899 // Saturate overflow. 900 ICmpInst::Predicate Pred = IsSigned ? ICmpInst::ICMP_SLE 901 : ICmpInst::ICMP_ULE; 902 Value *Cmp = Builder.CreateICmp(Pred, Res, 903 MaxVec); // 1 if no overflow. 904 Res = Builder.CreateSelect(Cmp, Res, 905 MaxVec); // If overflowed, copy from max vec. 906 907 // Saturate underflow. 908 if (IsSigned) { 909 APInt MinInt = APInt::getSignedMinValue(EltSizeInBits); 910 Value *MinVec = ConstantInt::get(ResultType, MinInt); 911 // Extend so that it can be compared to result of add/sub. 912 MinVec = Builder.CreateSExt(MinVec, ExtVT); 913 Value *Cmp = Builder.CreateICmp(ICmpInst::ICMP_SGT, Res, 914 MinVec); // 1 if no underflow. 915 Res = Builder.CreateSelect(Cmp, Res, 916 MinVec); // If underflowed, copy from min vec. 917 } 918 919 // Truncate to original type. 920 Res = Builder.CreateTrunc(Res, ResultType); 921 } 922 923 if (CI.getNumArgOperands() == 4) { // For masked intrinsics. 924 Value *VecSRC = CI.getArgOperand(2); 925 Value *Mask = CI.getArgOperand(3); 926 Res = EmitX86Select(Builder, Mask, Res, VecSRC); 927 } 928 return Res; 929 } 930 931 static Value *UpgradeMaskedStore(IRBuilder<> &Builder, 932 Value *Ptr, Value *Data, Value *Mask, 933 bool Aligned) { 934 // Cast the pointer to the right type. 935 Ptr = Builder.CreateBitCast(Ptr, 936 llvm::PointerType::getUnqual(Data->getType())); 937 unsigned Align = 938 Aligned ? cast<VectorType>(Data->getType())->getBitWidth() / 8 : 1; 939 940 // If the mask is all ones just emit a regular store. 941 if (const auto *C = dyn_cast<Constant>(Mask)) 942 if (C->isAllOnesValue()) 943 return Builder.CreateAlignedStore(Data, Ptr, Align); 944 945 // Convert the mask from an integer type to a vector of i1. 946 unsigned NumElts = Data->getType()->getVectorNumElements(); 947 Mask = getX86MaskVec(Builder, Mask, NumElts); 948 return Builder.CreateMaskedStore(Data, Ptr, Align, Mask); 949 } 950 951 static Value *UpgradeMaskedLoad(IRBuilder<> &Builder, 952 Value *Ptr, Value *Passthru, Value *Mask, 953 bool Aligned) { 954 // Cast the pointer to the right type. 955 Ptr = Builder.CreateBitCast(Ptr, 956 llvm::PointerType::getUnqual(Passthru->getType())); 957 unsigned Align = 958 Aligned ? cast<VectorType>(Passthru->getType())->getBitWidth() / 8 : 1; 959 960 // If the mask is all ones just emit a regular store. 961 if (const auto *C = dyn_cast<Constant>(Mask)) 962 if (C->isAllOnesValue()) 963 return Builder.CreateAlignedLoad(Ptr, Align); 964 965 // Convert the mask from an integer type to a vector of i1. 966 unsigned NumElts = Passthru->getType()->getVectorNumElements(); 967 Mask = getX86MaskVec(Builder, Mask, NumElts); 968 return Builder.CreateMaskedLoad(Ptr, Align, Mask, Passthru); 969 } 970 971 static Value *upgradeAbs(IRBuilder<> &Builder, CallInst &CI) { 972 Value *Op0 = CI.getArgOperand(0); 973 llvm::Type *Ty = Op0->getType(); 974 Value *Zero = llvm::Constant::getNullValue(Ty); 975 Value *Cmp = Builder.CreateICmp(ICmpInst::ICMP_SGT, Op0, Zero); 976 Value *Neg = Builder.CreateNeg(Op0); 977 Value *Res = Builder.CreateSelect(Cmp, Op0, Neg); 978 979 if (CI.getNumArgOperands() == 3) 980 Res = EmitX86Select(Builder,CI.getArgOperand(2), Res, CI.getArgOperand(1)); 981 982 return Res; 983 } 984 985 static Value *upgradeIntMinMax(IRBuilder<> &Builder, CallInst &CI, 986 ICmpInst::Predicate Pred) { 987 Value *Op0 = CI.getArgOperand(0); 988 Value *Op1 = CI.getArgOperand(1); 989 Value *Cmp = Builder.CreateICmp(Pred, Op0, Op1); 990 Value *Res = Builder.CreateSelect(Cmp, Op0, Op1); 991 992 if (CI.getNumArgOperands() == 4) 993 Res = EmitX86Select(Builder, CI.getArgOperand(3), Res, CI.getArgOperand(2)); 994 995 return Res; 996 } 997 998 static Value *upgradePMULDQ(IRBuilder<> &Builder, CallInst &CI, bool IsSigned) { 999 Type *Ty = CI.getType(); 1000 1001 // Arguments have a vXi32 type so cast to vXi64. 1002 Value *LHS = Builder.CreateBitCast(CI.getArgOperand(0), Ty); 1003 Value *RHS = Builder.CreateBitCast(CI.getArgOperand(1), Ty); 1004 1005 if (IsSigned) { 1006 // Shift left then arithmetic shift right. 1007 Constant *ShiftAmt = ConstantInt::get(Ty, 32); 1008 LHS = Builder.CreateShl(LHS, ShiftAmt); 1009 LHS = Builder.CreateAShr(LHS, ShiftAmt); 1010 RHS = Builder.CreateShl(RHS, ShiftAmt); 1011 RHS = Builder.CreateAShr(RHS, ShiftAmt); 1012 } else { 1013 // Clear the upper bits. 1014 Constant *Mask = ConstantInt::get(Ty, 0xffffffff); 1015 LHS = Builder.CreateAnd(LHS, Mask); 1016 RHS = Builder.CreateAnd(RHS, Mask); 1017 } 1018 1019 Value *Res = Builder.CreateMul(LHS, RHS); 1020 1021 if (CI.getNumArgOperands() == 4) 1022 Res = EmitX86Select(Builder, CI.getArgOperand(3), Res, CI.getArgOperand(2)); 1023 1024 return Res; 1025 } 1026 1027 // Applying mask on vector of i1's and make sure result is at least 8 bits wide. 1028 static Value *ApplyX86MaskOn1BitsVec(IRBuilder<> &Builder,Value *Vec, Value *Mask, 1029 unsigned NumElts) { 1030 if (Mask) { 1031 const auto *C = dyn_cast<Constant>(Mask); 1032 if (!C || !C->isAllOnesValue()) 1033 Vec = Builder.CreateAnd(Vec, getX86MaskVec(Builder, Mask, NumElts)); 1034 } 1035 1036 if (NumElts < 8) { 1037 uint32_t Indices[8]; 1038 for (unsigned i = 0; i != NumElts; ++i) 1039 Indices[i] = i; 1040 for (unsigned i = NumElts; i != 8; ++i) 1041 Indices[i] = NumElts + i % NumElts; 1042 Vec = Builder.CreateShuffleVector(Vec, 1043 Constant::getNullValue(Vec->getType()), 1044 Indices); 1045 } 1046 return Builder.CreateBitCast(Vec, Builder.getIntNTy(std::max(NumElts, 8U))); 1047 } 1048 1049 static Value *upgradeMaskedCompare(IRBuilder<> &Builder, CallInst &CI, 1050 unsigned CC, bool Signed) { 1051 Value *Op0 = CI.getArgOperand(0); 1052 unsigned NumElts = Op0->getType()->getVectorNumElements(); 1053 1054 Value *Cmp; 1055 if (CC == 3) { 1056 Cmp = Constant::getNullValue(llvm::VectorType::get(Builder.getInt1Ty(), NumElts)); 1057 } else if (CC == 7) { 1058 Cmp = Constant::getAllOnesValue(llvm::VectorType::get(Builder.getInt1Ty(), NumElts)); 1059 } else { 1060 ICmpInst::Predicate Pred; 1061 switch (CC) { 1062 default: llvm_unreachable("Unknown condition code"); 1063 case 0: Pred = ICmpInst::ICMP_EQ; break; 1064 case 1: Pred = Signed ? ICmpInst::ICMP_SLT : ICmpInst::ICMP_ULT; break; 1065 case 2: Pred = Signed ? ICmpInst::ICMP_SLE : ICmpInst::ICMP_ULE; break; 1066 case 4: Pred = ICmpInst::ICMP_NE; break; 1067 case 5: Pred = Signed ? ICmpInst::ICMP_SGE : ICmpInst::ICMP_UGE; break; 1068 case 6: Pred = Signed ? ICmpInst::ICMP_SGT : ICmpInst::ICMP_UGT; break; 1069 } 1070 Cmp = Builder.CreateICmp(Pred, Op0, CI.getArgOperand(1)); 1071 } 1072 1073 Value *Mask = CI.getArgOperand(CI.getNumArgOperands() - 1); 1074 1075 return ApplyX86MaskOn1BitsVec(Builder, Cmp, Mask, NumElts); 1076 } 1077 1078 // Replace a masked intrinsic with an older unmasked intrinsic. 1079 static Value *UpgradeX86MaskedShift(IRBuilder<> &Builder, CallInst &CI, 1080 Intrinsic::ID IID) { 1081 Function *Intrin = Intrinsic::getDeclaration(CI.getModule(), IID); 1082 Value *Rep = Builder.CreateCall(Intrin, 1083 { CI.getArgOperand(0), CI.getArgOperand(1) }); 1084 return EmitX86Select(Builder, CI.getArgOperand(3), Rep, CI.getArgOperand(2)); 1085 } 1086 1087 static Value* upgradeMaskedMove(IRBuilder<> &Builder, CallInst &CI) { 1088 Value* A = CI.getArgOperand(0); 1089 Value* B = CI.getArgOperand(1); 1090 Value* Src = CI.getArgOperand(2); 1091 Value* Mask = CI.getArgOperand(3); 1092 1093 Value* AndNode = Builder.CreateAnd(Mask, APInt(8, 1)); 1094 Value* Cmp = Builder.CreateIsNotNull(AndNode); 1095 Value* Extract1 = Builder.CreateExtractElement(B, (uint64_t)0); 1096 Value* Extract2 = Builder.CreateExtractElement(Src, (uint64_t)0); 1097 Value* Select = Builder.CreateSelect(Cmp, Extract1, Extract2); 1098 return Builder.CreateInsertElement(A, Select, (uint64_t)0); 1099 } 1100 1101 1102 static Value* UpgradeMaskToInt(IRBuilder<> &Builder, CallInst &CI) { 1103 Value* Op = CI.getArgOperand(0); 1104 Type* ReturnOp = CI.getType(); 1105 unsigned NumElts = CI.getType()->getVectorNumElements(); 1106 Value *Mask = getX86MaskVec(Builder, Op, NumElts); 1107 return Builder.CreateSExt(Mask, ReturnOp, "vpmovm2"); 1108 } 1109 1110 // Replace intrinsic with unmasked version and a select. 1111 static bool upgradeAVX512MaskToSelect(StringRef Name, IRBuilder<> &Builder, 1112 CallInst &CI, Value *&Rep) { 1113 Name = Name.substr(12); // Remove avx512.mask. 1114 1115 unsigned VecWidth = CI.getType()->getPrimitiveSizeInBits(); 1116 unsigned EltWidth = CI.getType()->getScalarSizeInBits(); 1117 Intrinsic::ID IID; 1118 if (Name.startswith("max.p")) { 1119 if (VecWidth == 128 && EltWidth == 32) 1120 IID = Intrinsic::x86_sse_max_ps; 1121 else if (VecWidth == 128 && EltWidth == 64) 1122 IID = Intrinsic::x86_sse2_max_pd; 1123 else if (VecWidth == 256 && EltWidth == 32) 1124 IID = Intrinsic::x86_avx_max_ps_256; 1125 else if (VecWidth == 256 && EltWidth == 64) 1126 IID = Intrinsic::x86_avx_max_pd_256; 1127 else 1128 llvm_unreachable("Unexpected intrinsic"); 1129 } else if (Name.startswith("min.p")) { 1130 if (VecWidth == 128 && EltWidth == 32) 1131 IID = Intrinsic::x86_sse_min_ps; 1132 else if (VecWidth == 128 && EltWidth == 64) 1133 IID = Intrinsic::x86_sse2_min_pd; 1134 else if (VecWidth == 256 && EltWidth == 32) 1135 IID = Intrinsic::x86_avx_min_ps_256; 1136 else if (VecWidth == 256 && EltWidth == 64) 1137 IID = Intrinsic::x86_avx_min_pd_256; 1138 else 1139 llvm_unreachable("Unexpected intrinsic"); 1140 } else if (Name.startswith("pshuf.b.")) { 1141 if (VecWidth == 128) 1142 IID = Intrinsic::x86_ssse3_pshuf_b_128; 1143 else if (VecWidth == 256) 1144 IID = Intrinsic::x86_avx2_pshuf_b; 1145 else if (VecWidth == 512) 1146 IID = Intrinsic::x86_avx512_pshuf_b_512; 1147 else 1148 llvm_unreachable("Unexpected intrinsic"); 1149 } else if (Name.startswith("pmul.hr.sw.")) { 1150 if (VecWidth == 128) 1151 IID = Intrinsic::x86_ssse3_pmul_hr_sw_128; 1152 else if (VecWidth == 256) 1153 IID = Intrinsic::x86_avx2_pmul_hr_sw; 1154 else if (VecWidth == 512) 1155 IID = Intrinsic::x86_avx512_pmul_hr_sw_512; 1156 else 1157 llvm_unreachable("Unexpected intrinsic"); 1158 } else if (Name.startswith("pmulh.w.")) { 1159 if (VecWidth == 128) 1160 IID = Intrinsic::x86_sse2_pmulh_w; 1161 else if (VecWidth == 256) 1162 IID = Intrinsic::x86_avx2_pmulh_w; 1163 else if (VecWidth == 512) 1164 IID = Intrinsic::x86_avx512_pmulh_w_512; 1165 else 1166 llvm_unreachable("Unexpected intrinsic"); 1167 } else if (Name.startswith("pmulhu.w.")) { 1168 if (VecWidth == 128) 1169 IID = Intrinsic::x86_sse2_pmulhu_w; 1170 else if (VecWidth == 256) 1171 IID = Intrinsic::x86_avx2_pmulhu_w; 1172 else if (VecWidth == 512) 1173 IID = Intrinsic::x86_avx512_pmulhu_w_512; 1174 else 1175 llvm_unreachable("Unexpected intrinsic"); 1176 } else if (Name.startswith("pmaddw.d.")) { 1177 if (VecWidth == 128) 1178 IID = Intrinsic::x86_sse2_pmadd_wd; 1179 else if (VecWidth == 256) 1180 IID = Intrinsic::x86_avx2_pmadd_wd; 1181 else if (VecWidth == 512) 1182 IID = Intrinsic::x86_avx512_pmaddw_d_512; 1183 else 1184 llvm_unreachable("Unexpected intrinsic"); 1185 } else if (Name.startswith("pmaddubs.w.")) { 1186 if (VecWidth == 128) 1187 IID = Intrinsic::x86_ssse3_pmadd_ub_sw_128; 1188 else if (VecWidth == 256) 1189 IID = Intrinsic::x86_avx2_pmadd_ub_sw; 1190 else if (VecWidth == 512) 1191 IID = Intrinsic::x86_avx512_pmaddubs_w_512; 1192 else 1193 llvm_unreachable("Unexpected intrinsic"); 1194 } else if (Name.startswith("packsswb.")) { 1195 if (VecWidth == 128) 1196 IID = Intrinsic::x86_sse2_packsswb_128; 1197 else if (VecWidth == 256) 1198 IID = Intrinsic::x86_avx2_packsswb; 1199 else if (VecWidth == 512) 1200 IID = Intrinsic::x86_avx512_packsswb_512; 1201 else 1202 llvm_unreachable("Unexpected intrinsic"); 1203 } else if (Name.startswith("packssdw.")) { 1204 if (VecWidth == 128) 1205 IID = Intrinsic::x86_sse2_packssdw_128; 1206 else if (VecWidth == 256) 1207 IID = Intrinsic::x86_avx2_packssdw; 1208 else if (VecWidth == 512) 1209 IID = Intrinsic::x86_avx512_packssdw_512; 1210 else 1211 llvm_unreachable("Unexpected intrinsic"); 1212 } else if (Name.startswith("packuswb.")) { 1213 if (VecWidth == 128) 1214 IID = Intrinsic::x86_sse2_packuswb_128; 1215 else if (VecWidth == 256) 1216 IID = Intrinsic::x86_avx2_packuswb; 1217 else if (VecWidth == 512) 1218 IID = Intrinsic::x86_avx512_packuswb_512; 1219 else 1220 llvm_unreachable("Unexpected intrinsic"); 1221 } else if (Name.startswith("packusdw.")) { 1222 if (VecWidth == 128) 1223 IID = Intrinsic::x86_sse41_packusdw; 1224 else if (VecWidth == 256) 1225 IID = Intrinsic::x86_avx2_packusdw; 1226 else if (VecWidth == 512) 1227 IID = Intrinsic::x86_avx512_packusdw_512; 1228 else 1229 llvm_unreachable("Unexpected intrinsic"); 1230 } else if (Name.startswith("vpermilvar.")) { 1231 if (VecWidth == 128 && EltWidth == 32) 1232 IID = Intrinsic::x86_avx_vpermilvar_ps; 1233 else if (VecWidth == 128 && EltWidth == 64) 1234 IID = Intrinsic::x86_avx_vpermilvar_pd; 1235 else if (VecWidth == 256 && EltWidth == 32) 1236 IID = Intrinsic::x86_avx_vpermilvar_ps_256; 1237 else if (VecWidth == 256 && EltWidth == 64) 1238 IID = Intrinsic::x86_avx_vpermilvar_pd_256; 1239 else if (VecWidth == 512 && EltWidth == 32) 1240 IID = Intrinsic::x86_avx512_vpermilvar_ps_512; 1241 else if (VecWidth == 512 && EltWidth == 64) 1242 IID = Intrinsic::x86_avx512_vpermilvar_pd_512; 1243 else 1244 llvm_unreachable("Unexpected intrinsic"); 1245 } else 1246 return false; 1247 1248 Rep = Builder.CreateCall(Intrinsic::getDeclaration(CI.getModule(), IID), 1249 { CI.getArgOperand(0), CI.getArgOperand(1) }); 1250 Rep = EmitX86Select(Builder, CI.getArgOperand(3), Rep, 1251 CI.getArgOperand(2)); 1252 return true; 1253 } 1254 1255 /// Upgrade comment in call to inline asm that represents an objc retain release 1256 /// marker. 1257 void llvm::UpgradeInlineAsmString(std::string *AsmStr) { 1258 1259 unsigned long Pos; 1260 if (AsmStr->find("mov\tfp") == 0 && 1261 AsmStr->find("objc_retainAutoreleaseReturnValue") != std::string::npos && 1262 (Pos = AsmStr->find("# marker")) != std::string::npos) { 1263 AsmStr->replace(Pos, 1, ";"); 1264 } 1265 return; 1266 } 1267 1268 /// Upgrade a call to an old intrinsic. All argument and return casting must be 1269 /// provided to seamlessly integrate with existing context. 1270 void llvm::UpgradeIntrinsicCall(CallInst *CI, Function *NewFn) { 1271 Function *F = CI->getCalledFunction(); 1272 LLVMContext &C = CI->getContext(); 1273 IRBuilder<> Builder(C); 1274 Builder.SetInsertPoint(CI->getParent(), CI->getIterator()); 1275 1276 assert(F && "Intrinsic call is not direct?"); 1277 1278 if (!NewFn) { 1279 // Get the Function's name. 1280 StringRef Name = F->getName(); 1281 1282 assert(Name.startswith("llvm.") && "Intrinsic doesn't start with 'llvm.'"); 1283 Name = Name.substr(5); 1284 1285 bool IsX86 = Name.startswith("x86."); 1286 if (IsX86) 1287 Name = Name.substr(4); 1288 bool IsNVVM = Name.startswith("nvvm."); 1289 if (IsNVVM) 1290 Name = Name.substr(5); 1291 1292 if (IsX86 && Name.startswith("sse4a.movnt.")) { 1293 Module *M = F->getParent(); 1294 SmallVector<Metadata *, 1> Elts; 1295 Elts.push_back( 1296 ConstantAsMetadata::get(ConstantInt::get(Type::getInt32Ty(C), 1))); 1297 MDNode *Node = MDNode::get(C, Elts); 1298 1299 Value *Arg0 = CI->getArgOperand(0); 1300 Value *Arg1 = CI->getArgOperand(1); 1301 1302 // Nontemporal (unaligned) store of the 0'th element of the float/double 1303 // vector. 1304 Type *SrcEltTy = cast<VectorType>(Arg1->getType())->getElementType(); 1305 PointerType *EltPtrTy = PointerType::getUnqual(SrcEltTy); 1306 Value *Addr = Builder.CreateBitCast(Arg0, EltPtrTy, "cast"); 1307 Value *Extract = 1308 Builder.CreateExtractElement(Arg1, (uint64_t)0, "extractelement"); 1309 1310 StoreInst *SI = Builder.CreateAlignedStore(Extract, Addr, 1); 1311 SI->setMetadata(M->getMDKindID("nontemporal"), Node); 1312 1313 // Remove intrinsic. 1314 CI->eraseFromParent(); 1315 return; 1316 } 1317 1318 if (IsX86 && (Name.startswith("avx.movnt.") || 1319 Name.startswith("avx512.storent."))) { 1320 Module *M = F->getParent(); 1321 SmallVector<Metadata *, 1> Elts; 1322 Elts.push_back( 1323 ConstantAsMetadata::get(ConstantInt::get(Type::getInt32Ty(C), 1))); 1324 MDNode *Node = MDNode::get(C, Elts); 1325 1326 Value *Arg0 = CI->getArgOperand(0); 1327 Value *Arg1 = CI->getArgOperand(1); 1328 1329 // Convert the type of the pointer to a pointer to the stored type. 1330 Value *BC = Builder.CreateBitCast(Arg0, 1331 PointerType::getUnqual(Arg1->getType()), 1332 "cast"); 1333 VectorType *VTy = cast<VectorType>(Arg1->getType()); 1334 StoreInst *SI = Builder.CreateAlignedStore(Arg1, BC, 1335 VTy->getBitWidth() / 8); 1336 SI->setMetadata(M->getMDKindID("nontemporal"), Node); 1337 1338 // Remove intrinsic. 1339 CI->eraseFromParent(); 1340 return; 1341 } 1342 1343 if (IsX86 && Name == "sse2.storel.dq") { 1344 Value *Arg0 = CI->getArgOperand(0); 1345 Value *Arg1 = CI->getArgOperand(1); 1346 1347 Type *NewVecTy = VectorType::get(Type::getInt64Ty(C), 2); 1348 Value *BC0 = Builder.CreateBitCast(Arg1, NewVecTy, "cast"); 1349 Value *Elt = Builder.CreateExtractElement(BC0, (uint64_t)0); 1350 Value *BC = Builder.CreateBitCast(Arg0, 1351 PointerType::getUnqual(Elt->getType()), 1352 "cast"); 1353 Builder.CreateAlignedStore(Elt, BC, 1); 1354 1355 // Remove intrinsic. 1356 CI->eraseFromParent(); 1357 return; 1358 } 1359 1360 if (IsX86 && (Name.startswith("sse.storeu.") || 1361 Name.startswith("sse2.storeu.") || 1362 Name.startswith("avx.storeu."))) { 1363 Value *Arg0 = CI->getArgOperand(0); 1364 Value *Arg1 = CI->getArgOperand(1); 1365 1366 Arg0 = Builder.CreateBitCast(Arg0, 1367 PointerType::getUnqual(Arg1->getType()), 1368 "cast"); 1369 Builder.CreateAlignedStore(Arg1, Arg0, 1); 1370 1371 // Remove intrinsic. 1372 CI->eraseFromParent(); 1373 return; 1374 } 1375 1376 if (IsX86 && (Name.startswith("avx512.mask.store"))) { 1377 // "avx512.mask.storeu." or "avx512.mask.store." 1378 bool Aligned = Name[17] != 'u'; // "avx512.mask.storeu". 1379 UpgradeMaskedStore(Builder, CI->getArgOperand(0), CI->getArgOperand(1), 1380 CI->getArgOperand(2), Aligned); 1381 1382 // Remove intrinsic. 1383 CI->eraseFromParent(); 1384 return; 1385 } 1386 1387 Value *Rep; 1388 // Upgrade packed integer vector compare intrinsics to compare instructions. 1389 if (IsX86 && (Name.startswith("sse2.pcmp") || 1390 Name.startswith("avx2.pcmp"))) { 1391 // "sse2.pcpmpeq." "sse2.pcmpgt." "avx2.pcmpeq." or "avx2.pcmpgt." 1392 bool CmpEq = Name[9] == 'e'; 1393 Rep = Builder.CreateICmp(CmpEq ? ICmpInst::ICMP_EQ : ICmpInst::ICMP_SGT, 1394 CI->getArgOperand(0), CI->getArgOperand(1)); 1395 Rep = Builder.CreateSExt(Rep, CI->getType(), ""); 1396 } else if (IsX86 && (Name.startswith("avx512.broadcastm"))) { 1397 Type *ExtTy = Type::getInt32Ty(C); 1398 if (CI->getOperand(0)->getType()->isIntegerTy(8)) 1399 ExtTy = Type::getInt64Ty(C); 1400 unsigned NumElts = CI->getType()->getPrimitiveSizeInBits() / 1401 ExtTy->getPrimitiveSizeInBits(); 1402 Rep = Builder.CreateZExt(CI->getArgOperand(0), ExtTy); 1403 Rep = Builder.CreateVectorSplat(NumElts, Rep); 1404 } else if (IsX86 && (Name.startswith("avx512.ptestm") || 1405 Name.startswith("avx512.ptestnm"))) { 1406 Value *Op0 = CI->getArgOperand(0); 1407 Value *Op1 = CI->getArgOperand(1); 1408 Value *Mask = CI->getArgOperand(2); 1409 Rep = Builder.CreateAnd(Op0, Op1); 1410 llvm::Type *Ty = Op0->getType(); 1411 Value *Zero = llvm::Constant::getNullValue(Ty); 1412 ICmpInst::Predicate Pred = 1413 Name.startswith("avx512.ptestm") ? ICmpInst::ICMP_NE : ICmpInst::ICMP_EQ; 1414 Rep = Builder.CreateICmp(Pred, Rep, Zero); 1415 unsigned NumElts = Op0->getType()->getVectorNumElements(); 1416 Rep = ApplyX86MaskOn1BitsVec(Builder, Rep, Mask, NumElts); 1417 } else if (IsX86 && (Name.startswith("avx512.mask.pbroadcast"))){ 1418 unsigned NumElts = 1419 CI->getArgOperand(1)->getType()->getVectorNumElements(); 1420 Rep = Builder.CreateVectorSplat(NumElts, CI->getArgOperand(0)); 1421 Rep = EmitX86Select(Builder, CI->getArgOperand(2), Rep, 1422 CI->getArgOperand(1)); 1423 } else if (IsX86 && (Name.startswith("avx512.kunpck"))) { 1424 unsigned NumElts = CI->getType()->getScalarSizeInBits(); 1425 Value *LHS = getX86MaskVec(Builder, CI->getArgOperand(0), NumElts); 1426 Value *RHS = getX86MaskVec(Builder, CI->getArgOperand(1), NumElts); 1427 uint32_t Indices[64]; 1428 for (unsigned i = 0; i != NumElts; ++i) 1429 Indices[i] = i; 1430 1431 // First extract half of each vector. This gives better codegen than 1432 // doing it in a single shuffle. 1433 LHS = Builder.CreateShuffleVector(LHS, LHS, 1434 makeArrayRef(Indices, NumElts / 2)); 1435 RHS = Builder.CreateShuffleVector(RHS, RHS, 1436 makeArrayRef(Indices, NumElts / 2)); 1437 // Concat the vectors. 1438 // NOTE: Operands have to be swapped to match intrinsic definition. 1439 Rep = Builder.CreateShuffleVector(RHS, LHS, 1440 makeArrayRef(Indices, NumElts)); 1441 Rep = Builder.CreateBitCast(Rep, CI->getType()); 1442 } else if (IsX86 && Name == "avx512.kand.w") { 1443 Value *LHS = getX86MaskVec(Builder, CI->getArgOperand(0), 16); 1444 Value *RHS = getX86MaskVec(Builder, CI->getArgOperand(1), 16); 1445 Rep = Builder.CreateAnd(LHS, RHS); 1446 Rep = Builder.CreateBitCast(Rep, CI->getType()); 1447 } else if (IsX86 && Name == "avx512.kandn.w") { 1448 Value *LHS = getX86MaskVec(Builder, CI->getArgOperand(0), 16); 1449 Value *RHS = getX86MaskVec(Builder, CI->getArgOperand(1), 16); 1450 LHS = Builder.CreateNot(LHS); 1451 Rep = Builder.CreateAnd(LHS, RHS); 1452 Rep = Builder.CreateBitCast(Rep, CI->getType()); 1453 } else if (IsX86 && Name == "avx512.kor.w") { 1454 Value *LHS = getX86MaskVec(Builder, CI->getArgOperand(0), 16); 1455 Value *RHS = getX86MaskVec(Builder, CI->getArgOperand(1), 16); 1456 Rep = Builder.CreateOr(LHS, RHS); 1457 Rep = Builder.CreateBitCast(Rep, CI->getType()); 1458 } else if (IsX86 && Name == "avx512.kxor.w") { 1459 Value *LHS = getX86MaskVec(Builder, CI->getArgOperand(0), 16); 1460 Value *RHS = getX86MaskVec(Builder, CI->getArgOperand(1), 16); 1461 Rep = Builder.CreateXor(LHS, RHS); 1462 Rep = Builder.CreateBitCast(Rep, CI->getType()); 1463 } else if (IsX86 && Name == "avx512.kxnor.w") { 1464 Value *LHS = getX86MaskVec(Builder, CI->getArgOperand(0), 16); 1465 Value *RHS = getX86MaskVec(Builder, CI->getArgOperand(1), 16); 1466 LHS = Builder.CreateNot(LHS); 1467 Rep = Builder.CreateXor(LHS, RHS); 1468 Rep = Builder.CreateBitCast(Rep, CI->getType()); 1469 } else if (IsX86 && Name == "avx512.knot.w") { 1470 Rep = getX86MaskVec(Builder, CI->getArgOperand(0), 16); 1471 Rep = Builder.CreateNot(Rep); 1472 Rep = Builder.CreateBitCast(Rep, CI->getType()); 1473 } else if (IsX86 && 1474 (Name == "avx512.kortestz.w" || Name == "avx512.kortestc.w")) { 1475 Value *LHS = getX86MaskVec(Builder, CI->getArgOperand(0), 16); 1476 Value *RHS = getX86MaskVec(Builder, CI->getArgOperand(1), 16); 1477 Rep = Builder.CreateOr(LHS, RHS); 1478 Rep = Builder.CreateBitCast(Rep, Builder.getInt16Ty()); 1479 Value *C; 1480 if (Name[14] == 'c') 1481 C = ConstantInt::getAllOnesValue(Builder.getInt16Ty()); 1482 else 1483 C = ConstantInt::getNullValue(Builder.getInt16Ty()); 1484 Rep = Builder.CreateICmpEQ(Rep, C); 1485 Rep = Builder.CreateZExt(Rep, Builder.getInt32Ty()); 1486 } else if (IsX86 && (Name == "sse.add.ss" || Name == "sse2.add.sd")) { 1487 Type *I32Ty = Type::getInt32Ty(C); 1488 Value *Elt0 = Builder.CreateExtractElement(CI->getArgOperand(0), 1489 ConstantInt::get(I32Ty, 0)); 1490 Value *Elt1 = Builder.CreateExtractElement(CI->getArgOperand(1), 1491 ConstantInt::get(I32Ty, 0)); 1492 Rep = Builder.CreateInsertElement(CI->getArgOperand(0), 1493 Builder.CreateFAdd(Elt0, Elt1), 1494 ConstantInt::get(I32Ty, 0)); 1495 } else if (IsX86 && (Name == "sse.sub.ss" || Name == "sse2.sub.sd")) { 1496 Type *I32Ty = Type::getInt32Ty(C); 1497 Value *Elt0 = Builder.CreateExtractElement(CI->getArgOperand(0), 1498 ConstantInt::get(I32Ty, 0)); 1499 Value *Elt1 = Builder.CreateExtractElement(CI->getArgOperand(1), 1500 ConstantInt::get(I32Ty, 0)); 1501 Rep = Builder.CreateInsertElement(CI->getArgOperand(0), 1502 Builder.CreateFSub(Elt0, Elt1), 1503 ConstantInt::get(I32Ty, 0)); 1504 } else if (IsX86 && (Name == "sse.mul.ss" || Name == "sse2.mul.sd")) { 1505 Type *I32Ty = Type::getInt32Ty(C); 1506 Value *Elt0 = Builder.CreateExtractElement(CI->getArgOperand(0), 1507 ConstantInt::get(I32Ty, 0)); 1508 Value *Elt1 = Builder.CreateExtractElement(CI->getArgOperand(1), 1509 ConstantInt::get(I32Ty, 0)); 1510 Rep = Builder.CreateInsertElement(CI->getArgOperand(0), 1511 Builder.CreateFMul(Elt0, Elt1), 1512 ConstantInt::get(I32Ty, 0)); 1513 } else if (IsX86 && (Name == "sse.div.ss" || Name == "sse2.div.sd")) { 1514 Type *I32Ty = Type::getInt32Ty(C); 1515 Value *Elt0 = Builder.CreateExtractElement(CI->getArgOperand(0), 1516 ConstantInt::get(I32Ty, 0)); 1517 Value *Elt1 = Builder.CreateExtractElement(CI->getArgOperand(1), 1518 ConstantInt::get(I32Ty, 0)); 1519 Rep = Builder.CreateInsertElement(CI->getArgOperand(0), 1520 Builder.CreateFDiv(Elt0, Elt1), 1521 ConstantInt::get(I32Ty, 0)); 1522 } else if (IsX86 && Name.startswith("avx512.mask.pcmp")) { 1523 // "avx512.mask.pcmpeq." or "avx512.mask.pcmpgt." 1524 bool CmpEq = Name[16] == 'e'; 1525 Rep = upgradeMaskedCompare(Builder, *CI, CmpEq ? 0 : 6, true); 1526 } else if (IsX86 && Name.startswith("avx512.mask.cmp")) { 1527 unsigned Imm = cast<ConstantInt>(CI->getArgOperand(2))->getZExtValue(); 1528 Rep = upgradeMaskedCompare(Builder, *CI, Imm, true); 1529 } else if (IsX86 && Name.startswith("avx512.mask.ucmp")) { 1530 unsigned Imm = cast<ConstantInt>(CI->getArgOperand(2))->getZExtValue(); 1531 Rep = upgradeMaskedCompare(Builder, *CI, Imm, false); 1532 } else if (IsX86 && (Name.startswith("avx512.cvtb2mask.") || 1533 Name.startswith("avx512.cvtw2mask.") || 1534 Name.startswith("avx512.cvtd2mask.") || 1535 Name.startswith("avx512.cvtq2mask."))) { 1536 Value *Op = CI->getArgOperand(0); 1537 Value *Zero = llvm::Constant::getNullValue(Op->getType()); 1538 Rep = Builder.CreateICmp(ICmpInst::ICMP_SLT, Op, Zero); 1539 Rep = ApplyX86MaskOn1BitsVec(Builder, Rep, nullptr, 1540 Op->getType()->getVectorNumElements()); 1541 } else if(IsX86 && (Name == "ssse3.pabs.b.128" || 1542 Name == "ssse3.pabs.w.128" || 1543 Name == "ssse3.pabs.d.128" || 1544 Name.startswith("avx2.pabs") || 1545 Name.startswith("avx512.mask.pabs"))) { 1546 Rep = upgradeAbs(Builder, *CI); 1547 } else if (IsX86 && (Name == "sse41.pmaxsb" || 1548 Name == "sse2.pmaxs.w" || 1549 Name == "sse41.pmaxsd" || 1550 Name.startswith("avx2.pmaxs") || 1551 Name.startswith("avx512.mask.pmaxs"))) { 1552 Rep = upgradeIntMinMax(Builder, *CI, ICmpInst::ICMP_SGT); 1553 } else if (IsX86 && (Name == "sse2.pmaxu.b" || 1554 Name == "sse41.pmaxuw" || 1555 Name == "sse41.pmaxud" || 1556 Name.startswith("avx2.pmaxu") || 1557 Name.startswith("avx512.mask.pmaxu"))) { 1558 Rep = upgradeIntMinMax(Builder, *CI, ICmpInst::ICMP_UGT); 1559 } else if (IsX86 && (Name == "sse41.pminsb" || 1560 Name == "sse2.pmins.w" || 1561 Name == "sse41.pminsd" || 1562 Name.startswith("avx2.pmins") || 1563 Name.startswith("avx512.mask.pmins"))) { 1564 Rep = upgradeIntMinMax(Builder, *CI, ICmpInst::ICMP_SLT); 1565 } else if (IsX86 && (Name == "sse2.pminu.b" || 1566 Name == "sse41.pminuw" || 1567 Name == "sse41.pminud" || 1568 Name.startswith("avx2.pminu") || 1569 Name.startswith("avx512.mask.pminu"))) { 1570 Rep = upgradeIntMinMax(Builder, *CI, ICmpInst::ICMP_ULT); 1571 } else if (IsX86 && (Name == "sse2.pmulu.dq" || 1572 Name == "avx2.pmulu.dq" || 1573 Name == "avx512.pmulu.dq.512" || 1574 Name.startswith("avx512.mask.pmulu.dq."))) { 1575 Rep = upgradePMULDQ(Builder, *CI, /*Signed*/false); 1576 } else if (IsX86 && (Name == "sse41.pmuldq" || 1577 Name == "avx2.pmul.dq" || 1578 Name == "avx512.pmul.dq.512" || 1579 Name.startswith("avx512.mask.pmul.dq."))) { 1580 Rep = upgradePMULDQ(Builder, *CI, /*Signed*/true); 1581 } else if (IsX86 && (Name == "sse2.cvtdq2pd" || 1582 Name == "sse2.cvtps2pd" || 1583 Name == "avx.cvtdq2.pd.256" || 1584 Name == "avx.cvt.ps2.pd.256" || 1585 Name.startswith("avx512.mask.cvtdq2pd.") || 1586 Name.startswith("avx512.mask.cvtudq2pd."))) { 1587 // Lossless i32/float to double conversion. 1588 // Extract the bottom elements if necessary and convert to double vector. 1589 Value *Src = CI->getArgOperand(0); 1590 VectorType *SrcTy = cast<VectorType>(Src->getType()); 1591 VectorType *DstTy = cast<VectorType>(CI->getType()); 1592 Rep = CI->getArgOperand(0); 1593 1594 unsigned NumDstElts = DstTy->getNumElements(); 1595 if (NumDstElts < SrcTy->getNumElements()) { 1596 assert(NumDstElts == 2 && "Unexpected vector size"); 1597 uint32_t ShuffleMask[2] = { 0, 1 }; 1598 Rep = Builder.CreateShuffleVector(Rep, UndefValue::get(SrcTy), 1599 ShuffleMask); 1600 } 1601 1602 bool SInt2Double = (StringRef::npos != Name.find("cvtdq2")); 1603 bool UInt2Double = (StringRef::npos != Name.find("cvtudq2")); 1604 if (SInt2Double) 1605 Rep = Builder.CreateSIToFP(Rep, DstTy, "cvtdq2pd"); 1606 else if (UInt2Double) 1607 Rep = Builder.CreateUIToFP(Rep, DstTy, "cvtudq2pd"); 1608 else 1609 Rep = Builder.CreateFPExt(Rep, DstTy, "cvtps2pd"); 1610 1611 if (CI->getNumArgOperands() == 3) 1612 Rep = EmitX86Select(Builder, CI->getArgOperand(2), Rep, 1613 CI->getArgOperand(1)); 1614 } else if (IsX86 && (Name.startswith("avx512.mask.loadu."))) { 1615 Rep = UpgradeMaskedLoad(Builder, CI->getArgOperand(0), 1616 CI->getArgOperand(1), CI->getArgOperand(2), 1617 /*Aligned*/false); 1618 } else if (IsX86 && (Name.startswith("avx512.mask.load."))) { 1619 Rep = UpgradeMaskedLoad(Builder, CI->getArgOperand(0), 1620 CI->getArgOperand(1),CI->getArgOperand(2), 1621 /*Aligned*/true); 1622 } else if (IsX86 && Name.startswith("xop.vpcom")) { 1623 Intrinsic::ID intID; 1624 if (Name.endswith("ub")) 1625 intID = Intrinsic::x86_xop_vpcomub; 1626 else if (Name.endswith("uw")) 1627 intID = Intrinsic::x86_xop_vpcomuw; 1628 else if (Name.endswith("ud")) 1629 intID = Intrinsic::x86_xop_vpcomud; 1630 else if (Name.endswith("uq")) 1631 intID = Intrinsic::x86_xop_vpcomuq; 1632 else if (Name.endswith("b")) 1633 intID = Intrinsic::x86_xop_vpcomb; 1634 else if (Name.endswith("w")) 1635 intID = Intrinsic::x86_xop_vpcomw; 1636 else if (Name.endswith("d")) 1637 intID = Intrinsic::x86_xop_vpcomd; 1638 else if (Name.endswith("q")) 1639 intID = Intrinsic::x86_xop_vpcomq; 1640 else 1641 llvm_unreachable("Unknown suffix"); 1642 1643 Name = Name.substr(9); // strip off "xop.vpcom" 1644 unsigned Imm; 1645 if (Name.startswith("lt")) 1646 Imm = 0; 1647 else if (Name.startswith("le")) 1648 Imm = 1; 1649 else if (Name.startswith("gt")) 1650 Imm = 2; 1651 else if (Name.startswith("ge")) 1652 Imm = 3; 1653 else if (Name.startswith("eq")) 1654 Imm = 4; 1655 else if (Name.startswith("ne")) 1656 Imm = 5; 1657 else if (Name.startswith("false")) 1658 Imm = 6; 1659 else if (Name.startswith("true")) 1660 Imm = 7; 1661 else 1662 llvm_unreachable("Unknown condition"); 1663 1664 Function *VPCOM = Intrinsic::getDeclaration(F->getParent(), intID); 1665 Rep = 1666 Builder.CreateCall(VPCOM, {CI->getArgOperand(0), CI->getArgOperand(1), 1667 Builder.getInt8(Imm)}); 1668 } else if (IsX86 && Name.startswith("xop.vpcmov")) { 1669 Value *Sel = CI->getArgOperand(2); 1670 Value *NotSel = Builder.CreateNot(Sel); 1671 Value *Sel0 = Builder.CreateAnd(CI->getArgOperand(0), Sel); 1672 Value *Sel1 = Builder.CreateAnd(CI->getArgOperand(1), NotSel); 1673 Rep = Builder.CreateOr(Sel0, Sel1); 1674 } else if (IsX86 && Name == "sse42.crc32.64.8") { 1675 Function *CRC32 = Intrinsic::getDeclaration(F->getParent(), 1676 Intrinsic::x86_sse42_crc32_32_8); 1677 Value *Trunc0 = Builder.CreateTrunc(CI->getArgOperand(0), Type::getInt32Ty(C)); 1678 Rep = Builder.CreateCall(CRC32, {Trunc0, CI->getArgOperand(1)}); 1679 Rep = Builder.CreateZExt(Rep, CI->getType(), ""); 1680 } else if (IsX86 && Name.startswith("avx.vbroadcast.s")) { 1681 // Replace broadcasts with a series of insertelements. 1682 Type *VecTy = CI->getType(); 1683 Type *EltTy = VecTy->getVectorElementType(); 1684 unsigned EltNum = VecTy->getVectorNumElements(); 1685 Value *Cast = Builder.CreateBitCast(CI->getArgOperand(0), 1686 EltTy->getPointerTo()); 1687 Value *Load = Builder.CreateLoad(EltTy, Cast); 1688 Type *I32Ty = Type::getInt32Ty(C); 1689 Rep = UndefValue::get(VecTy); 1690 for (unsigned I = 0; I < EltNum; ++I) 1691 Rep = Builder.CreateInsertElement(Rep, Load, 1692 ConstantInt::get(I32Ty, I)); 1693 } else if (IsX86 && (Name.startswith("sse41.pmovsx") || 1694 Name.startswith("sse41.pmovzx") || 1695 Name.startswith("avx2.pmovsx") || 1696 Name.startswith("avx2.pmovzx") || 1697 Name.startswith("avx512.mask.pmovsx") || 1698 Name.startswith("avx512.mask.pmovzx"))) { 1699 VectorType *SrcTy = cast<VectorType>(CI->getArgOperand(0)->getType()); 1700 VectorType *DstTy = cast<VectorType>(CI->getType()); 1701 unsigned NumDstElts = DstTy->getNumElements(); 1702 1703 // Extract a subvector of the first NumDstElts lanes and sign/zero extend. 1704 SmallVector<uint32_t, 8> ShuffleMask(NumDstElts); 1705 for (unsigned i = 0; i != NumDstElts; ++i) 1706 ShuffleMask[i] = i; 1707 1708 Value *SV = Builder.CreateShuffleVector( 1709 CI->getArgOperand(0), UndefValue::get(SrcTy), ShuffleMask); 1710 1711 bool DoSext = (StringRef::npos != Name.find("pmovsx")); 1712 Rep = DoSext ? Builder.CreateSExt(SV, DstTy) 1713 : Builder.CreateZExt(SV, DstTy); 1714 // If there are 3 arguments, it's a masked intrinsic so we need a select. 1715 if (CI->getNumArgOperands() == 3) 1716 Rep = EmitX86Select(Builder, CI->getArgOperand(2), Rep, 1717 CI->getArgOperand(1)); 1718 } else if (IsX86 && (Name.startswith("avx.vbroadcastf128") || 1719 Name == "avx2.vbroadcasti128")) { 1720 // Replace vbroadcastf128/vbroadcasti128 with a vector load+shuffle. 1721 Type *EltTy = CI->getType()->getVectorElementType(); 1722 unsigned NumSrcElts = 128 / EltTy->getPrimitiveSizeInBits(); 1723 Type *VT = VectorType::get(EltTy, NumSrcElts); 1724 Value *Op = Builder.CreatePointerCast(CI->getArgOperand(0), 1725 PointerType::getUnqual(VT)); 1726 Value *Load = Builder.CreateAlignedLoad(Op, 1); 1727 if (NumSrcElts == 2) 1728 Rep = Builder.CreateShuffleVector(Load, UndefValue::get(Load->getType()), 1729 { 0, 1, 0, 1 }); 1730 else 1731 Rep = Builder.CreateShuffleVector(Load, UndefValue::get(Load->getType()), 1732 { 0, 1, 2, 3, 0, 1, 2, 3 }); 1733 } else if (IsX86 && (Name.startswith("avx512.mask.shuf.i") || 1734 Name.startswith("avx512.mask.shuf.f"))) { 1735 unsigned Imm = cast<ConstantInt>(CI->getArgOperand(2))->getZExtValue(); 1736 Type *VT = CI->getType(); 1737 unsigned NumLanes = VT->getPrimitiveSizeInBits() / 128; 1738 unsigned NumElementsInLane = 128 / VT->getScalarSizeInBits(); 1739 unsigned ControlBitsMask = NumLanes - 1; 1740 unsigned NumControlBits = NumLanes / 2; 1741 SmallVector<uint32_t, 8> ShuffleMask(0); 1742 1743 for (unsigned l = 0; l != NumLanes; ++l) { 1744 unsigned LaneMask = (Imm >> (l * NumControlBits)) & ControlBitsMask; 1745 // We actually need the other source. 1746 if (l >= NumLanes / 2) 1747 LaneMask += NumLanes; 1748 for (unsigned i = 0; i != NumElementsInLane; ++i) 1749 ShuffleMask.push_back(LaneMask * NumElementsInLane + i); 1750 } 1751 Rep = Builder.CreateShuffleVector(CI->getArgOperand(0), 1752 CI->getArgOperand(1), ShuffleMask); 1753 Rep = EmitX86Select(Builder, CI->getArgOperand(4), Rep, 1754 CI->getArgOperand(3)); 1755 }else if (IsX86 && (Name.startswith("avx512.mask.broadcastf") || 1756 Name.startswith("avx512.mask.broadcasti"))) { 1757 unsigned NumSrcElts = 1758 CI->getArgOperand(0)->getType()->getVectorNumElements(); 1759 unsigned NumDstElts = CI->getType()->getVectorNumElements(); 1760 1761 SmallVector<uint32_t, 8> ShuffleMask(NumDstElts); 1762 for (unsigned i = 0; i != NumDstElts; ++i) 1763 ShuffleMask[i] = i % NumSrcElts; 1764 1765 Rep = Builder.CreateShuffleVector(CI->getArgOperand(0), 1766 CI->getArgOperand(0), 1767 ShuffleMask); 1768 Rep = EmitX86Select(Builder, CI->getArgOperand(2), Rep, 1769 CI->getArgOperand(1)); 1770 } else if (IsX86 && (Name.startswith("sse2.padds") || 1771 Name.startswith("avx2.padds") || 1772 Name.startswith("avx512.mask.padds"))) { 1773 Rep = UpgradeX86AddSubSatIntrinsics(Builder, *CI, 1774 true, true); // Signed add. 1775 } else if (IsX86 && (Name.startswith("sse2.paddus") || 1776 Name.startswith("avx2.paddus") || 1777 Name.startswith("avx512.mask.paddus"))) { 1778 Rep = UpgradeX86AddSubSatIntrinsics(Builder, *CI, 1779 false, true); // Unsigned add. 1780 } else if (IsX86 && (Name.startswith("sse2.psubs") || 1781 Name.startswith("avx2.psubs") || 1782 Name.startswith("avx512.mask.psubs"))) { 1783 Rep = UpgradeX86AddSubSatIntrinsics(Builder, *CI, 1784 true, false); // Signed sub. 1785 } else if (IsX86 && (Name.startswith("sse2.psubus") || 1786 Name.startswith("avx2.psubus") || 1787 Name.startswith("avx512.mask.psubus"))) { 1788 Rep = UpgradeX86AddSubSatIntrinsics(Builder, *CI, 1789 false, false); // Unsigned sub. 1790 } else if (IsX86 && (Name.startswith("avx2.pbroadcast") || 1791 Name.startswith("avx2.vbroadcast") || 1792 Name.startswith("avx512.pbroadcast") || 1793 Name.startswith("avx512.mask.broadcast.s"))) { 1794 // Replace vp?broadcasts with a vector shuffle. 1795 Value *Op = CI->getArgOperand(0); 1796 unsigned NumElts = CI->getType()->getVectorNumElements(); 1797 Type *MaskTy = VectorType::get(Type::getInt32Ty(C), NumElts); 1798 Rep = Builder.CreateShuffleVector(Op, UndefValue::get(Op->getType()), 1799 Constant::getNullValue(MaskTy)); 1800 if (CI->getNumArgOperands() == 3) 1801 Rep = EmitX86Select(Builder, CI->getArgOperand(2), Rep, 1802 CI->getArgOperand(1)); 1803 } else if (IsX86 && Name.startswith("avx512.mask.palignr.")) { 1804 Rep = UpgradeX86ALIGNIntrinsics(Builder, CI->getArgOperand(0), 1805 CI->getArgOperand(1), 1806 CI->getArgOperand(2), 1807 CI->getArgOperand(3), 1808 CI->getArgOperand(4), 1809 false); 1810 } else if (IsX86 && Name.startswith("avx512.mask.valign.")) { 1811 Rep = UpgradeX86ALIGNIntrinsics(Builder, CI->getArgOperand(0), 1812 CI->getArgOperand(1), 1813 CI->getArgOperand(2), 1814 CI->getArgOperand(3), 1815 CI->getArgOperand(4), 1816 true); 1817 } else if (IsX86 && (Name == "sse2.psll.dq" || 1818 Name == "avx2.psll.dq")) { 1819 // 128/256-bit shift left specified in bits. 1820 unsigned Shift = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue(); 1821 Rep = UpgradeX86PSLLDQIntrinsics(Builder, CI->getArgOperand(0), 1822 Shift / 8); // Shift is in bits. 1823 } else if (IsX86 && (Name == "sse2.psrl.dq" || 1824 Name == "avx2.psrl.dq")) { 1825 // 128/256-bit shift right specified in bits. 1826 unsigned Shift = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue(); 1827 Rep = UpgradeX86PSRLDQIntrinsics(Builder, CI->getArgOperand(0), 1828 Shift / 8); // Shift is in bits. 1829 } else if (IsX86 && (Name == "sse2.psll.dq.bs" || 1830 Name == "avx2.psll.dq.bs" || 1831 Name == "avx512.psll.dq.512")) { 1832 // 128/256/512-bit shift left specified in bytes. 1833 unsigned Shift = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue(); 1834 Rep = UpgradeX86PSLLDQIntrinsics(Builder, CI->getArgOperand(0), Shift); 1835 } else if (IsX86 && (Name == "sse2.psrl.dq.bs" || 1836 Name == "avx2.psrl.dq.bs" || 1837 Name == "avx512.psrl.dq.512")) { 1838 // 128/256/512-bit shift right specified in bytes. 1839 unsigned Shift = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue(); 1840 Rep = UpgradeX86PSRLDQIntrinsics(Builder, CI->getArgOperand(0), Shift); 1841 } else if (IsX86 && (Name == "sse41.pblendw" || 1842 Name.startswith("sse41.blendp") || 1843 Name.startswith("avx.blend.p") || 1844 Name == "avx2.pblendw" || 1845 Name.startswith("avx2.pblendd."))) { 1846 Value *Op0 = CI->getArgOperand(0); 1847 Value *Op1 = CI->getArgOperand(1); 1848 unsigned Imm = cast <ConstantInt>(CI->getArgOperand(2))->getZExtValue(); 1849 VectorType *VecTy = cast<VectorType>(CI->getType()); 1850 unsigned NumElts = VecTy->getNumElements(); 1851 1852 SmallVector<uint32_t, 16> Idxs(NumElts); 1853 for (unsigned i = 0; i != NumElts; ++i) 1854 Idxs[i] = ((Imm >> (i%8)) & 1) ? i + NumElts : i; 1855 1856 Rep = Builder.CreateShuffleVector(Op0, Op1, Idxs); 1857 } else if (IsX86 && (Name.startswith("avx.vinsertf128.") || 1858 Name == "avx2.vinserti128" || 1859 Name.startswith("avx512.mask.insert"))) { 1860 Value *Op0 = CI->getArgOperand(0); 1861 Value *Op1 = CI->getArgOperand(1); 1862 unsigned Imm = cast<ConstantInt>(CI->getArgOperand(2))->getZExtValue(); 1863 unsigned DstNumElts = CI->getType()->getVectorNumElements(); 1864 unsigned SrcNumElts = Op1->getType()->getVectorNumElements(); 1865 unsigned Scale = DstNumElts / SrcNumElts; 1866 1867 // Mask off the high bits of the immediate value; hardware ignores those. 1868 Imm = Imm % Scale; 1869 1870 // Extend the second operand into a vector the size of the destination. 1871 Value *UndefV = UndefValue::get(Op1->getType()); 1872 SmallVector<uint32_t, 8> Idxs(DstNumElts); 1873 for (unsigned i = 0; i != SrcNumElts; ++i) 1874 Idxs[i] = i; 1875 for (unsigned i = SrcNumElts; i != DstNumElts; ++i) 1876 Idxs[i] = SrcNumElts; 1877 Rep = Builder.CreateShuffleVector(Op1, UndefV, Idxs); 1878 1879 // Insert the second operand into the first operand. 1880 1881 // Note that there is no guarantee that instruction lowering will actually 1882 // produce a vinsertf128 instruction for the created shuffles. In 1883 // particular, the 0 immediate case involves no lane changes, so it can 1884 // be handled as a blend. 1885 1886 // Example of shuffle mask for 32-bit elements: 1887 // Imm = 1 <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11> 1888 // Imm = 0 <i32 8, i32 9, i32 10, i32 11, i32 4, i32 5, i32 6, i32 7 > 1889 1890 // First fill with identify mask. 1891 for (unsigned i = 0; i != DstNumElts; ++i) 1892 Idxs[i] = i; 1893 // Then replace the elements where we need to insert. 1894 for (unsigned i = 0; i != SrcNumElts; ++i) 1895 Idxs[i + Imm * SrcNumElts] = i + DstNumElts; 1896 Rep = Builder.CreateShuffleVector(Op0, Rep, Idxs); 1897 1898 // If the intrinsic has a mask operand, handle that. 1899 if (CI->getNumArgOperands() == 5) 1900 Rep = EmitX86Select(Builder, CI->getArgOperand(4), Rep, 1901 CI->getArgOperand(3)); 1902 } else if (IsX86 && (Name.startswith("avx.vextractf128.") || 1903 Name == "avx2.vextracti128" || 1904 Name.startswith("avx512.mask.vextract"))) { 1905 Value *Op0 = CI->getArgOperand(0); 1906 unsigned Imm = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue(); 1907 unsigned DstNumElts = CI->getType()->getVectorNumElements(); 1908 unsigned SrcNumElts = Op0->getType()->getVectorNumElements(); 1909 unsigned Scale = SrcNumElts / DstNumElts; 1910 1911 // Mask off the high bits of the immediate value; hardware ignores those. 1912 Imm = Imm % Scale; 1913 1914 // Get indexes for the subvector of the input vector. 1915 SmallVector<uint32_t, 8> Idxs(DstNumElts); 1916 for (unsigned i = 0; i != DstNumElts; ++i) { 1917 Idxs[i] = i + (Imm * DstNumElts); 1918 } 1919 Rep = Builder.CreateShuffleVector(Op0, Op0, Idxs); 1920 1921 // If the intrinsic has a mask operand, handle that. 1922 if (CI->getNumArgOperands() == 4) 1923 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1924 CI->getArgOperand(2)); 1925 } else if (!IsX86 && Name == "stackprotectorcheck") { 1926 Rep = nullptr; 1927 } else if (IsX86 && (Name.startswith("avx512.mask.perm.df.") || 1928 Name.startswith("avx512.mask.perm.di."))) { 1929 Value *Op0 = CI->getArgOperand(0); 1930 unsigned Imm = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue(); 1931 VectorType *VecTy = cast<VectorType>(CI->getType()); 1932 unsigned NumElts = VecTy->getNumElements(); 1933 1934 SmallVector<uint32_t, 8> Idxs(NumElts); 1935 for (unsigned i = 0; i != NumElts; ++i) 1936 Idxs[i] = (i & ~0x3) + ((Imm >> (2 * (i & 0x3))) & 3); 1937 1938 Rep = Builder.CreateShuffleVector(Op0, Op0, Idxs); 1939 1940 if (CI->getNumArgOperands() == 4) 1941 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1942 CI->getArgOperand(2)); 1943 } else if (IsX86 && (Name.startswith("avx.vperm2f128.") || 1944 Name == "avx2.vperm2i128")) { 1945 // The immediate permute control byte looks like this: 1946 // [1:0] - select 128 bits from sources for low half of destination 1947 // [2] - ignore 1948 // [3] - zero low half of destination 1949 // [5:4] - select 128 bits from sources for high half of destination 1950 // [6] - ignore 1951 // [7] - zero high half of destination 1952 1953 uint8_t Imm = cast<ConstantInt>(CI->getArgOperand(2))->getZExtValue(); 1954 1955 unsigned NumElts = CI->getType()->getVectorNumElements(); 1956 unsigned HalfSize = NumElts / 2; 1957 SmallVector<uint32_t, 8> ShuffleMask(NumElts); 1958 1959 // Determine which operand(s) are actually in use for this instruction. 1960 Value *V0 = (Imm & 0x02) ? CI->getArgOperand(1) : CI->getArgOperand(0); 1961 Value *V1 = (Imm & 0x20) ? CI->getArgOperand(1) : CI->getArgOperand(0); 1962 1963 // If needed, replace operands based on zero mask. 1964 V0 = (Imm & 0x08) ? ConstantAggregateZero::get(CI->getType()) : V0; 1965 V1 = (Imm & 0x80) ? ConstantAggregateZero::get(CI->getType()) : V1; 1966 1967 // Permute low half of result. 1968 unsigned StartIndex = (Imm & 0x01) ? HalfSize : 0; 1969 for (unsigned i = 0; i < HalfSize; ++i) 1970 ShuffleMask[i] = StartIndex + i; 1971 1972 // Permute high half of result. 1973 StartIndex = (Imm & 0x10) ? HalfSize : 0; 1974 for (unsigned i = 0; i < HalfSize; ++i) 1975 ShuffleMask[i + HalfSize] = NumElts + StartIndex + i; 1976 1977 Rep = Builder.CreateShuffleVector(V0, V1, ShuffleMask); 1978 1979 } else if (IsX86 && (Name.startswith("avx.vpermil.") || 1980 Name == "sse2.pshuf.d" || 1981 Name.startswith("avx512.mask.vpermil.p") || 1982 Name.startswith("avx512.mask.pshuf.d."))) { 1983 Value *Op0 = CI->getArgOperand(0); 1984 unsigned Imm = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue(); 1985 VectorType *VecTy = cast<VectorType>(CI->getType()); 1986 unsigned NumElts = VecTy->getNumElements(); 1987 // Calculate the size of each index in the immediate. 1988 unsigned IdxSize = 64 / VecTy->getScalarSizeInBits(); 1989 unsigned IdxMask = ((1 << IdxSize) - 1); 1990 1991 SmallVector<uint32_t, 8> Idxs(NumElts); 1992 // Lookup the bits for this element, wrapping around the immediate every 1993 // 8-bits. Elements are grouped into sets of 2 or 4 elements so we need 1994 // to offset by the first index of each group. 1995 for (unsigned i = 0; i != NumElts; ++i) 1996 Idxs[i] = ((Imm >> ((i * IdxSize) % 8)) & IdxMask) | (i & ~IdxMask); 1997 1998 Rep = Builder.CreateShuffleVector(Op0, Op0, Idxs); 1999 2000 if (CI->getNumArgOperands() == 4) 2001 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 2002 CI->getArgOperand(2)); 2003 } else if (IsX86 && (Name == "sse2.pshufl.w" || 2004 Name.startswith("avx512.mask.pshufl.w."))) { 2005 Value *Op0 = CI->getArgOperand(0); 2006 unsigned Imm = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue(); 2007 unsigned NumElts = CI->getType()->getVectorNumElements(); 2008 2009 SmallVector<uint32_t, 16> Idxs(NumElts); 2010 for (unsigned l = 0; l != NumElts; l += 8) { 2011 for (unsigned i = 0; i != 4; ++i) 2012 Idxs[i + l] = ((Imm >> (2 * i)) & 0x3) + l; 2013 for (unsigned i = 4; i != 8; ++i) 2014 Idxs[i + l] = i + l; 2015 } 2016 2017 Rep = Builder.CreateShuffleVector(Op0, Op0, Idxs); 2018 2019 if (CI->getNumArgOperands() == 4) 2020 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 2021 CI->getArgOperand(2)); 2022 } else if (IsX86 && (Name == "sse2.pshufh.w" || 2023 Name.startswith("avx512.mask.pshufh.w."))) { 2024 Value *Op0 = CI->getArgOperand(0); 2025 unsigned Imm = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue(); 2026 unsigned NumElts = CI->getType()->getVectorNumElements(); 2027 2028 SmallVector<uint32_t, 16> Idxs(NumElts); 2029 for (unsigned l = 0; l != NumElts; l += 8) { 2030 for (unsigned i = 0; i != 4; ++i) 2031 Idxs[i + l] = i + l; 2032 for (unsigned i = 0; i != 4; ++i) 2033 Idxs[i + l + 4] = ((Imm >> (2 * i)) & 0x3) + 4 + l; 2034 } 2035 2036 Rep = Builder.CreateShuffleVector(Op0, Op0, Idxs); 2037 2038 if (CI->getNumArgOperands() == 4) 2039 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 2040 CI->getArgOperand(2)); 2041 } else if (IsX86 && Name.startswith("avx512.mask.shuf.p")) { 2042 Value *Op0 = CI->getArgOperand(0); 2043 Value *Op1 = CI->getArgOperand(1); 2044 unsigned Imm = cast<ConstantInt>(CI->getArgOperand(2))->getZExtValue(); 2045 unsigned NumElts = CI->getType()->getVectorNumElements(); 2046 2047 unsigned NumLaneElts = 128/CI->getType()->getScalarSizeInBits(); 2048 unsigned HalfLaneElts = NumLaneElts / 2; 2049 2050 SmallVector<uint32_t, 16> Idxs(NumElts); 2051 for (unsigned i = 0; i != NumElts; ++i) { 2052 // Base index is the starting element of the lane. 2053 Idxs[i] = i - (i % NumLaneElts); 2054 // If we are half way through the lane switch to the other source. 2055 if ((i % NumLaneElts) >= HalfLaneElts) 2056 Idxs[i] += NumElts; 2057 // Now select the specific element. By adding HalfLaneElts bits from 2058 // the immediate. Wrapping around the immediate every 8-bits. 2059 Idxs[i] += (Imm >> ((i * HalfLaneElts) % 8)) & ((1 << HalfLaneElts) - 1); 2060 } 2061 2062 Rep = Builder.CreateShuffleVector(Op0, Op1, Idxs); 2063 2064 Rep = EmitX86Select(Builder, CI->getArgOperand(4), Rep, 2065 CI->getArgOperand(3)); 2066 } else if (IsX86 && (Name.startswith("avx512.mask.movddup") || 2067 Name.startswith("avx512.mask.movshdup") || 2068 Name.startswith("avx512.mask.movsldup"))) { 2069 Value *Op0 = CI->getArgOperand(0); 2070 unsigned NumElts = CI->getType()->getVectorNumElements(); 2071 unsigned NumLaneElts = 128/CI->getType()->getScalarSizeInBits(); 2072 2073 unsigned Offset = 0; 2074 if (Name.startswith("avx512.mask.movshdup.")) 2075 Offset = 1; 2076 2077 SmallVector<uint32_t, 16> Idxs(NumElts); 2078 for (unsigned l = 0; l != NumElts; l += NumLaneElts) 2079 for (unsigned i = 0; i != NumLaneElts; i += 2) { 2080 Idxs[i + l + 0] = i + l + Offset; 2081 Idxs[i + l + 1] = i + l + Offset; 2082 } 2083 2084 Rep = Builder.CreateShuffleVector(Op0, Op0, Idxs); 2085 2086 Rep = EmitX86Select(Builder, CI->getArgOperand(2), Rep, 2087 CI->getArgOperand(1)); 2088 } else if (IsX86 && (Name.startswith("avx512.mask.punpckl") || 2089 Name.startswith("avx512.mask.unpckl."))) { 2090 Value *Op0 = CI->getArgOperand(0); 2091 Value *Op1 = CI->getArgOperand(1); 2092 int NumElts = CI->getType()->getVectorNumElements(); 2093 int NumLaneElts = 128/CI->getType()->getScalarSizeInBits(); 2094 2095 SmallVector<uint32_t, 64> Idxs(NumElts); 2096 for (int l = 0; l != NumElts; l += NumLaneElts) 2097 for (int i = 0; i != NumLaneElts; ++i) 2098 Idxs[i + l] = l + (i / 2) + NumElts * (i % 2); 2099 2100 Rep = Builder.CreateShuffleVector(Op0, Op1, Idxs); 2101 2102 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 2103 CI->getArgOperand(2)); 2104 } else if (IsX86 && (Name.startswith("avx512.mask.punpckh") || 2105 Name.startswith("avx512.mask.unpckh."))) { 2106 Value *Op0 = CI->getArgOperand(0); 2107 Value *Op1 = CI->getArgOperand(1); 2108 int NumElts = CI->getType()->getVectorNumElements(); 2109 int NumLaneElts = 128/CI->getType()->getScalarSizeInBits(); 2110 2111 SmallVector<uint32_t, 64> Idxs(NumElts); 2112 for (int l = 0; l != NumElts; l += NumLaneElts) 2113 for (int i = 0; i != NumLaneElts; ++i) 2114 Idxs[i + l] = (NumLaneElts / 2) + l + (i / 2) + NumElts * (i % 2); 2115 2116 Rep = Builder.CreateShuffleVector(Op0, Op1, Idxs); 2117 2118 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 2119 CI->getArgOperand(2)); 2120 } else if (IsX86 && Name.startswith("avx512.mask.pand.")) { 2121 Rep = Builder.CreateAnd(CI->getArgOperand(0), CI->getArgOperand(1)); 2122 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 2123 CI->getArgOperand(2)); 2124 } else if (IsX86 && Name.startswith("avx512.mask.pandn.")) { 2125 Rep = Builder.CreateAnd(Builder.CreateNot(CI->getArgOperand(0)), 2126 CI->getArgOperand(1)); 2127 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 2128 CI->getArgOperand(2)); 2129 } else if (IsX86 && Name.startswith("avx512.mask.por.")) { 2130 Rep = Builder.CreateOr(CI->getArgOperand(0), CI->getArgOperand(1)); 2131 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 2132 CI->getArgOperand(2)); 2133 } else if (IsX86 && Name.startswith("avx512.mask.pxor.")) { 2134 Rep = Builder.CreateXor(CI->getArgOperand(0), CI->getArgOperand(1)); 2135 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 2136 CI->getArgOperand(2)); 2137 } else if (IsX86 && Name.startswith("avx512.mask.and.")) { 2138 VectorType *FTy = cast<VectorType>(CI->getType()); 2139 VectorType *ITy = VectorType::getInteger(FTy); 2140 Rep = Builder.CreateAnd(Builder.CreateBitCast(CI->getArgOperand(0), ITy), 2141 Builder.CreateBitCast(CI->getArgOperand(1), ITy)); 2142 Rep = Builder.CreateBitCast(Rep, FTy); 2143 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 2144 CI->getArgOperand(2)); 2145 } else if (IsX86 && Name.startswith("avx512.mask.andn.")) { 2146 VectorType *FTy = cast<VectorType>(CI->getType()); 2147 VectorType *ITy = VectorType::getInteger(FTy); 2148 Rep = Builder.CreateNot(Builder.CreateBitCast(CI->getArgOperand(0), ITy)); 2149 Rep = Builder.CreateAnd(Rep, 2150 Builder.CreateBitCast(CI->getArgOperand(1), ITy)); 2151 Rep = Builder.CreateBitCast(Rep, FTy); 2152 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 2153 CI->getArgOperand(2)); 2154 } else if (IsX86 && Name.startswith("avx512.mask.or.")) { 2155 VectorType *FTy = cast<VectorType>(CI->getType()); 2156 VectorType *ITy = VectorType::getInteger(FTy); 2157 Rep = Builder.CreateOr(Builder.CreateBitCast(CI->getArgOperand(0), ITy), 2158 Builder.CreateBitCast(CI->getArgOperand(1), ITy)); 2159 Rep = Builder.CreateBitCast(Rep, FTy); 2160 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 2161 CI->getArgOperand(2)); 2162 } else if (IsX86 && Name.startswith("avx512.mask.xor.")) { 2163 VectorType *FTy = cast<VectorType>(CI->getType()); 2164 VectorType *ITy = VectorType::getInteger(FTy); 2165 Rep = Builder.CreateXor(Builder.CreateBitCast(CI->getArgOperand(0), ITy), 2166 Builder.CreateBitCast(CI->getArgOperand(1), ITy)); 2167 Rep = Builder.CreateBitCast(Rep, FTy); 2168 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 2169 CI->getArgOperand(2)); 2170 } else if (IsX86 && Name.startswith("avx512.mask.padd.")) { 2171 Rep = Builder.CreateAdd(CI->getArgOperand(0), CI->getArgOperand(1)); 2172 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 2173 CI->getArgOperand(2)); 2174 } else if (IsX86 && Name.startswith("avx512.mask.psub.")) { 2175 Rep = Builder.CreateSub(CI->getArgOperand(0), CI->getArgOperand(1)); 2176 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 2177 CI->getArgOperand(2)); 2178 } else if (IsX86 && Name.startswith("avx512.mask.pmull.")) { 2179 Rep = Builder.CreateMul(CI->getArgOperand(0), CI->getArgOperand(1)); 2180 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 2181 CI->getArgOperand(2)); 2182 } else if (IsX86 && (Name.startswith("avx512.mask.add.p"))) { 2183 Rep = Builder.CreateFAdd(CI->getArgOperand(0), CI->getArgOperand(1)); 2184 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 2185 CI->getArgOperand(2)); 2186 } else if (IsX86 && Name.startswith("avx512.mask.div.p")) { 2187 Rep = Builder.CreateFDiv(CI->getArgOperand(0), CI->getArgOperand(1)); 2188 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 2189 CI->getArgOperand(2)); 2190 } else if (IsX86 && Name.startswith("avx512.mask.mul.p")) { 2191 Rep = Builder.CreateFMul(CI->getArgOperand(0), CI->getArgOperand(1)); 2192 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 2193 CI->getArgOperand(2)); 2194 } else if (IsX86 && Name.startswith("avx512.mask.sub.p")) { 2195 Rep = Builder.CreateFSub(CI->getArgOperand(0), CI->getArgOperand(1)); 2196 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 2197 CI->getArgOperand(2)); 2198 } else if (IsX86 && Name.startswith("avx512.mask.lzcnt.")) { 2199 Rep = Builder.CreateCall(Intrinsic::getDeclaration(F->getParent(), 2200 Intrinsic::ctlz, 2201 CI->getType()), 2202 { CI->getArgOperand(0), Builder.getInt1(false) }); 2203 Rep = EmitX86Select(Builder, CI->getArgOperand(2), Rep, 2204 CI->getArgOperand(1)); 2205 } else if (IsX86 && Name.startswith("avx512.mask.psll")) { 2206 bool IsImmediate = Name[16] == 'i' || 2207 (Name.size() > 18 && Name[18] == 'i'); 2208 bool IsVariable = Name[16] == 'v'; 2209 char Size = Name[16] == '.' ? Name[17] : 2210 Name[17] == '.' ? Name[18] : 2211 Name[18] == '.' ? Name[19] : 2212 Name[20]; 2213 2214 Intrinsic::ID IID; 2215 if (IsVariable && Name[17] != '.') { 2216 if (Size == 'd' && Name[17] == '2') // avx512.mask.psllv2.di 2217 IID = Intrinsic::x86_avx2_psllv_q; 2218 else if (Size == 'd' && Name[17] == '4') // avx512.mask.psllv4.di 2219 IID = Intrinsic::x86_avx2_psllv_q_256; 2220 else if (Size == 's' && Name[17] == '4') // avx512.mask.psllv4.si 2221 IID = Intrinsic::x86_avx2_psllv_d; 2222 else if (Size == 's' && Name[17] == '8') // avx512.mask.psllv8.si 2223 IID = Intrinsic::x86_avx2_psllv_d_256; 2224 else if (Size == 'h' && Name[17] == '8') // avx512.mask.psllv8.hi 2225 IID = Intrinsic::x86_avx512_psllv_w_128; 2226 else if (Size == 'h' && Name[17] == '1') // avx512.mask.psllv16.hi 2227 IID = Intrinsic::x86_avx512_psllv_w_256; 2228 else if (Name[17] == '3' && Name[18] == '2') // avx512.mask.psllv32hi 2229 IID = Intrinsic::x86_avx512_psllv_w_512; 2230 else 2231 llvm_unreachable("Unexpected size"); 2232 } else if (Name.endswith(".128")) { 2233 if (Size == 'd') // avx512.mask.psll.d.128, avx512.mask.psll.di.128 2234 IID = IsImmediate ? Intrinsic::x86_sse2_pslli_d 2235 : Intrinsic::x86_sse2_psll_d; 2236 else if (Size == 'q') // avx512.mask.psll.q.128, avx512.mask.psll.qi.128 2237 IID = IsImmediate ? Intrinsic::x86_sse2_pslli_q 2238 : Intrinsic::x86_sse2_psll_q; 2239 else if (Size == 'w') // avx512.mask.psll.w.128, avx512.mask.psll.wi.128 2240 IID = IsImmediate ? Intrinsic::x86_sse2_pslli_w 2241 : Intrinsic::x86_sse2_psll_w; 2242 else 2243 llvm_unreachable("Unexpected size"); 2244 } else if (Name.endswith(".256")) { 2245 if (Size == 'd') // avx512.mask.psll.d.256, avx512.mask.psll.di.256 2246 IID = IsImmediate ? Intrinsic::x86_avx2_pslli_d 2247 : Intrinsic::x86_avx2_psll_d; 2248 else if (Size == 'q') // avx512.mask.psll.q.256, avx512.mask.psll.qi.256 2249 IID = IsImmediate ? Intrinsic::x86_avx2_pslli_q 2250 : Intrinsic::x86_avx2_psll_q; 2251 else if (Size == 'w') // avx512.mask.psll.w.256, avx512.mask.psll.wi.256 2252 IID = IsImmediate ? Intrinsic::x86_avx2_pslli_w 2253 : Intrinsic::x86_avx2_psll_w; 2254 else 2255 llvm_unreachable("Unexpected size"); 2256 } else { 2257 if (Size == 'd') // psll.di.512, pslli.d, psll.d, psllv.d.512 2258 IID = IsImmediate ? Intrinsic::x86_avx512_pslli_d_512 : 2259 IsVariable ? Intrinsic::x86_avx512_psllv_d_512 : 2260 Intrinsic::x86_avx512_psll_d_512; 2261 else if (Size == 'q') // psll.qi.512, pslli.q, psll.q, psllv.q.512 2262 IID = IsImmediate ? Intrinsic::x86_avx512_pslli_q_512 : 2263 IsVariable ? Intrinsic::x86_avx512_psllv_q_512 : 2264 Intrinsic::x86_avx512_psll_q_512; 2265 else if (Size == 'w') // psll.wi.512, pslli.w, psll.w 2266 IID = IsImmediate ? Intrinsic::x86_avx512_pslli_w_512 2267 : Intrinsic::x86_avx512_psll_w_512; 2268 else 2269 llvm_unreachable("Unexpected size"); 2270 } 2271 2272 Rep = UpgradeX86MaskedShift(Builder, *CI, IID); 2273 } else if (IsX86 && Name.startswith("avx512.mask.psrl")) { 2274 bool IsImmediate = Name[16] == 'i' || 2275 (Name.size() > 18 && Name[18] == 'i'); 2276 bool IsVariable = Name[16] == 'v'; 2277 char Size = Name[16] == '.' ? Name[17] : 2278 Name[17] == '.' ? Name[18] : 2279 Name[18] == '.' ? Name[19] : 2280 Name[20]; 2281 2282 Intrinsic::ID IID; 2283 if (IsVariable && Name[17] != '.') { 2284 if (Size == 'd' && Name[17] == '2') // avx512.mask.psrlv2.di 2285 IID = Intrinsic::x86_avx2_psrlv_q; 2286 else if (Size == 'd' && Name[17] == '4') // avx512.mask.psrlv4.di 2287 IID = Intrinsic::x86_avx2_psrlv_q_256; 2288 else if (Size == 's' && Name[17] == '4') // avx512.mask.psrlv4.si 2289 IID = Intrinsic::x86_avx2_psrlv_d; 2290 else if (Size == 's' && Name[17] == '8') // avx512.mask.psrlv8.si 2291 IID = Intrinsic::x86_avx2_psrlv_d_256; 2292 else if (Size == 'h' && Name[17] == '8') // avx512.mask.psrlv8.hi 2293 IID = Intrinsic::x86_avx512_psrlv_w_128; 2294 else if (Size == 'h' && Name[17] == '1') // avx512.mask.psrlv16.hi 2295 IID = Intrinsic::x86_avx512_psrlv_w_256; 2296 else if (Name[17] == '3' && Name[18] == '2') // avx512.mask.psrlv32hi 2297 IID = Intrinsic::x86_avx512_psrlv_w_512; 2298 else 2299 llvm_unreachable("Unexpected size"); 2300 } else if (Name.endswith(".128")) { 2301 if (Size == 'd') // avx512.mask.psrl.d.128, avx512.mask.psrl.di.128 2302 IID = IsImmediate ? Intrinsic::x86_sse2_psrli_d 2303 : Intrinsic::x86_sse2_psrl_d; 2304 else if (Size == 'q') // avx512.mask.psrl.q.128, avx512.mask.psrl.qi.128 2305 IID = IsImmediate ? Intrinsic::x86_sse2_psrli_q 2306 : Intrinsic::x86_sse2_psrl_q; 2307 else if (Size == 'w') // avx512.mask.psrl.w.128, avx512.mask.psrl.wi.128 2308 IID = IsImmediate ? Intrinsic::x86_sse2_psrli_w 2309 : Intrinsic::x86_sse2_psrl_w; 2310 else 2311 llvm_unreachable("Unexpected size"); 2312 } else if (Name.endswith(".256")) { 2313 if (Size == 'd') // avx512.mask.psrl.d.256, avx512.mask.psrl.di.256 2314 IID = IsImmediate ? Intrinsic::x86_avx2_psrli_d 2315 : Intrinsic::x86_avx2_psrl_d; 2316 else if (Size == 'q') // avx512.mask.psrl.q.256, avx512.mask.psrl.qi.256 2317 IID = IsImmediate ? Intrinsic::x86_avx2_psrli_q 2318 : Intrinsic::x86_avx2_psrl_q; 2319 else if (Size == 'w') // avx512.mask.psrl.w.256, avx512.mask.psrl.wi.256 2320 IID = IsImmediate ? Intrinsic::x86_avx2_psrli_w 2321 : Intrinsic::x86_avx2_psrl_w; 2322 else 2323 llvm_unreachable("Unexpected size"); 2324 } else { 2325 if (Size == 'd') // psrl.di.512, psrli.d, psrl.d, psrl.d.512 2326 IID = IsImmediate ? Intrinsic::x86_avx512_psrli_d_512 : 2327 IsVariable ? Intrinsic::x86_avx512_psrlv_d_512 : 2328 Intrinsic::x86_avx512_psrl_d_512; 2329 else if (Size == 'q') // psrl.qi.512, psrli.q, psrl.q, psrl.q.512 2330 IID = IsImmediate ? Intrinsic::x86_avx512_psrli_q_512 : 2331 IsVariable ? Intrinsic::x86_avx512_psrlv_q_512 : 2332 Intrinsic::x86_avx512_psrl_q_512; 2333 else if (Size == 'w') // psrl.wi.512, psrli.w, psrl.w) 2334 IID = IsImmediate ? Intrinsic::x86_avx512_psrli_w_512 2335 : Intrinsic::x86_avx512_psrl_w_512; 2336 else 2337 llvm_unreachable("Unexpected size"); 2338 } 2339 2340 Rep = UpgradeX86MaskedShift(Builder, *CI, IID); 2341 } else if (IsX86 && Name.startswith("avx512.mask.psra")) { 2342 bool IsImmediate = Name[16] == 'i' || 2343 (Name.size() > 18 && Name[18] == 'i'); 2344 bool IsVariable = Name[16] == 'v'; 2345 char Size = Name[16] == '.' ? Name[17] : 2346 Name[17] == '.' ? Name[18] : 2347 Name[18] == '.' ? Name[19] : 2348 Name[20]; 2349 2350 Intrinsic::ID IID; 2351 if (IsVariable && Name[17] != '.') { 2352 if (Size == 's' && Name[17] == '4') // avx512.mask.psrav4.si 2353 IID = Intrinsic::x86_avx2_psrav_d; 2354 else if (Size == 's' && Name[17] == '8') // avx512.mask.psrav8.si 2355 IID = Intrinsic::x86_avx2_psrav_d_256; 2356 else if (Size == 'h' && Name[17] == '8') // avx512.mask.psrav8.hi 2357 IID = Intrinsic::x86_avx512_psrav_w_128; 2358 else if (Size == 'h' && Name[17] == '1') // avx512.mask.psrav16.hi 2359 IID = Intrinsic::x86_avx512_psrav_w_256; 2360 else if (Name[17] == '3' && Name[18] == '2') // avx512.mask.psrav32hi 2361 IID = Intrinsic::x86_avx512_psrav_w_512; 2362 else 2363 llvm_unreachable("Unexpected size"); 2364 } else if (Name.endswith(".128")) { 2365 if (Size == 'd') // avx512.mask.psra.d.128, avx512.mask.psra.di.128 2366 IID = IsImmediate ? Intrinsic::x86_sse2_psrai_d 2367 : Intrinsic::x86_sse2_psra_d; 2368 else if (Size == 'q') // avx512.mask.psra.q.128, avx512.mask.psra.qi.128 2369 IID = IsImmediate ? Intrinsic::x86_avx512_psrai_q_128 : 2370 IsVariable ? Intrinsic::x86_avx512_psrav_q_128 : 2371 Intrinsic::x86_avx512_psra_q_128; 2372 else if (Size == 'w') // avx512.mask.psra.w.128, avx512.mask.psra.wi.128 2373 IID = IsImmediate ? Intrinsic::x86_sse2_psrai_w 2374 : Intrinsic::x86_sse2_psra_w; 2375 else 2376 llvm_unreachable("Unexpected size"); 2377 } else if (Name.endswith(".256")) { 2378 if (Size == 'd') // avx512.mask.psra.d.256, avx512.mask.psra.di.256 2379 IID = IsImmediate ? Intrinsic::x86_avx2_psrai_d 2380 : Intrinsic::x86_avx2_psra_d; 2381 else if (Size == 'q') // avx512.mask.psra.q.256, avx512.mask.psra.qi.256 2382 IID = IsImmediate ? Intrinsic::x86_avx512_psrai_q_256 : 2383 IsVariable ? Intrinsic::x86_avx512_psrav_q_256 : 2384 Intrinsic::x86_avx512_psra_q_256; 2385 else if (Size == 'w') // avx512.mask.psra.w.256, avx512.mask.psra.wi.256 2386 IID = IsImmediate ? Intrinsic::x86_avx2_psrai_w 2387 : Intrinsic::x86_avx2_psra_w; 2388 else 2389 llvm_unreachable("Unexpected size"); 2390 } else { 2391 if (Size == 'd') // psra.di.512, psrai.d, psra.d, psrav.d.512 2392 IID = IsImmediate ? Intrinsic::x86_avx512_psrai_d_512 : 2393 IsVariable ? Intrinsic::x86_avx512_psrav_d_512 : 2394 Intrinsic::x86_avx512_psra_d_512; 2395 else if (Size == 'q') // psra.qi.512, psrai.q, psra.q 2396 IID = IsImmediate ? Intrinsic::x86_avx512_psrai_q_512 : 2397 IsVariable ? Intrinsic::x86_avx512_psrav_q_512 : 2398 Intrinsic::x86_avx512_psra_q_512; 2399 else if (Size == 'w') // psra.wi.512, psrai.w, psra.w 2400 IID = IsImmediate ? Intrinsic::x86_avx512_psrai_w_512 2401 : Intrinsic::x86_avx512_psra_w_512; 2402 else 2403 llvm_unreachable("Unexpected size"); 2404 } 2405 2406 Rep = UpgradeX86MaskedShift(Builder, *CI, IID); 2407 } else if (IsX86 && Name.startswith("avx512.mask.move.s")) { 2408 Rep = upgradeMaskedMove(Builder, *CI); 2409 } else if (IsX86 && Name.startswith("avx512.cvtmask2")) { 2410 Rep = UpgradeMaskToInt(Builder, *CI); 2411 } else if (IsX86 && Name.endswith(".movntdqa")) { 2412 Module *M = F->getParent(); 2413 MDNode *Node = MDNode::get( 2414 C, ConstantAsMetadata::get(ConstantInt::get(Type::getInt32Ty(C), 1))); 2415 2416 Value *Ptr = CI->getArgOperand(0); 2417 VectorType *VTy = cast<VectorType>(CI->getType()); 2418 2419 // Convert the type of the pointer to a pointer to the stored type. 2420 Value *BC = 2421 Builder.CreateBitCast(Ptr, PointerType::getUnqual(VTy), "cast"); 2422 LoadInst *LI = Builder.CreateAlignedLoad(BC, VTy->getBitWidth() / 8); 2423 LI->setMetadata(M->getMDKindID("nontemporal"), Node); 2424 Rep = LI; 2425 } else if (IsX86 && 2426 (Name.startswith("sse2.pavg") || Name.startswith("avx2.pavg") || 2427 Name.startswith("avx512.mask.pavg"))) { 2428 // llvm.x86.sse2.pavg.b/w, llvm.x86.avx2.pavg.b/w, 2429 // llvm.x86.avx512.mask.pavg.b/w 2430 Value *A = CI->getArgOperand(0); 2431 Value *B = CI->getArgOperand(1); 2432 VectorType *ZextType = VectorType::getExtendedElementVectorType( 2433 cast<VectorType>(A->getType())); 2434 Value *ExtendedA = Builder.CreateZExt(A, ZextType); 2435 Value *ExtendedB = Builder.CreateZExt(B, ZextType); 2436 Value *Sum = Builder.CreateAdd(ExtendedA, ExtendedB); 2437 Value *AddOne = Builder.CreateAdd(Sum, ConstantInt::get(ZextType, 1)); 2438 Value *ShiftR = Builder.CreateLShr(AddOne, ConstantInt::get(ZextType, 1)); 2439 Rep = Builder.CreateTrunc(ShiftR, A->getType()); 2440 if (CI->getNumArgOperands() > 2) { 2441 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 2442 CI->getArgOperand(2)); 2443 } 2444 } else if (IsX86 && Name.startswith("avx512.mask.") && 2445 upgradeAVX512MaskToSelect(Name, Builder, *CI, Rep)) { 2446 // Rep will be updated by the call in the condition. 2447 } else if (IsNVVM && (Name == "abs.i" || Name == "abs.ll")) { 2448 Value *Arg = CI->getArgOperand(0); 2449 Value *Neg = Builder.CreateNeg(Arg, "neg"); 2450 Value *Cmp = Builder.CreateICmpSGE( 2451 Arg, llvm::Constant::getNullValue(Arg->getType()), "abs.cond"); 2452 Rep = Builder.CreateSelect(Cmp, Arg, Neg, "abs"); 2453 } else if (IsNVVM && (Name == "max.i" || Name == "max.ll" || 2454 Name == "max.ui" || Name == "max.ull")) { 2455 Value *Arg0 = CI->getArgOperand(0); 2456 Value *Arg1 = CI->getArgOperand(1); 2457 Value *Cmp = Name.endswith(".ui") || Name.endswith(".ull") 2458 ? Builder.CreateICmpUGE(Arg0, Arg1, "max.cond") 2459 : Builder.CreateICmpSGE(Arg0, Arg1, "max.cond"); 2460 Rep = Builder.CreateSelect(Cmp, Arg0, Arg1, "max"); 2461 } else if (IsNVVM && (Name == "min.i" || Name == "min.ll" || 2462 Name == "min.ui" || Name == "min.ull")) { 2463 Value *Arg0 = CI->getArgOperand(0); 2464 Value *Arg1 = CI->getArgOperand(1); 2465 Value *Cmp = Name.endswith(".ui") || Name.endswith(".ull") 2466 ? Builder.CreateICmpULE(Arg0, Arg1, "min.cond") 2467 : Builder.CreateICmpSLE(Arg0, Arg1, "min.cond"); 2468 Rep = Builder.CreateSelect(Cmp, Arg0, Arg1, "min"); 2469 } else if (IsNVVM && Name == "clz.ll") { 2470 // llvm.nvvm.clz.ll returns an i32, but llvm.ctlz.i64 and returns an i64. 2471 Value *Arg = CI->getArgOperand(0); 2472 Value *Ctlz = Builder.CreateCall( 2473 Intrinsic::getDeclaration(F->getParent(), Intrinsic::ctlz, 2474 {Arg->getType()}), 2475 {Arg, Builder.getFalse()}, "ctlz"); 2476 Rep = Builder.CreateTrunc(Ctlz, Builder.getInt32Ty(), "ctlz.trunc"); 2477 } else if (IsNVVM && Name == "popc.ll") { 2478 // llvm.nvvm.popc.ll returns an i32, but llvm.ctpop.i64 and returns an 2479 // i64. 2480 Value *Arg = CI->getArgOperand(0); 2481 Value *Popc = Builder.CreateCall( 2482 Intrinsic::getDeclaration(F->getParent(), Intrinsic::ctpop, 2483 {Arg->getType()}), 2484 Arg, "ctpop"); 2485 Rep = Builder.CreateTrunc(Popc, Builder.getInt32Ty(), "ctpop.trunc"); 2486 } else if (IsNVVM && Name == "h2f") { 2487 Rep = Builder.CreateCall(Intrinsic::getDeclaration( 2488 F->getParent(), Intrinsic::convert_from_fp16, 2489 {Builder.getFloatTy()}), 2490 CI->getArgOperand(0), "h2f"); 2491 } else { 2492 llvm_unreachable("Unknown function for CallInst upgrade."); 2493 } 2494 2495 if (Rep) 2496 CI->replaceAllUsesWith(Rep); 2497 CI->eraseFromParent(); 2498 return; 2499 } 2500 2501 const auto &DefaultCase = [&NewFn, &CI]() -> void { 2502 // Handle generic mangling change, but nothing else 2503 assert( 2504 (CI->getCalledFunction()->getName() != NewFn->getName()) && 2505 "Unknown function for CallInst upgrade and isn't just a name change"); 2506 CI->setCalledFunction(NewFn); 2507 }; 2508 CallInst *NewCall = nullptr; 2509 switch (NewFn->getIntrinsicID()) { 2510 default: { 2511 DefaultCase(); 2512 return; 2513 } 2514 2515 case Intrinsic::arm_neon_vld1: 2516 case Intrinsic::arm_neon_vld2: 2517 case Intrinsic::arm_neon_vld3: 2518 case Intrinsic::arm_neon_vld4: 2519 case Intrinsic::arm_neon_vld2lane: 2520 case Intrinsic::arm_neon_vld3lane: 2521 case Intrinsic::arm_neon_vld4lane: 2522 case Intrinsic::arm_neon_vst1: 2523 case Intrinsic::arm_neon_vst2: 2524 case Intrinsic::arm_neon_vst3: 2525 case Intrinsic::arm_neon_vst4: 2526 case Intrinsic::arm_neon_vst2lane: 2527 case Intrinsic::arm_neon_vst3lane: 2528 case Intrinsic::arm_neon_vst4lane: { 2529 SmallVector<Value *, 4> Args(CI->arg_operands().begin(), 2530 CI->arg_operands().end()); 2531 NewCall = Builder.CreateCall(NewFn, Args); 2532 break; 2533 } 2534 2535 case Intrinsic::bitreverse: 2536 NewCall = Builder.CreateCall(NewFn, {CI->getArgOperand(0)}); 2537 break; 2538 2539 case Intrinsic::ctlz: 2540 case Intrinsic::cttz: 2541 assert(CI->getNumArgOperands() == 1 && 2542 "Mismatch between function args and call args"); 2543 NewCall = 2544 Builder.CreateCall(NewFn, {CI->getArgOperand(0), Builder.getFalse()}); 2545 break; 2546 2547 case Intrinsic::objectsize: { 2548 Value *NullIsUnknownSize = CI->getNumArgOperands() == 2 2549 ? Builder.getFalse() 2550 : CI->getArgOperand(2); 2551 NewCall = Builder.CreateCall( 2552 NewFn, {CI->getArgOperand(0), CI->getArgOperand(1), NullIsUnknownSize}); 2553 break; 2554 } 2555 2556 case Intrinsic::ctpop: 2557 NewCall = Builder.CreateCall(NewFn, {CI->getArgOperand(0)}); 2558 break; 2559 2560 case Intrinsic::convert_from_fp16: 2561 NewCall = Builder.CreateCall(NewFn, {CI->getArgOperand(0)}); 2562 break; 2563 2564 case Intrinsic::dbg_value: 2565 // Upgrade from the old version that had an extra offset argument. 2566 assert(CI->getNumArgOperands() == 4); 2567 // Drop nonzero offsets instead of attempting to upgrade them. 2568 if (auto *Offset = dyn_cast_or_null<Constant>(CI->getArgOperand(1))) 2569 if (Offset->isZeroValue()) { 2570 NewCall = Builder.CreateCall( 2571 NewFn, 2572 {CI->getArgOperand(0), CI->getArgOperand(2), CI->getArgOperand(3)}); 2573 break; 2574 } 2575 CI->eraseFromParent(); 2576 return; 2577 2578 case Intrinsic::x86_xop_vfrcz_ss: 2579 case Intrinsic::x86_xop_vfrcz_sd: 2580 NewCall = Builder.CreateCall(NewFn, {CI->getArgOperand(1)}); 2581 break; 2582 2583 case Intrinsic::x86_xop_vpermil2pd: 2584 case Intrinsic::x86_xop_vpermil2ps: 2585 case Intrinsic::x86_xop_vpermil2pd_256: 2586 case Intrinsic::x86_xop_vpermil2ps_256: { 2587 SmallVector<Value *, 4> Args(CI->arg_operands().begin(), 2588 CI->arg_operands().end()); 2589 VectorType *FltIdxTy = cast<VectorType>(Args[2]->getType()); 2590 VectorType *IntIdxTy = VectorType::getInteger(FltIdxTy); 2591 Args[2] = Builder.CreateBitCast(Args[2], IntIdxTy); 2592 NewCall = Builder.CreateCall(NewFn, Args); 2593 break; 2594 } 2595 2596 case Intrinsic::x86_sse41_ptestc: 2597 case Intrinsic::x86_sse41_ptestz: 2598 case Intrinsic::x86_sse41_ptestnzc: { 2599 // The arguments for these intrinsics used to be v4f32, and changed 2600 // to v2i64. This is purely a nop, since those are bitwise intrinsics. 2601 // So, the only thing required is a bitcast for both arguments. 2602 // First, check the arguments have the old type. 2603 Value *Arg0 = CI->getArgOperand(0); 2604 if (Arg0->getType() != VectorType::get(Type::getFloatTy(C), 4)) 2605 return; 2606 2607 // Old intrinsic, add bitcasts 2608 Value *Arg1 = CI->getArgOperand(1); 2609 2610 Type *NewVecTy = VectorType::get(Type::getInt64Ty(C), 2); 2611 2612 Value *BC0 = Builder.CreateBitCast(Arg0, NewVecTy, "cast"); 2613 Value *BC1 = Builder.CreateBitCast(Arg1, NewVecTy, "cast"); 2614 2615 NewCall = Builder.CreateCall(NewFn, {BC0, BC1}); 2616 break; 2617 } 2618 2619 case Intrinsic::x86_sse41_insertps: 2620 case Intrinsic::x86_sse41_dppd: 2621 case Intrinsic::x86_sse41_dpps: 2622 case Intrinsic::x86_sse41_mpsadbw: 2623 case Intrinsic::x86_avx_dp_ps_256: 2624 case Intrinsic::x86_avx2_mpsadbw: { 2625 // Need to truncate the last argument from i32 to i8 -- this argument models 2626 // an inherently 8-bit immediate operand to these x86 instructions. 2627 SmallVector<Value *, 4> Args(CI->arg_operands().begin(), 2628 CI->arg_operands().end()); 2629 2630 // Replace the last argument with a trunc. 2631 Args.back() = Builder.CreateTrunc(Args.back(), Type::getInt8Ty(C), "trunc"); 2632 NewCall = Builder.CreateCall(NewFn, Args); 2633 break; 2634 } 2635 2636 case Intrinsic::x86_avx512_mask_cmp_pd_128: 2637 case Intrinsic::x86_avx512_mask_cmp_pd_256: 2638 case Intrinsic::x86_avx512_mask_cmp_pd_512: 2639 case Intrinsic::x86_avx512_mask_cmp_ps_128: 2640 case Intrinsic::x86_avx512_mask_cmp_ps_256: 2641 case Intrinsic::x86_avx512_mask_cmp_ps_512: { 2642 SmallVector<Value *, 4> Args; 2643 Args.push_back(CI->getArgOperand(0)); 2644 Args.push_back(CI->getArgOperand(1)); 2645 Args.push_back(CI->getArgOperand(2)); 2646 if (CI->getNumArgOperands() == 5) 2647 Args.push_back(CI->getArgOperand(4)); 2648 2649 NewCall = Builder.CreateCall(NewFn, Args); 2650 unsigned NumElts = Args[0]->getType()->getVectorNumElements(); 2651 Value *Res = ApplyX86MaskOn1BitsVec(Builder, NewCall, CI->getArgOperand(3), 2652 NumElts); 2653 2654 std::string Name = CI->getName(); 2655 if (!Name.empty()) { 2656 CI->setName(Name + ".old"); 2657 NewCall->setName(Name); 2658 } 2659 CI->replaceAllUsesWith(Res); 2660 CI->eraseFromParent(); 2661 return; 2662 } 2663 2664 case Intrinsic::thread_pointer: { 2665 NewCall = Builder.CreateCall(NewFn, {}); 2666 break; 2667 } 2668 2669 case Intrinsic::invariant_start: 2670 case Intrinsic::invariant_end: 2671 case Intrinsic::masked_load: 2672 case Intrinsic::masked_store: 2673 case Intrinsic::masked_gather: 2674 case Intrinsic::masked_scatter: { 2675 SmallVector<Value *, 4> Args(CI->arg_operands().begin(), 2676 CI->arg_operands().end()); 2677 NewCall = Builder.CreateCall(NewFn, Args); 2678 break; 2679 } 2680 2681 case Intrinsic::memcpy: 2682 case Intrinsic::memmove: 2683 case Intrinsic::memset: { 2684 // We have to make sure that the call signature is what we're expecting. 2685 // We only want to change the old signatures by removing the alignment arg: 2686 // @llvm.mem[cpy|move]...(i8*, i8*, i[32|i64], i32, i1) 2687 // -> @llvm.mem[cpy|move]...(i8*, i8*, i[32|i64], i1) 2688 // @llvm.memset...(i8*, i8, i[32|64], i32, i1) 2689 // -> @llvm.memset...(i8*, i8, i[32|64], i1) 2690 // Note: i8*'s in the above can be any pointer type 2691 if (CI->getNumArgOperands() != 5) { 2692 DefaultCase(); 2693 return; 2694 } 2695 // Remove alignment argument (3), and add alignment attributes to the 2696 // dest/src pointers. 2697 Value *Args[4] = {CI->getArgOperand(0), CI->getArgOperand(1), 2698 CI->getArgOperand(2), CI->getArgOperand(4)}; 2699 NewCall = Builder.CreateCall(NewFn, Args); 2700 auto *MemCI = cast<MemIntrinsic>(NewCall); 2701 // All mem intrinsics support dest alignment. 2702 const ConstantInt *Align = cast<ConstantInt>(CI->getArgOperand(3)); 2703 MemCI->setDestAlignment(Align->getZExtValue()); 2704 // Memcpy/Memmove also support source alignment. 2705 if (auto *MTI = dyn_cast<MemTransferInst>(MemCI)) 2706 MTI->setSourceAlignment(Align->getZExtValue()); 2707 break; 2708 } 2709 } 2710 assert(NewCall && "Should have either set this variable or returned through " 2711 "the default case"); 2712 std::string Name = CI->getName(); 2713 if (!Name.empty()) { 2714 CI->setName(Name + ".old"); 2715 NewCall->setName(Name); 2716 } 2717 CI->replaceAllUsesWith(NewCall); 2718 CI->eraseFromParent(); 2719 } 2720 2721 void llvm::UpgradeCallsToIntrinsic(Function *F) { 2722 assert(F && "Illegal attempt to upgrade a non-existent intrinsic."); 2723 2724 // Check if this function should be upgraded and get the replacement function 2725 // if there is one. 2726 Function *NewFn; 2727 if (UpgradeIntrinsicFunction(F, NewFn)) { 2728 // Replace all users of the old function with the new function or new 2729 // instructions. This is not a range loop because the call is deleted. 2730 for (auto UI = F->user_begin(), UE = F->user_end(); UI != UE; ) 2731 if (CallInst *CI = dyn_cast<CallInst>(*UI++)) 2732 UpgradeIntrinsicCall(CI, NewFn); 2733 2734 // Remove old function, no longer used, from the module. 2735 F->eraseFromParent(); 2736 } 2737 } 2738 2739 MDNode *llvm::UpgradeTBAANode(MDNode &MD) { 2740 // Check if the tag uses struct-path aware TBAA format. 2741 if (isa<MDNode>(MD.getOperand(0)) && MD.getNumOperands() >= 3) 2742 return &MD; 2743 2744 auto &Context = MD.getContext(); 2745 if (MD.getNumOperands() == 3) { 2746 Metadata *Elts[] = {MD.getOperand(0), MD.getOperand(1)}; 2747 MDNode *ScalarType = MDNode::get(Context, Elts); 2748 // Create a MDNode <ScalarType, ScalarType, offset 0, const> 2749 Metadata *Elts2[] = {ScalarType, ScalarType, 2750 ConstantAsMetadata::get( 2751 Constant::getNullValue(Type::getInt64Ty(Context))), 2752 MD.getOperand(2)}; 2753 return MDNode::get(Context, Elts2); 2754 } 2755 // Create a MDNode <MD, MD, offset 0> 2756 Metadata *Elts[] = {&MD, &MD, ConstantAsMetadata::get(Constant::getNullValue( 2757 Type::getInt64Ty(Context)))}; 2758 return MDNode::get(Context, Elts); 2759 } 2760 2761 Instruction *llvm::UpgradeBitCastInst(unsigned Opc, Value *V, Type *DestTy, 2762 Instruction *&Temp) { 2763 if (Opc != Instruction::BitCast) 2764 return nullptr; 2765 2766 Temp = nullptr; 2767 Type *SrcTy = V->getType(); 2768 if (SrcTy->isPtrOrPtrVectorTy() && DestTy->isPtrOrPtrVectorTy() && 2769 SrcTy->getPointerAddressSpace() != DestTy->getPointerAddressSpace()) { 2770 LLVMContext &Context = V->getContext(); 2771 2772 // We have no information about target data layout, so we assume that 2773 // the maximum pointer size is 64bit. 2774 Type *MidTy = Type::getInt64Ty(Context); 2775 Temp = CastInst::Create(Instruction::PtrToInt, V, MidTy); 2776 2777 return CastInst::Create(Instruction::IntToPtr, Temp, DestTy); 2778 } 2779 2780 return nullptr; 2781 } 2782 2783 Value *llvm::UpgradeBitCastExpr(unsigned Opc, Constant *C, Type *DestTy) { 2784 if (Opc != Instruction::BitCast) 2785 return nullptr; 2786 2787 Type *SrcTy = C->getType(); 2788 if (SrcTy->isPtrOrPtrVectorTy() && DestTy->isPtrOrPtrVectorTy() && 2789 SrcTy->getPointerAddressSpace() != DestTy->getPointerAddressSpace()) { 2790 LLVMContext &Context = C->getContext(); 2791 2792 // We have no information about target data layout, so we assume that 2793 // the maximum pointer size is 64bit. 2794 Type *MidTy = Type::getInt64Ty(Context); 2795 2796 return ConstantExpr::getIntToPtr(ConstantExpr::getPtrToInt(C, MidTy), 2797 DestTy); 2798 } 2799 2800 return nullptr; 2801 } 2802 2803 /// Check the debug info version number, if it is out-dated, drop the debug 2804 /// info. Return true if module is modified. 2805 bool llvm::UpgradeDebugInfo(Module &M) { 2806 unsigned Version = getDebugMetadataVersionFromModule(M); 2807 if (Version == DEBUG_METADATA_VERSION) { 2808 bool BrokenDebugInfo = false; 2809 if (verifyModule(M, &llvm::errs(), &BrokenDebugInfo)) 2810 report_fatal_error("Broken module found, compilation aborted!"); 2811 if (!BrokenDebugInfo) 2812 // Everything is ok. 2813 return false; 2814 else { 2815 // Diagnose malformed debug info. 2816 DiagnosticInfoIgnoringInvalidDebugMetadata Diag(M); 2817 M.getContext().diagnose(Diag); 2818 } 2819 } 2820 bool Modified = StripDebugInfo(M); 2821 if (Modified && Version != DEBUG_METADATA_VERSION) { 2822 // Diagnose a version mismatch. 2823 DiagnosticInfoDebugMetadataVersion DiagVersion(M, Version); 2824 M.getContext().diagnose(DiagVersion); 2825 } 2826 return Modified; 2827 } 2828 2829 bool llvm::UpgradeRetainReleaseMarker(Module &M) { 2830 bool Changed = false; 2831 NamedMDNode *ModRetainReleaseMarker = 2832 M.getNamedMetadata("clang.arc.retainAutoreleasedReturnValueMarker"); 2833 if (ModRetainReleaseMarker) { 2834 MDNode *Op = ModRetainReleaseMarker->getOperand(0); 2835 if (Op) { 2836 MDString *ID = dyn_cast_or_null<MDString>(Op->getOperand(0)); 2837 if (ID) { 2838 SmallVector<StringRef, 4> ValueComp; 2839 ID->getString().split(ValueComp, "#"); 2840 if (ValueComp.size() == 2) { 2841 std::string NewValue = ValueComp[0].str() + ";" + ValueComp[1].str(); 2842 Metadata *Ops[1] = {MDString::get(M.getContext(), NewValue)}; 2843 ModRetainReleaseMarker->setOperand(0, 2844 MDNode::get(M.getContext(), Ops)); 2845 Changed = true; 2846 } 2847 } 2848 } 2849 } 2850 return Changed; 2851 } 2852 2853 bool llvm::UpgradeModuleFlags(Module &M) { 2854 NamedMDNode *ModFlags = M.getModuleFlagsMetadata(); 2855 if (!ModFlags) 2856 return false; 2857 2858 bool HasObjCFlag = false, HasClassProperties = false, Changed = false; 2859 for (unsigned I = 0, E = ModFlags->getNumOperands(); I != E; ++I) { 2860 MDNode *Op = ModFlags->getOperand(I); 2861 if (Op->getNumOperands() != 3) 2862 continue; 2863 MDString *ID = dyn_cast_or_null<MDString>(Op->getOperand(1)); 2864 if (!ID) 2865 continue; 2866 if (ID->getString() == "Objective-C Image Info Version") 2867 HasObjCFlag = true; 2868 if (ID->getString() == "Objective-C Class Properties") 2869 HasClassProperties = true; 2870 // Upgrade PIC/PIE Module Flags. The module flag behavior for these two 2871 // field was Error and now they are Max. 2872 if (ID->getString() == "PIC Level" || ID->getString() == "PIE Level") { 2873 if (auto *Behavior = 2874 mdconst::dyn_extract_or_null<ConstantInt>(Op->getOperand(0))) { 2875 if (Behavior->getLimitedValue() == Module::Error) { 2876 Type *Int32Ty = Type::getInt32Ty(M.getContext()); 2877 Metadata *Ops[3] = { 2878 ConstantAsMetadata::get(ConstantInt::get(Int32Ty, Module::Max)), 2879 MDString::get(M.getContext(), ID->getString()), 2880 Op->getOperand(2)}; 2881 ModFlags->setOperand(I, MDNode::get(M.getContext(), Ops)); 2882 Changed = true; 2883 } 2884 } 2885 } 2886 // Upgrade Objective-C Image Info Section. Removed the whitespce in the 2887 // section name so that llvm-lto will not complain about mismatching 2888 // module flags that is functionally the same. 2889 if (ID->getString() == "Objective-C Image Info Section") { 2890 if (auto *Value = dyn_cast_or_null<MDString>(Op->getOperand(2))) { 2891 SmallVector<StringRef, 4> ValueComp; 2892 Value->getString().split(ValueComp, " "); 2893 if (ValueComp.size() != 1) { 2894 std::string NewValue; 2895 for (auto &S : ValueComp) 2896 NewValue += S.str(); 2897 Metadata *Ops[3] = {Op->getOperand(0), Op->getOperand(1), 2898 MDString::get(M.getContext(), NewValue)}; 2899 ModFlags->setOperand(I, MDNode::get(M.getContext(), Ops)); 2900 Changed = true; 2901 } 2902 } 2903 } 2904 } 2905 2906 // "Objective-C Class Properties" is recently added for Objective-C. We 2907 // upgrade ObjC bitcodes to contain a "Objective-C Class Properties" module 2908 // flag of value 0, so we can correclty downgrade this flag when trying to 2909 // link an ObjC bitcode without this module flag with an ObjC bitcode with 2910 // this module flag. 2911 if (HasObjCFlag && !HasClassProperties) { 2912 M.addModuleFlag(llvm::Module::Override, "Objective-C Class Properties", 2913 (uint32_t)0); 2914 Changed = true; 2915 } 2916 2917 return Changed; 2918 } 2919 2920 void llvm::UpgradeSectionAttributes(Module &M) { 2921 auto TrimSpaces = [](StringRef Section) -> std::string { 2922 SmallVector<StringRef, 5> Components; 2923 Section.split(Components, ','); 2924 2925 SmallString<32> Buffer; 2926 raw_svector_ostream OS(Buffer); 2927 2928 for (auto Component : Components) 2929 OS << ',' << Component.trim(); 2930 2931 return OS.str().substr(1); 2932 }; 2933 2934 for (auto &GV : M.globals()) { 2935 if (!GV.hasSection()) 2936 continue; 2937 2938 StringRef Section = GV.getSection(); 2939 2940 if (!Section.startswith("__DATA, __objc_catlist")) 2941 continue; 2942 2943 // __DATA, __objc_catlist, regular, no_dead_strip 2944 // __DATA,__objc_catlist,regular,no_dead_strip 2945 GV.setSection(TrimSpaces(Section)); 2946 } 2947 } 2948 2949 static bool isOldLoopArgument(Metadata *MD) { 2950 auto *T = dyn_cast_or_null<MDTuple>(MD); 2951 if (!T) 2952 return false; 2953 if (T->getNumOperands() < 1) 2954 return false; 2955 auto *S = dyn_cast_or_null<MDString>(T->getOperand(0)); 2956 if (!S) 2957 return false; 2958 return S->getString().startswith("llvm.vectorizer."); 2959 } 2960 2961 static MDString *upgradeLoopTag(LLVMContext &C, StringRef OldTag) { 2962 StringRef OldPrefix = "llvm.vectorizer."; 2963 assert(OldTag.startswith(OldPrefix) && "Expected old prefix"); 2964 2965 if (OldTag == "llvm.vectorizer.unroll") 2966 return MDString::get(C, "llvm.loop.interleave.count"); 2967 2968 return MDString::get( 2969 C, (Twine("llvm.loop.vectorize.") + OldTag.drop_front(OldPrefix.size())) 2970 .str()); 2971 } 2972 2973 static Metadata *upgradeLoopArgument(Metadata *MD) { 2974 auto *T = dyn_cast_or_null<MDTuple>(MD); 2975 if (!T) 2976 return MD; 2977 if (T->getNumOperands() < 1) 2978 return MD; 2979 auto *OldTag = dyn_cast_or_null<MDString>(T->getOperand(0)); 2980 if (!OldTag) 2981 return MD; 2982 if (!OldTag->getString().startswith("llvm.vectorizer.")) 2983 return MD; 2984 2985 // This has an old tag. Upgrade it. 2986 SmallVector<Metadata *, 8> Ops; 2987 Ops.reserve(T->getNumOperands()); 2988 Ops.push_back(upgradeLoopTag(T->getContext(), OldTag->getString())); 2989 for (unsigned I = 1, E = T->getNumOperands(); I != E; ++I) 2990 Ops.push_back(T->getOperand(I)); 2991 2992 return MDTuple::get(T->getContext(), Ops); 2993 } 2994 2995 MDNode *llvm::upgradeInstructionLoopAttachment(MDNode &N) { 2996 auto *T = dyn_cast<MDTuple>(&N); 2997 if (!T) 2998 return &N; 2999 3000 if (none_of(T->operands(), isOldLoopArgument)) 3001 return &N; 3002 3003 SmallVector<Metadata *, 8> Ops; 3004 Ops.reserve(T->getNumOperands()); 3005 for (Metadata *MD : T->operands()) 3006 Ops.push_back(upgradeLoopArgument(MD)); 3007 3008 return MDTuple::get(T->getContext(), Ops); 3009 } 3010