1 //===-- AutoUpgrade.cpp - Implement auto-upgrade helper functions ---------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements the auto-upgrade helper functions. 10 // This is where deprecated IR intrinsics and other IR features are updated to 11 // current specifications. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "llvm/IR/AutoUpgrade.h" 16 #include "llvm/ADT/StringSwitch.h" 17 #include "llvm/IR/Constants.h" 18 #include "llvm/IR/DIBuilder.h" 19 #include "llvm/IR/DebugInfo.h" 20 #include "llvm/IR/DiagnosticInfo.h" 21 #include "llvm/IR/Function.h" 22 #include "llvm/IR/IRBuilder.h" 23 #include "llvm/IR/InstVisitor.h" 24 #include "llvm/IR/Instruction.h" 25 #include "llvm/IR/IntrinsicInst.h" 26 #include "llvm/IR/Intrinsics.h" 27 #include "llvm/IR/IntrinsicsAArch64.h" 28 #include "llvm/IR/IntrinsicsARM.h" 29 #include "llvm/IR/IntrinsicsX86.h" 30 #include "llvm/IR/LLVMContext.h" 31 #include "llvm/IR/Module.h" 32 #include "llvm/IR/Verifier.h" 33 #include "llvm/Support/ErrorHandling.h" 34 #include "llvm/Support/Regex.h" 35 #include <cstring> 36 using namespace llvm; 37 38 static void rename(GlobalValue *GV) { GV->setName(GV->getName() + ".old"); } 39 40 // Upgrade the declarations of the SSE4.1 ptest intrinsics whose arguments have 41 // changed their type from v4f32 to v2i64. 42 static bool UpgradePTESTIntrinsic(Function* F, Intrinsic::ID IID, 43 Function *&NewFn) { 44 // Check whether this is an old version of the function, which received 45 // v4f32 arguments. 46 Type *Arg0Type = F->getFunctionType()->getParamType(0); 47 if (Arg0Type != FixedVectorType::get(Type::getFloatTy(F->getContext()), 4)) 48 return false; 49 50 // Yes, it's old, replace it with new version. 51 rename(F); 52 NewFn = Intrinsic::getDeclaration(F->getParent(), IID); 53 return true; 54 } 55 56 // Upgrade the declarations of intrinsic functions whose 8-bit immediate mask 57 // arguments have changed their type from i32 to i8. 58 static bool UpgradeX86IntrinsicsWith8BitMask(Function *F, Intrinsic::ID IID, 59 Function *&NewFn) { 60 // Check that the last argument is an i32. 61 Type *LastArgType = F->getFunctionType()->getParamType( 62 F->getFunctionType()->getNumParams() - 1); 63 if (!LastArgType->isIntegerTy(32)) 64 return false; 65 66 // Move this function aside and map down. 67 rename(F); 68 NewFn = Intrinsic::getDeclaration(F->getParent(), IID); 69 return true; 70 } 71 72 // Upgrade the declaration of fp compare intrinsics that change return type 73 // from scalar to vXi1 mask. 74 static bool UpgradeX86MaskedFPCompare(Function *F, Intrinsic::ID IID, 75 Function *&NewFn) { 76 // Check if the return type is a vector. 77 if (F->getReturnType()->isVectorTy()) 78 return false; 79 80 rename(F); 81 NewFn = Intrinsic::getDeclaration(F->getParent(), IID); 82 return true; 83 } 84 85 static bool ShouldUpgradeX86Intrinsic(Function *F, StringRef Name) { 86 // All of the intrinsics matches below should be marked with which llvm 87 // version started autoupgrading them. At some point in the future we would 88 // like to use this information to remove upgrade code for some older 89 // intrinsics. It is currently undecided how we will determine that future 90 // point. 91 if (Name == "addcarryx.u32" || // Added in 8.0 92 Name == "addcarryx.u64" || // Added in 8.0 93 Name == "addcarry.u32" || // Added in 8.0 94 Name == "addcarry.u64" || // Added in 8.0 95 Name == "subborrow.u32" || // Added in 8.0 96 Name == "subborrow.u64" || // Added in 8.0 97 Name.startswith("sse2.padds.") || // Added in 8.0 98 Name.startswith("sse2.psubs.") || // Added in 8.0 99 Name.startswith("sse2.paddus.") || // Added in 8.0 100 Name.startswith("sse2.psubus.") || // Added in 8.0 101 Name.startswith("avx2.padds.") || // Added in 8.0 102 Name.startswith("avx2.psubs.") || // Added in 8.0 103 Name.startswith("avx2.paddus.") || // Added in 8.0 104 Name.startswith("avx2.psubus.") || // Added in 8.0 105 Name.startswith("avx512.padds.") || // Added in 8.0 106 Name.startswith("avx512.psubs.") || // Added in 8.0 107 Name.startswith("avx512.mask.padds.") || // Added in 8.0 108 Name.startswith("avx512.mask.psubs.") || // Added in 8.0 109 Name.startswith("avx512.mask.paddus.") || // Added in 8.0 110 Name.startswith("avx512.mask.psubus.") || // Added in 8.0 111 Name=="ssse3.pabs.b.128" || // Added in 6.0 112 Name=="ssse3.pabs.w.128" || // Added in 6.0 113 Name=="ssse3.pabs.d.128" || // Added in 6.0 114 Name.startswith("fma4.vfmadd.s") || // Added in 7.0 115 Name.startswith("fma.vfmadd.") || // Added in 7.0 116 Name.startswith("fma.vfmsub.") || // Added in 7.0 117 Name.startswith("fma.vfmsubadd.") || // Added in 7.0 118 Name.startswith("fma.vfnmadd.") || // Added in 7.0 119 Name.startswith("fma.vfnmsub.") || // Added in 7.0 120 Name.startswith("avx512.mask.vfmadd.") || // Added in 7.0 121 Name.startswith("avx512.mask.vfnmadd.") || // Added in 7.0 122 Name.startswith("avx512.mask.vfnmsub.") || // Added in 7.0 123 Name.startswith("avx512.mask3.vfmadd.") || // Added in 7.0 124 Name.startswith("avx512.maskz.vfmadd.") || // Added in 7.0 125 Name.startswith("avx512.mask3.vfmsub.") || // Added in 7.0 126 Name.startswith("avx512.mask3.vfnmsub.") || // Added in 7.0 127 Name.startswith("avx512.mask.vfmaddsub.") || // Added in 7.0 128 Name.startswith("avx512.maskz.vfmaddsub.") || // Added in 7.0 129 Name.startswith("avx512.mask3.vfmaddsub.") || // Added in 7.0 130 Name.startswith("avx512.mask3.vfmsubadd.") || // Added in 7.0 131 Name.startswith("avx512.mask.shuf.i") || // Added in 6.0 132 Name.startswith("avx512.mask.shuf.f") || // Added in 6.0 133 Name.startswith("avx512.kunpck") || //added in 6.0 134 Name.startswith("avx2.pabs.") || // Added in 6.0 135 Name.startswith("avx512.mask.pabs.") || // Added in 6.0 136 Name.startswith("avx512.broadcastm") || // Added in 6.0 137 Name == "sse.sqrt.ss" || // Added in 7.0 138 Name == "sse2.sqrt.sd" || // Added in 7.0 139 Name.startswith("avx512.mask.sqrt.p") || // Added in 7.0 140 Name.startswith("avx.sqrt.p") || // Added in 7.0 141 Name.startswith("sse2.sqrt.p") || // Added in 7.0 142 Name.startswith("sse.sqrt.p") || // Added in 7.0 143 Name.startswith("avx512.mask.pbroadcast") || // Added in 6.0 144 Name.startswith("sse2.pcmpeq.") || // Added in 3.1 145 Name.startswith("sse2.pcmpgt.") || // Added in 3.1 146 Name.startswith("avx2.pcmpeq.") || // Added in 3.1 147 Name.startswith("avx2.pcmpgt.") || // Added in 3.1 148 Name.startswith("avx512.mask.pcmpeq.") || // Added in 3.9 149 Name.startswith("avx512.mask.pcmpgt.") || // Added in 3.9 150 Name.startswith("avx.vperm2f128.") || // Added in 6.0 151 Name == "avx2.vperm2i128" || // Added in 6.0 152 Name == "sse.add.ss" || // Added in 4.0 153 Name == "sse2.add.sd" || // Added in 4.0 154 Name == "sse.sub.ss" || // Added in 4.0 155 Name == "sse2.sub.sd" || // Added in 4.0 156 Name == "sse.mul.ss" || // Added in 4.0 157 Name == "sse2.mul.sd" || // Added in 4.0 158 Name == "sse.div.ss" || // Added in 4.0 159 Name == "sse2.div.sd" || // Added in 4.0 160 Name == "sse41.pmaxsb" || // Added in 3.9 161 Name == "sse2.pmaxs.w" || // Added in 3.9 162 Name == "sse41.pmaxsd" || // Added in 3.9 163 Name == "sse2.pmaxu.b" || // Added in 3.9 164 Name == "sse41.pmaxuw" || // Added in 3.9 165 Name == "sse41.pmaxud" || // Added in 3.9 166 Name == "sse41.pminsb" || // Added in 3.9 167 Name == "sse2.pmins.w" || // Added in 3.9 168 Name == "sse41.pminsd" || // Added in 3.9 169 Name == "sse2.pminu.b" || // Added in 3.9 170 Name == "sse41.pminuw" || // Added in 3.9 171 Name == "sse41.pminud" || // Added in 3.9 172 Name == "avx512.kand.w" || // Added in 7.0 173 Name == "avx512.kandn.w" || // Added in 7.0 174 Name == "avx512.knot.w" || // Added in 7.0 175 Name == "avx512.kor.w" || // Added in 7.0 176 Name == "avx512.kxor.w" || // Added in 7.0 177 Name == "avx512.kxnor.w" || // Added in 7.0 178 Name == "avx512.kortestc.w" || // Added in 7.0 179 Name == "avx512.kortestz.w" || // Added in 7.0 180 Name.startswith("avx512.mask.pshuf.b.") || // Added in 4.0 181 Name.startswith("avx2.pmax") || // Added in 3.9 182 Name.startswith("avx2.pmin") || // Added in 3.9 183 Name.startswith("avx512.mask.pmax") || // Added in 4.0 184 Name.startswith("avx512.mask.pmin") || // Added in 4.0 185 Name.startswith("avx2.vbroadcast") || // Added in 3.8 186 Name.startswith("avx2.pbroadcast") || // Added in 3.8 187 Name.startswith("avx.vpermil.") || // Added in 3.1 188 Name.startswith("sse2.pshuf") || // Added in 3.9 189 Name.startswith("avx512.pbroadcast") || // Added in 3.9 190 Name.startswith("avx512.mask.broadcast.s") || // Added in 3.9 191 Name.startswith("avx512.mask.movddup") || // Added in 3.9 192 Name.startswith("avx512.mask.movshdup") || // Added in 3.9 193 Name.startswith("avx512.mask.movsldup") || // Added in 3.9 194 Name.startswith("avx512.mask.pshuf.d.") || // Added in 3.9 195 Name.startswith("avx512.mask.pshufl.w.") || // Added in 3.9 196 Name.startswith("avx512.mask.pshufh.w.") || // Added in 3.9 197 Name.startswith("avx512.mask.shuf.p") || // Added in 4.0 198 Name.startswith("avx512.mask.vpermil.p") || // Added in 3.9 199 Name.startswith("avx512.mask.perm.df.") || // Added in 3.9 200 Name.startswith("avx512.mask.perm.di.") || // Added in 3.9 201 Name.startswith("avx512.mask.punpckl") || // Added in 3.9 202 Name.startswith("avx512.mask.punpckh") || // Added in 3.9 203 Name.startswith("avx512.mask.unpckl.") || // Added in 3.9 204 Name.startswith("avx512.mask.unpckh.") || // Added in 3.9 205 Name.startswith("avx512.mask.pand.") || // Added in 3.9 206 Name.startswith("avx512.mask.pandn.") || // Added in 3.9 207 Name.startswith("avx512.mask.por.") || // Added in 3.9 208 Name.startswith("avx512.mask.pxor.") || // Added in 3.9 209 Name.startswith("avx512.mask.and.") || // Added in 3.9 210 Name.startswith("avx512.mask.andn.") || // Added in 3.9 211 Name.startswith("avx512.mask.or.") || // Added in 3.9 212 Name.startswith("avx512.mask.xor.") || // Added in 3.9 213 Name.startswith("avx512.mask.padd.") || // Added in 4.0 214 Name.startswith("avx512.mask.psub.") || // Added in 4.0 215 Name.startswith("avx512.mask.pmull.") || // Added in 4.0 216 Name.startswith("avx512.mask.cvtdq2pd.") || // Added in 4.0 217 Name.startswith("avx512.mask.cvtudq2pd.") || // Added in 4.0 218 Name.startswith("avx512.mask.cvtudq2ps.") || // Added in 7.0 updated 9.0 219 Name.startswith("avx512.mask.cvtqq2pd.") || // Added in 7.0 updated 9.0 220 Name.startswith("avx512.mask.cvtuqq2pd.") || // Added in 7.0 updated 9.0 221 Name.startswith("avx512.mask.cvtdq2ps.") || // Added in 7.0 updated 9.0 222 Name == "avx512.mask.vcvtph2ps.128" || // Added in 11.0 223 Name == "avx512.mask.vcvtph2ps.256" || // Added in 11.0 224 Name == "avx512.mask.cvtqq2ps.256" || // Added in 9.0 225 Name == "avx512.mask.cvtqq2ps.512" || // Added in 9.0 226 Name == "avx512.mask.cvtuqq2ps.256" || // Added in 9.0 227 Name == "avx512.mask.cvtuqq2ps.512" || // Added in 9.0 228 Name == "avx512.mask.cvtpd2dq.256" || // Added in 7.0 229 Name == "avx512.mask.cvtpd2ps.256" || // Added in 7.0 230 Name == "avx512.mask.cvttpd2dq.256" || // Added in 7.0 231 Name == "avx512.mask.cvttps2dq.128" || // Added in 7.0 232 Name == "avx512.mask.cvttps2dq.256" || // Added in 7.0 233 Name == "avx512.mask.cvtps2pd.128" || // Added in 7.0 234 Name == "avx512.mask.cvtps2pd.256" || // Added in 7.0 235 Name == "avx512.cvtusi2sd" || // Added in 7.0 236 Name.startswith("avx512.mask.permvar.") || // Added in 7.0 237 Name == "sse2.pmulu.dq" || // Added in 7.0 238 Name == "sse41.pmuldq" || // Added in 7.0 239 Name == "avx2.pmulu.dq" || // Added in 7.0 240 Name == "avx2.pmul.dq" || // Added in 7.0 241 Name == "avx512.pmulu.dq.512" || // Added in 7.0 242 Name == "avx512.pmul.dq.512" || // Added in 7.0 243 Name.startswith("avx512.mask.pmul.dq.") || // Added in 4.0 244 Name.startswith("avx512.mask.pmulu.dq.") || // Added in 4.0 245 Name.startswith("avx512.mask.pmul.hr.sw.") || // Added in 7.0 246 Name.startswith("avx512.mask.pmulh.w.") || // Added in 7.0 247 Name.startswith("avx512.mask.pmulhu.w.") || // Added in 7.0 248 Name.startswith("avx512.mask.pmaddw.d.") || // Added in 7.0 249 Name.startswith("avx512.mask.pmaddubs.w.") || // Added in 7.0 250 Name.startswith("avx512.mask.packsswb.") || // Added in 5.0 251 Name.startswith("avx512.mask.packssdw.") || // Added in 5.0 252 Name.startswith("avx512.mask.packuswb.") || // Added in 5.0 253 Name.startswith("avx512.mask.packusdw.") || // Added in 5.0 254 Name.startswith("avx512.mask.cmp.b") || // Added in 5.0 255 Name.startswith("avx512.mask.cmp.d") || // Added in 5.0 256 Name.startswith("avx512.mask.cmp.q") || // Added in 5.0 257 Name.startswith("avx512.mask.cmp.w") || // Added in 5.0 258 Name.startswith("avx512.cmp.p") || // Added in 12.0 259 Name.startswith("avx512.mask.ucmp.") || // Added in 5.0 260 Name.startswith("avx512.cvtb2mask.") || // Added in 7.0 261 Name.startswith("avx512.cvtw2mask.") || // Added in 7.0 262 Name.startswith("avx512.cvtd2mask.") || // Added in 7.0 263 Name.startswith("avx512.cvtq2mask.") || // Added in 7.0 264 Name.startswith("avx512.mask.vpermilvar.") || // Added in 4.0 265 Name.startswith("avx512.mask.psll.d") || // Added in 4.0 266 Name.startswith("avx512.mask.psll.q") || // Added in 4.0 267 Name.startswith("avx512.mask.psll.w") || // Added in 4.0 268 Name.startswith("avx512.mask.psra.d") || // Added in 4.0 269 Name.startswith("avx512.mask.psra.q") || // Added in 4.0 270 Name.startswith("avx512.mask.psra.w") || // Added in 4.0 271 Name.startswith("avx512.mask.psrl.d") || // Added in 4.0 272 Name.startswith("avx512.mask.psrl.q") || // Added in 4.0 273 Name.startswith("avx512.mask.psrl.w") || // Added in 4.0 274 Name.startswith("avx512.mask.pslli") || // Added in 4.0 275 Name.startswith("avx512.mask.psrai") || // Added in 4.0 276 Name.startswith("avx512.mask.psrli") || // Added in 4.0 277 Name.startswith("avx512.mask.psllv") || // Added in 4.0 278 Name.startswith("avx512.mask.psrav") || // Added in 4.0 279 Name.startswith("avx512.mask.psrlv") || // Added in 4.0 280 Name.startswith("sse41.pmovsx") || // Added in 3.8 281 Name.startswith("sse41.pmovzx") || // Added in 3.9 282 Name.startswith("avx2.pmovsx") || // Added in 3.9 283 Name.startswith("avx2.pmovzx") || // Added in 3.9 284 Name.startswith("avx512.mask.pmovsx") || // Added in 4.0 285 Name.startswith("avx512.mask.pmovzx") || // Added in 4.0 286 Name.startswith("avx512.mask.lzcnt.") || // Added in 5.0 287 Name.startswith("avx512.mask.pternlog.") || // Added in 7.0 288 Name.startswith("avx512.maskz.pternlog.") || // Added in 7.0 289 Name.startswith("avx512.mask.vpmadd52") || // Added in 7.0 290 Name.startswith("avx512.maskz.vpmadd52") || // Added in 7.0 291 Name.startswith("avx512.mask.vpermi2var.") || // Added in 7.0 292 Name.startswith("avx512.mask.vpermt2var.") || // Added in 7.0 293 Name.startswith("avx512.maskz.vpermt2var.") || // Added in 7.0 294 Name.startswith("avx512.mask.vpdpbusd.") || // Added in 7.0 295 Name.startswith("avx512.maskz.vpdpbusd.") || // Added in 7.0 296 Name.startswith("avx512.mask.vpdpbusds.") || // Added in 7.0 297 Name.startswith("avx512.maskz.vpdpbusds.") || // Added in 7.0 298 Name.startswith("avx512.mask.vpdpwssd.") || // Added in 7.0 299 Name.startswith("avx512.maskz.vpdpwssd.") || // Added in 7.0 300 Name.startswith("avx512.mask.vpdpwssds.") || // Added in 7.0 301 Name.startswith("avx512.maskz.vpdpwssds.") || // Added in 7.0 302 Name.startswith("avx512.mask.dbpsadbw.") || // Added in 7.0 303 Name.startswith("avx512.mask.vpshld.") || // Added in 7.0 304 Name.startswith("avx512.mask.vpshrd.") || // Added in 7.0 305 Name.startswith("avx512.mask.vpshldv.") || // Added in 8.0 306 Name.startswith("avx512.mask.vpshrdv.") || // Added in 8.0 307 Name.startswith("avx512.maskz.vpshldv.") || // Added in 8.0 308 Name.startswith("avx512.maskz.vpshrdv.") || // Added in 8.0 309 Name.startswith("avx512.vpshld.") || // Added in 8.0 310 Name.startswith("avx512.vpshrd.") || // Added in 8.0 311 Name.startswith("avx512.mask.add.p") || // Added in 7.0. 128/256 in 4.0 312 Name.startswith("avx512.mask.sub.p") || // Added in 7.0. 128/256 in 4.0 313 Name.startswith("avx512.mask.mul.p") || // Added in 7.0. 128/256 in 4.0 314 Name.startswith("avx512.mask.div.p") || // Added in 7.0. 128/256 in 4.0 315 Name.startswith("avx512.mask.max.p") || // Added in 7.0. 128/256 in 5.0 316 Name.startswith("avx512.mask.min.p") || // Added in 7.0. 128/256 in 5.0 317 Name.startswith("avx512.mask.fpclass.p") || // Added in 7.0 318 Name.startswith("avx512.mask.vpshufbitqmb.") || // Added in 8.0 319 Name.startswith("avx512.mask.pmultishift.qb.") || // Added in 8.0 320 Name.startswith("avx512.mask.conflict.") || // Added in 9.0 321 Name == "avx512.mask.pmov.qd.256" || // Added in 9.0 322 Name == "avx512.mask.pmov.qd.512" || // Added in 9.0 323 Name == "avx512.mask.pmov.wb.256" || // Added in 9.0 324 Name == "avx512.mask.pmov.wb.512" || // Added in 9.0 325 Name == "sse.cvtsi2ss" || // Added in 7.0 326 Name == "sse.cvtsi642ss" || // Added in 7.0 327 Name == "sse2.cvtsi2sd" || // Added in 7.0 328 Name == "sse2.cvtsi642sd" || // Added in 7.0 329 Name == "sse2.cvtss2sd" || // Added in 7.0 330 Name == "sse2.cvtdq2pd" || // Added in 3.9 331 Name == "sse2.cvtdq2ps" || // Added in 7.0 332 Name == "sse2.cvtps2pd" || // Added in 3.9 333 Name == "avx.cvtdq2.pd.256" || // Added in 3.9 334 Name == "avx.cvtdq2.ps.256" || // Added in 7.0 335 Name == "avx.cvt.ps2.pd.256" || // Added in 3.9 336 Name.startswith("vcvtph2ps.") || // Added in 11.0 337 Name.startswith("avx.vinsertf128.") || // Added in 3.7 338 Name == "avx2.vinserti128" || // Added in 3.7 339 Name.startswith("avx512.mask.insert") || // Added in 4.0 340 Name.startswith("avx.vextractf128.") || // Added in 3.7 341 Name == "avx2.vextracti128" || // Added in 3.7 342 Name.startswith("avx512.mask.vextract") || // Added in 4.0 343 Name.startswith("sse4a.movnt.") || // Added in 3.9 344 Name.startswith("avx.movnt.") || // Added in 3.2 345 Name.startswith("avx512.storent.") || // Added in 3.9 346 Name == "sse41.movntdqa" || // Added in 5.0 347 Name == "avx2.movntdqa" || // Added in 5.0 348 Name == "avx512.movntdqa" || // Added in 5.0 349 Name == "sse2.storel.dq" || // Added in 3.9 350 Name.startswith("sse.storeu.") || // Added in 3.9 351 Name.startswith("sse2.storeu.") || // Added in 3.9 352 Name.startswith("avx.storeu.") || // Added in 3.9 353 Name.startswith("avx512.mask.storeu.") || // Added in 3.9 354 Name.startswith("avx512.mask.store.p") || // Added in 3.9 355 Name.startswith("avx512.mask.store.b.") || // Added in 3.9 356 Name.startswith("avx512.mask.store.w.") || // Added in 3.9 357 Name.startswith("avx512.mask.store.d.") || // Added in 3.9 358 Name.startswith("avx512.mask.store.q.") || // Added in 3.9 359 Name == "avx512.mask.store.ss" || // Added in 7.0 360 Name.startswith("avx512.mask.loadu.") || // Added in 3.9 361 Name.startswith("avx512.mask.load.") || // Added in 3.9 362 Name.startswith("avx512.mask.expand.load.") || // Added in 7.0 363 Name.startswith("avx512.mask.compress.store.") || // Added in 7.0 364 Name.startswith("avx512.mask.expand.b") || // Added in 9.0 365 Name.startswith("avx512.mask.expand.w") || // Added in 9.0 366 Name.startswith("avx512.mask.expand.d") || // Added in 9.0 367 Name.startswith("avx512.mask.expand.q") || // Added in 9.0 368 Name.startswith("avx512.mask.expand.p") || // Added in 9.0 369 Name.startswith("avx512.mask.compress.b") || // Added in 9.0 370 Name.startswith("avx512.mask.compress.w") || // Added in 9.0 371 Name.startswith("avx512.mask.compress.d") || // Added in 9.0 372 Name.startswith("avx512.mask.compress.q") || // Added in 9.0 373 Name.startswith("avx512.mask.compress.p") || // Added in 9.0 374 Name == "sse42.crc32.64.8" || // Added in 3.4 375 Name.startswith("avx.vbroadcast.s") || // Added in 3.5 376 Name.startswith("avx512.vbroadcast.s") || // Added in 7.0 377 Name.startswith("avx512.mask.palignr.") || // Added in 3.9 378 Name.startswith("avx512.mask.valign.") || // Added in 4.0 379 Name.startswith("sse2.psll.dq") || // Added in 3.7 380 Name.startswith("sse2.psrl.dq") || // Added in 3.7 381 Name.startswith("avx2.psll.dq") || // Added in 3.7 382 Name.startswith("avx2.psrl.dq") || // Added in 3.7 383 Name.startswith("avx512.psll.dq") || // Added in 3.9 384 Name.startswith("avx512.psrl.dq") || // Added in 3.9 385 Name == "sse41.pblendw" || // Added in 3.7 386 Name.startswith("sse41.blendp") || // Added in 3.7 387 Name.startswith("avx.blend.p") || // Added in 3.7 388 Name == "avx2.pblendw" || // Added in 3.7 389 Name.startswith("avx2.pblendd.") || // Added in 3.7 390 Name.startswith("avx.vbroadcastf128") || // Added in 4.0 391 Name == "avx2.vbroadcasti128" || // Added in 3.7 392 Name.startswith("avx512.mask.broadcastf32x4.") || // Added in 6.0 393 Name.startswith("avx512.mask.broadcastf64x2.") || // Added in 6.0 394 Name.startswith("avx512.mask.broadcastf32x8.") || // Added in 6.0 395 Name.startswith("avx512.mask.broadcastf64x4.") || // Added in 6.0 396 Name.startswith("avx512.mask.broadcasti32x4.") || // Added in 6.0 397 Name.startswith("avx512.mask.broadcasti64x2.") || // Added in 6.0 398 Name.startswith("avx512.mask.broadcasti32x8.") || // Added in 6.0 399 Name.startswith("avx512.mask.broadcasti64x4.") || // Added in 6.0 400 Name == "xop.vpcmov" || // Added in 3.8 401 Name == "xop.vpcmov.256" || // Added in 5.0 402 Name.startswith("avx512.mask.move.s") || // Added in 4.0 403 Name.startswith("avx512.cvtmask2") || // Added in 5.0 404 Name.startswith("xop.vpcom") || // Added in 3.2, Updated in 9.0 405 Name.startswith("xop.vprot") || // Added in 8.0 406 Name.startswith("avx512.prol") || // Added in 8.0 407 Name.startswith("avx512.pror") || // Added in 8.0 408 Name.startswith("avx512.mask.prorv.") || // Added in 8.0 409 Name.startswith("avx512.mask.pror.") || // Added in 8.0 410 Name.startswith("avx512.mask.prolv.") || // Added in 8.0 411 Name.startswith("avx512.mask.prol.") || // Added in 8.0 412 Name.startswith("avx512.ptestm") || //Added in 6.0 413 Name.startswith("avx512.ptestnm") || //Added in 6.0 414 Name.startswith("avx512.mask.pavg")) // Added in 6.0 415 return true; 416 417 return false; 418 } 419 420 static bool UpgradeX86IntrinsicFunction(Function *F, StringRef Name, 421 Function *&NewFn) { 422 // Only handle intrinsics that start with "x86.". 423 if (!Name.startswith("x86.")) 424 return false; 425 // Remove "x86." prefix. 426 Name = Name.substr(4); 427 428 if (ShouldUpgradeX86Intrinsic(F, Name)) { 429 NewFn = nullptr; 430 return true; 431 } 432 433 if (Name == "rdtscp") { // Added in 8.0 434 // If this intrinsic has 0 operands, it's the new version. 435 if (F->getFunctionType()->getNumParams() == 0) 436 return false; 437 438 rename(F); 439 NewFn = Intrinsic::getDeclaration(F->getParent(), 440 Intrinsic::x86_rdtscp); 441 return true; 442 } 443 444 // SSE4.1 ptest functions may have an old signature. 445 if (Name.startswith("sse41.ptest")) { // Added in 3.2 446 if (Name.substr(11) == "c") 447 return UpgradePTESTIntrinsic(F, Intrinsic::x86_sse41_ptestc, NewFn); 448 if (Name.substr(11) == "z") 449 return UpgradePTESTIntrinsic(F, Intrinsic::x86_sse41_ptestz, NewFn); 450 if (Name.substr(11) == "nzc") 451 return UpgradePTESTIntrinsic(F, Intrinsic::x86_sse41_ptestnzc, NewFn); 452 } 453 // Several blend and other instructions with masks used the wrong number of 454 // bits. 455 if (Name == "sse41.insertps") // Added in 3.6 456 return UpgradeX86IntrinsicsWith8BitMask(F, Intrinsic::x86_sse41_insertps, 457 NewFn); 458 if (Name == "sse41.dppd") // Added in 3.6 459 return UpgradeX86IntrinsicsWith8BitMask(F, Intrinsic::x86_sse41_dppd, 460 NewFn); 461 if (Name == "sse41.dpps") // Added in 3.6 462 return UpgradeX86IntrinsicsWith8BitMask(F, Intrinsic::x86_sse41_dpps, 463 NewFn); 464 if (Name == "sse41.mpsadbw") // Added in 3.6 465 return UpgradeX86IntrinsicsWith8BitMask(F, Intrinsic::x86_sse41_mpsadbw, 466 NewFn); 467 if (Name == "avx.dp.ps.256") // Added in 3.6 468 return UpgradeX86IntrinsicsWith8BitMask(F, Intrinsic::x86_avx_dp_ps_256, 469 NewFn); 470 if (Name == "avx2.mpsadbw") // Added in 3.6 471 return UpgradeX86IntrinsicsWith8BitMask(F, Intrinsic::x86_avx2_mpsadbw, 472 NewFn); 473 if (Name == "avx512.mask.cmp.pd.128") // Added in 7.0 474 return UpgradeX86MaskedFPCompare(F, Intrinsic::x86_avx512_mask_cmp_pd_128, 475 NewFn); 476 if (Name == "avx512.mask.cmp.pd.256") // Added in 7.0 477 return UpgradeX86MaskedFPCompare(F, Intrinsic::x86_avx512_mask_cmp_pd_256, 478 NewFn); 479 if (Name == "avx512.mask.cmp.pd.512") // Added in 7.0 480 return UpgradeX86MaskedFPCompare(F, Intrinsic::x86_avx512_mask_cmp_pd_512, 481 NewFn); 482 if (Name == "avx512.mask.cmp.ps.128") // Added in 7.0 483 return UpgradeX86MaskedFPCompare(F, Intrinsic::x86_avx512_mask_cmp_ps_128, 484 NewFn); 485 if (Name == "avx512.mask.cmp.ps.256") // Added in 7.0 486 return UpgradeX86MaskedFPCompare(F, Intrinsic::x86_avx512_mask_cmp_ps_256, 487 NewFn); 488 if (Name == "avx512.mask.cmp.ps.512") // Added in 7.0 489 return UpgradeX86MaskedFPCompare(F, Intrinsic::x86_avx512_mask_cmp_ps_512, 490 NewFn); 491 492 // frcz.ss/sd may need to have an argument dropped. Added in 3.2 493 if (Name.startswith("xop.vfrcz.ss") && F->arg_size() == 2) { 494 rename(F); 495 NewFn = Intrinsic::getDeclaration(F->getParent(), 496 Intrinsic::x86_xop_vfrcz_ss); 497 return true; 498 } 499 if (Name.startswith("xop.vfrcz.sd") && F->arg_size() == 2) { 500 rename(F); 501 NewFn = Intrinsic::getDeclaration(F->getParent(), 502 Intrinsic::x86_xop_vfrcz_sd); 503 return true; 504 } 505 // Upgrade any XOP PERMIL2 index operand still using a float/double vector. 506 if (Name.startswith("xop.vpermil2")) { // Added in 3.9 507 auto Idx = F->getFunctionType()->getParamType(2); 508 if (Idx->isFPOrFPVectorTy()) { 509 rename(F); 510 unsigned IdxSize = Idx->getPrimitiveSizeInBits(); 511 unsigned EltSize = Idx->getScalarSizeInBits(); 512 Intrinsic::ID Permil2ID; 513 if (EltSize == 64 && IdxSize == 128) 514 Permil2ID = Intrinsic::x86_xop_vpermil2pd; 515 else if (EltSize == 32 && IdxSize == 128) 516 Permil2ID = Intrinsic::x86_xop_vpermil2ps; 517 else if (EltSize == 64 && IdxSize == 256) 518 Permil2ID = Intrinsic::x86_xop_vpermil2pd_256; 519 else 520 Permil2ID = Intrinsic::x86_xop_vpermil2ps_256; 521 NewFn = Intrinsic::getDeclaration(F->getParent(), Permil2ID); 522 return true; 523 } 524 } 525 526 if (Name == "seh.recoverfp") { 527 NewFn = Intrinsic::getDeclaration(F->getParent(), Intrinsic::eh_recoverfp); 528 return true; 529 } 530 531 return false; 532 } 533 534 static bool UpgradeIntrinsicFunction1(Function *F, Function *&NewFn) { 535 assert(F && "Illegal to upgrade a non-existent Function."); 536 537 // Quickly eliminate it, if it's not a candidate. 538 StringRef Name = F->getName(); 539 if (Name.size() <= 8 || !Name.startswith("llvm.")) 540 return false; 541 Name = Name.substr(5); // Strip off "llvm." 542 543 switch (Name[0]) { 544 default: break; 545 case 'a': { 546 if (Name.startswith("arm.rbit") || Name.startswith("aarch64.rbit")) { 547 NewFn = Intrinsic::getDeclaration(F->getParent(), Intrinsic::bitreverse, 548 F->arg_begin()->getType()); 549 return true; 550 } 551 if (Name.startswith("aarch64.neon.frintn")) { 552 NewFn = Intrinsic::getDeclaration(F->getParent(), Intrinsic::roundeven, 553 F->arg_begin()->getType()); 554 return true; 555 } 556 if (Name.startswith("aarch64.neon.rbit")) { 557 NewFn = Intrinsic::getDeclaration(F->getParent(), Intrinsic::bitreverse, 558 F->arg_begin()->getType()); 559 return true; 560 } 561 if (Name.startswith("arm.neon.vclz")) { 562 Type* args[2] = { 563 F->arg_begin()->getType(), 564 Type::getInt1Ty(F->getContext()) 565 }; 566 // Can't use Intrinsic::getDeclaration here as it adds a ".i1" to 567 // the end of the name. Change name from llvm.arm.neon.vclz.* to 568 // llvm.ctlz.* 569 FunctionType* fType = FunctionType::get(F->getReturnType(), args, false); 570 NewFn = Function::Create(fType, F->getLinkage(), F->getAddressSpace(), 571 "llvm.ctlz." + Name.substr(14), F->getParent()); 572 return true; 573 } 574 if (Name.startswith("arm.neon.vcnt")) { 575 NewFn = Intrinsic::getDeclaration(F->getParent(), Intrinsic::ctpop, 576 F->arg_begin()->getType()); 577 return true; 578 } 579 static const Regex vldRegex("^arm\\.neon\\.vld([1234]|[234]lane)\\.v[a-z0-9]*$"); 580 if (vldRegex.match(Name)) { 581 auto fArgs = F->getFunctionType()->params(); 582 SmallVector<Type *, 4> Tys(fArgs.begin(), fArgs.end()); 583 // Can't use Intrinsic::getDeclaration here as the return types might 584 // then only be structurally equal. 585 FunctionType* fType = FunctionType::get(F->getReturnType(), Tys, false); 586 NewFn = Function::Create(fType, F->getLinkage(), F->getAddressSpace(), 587 "llvm." + Name + ".p0i8", F->getParent()); 588 return true; 589 } 590 static const Regex vstRegex("^arm\\.neon\\.vst([1234]|[234]lane)\\.v[a-z0-9]*$"); 591 if (vstRegex.match(Name)) { 592 static const Intrinsic::ID StoreInts[] = {Intrinsic::arm_neon_vst1, 593 Intrinsic::arm_neon_vst2, 594 Intrinsic::arm_neon_vst3, 595 Intrinsic::arm_neon_vst4}; 596 597 static const Intrinsic::ID StoreLaneInts[] = { 598 Intrinsic::arm_neon_vst2lane, Intrinsic::arm_neon_vst3lane, 599 Intrinsic::arm_neon_vst4lane 600 }; 601 602 auto fArgs = F->getFunctionType()->params(); 603 Type *Tys[] = {fArgs[0], fArgs[1]}; 604 if (Name.find("lane") == StringRef::npos) 605 NewFn = Intrinsic::getDeclaration(F->getParent(), 606 StoreInts[fArgs.size() - 3], Tys); 607 else 608 NewFn = Intrinsic::getDeclaration(F->getParent(), 609 StoreLaneInts[fArgs.size() - 5], Tys); 610 return true; 611 } 612 if (Name == "aarch64.thread.pointer" || Name == "arm.thread.pointer") { 613 NewFn = Intrinsic::getDeclaration(F->getParent(), Intrinsic::thread_pointer); 614 return true; 615 } 616 if (Name.startswith("arm.neon.vqadds.")) { 617 NewFn = Intrinsic::getDeclaration(F->getParent(), Intrinsic::sadd_sat, 618 F->arg_begin()->getType()); 619 return true; 620 } 621 if (Name.startswith("arm.neon.vqaddu.")) { 622 NewFn = Intrinsic::getDeclaration(F->getParent(), Intrinsic::uadd_sat, 623 F->arg_begin()->getType()); 624 return true; 625 } 626 if (Name.startswith("arm.neon.vqsubs.")) { 627 NewFn = Intrinsic::getDeclaration(F->getParent(), Intrinsic::ssub_sat, 628 F->arg_begin()->getType()); 629 return true; 630 } 631 if (Name.startswith("arm.neon.vqsubu.")) { 632 NewFn = Intrinsic::getDeclaration(F->getParent(), Intrinsic::usub_sat, 633 F->arg_begin()->getType()); 634 return true; 635 } 636 if (Name.startswith("aarch64.neon.addp")) { 637 if (F->arg_size() != 2) 638 break; // Invalid IR. 639 VectorType *Ty = dyn_cast<VectorType>(F->getReturnType()); 640 if (Ty && Ty->getElementType()->isFloatingPointTy()) { 641 NewFn = Intrinsic::getDeclaration(F->getParent(), 642 Intrinsic::aarch64_neon_faddp, Ty); 643 return true; 644 } 645 } 646 647 // Changed in 12.0: bfdot accept v4bf16 and v8bf16 instead of v8i8 and v16i8 648 // respectively 649 if ((Name.startswith("arm.neon.bfdot.") || 650 Name.startswith("aarch64.neon.bfdot.")) && 651 Name.endswith("i8")) { 652 Intrinsic::ID IID = 653 StringSwitch<Intrinsic::ID>(Name) 654 .Cases("arm.neon.bfdot.v2f32.v8i8", 655 "arm.neon.bfdot.v4f32.v16i8", 656 Intrinsic::arm_neon_bfdot) 657 .Cases("aarch64.neon.bfdot.v2f32.v8i8", 658 "aarch64.neon.bfdot.v4f32.v16i8", 659 Intrinsic::aarch64_neon_bfdot) 660 .Default(Intrinsic::not_intrinsic); 661 if (IID == Intrinsic::not_intrinsic) 662 break; 663 664 size_t OperandWidth = F->getReturnType()->getPrimitiveSizeInBits(); 665 assert((OperandWidth == 64 || OperandWidth == 128) && 666 "Unexpected operand width"); 667 LLVMContext &Ctx = F->getParent()->getContext(); 668 std::array<Type *, 2> Tys {{ 669 F->getReturnType(), 670 FixedVectorType::get(Type::getBFloatTy(Ctx), OperandWidth / 16) 671 }}; 672 NewFn = Intrinsic::getDeclaration(F->getParent(), IID, Tys); 673 return true; 674 } 675 676 // Changed in 12.0: bfmmla, bfmlalb and bfmlalt are not polymorphic anymore 677 // and accept v8bf16 instead of v16i8 678 if ((Name.startswith("arm.neon.bfm") || 679 Name.startswith("aarch64.neon.bfm")) && 680 Name.endswith(".v4f32.v16i8")) { 681 Intrinsic::ID IID = 682 StringSwitch<Intrinsic::ID>(Name) 683 .Case("arm.neon.bfmmla.v4f32.v16i8", 684 Intrinsic::arm_neon_bfmmla) 685 .Case("arm.neon.bfmlalb.v4f32.v16i8", 686 Intrinsic::arm_neon_bfmlalb) 687 .Case("arm.neon.bfmlalt.v4f32.v16i8", 688 Intrinsic::arm_neon_bfmlalt) 689 .Case("aarch64.neon.bfmmla.v4f32.v16i8", 690 Intrinsic::aarch64_neon_bfmmla) 691 .Case("aarch64.neon.bfmlalb.v4f32.v16i8", 692 Intrinsic::aarch64_neon_bfmlalb) 693 .Case("aarch64.neon.bfmlalt.v4f32.v16i8", 694 Intrinsic::aarch64_neon_bfmlalt) 695 .Default(Intrinsic::not_intrinsic); 696 if (IID == Intrinsic::not_intrinsic) 697 break; 698 699 std::array<Type *, 0> Tys; 700 NewFn = Intrinsic::getDeclaration(F->getParent(), IID, Tys); 701 return true; 702 } 703 break; 704 } 705 706 case 'c': { 707 if (Name.startswith("ctlz.") && F->arg_size() == 1) { 708 rename(F); 709 NewFn = Intrinsic::getDeclaration(F->getParent(), Intrinsic::ctlz, 710 F->arg_begin()->getType()); 711 return true; 712 } 713 if (Name.startswith("cttz.") && F->arg_size() == 1) { 714 rename(F); 715 NewFn = Intrinsic::getDeclaration(F->getParent(), Intrinsic::cttz, 716 F->arg_begin()->getType()); 717 return true; 718 } 719 break; 720 } 721 case 'd': { 722 if (Name == "dbg.value" && F->arg_size() == 4) { 723 rename(F); 724 NewFn = Intrinsic::getDeclaration(F->getParent(), Intrinsic::dbg_value); 725 return true; 726 } 727 break; 728 } 729 case 'e': { 730 SmallVector<StringRef, 2> Groups; 731 static const Regex R("^experimental.vector.reduce.([a-z]+)\\.[a-z][0-9]+"); 732 if (R.match(Name, &Groups)) { 733 Intrinsic::ID ID; 734 ID = StringSwitch<Intrinsic::ID>(Groups[1]) 735 .Case("add", Intrinsic::vector_reduce_add) 736 .Case("mul", Intrinsic::vector_reduce_mul) 737 .Case("and", Intrinsic::vector_reduce_and) 738 .Case("or", Intrinsic::vector_reduce_or) 739 .Case("xor", Intrinsic::vector_reduce_xor) 740 .Case("smax", Intrinsic::vector_reduce_smax) 741 .Case("smin", Intrinsic::vector_reduce_smin) 742 .Case("umax", Intrinsic::vector_reduce_umax) 743 .Case("umin", Intrinsic::vector_reduce_umin) 744 .Case("fmax", Intrinsic::vector_reduce_fmax) 745 .Case("fmin", Intrinsic::vector_reduce_fmin) 746 .Default(Intrinsic::not_intrinsic); 747 if (ID != Intrinsic::not_intrinsic) { 748 rename(F); 749 auto Args = F->getFunctionType()->params(); 750 NewFn = Intrinsic::getDeclaration(F->getParent(), ID, {Args[0]}); 751 return true; 752 } 753 } 754 static const Regex R2( 755 "^experimental.vector.reduce.v2.([a-z]+)\\.[fi][0-9]+"); 756 Groups.clear(); 757 if (R2.match(Name, &Groups)) { 758 Intrinsic::ID ID = Intrinsic::not_intrinsic; 759 if (Groups[1] == "fadd") 760 ID = Intrinsic::vector_reduce_fadd; 761 if (Groups[1] == "fmul") 762 ID = Intrinsic::vector_reduce_fmul; 763 if (ID != Intrinsic::not_intrinsic) { 764 rename(F); 765 auto Args = F->getFunctionType()->params(); 766 Type *Tys[] = {Args[1]}; 767 NewFn = Intrinsic::getDeclaration(F->getParent(), ID, Tys); 768 return true; 769 } 770 } 771 break; 772 } 773 case 'i': 774 case 'l': { 775 bool IsLifetimeStart = Name.startswith("lifetime.start"); 776 if (IsLifetimeStart || Name.startswith("invariant.start")) { 777 Intrinsic::ID ID = IsLifetimeStart ? 778 Intrinsic::lifetime_start : Intrinsic::invariant_start; 779 auto Args = F->getFunctionType()->params(); 780 Type* ObjectPtr[1] = {Args[1]}; 781 if (F->getName() != Intrinsic::getName(ID, ObjectPtr, F->getParent())) { 782 rename(F); 783 NewFn = Intrinsic::getDeclaration(F->getParent(), ID, ObjectPtr); 784 return true; 785 } 786 } 787 788 bool IsLifetimeEnd = Name.startswith("lifetime.end"); 789 if (IsLifetimeEnd || Name.startswith("invariant.end")) { 790 Intrinsic::ID ID = IsLifetimeEnd ? 791 Intrinsic::lifetime_end : Intrinsic::invariant_end; 792 793 auto Args = F->getFunctionType()->params(); 794 Type* ObjectPtr[1] = {Args[IsLifetimeEnd ? 1 : 2]}; 795 if (F->getName() != Intrinsic::getName(ID, ObjectPtr, F->getParent())) { 796 rename(F); 797 NewFn = Intrinsic::getDeclaration(F->getParent(), ID, ObjectPtr); 798 return true; 799 } 800 } 801 if (Name.startswith("invariant.group.barrier")) { 802 // Rename invariant.group.barrier to launder.invariant.group 803 auto Args = F->getFunctionType()->params(); 804 Type* ObjectPtr[1] = {Args[0]}; 805 rename(F); 806 NewFn = Intrinsic::getDeclaration(F->getParent(), 807 Intrinsic::launder_invariant_group, ObjectPtr); 808 return true; 809 810 } 811 812 break; 813 } 814 case 'm': { 815 if (Name.startswith("masked.load.")) { 816 Type *Tys[] = { F->getReturnType(), F->arg_begin()->getType() }; 817 if (F->getName() != 818 Intrinsic::getName(Intrinsic::masked_load, Tys, F->getParent())) { 819 rename(F); 820 NewFn = Intrinsic::getDeclaration(F->getParent(), 821 Intrinsic::masked_load, 822 Tys); 823 return true; 824 } 825 } 826 if (Name.startswith("masked.store.")) { 827 auto Args = F->getFunctionType()->params(); 828 Type *Tys[] = { Args[0], Args[1] }; 829 if (F->getName() != 830 Intrinsic::getName(Intrinsic::masked_store, Tys, F->getParent())) { 831 rename(F); 832 NewFn = Intrinsic::getDeclaration(F->getParent(), 833 Intrinsic::masked_store, 834 Tys); 835 return true; 836 } 837 } 838 // Renaming gather/scatter intrinsics with no address space overloading 839 // to the new overload which includes an address space 840 if (Name.startswith("masked.gather.")) { 841 Type *Tys[] = {F->getReturnType(), F->arg_begin()->getType()}; 842 if (F->getName() != 843 Intrinsic::getName(Intrinsic::masked_gather, Tys, F->getParent())) { 844 rename(F); 845 NewFn = Intrinsic::getDeclaration(F->getParent(), 846 Intrinsic::masked_gather, Tys); 847 return true; 848 } 849 } 850 if (Name.startswith("masked.scatter.")) { 851 auto Args = F->getFunctionType()->params(); 852 Type *Tys[] = {Args[0], Args[1]}; 853 if (F->getName() != 854 Intrinsic::getName(Intrinsic::masked_scatter, Tys, F->getParent())) { 855 rename(F); 856 NewFn = Intrinsic::getDeclaration(F->getParent(), 857 Intrinsic::masked_scatter, Tys); 858 return true; 859 } 860 } 861 // Updating the memory intrinsics (memcpy/memmove/memset) that have an 862 // alignment parameter to embedding the alignment as an attribute of 863 // the pointer args. 864 if (Name.startswith("memcpy.") && F->arg_size() == 5) { 865 rename(F); 866 // Get the types of dest, src, and len 867 ArrayRef<Type *> ParamTypes = F->getFunctionType()->params().slice(0, 3); 868 NewFn = Intrinsic::getDeclaration(F->getParent(), Intrinsic::memcpy, 869 ParamTypes); 870 return true; 871 } 872 if (Name.startswith("memmove.") && F->arg_size() == 5) { 873 rename(F); 874 // Get the types of dest, src, and len 875 ArrayRef<Type *> ParamTypes = F->getFunctionType()->params().slice(0, 3); 876 NewFn = Intrinsic::getDeclaration(F->getParent(), Intrinsic::memmove, 877 ParamTypes); 878 return true; 879 } 880 if (Name.startswith("memset.") && F->arg_size() == 5) { 881 rename(F); 882 // Get the types of dest, and len 883 const auto *FT = F->getFunctionType(); 884 Type *ParamTypes[2] = { 885 FT->getParamType(0), // Dest 886 FT->getParamType(2) // len 887 }; 888 NewFn = Intrinsic::getDeclaration(F->getParent(), Intrinsic::memset, 889 ParamTypes); 890 return true; 891 } 892 break; 893 } 894 case 'n': { 895 if (Name.startswith("nvvm.")) { 896 Name = Name.substr(5); 897 898 // The following nvvm intrinsics correspond exactly to an LLVM intrinsic. 899 Intrinsic::ID IID = StringSwitch<Intrinsic::ID>(Name) 900 .Cases("brev32", "brev64", Intrinsic::bitreverse) 901 .Case("clz.i", Intrinsic::ctlz) 902 .Case("popc.i", Intrinsic::ctpop) 903 .Default(Intrinsic::not_intrinsic); 904 if (IID != Intrinsic::not_intrinsic && F->arg_size() == 1) { 905 NewFn = Intrinsic::getDeclaration(F->getParent(), IID, 906 {F->getReturnType()}); 907 return true; 908 } 909 910 // The following nvvm intrinsics correspond exactly to an LLVM idiom, but 911 // not to an intrinsic alone. We expand them in UpgradeIntrinsicCall. 912 // 913 // TODO: We could add lohi.i2d. 914 bool Expand = StringSwitch<bool>(Name) 915 .Cases("abs.i", "abs.ll", true) 916 .Cases("clz.ll", "popc.ll", "h2f", true) 917 .Cases("max.i", "max.ll", "max.ui", "max.ull", true) 918 .Cases("min.i", "min.ll", "min.ui", "min.ull", true) 919 .StartsWith("atomic.load.add.f32.p", true) 920 .StartsWith("atomic.load.add.f64.p", true) 921 .Default(false); 922 if (Expand) { 923 NewFn = nullptr; 924 return true; 925 } 926 } 927 break; 928 } 929 case 'o': 930 // We only need to change the name to match the mangling including the 931 // address space. 932 if (Name.startswith("objectsize.")) { 933 Type *Tys[2] = { F->getReturnType(), F->arg_begin()->getType() }; 934 if (F->arg_size() == 2 || F->arg_size() == 3 || 935 F->getName() != 936 Intrinsic::getName(Intrinsic::objectsize, Tys, F->getParent())) { 937 rename(F); 938 NewFn = Intrinsic::getDeclaration(F->getParent(), Intrinsic::objectsize, 939 Tys); 940 return true; 941 } 942 } 943 break; 944 945 case 'p': 946 if (Name == "prefetch") { 947 // Handle address space overloading. 948 Type *Tys[] = {F->arg_begin()->getType()}; 949 if (F->getName() != 950 Intrinsic::getName(Intrinsic::prefetch, Tys, F->getParent())) { 951 rename(F); 952 NewFn = 953 Intrinsic::getDeclaration(F->getParent(), Intrinsic::prefetch, Tys); 954 return true; 955 } 956 } else if (Name.startswith("ptr.annotation.") && F->arg_size() == 4) { 957 rename(F); 958 NewFn = Intrinsic::getDeclaration(F->getParent(), 959 Intrinsic::ptr_annotation, 960 F->arg_begin()->getType()); 961 return true; 962 } 963 break; 964 965 case 's': 966 if (Name == "stackprotectorcheck") { 967 NewFn = nullptr; 968 return true; 969 } 970 break; 971 972 case 'v': { 973 if (Name == "var.annotation" && F->arg_size() == 4) { 974 rename(F); 975 NewFn = Intrinsic::getDeclaration(F->getParent(), 976 Intrinsic::var_annotation); 977 return true; 978 } 979 break; 980 } 981 982 case 'x': 983 if (UpgradeX86IntrinsicFunction(F, Name, NewFn)) 984 return true; 985 } 986 // Remangle our intrinsic since we upgrade the mangling 987 auto Result = llvm::Intrinsic::remangleIntrinsicFunction(F); 988 if (Result != None) { 989 NewFn = Result.getValue(); 990 return true; 991 } 992 993 // This may not belong here. This function is effectively being overloaded 994 // to both detect an intrinsic which needs upgrading, and to provide the 995 // upgraded form of the intrinsic. We should perhaps have two separate 996 // functions for this. 997 return false; 998 } 999 1000 bool llvm::UpgradeIntrinsicFunction(Function *F, Function *&NewFn) { 1001 NewFn = nullptr; 1002 bool Upgraded = UpgradeIntrinsicFunction1(F, NewFn); 1003 assert(F != NewFn && "Intrinsic function upgraded to the same function"); 1004 1005 // Upgrade intrinsic attributes. This does not change the function. 1006 if (NewFn) 1007 F = NewFn; 1008 if (Intrinsic::ID id = F->getIntrinsicID()) 1009 F->setAttributes(Intrinsic::getAttributes(F->getContext(), id)); 1010 return Upgraded; 1011 } 1012 1013 GlobalVariable *llvm::UpgradeGlobalVariable(GlobalVariable *GV) { 1014 if (!(GV->hasName() && (GV->getName() == "llvm.global_ctors" || 1015 GV->getName() == "llvm.global_dtors")) || 1016 !GV->hasInitializer()) 1017 return nullptr; 1018 ArrayType *ATy = dyn_cast<ArrayType>(GV->getValueType()); 1019 if (!ATy) 1020 return nullptr; 1021 StructType *STy = dyn_cast<StructType>(ATy->getElementType()); 1022 if (!STy || STy->getNumElements() != 2) 1023 return nullptr; 1024 1025 LLVMContext &C = GV->getContext(); 1026 IRBuilder<> IRB(C); 1027 auto EltTy = StructType::get(STy->getElementType(0), STy->getElementType(1), 1028 IRB.getInt8PtrTy()); 1029 Constant *Init = GV->getInitializer(); 1030 unsigned N = Init->getNumOperands(); 1031 std::vector<Constant *> NewCtors(N); 1032 for (unsigned i = 0; i != N; ++i) { 1033 auto Ctor = cast<Constant>(Init->getOperand(i)); 1034 NewCtors[i] = ConstantStruct::get( 1035 EltTy, Ctor->getAggregateElement(0u), Ctor->getAggregateElement(1), 1036 Constant::getNullValue(IRB.getInt8PtrTy())); 1037 } 1038 Constant *NewInit = ConstantArray::get(ArrayType::get(EltTy, N), NewCtors); 1039 1040 return new GlobalVariable(NewInit->getType(), false, GV->getLinkage(), 1041 NewInit, GV->getName()); 1042 } 1043 1044 // Handles upgrading SSE2/AVX2/AVX512BW PSLLDQ intrinsics by converting them 1045 // to byte shuffles. 1046 static Value *UpgradeX86PSLLDQIntrinsics(IRBuilder<> &Builder, 1047 Value *Op, unsigned Shift) { 1048 auto *ResultTy = cast<FixedVectorType>(Op->getType()); 1049 unsigned NumElts = ResultTy->getNumElements() * 8; 1050 1051 // Bitcast from a 64-bit element type to a byte element type. 1052 Type *VecTy = FixedVectorType::get(Builder.getInt8Ty(), NumElts); 1053 Op = Builder.CreateBitCast(Op, VecTy, "cast"); 1054 1055 // We'll be shuffling in zeroes. 1056 Value *Res = Constant::getNullValue(VecTy); 1057 1058 // If shift is less than 16, emit a shuffle to move the bytes. Otherwise, 1059 // we'll just return the zero vector. 1060 if (Shift < 16) { 1061 int Idxs[64]; 1062 // 256/512-bit version is split into 2/4 16-byte lanes. 1063 for (unsigned l = 0; l != NumElts; l += 16) 1064 for (unsigned i = 0; i != 16; ++i) { 1065 unsigned Idx = NumElts + i - Shift; 1066 if (Idx < NumElts) 1067 Idx -= NumElts - 16; // end of lane, switch operand. 1068 Idxs[l + i] = Idx + l; 1069 } 1070 1071 Res = Builder.CreateShuffleVector(Res, Op, makeArrayRef(Idxs, NumElts)); 1072 } 1073 1074 // Bitcast back to a 64-bit element type. 1075 return Builder.CreateBitCast(Res, ResultTy, "cast"); 1076 } 1077 1078 // Handles upgrading SSE2/AVX2/AVX512BW PSRLDQ intrinsics by converting them 1079 // to byte shuffles. 1080 static Value *UpgradeX86PSRLDQIntrinsics(IRBuilder<> &Builder, Value *Op, 1081 unsigned Shift) { 1082 auto *ResultTy = cast<FixedVectorType>(Op->getType()); 1083 unsigned NumElts = ResultTy->getNumElements() * 8; 1084 1085 // Bitcast from a 64-bit element type to a byte element type. 1086 Type *VecTy = FixedVectorType::get(Builder.getInt8Ty(), NumElts); 1087 Op = Builder.CreateBitCast(Op, VecTy, "cast"); 1088 1089 // We'll be shuffling in zeroes. 1090 Value *Res = Constant::getNullValue(VecTy); 1091 1092 // If shift is less than 16, emit a shuffle to move the bytes. Otherwise, 1093 // we'll just return the zero vector. 1094 if (Shift < 16) { 1095 int Idxs[64]; 1096 // 256/512-bit version is split into 2/4 16-byte lanes. 1097 for (unsigned l = 0; l != NumElts; l += 16) 1098 for (unsigned i = 0; i != 16; ++i) { 1099 unsigned Idx = i + Shift; 1100 if (Idx >= 16) 1101 Idx += NumElts - 16; // end of lane, switch operand. 1102 Idxs[l + i] = Idx + l; 1103 } 1104 1105 Res = Builder.CreateShuffleVector(Op, Res, makeArrayRef(Idxs, NumElts)); 1106 } 1107 1108 // Bitcast back to a 64-bit element type. 1109 return Builder.CreateBitCast(Res, ResultTy, "cast"); 1110 } 1111 1112 static Value *getX86MaskVec(IRBuilder<> &Builder, Value *Mask, 1113 unsigned NumElts) { 1114 assert(isPowerOf2_32(NumElts) && "Expected power-of-2 mask elements"); 1115 llvm::VectorType *MaskTy = FixedVectorType::get( 1116 Builder.getInt1Ty(), cast<IntegerType>(Mask->getType())->getBitWidth()); 1117 Mask = Builder.CreateBitCast(Mask, MaskTy); 1118 1119 // If we have less than 8 elements (1, 2 or 4), then the starting mask was an 1120 // i8 and we need to extract down to the right number of elements. 1121 if (NumElts <= 4) { 1122 int Indices[4]; 1123 for (unsigned i = 0; i != NumElts; ++i) 1124 Indices[i] = i; 1125 Mask = Builder.CreateShuffleVector( 1126 Mask, Mask, makeArrayRef(Indices, NumElts), "extract"); 1127 } 1128 1129 return Mask; 1130 } 1131 1132 static Value *EmitX86Select(IRBuilder<> &Builder, Value *Mask, 1133 Value *Op0, Value *Op1) { 1134 // If the mask is all ones just emit the first operation. 1135 if (const auto *C = dyn_cast<Constant>(Mask)) 1136 if (C->isAllOnesValue()) 1137 return Op0; 1138 1139 Mask = getX86MaskVec(Builder, Mask, 1140 cast<FixedVectorType>(Op0->getType())->getNumElements()); 1141 return Builder.CreateSelect(Mask, Op0, Op1); 1142 } 1143 1144 static Value *EmitX86ScalarSelect(IRBuilder<> &Builder, Value *Mask, 1145 Value *Op0, Value *Op1) { 1146 // If the mask is all ones just emit the first operation. 1147 if (const auto *C = dyn_cast<Constant>(Mask)) 1148 if (C->isAllOnesValue()) 1149 return Op0; 1150 1151 auto *MaskTy = FixedVectorType::get(Builder.getInt1Ty(), 1152 Mask->getType()->getIntegerBitWidth()); 1153 Mask = Builder.CreateBitCast(Mask, MaskTy); 1154 Mask = Builder.CreateExtractElement(Mask, (uint64_t)0); 1155 return Builder.CreateSelect(Mask, Op0, Op1); 1156 } 1157 1158 // Handle autoupgrade for masked PALIGNR and VALIGND/Q intrinsics. 1159 // PALIGNR handles large immediates by shifting while VALIGN masks the immediate 1160 // so we need to handle both cases. VALIGN also doesn't have 128-bit lanes. 1161 static Value *UpgradeX86ALIGNIntrinsics(IRBuilder<> &Builder, Value *Op0, 1162 Value *Op1, Value *Shift, 1163 Value *Passthru, Value *Mask, 1164 bool IsVALIGN) { 1165 unsigned ShiftVal = cast<llvm::ConstantInt>(Shift)->getZExtValue(); 1166 1167 unsigned NumElts = cast<FixedVectorType>(Op0->getType())->getNumElements(); 1168 assert((IsVALIGN || NumElts % 16 == 0) && "Illegal NumElts for PALIGNR!"); 1169 assert((!IsVALIGN || NumElts <= 16) && "NumElts too large for VALIGN!"); 1170 assert(isPowerOf2_32(NumElts) && "NumElts not a power of 2!"); 1171 1172 // Mask the immediate for VALIGN. 1173 if (IsVALIGN) 1174 ShiftVal &= (NumElts - 1); 1175 1176 // If palignr is shifting the pair of vectors more than the size of two 1177 // lanes, emit zero. 1178 if (ShiftVal >= 32) 1179 return llvm::Constant::getNullValue(Op0->getType()); 1180 1181 // If palignr is shifting the pair of input vectors more than one lane, 1182 // but less than two lanes, convert to shifting in zeroes. 1183 if (ShiftVal > 16) { 1184 ShiftVal -= 16; 1185 Op1 = Op0; 1186 Op0 = llvm::Constant::getNullValue(Op0->getType()); 1187 } 1188 1189 int Indices[64]; 1190 // 256-bit palignr operates on 128-bit lanes so we need to handle that 1191 for (unsigned l = 0; l < NumElts; l += 16) { 1192 for (unsigned i = 0; i != 16; ++i) { 1193 unsigned Idx = ShiftVal + i; 1194 if (!IsVALIGN && Idx >= 16) // Disable wrap for VALIGN. 1195 Idx += NumElts - 16; // End of lane, switch operand. 1196 Indices[l + i] = Idx + l; 1197 } 1198 } 1199 1200 Value *Align = Builder.CreateShuffleVector(Op1, Op0, 1201 makeArrayRef(Indices, NumElts), 1202 "palignr"); 1203 1204 return EmitX86Select(Builder, Mask, Align, Passthru); 1205 } 1206 1207 static Value *UpgradeX86VPERMT2Intrinsics(IRBuilder<> &Builder, CallInst &CI, 1208 bool ZeroMask, bool IndexForm) { 1209 Type *Ty = CI.getType(); 1210 unsigned VecWidth = Ty->getPrimitiveSizeInBits(); 1211 unsigned EltWidth = Ty->getScalarSizeInBits(); 1212 bool IsFloat = Ty->isFPOrFPVectorTy(); 1213 Intrinsic::ID IID; 1214 if (VecWidth == 128 && EltWidth == 32 && IsFloat) 1215 IID = Intrinsic::x86_avx512_vpermi2var_ps_128; 1216 else if (VecWidth == 128 && EltWidth == 32 && !IsFloat) 1217 IID = Intrinsic::x86_avx512_vpermi2var_d_128; 1218 else if (VecWidth == 128 && EltWidth == 64 && IsFloat) 1219 IID = Intrinsic::x86_avx512_vpermi2var_pd_128; 1220 else if (VecWidth == 128 && EltWidth == 64 && !IsFloat) 1221 IID = Intrinsic::x86_avx512_vpermi2var_q_128; 1222 else if (VecWidth == 256 && EltWidth == 32 && IsFloat) 1223 IID = Intrinsic::x86_avx512_vpermi2var_ps_256; 1224 else if (VecWidth == 256 && EltWidth == 32 && !IsFloat) 1225 IID = Intrinsic::x86_avx512_vpermi2var_d_256; 1226 else if (VecWidth == 256 && EltWidth == 64 && IsFloat) 1227 IID = Intrinsic::x86_avx512_vpermi2var_pd_256; 1228 else if (VecWidth == 256 && EltWidth == 64 && !IsFloat) 1229 IID = Intrinsic::x86_avx512_vpermi2var_q_256; 1230 else if (VecWidth == 512 && EltWidth == 32 && IsFloat) 1231 IID = Intrinsic::x86_avx512_vpermi2var_ps_512; 1232 else if (VecWidth == 512 && EltWidth == 32 && !IsFloat) 1233 IID = Intrinsic::x86_avx512_vpermi2var_d_512; 1234 else if (VecWidth == 512 && EltWidth == 64 && IsFloat) 1235 IID = Intrinsic::x86_avx512_vpermi2var_pd_512; 1236 else if (VecWidth == 512 && EltWidth == 64 && !IsFloat) 1237 IID = Intrinsic::x86_avx512_vpermi2var_q_512; 1238 else if (VecWidth == 128 && EltWidth == 16) 1239 IID = Intrinsic::x86_avx512_vpermi2var_hi_128; 1240 else if (VecWidth == 256 && EltWidth == 16) 1241 IID = Intrinsic::x86_avx512_vpermi2var_hi_256; 1242 else if (VecWidth == 512 && EltWidth == 16) 1243 IID = Intrinsic::x86_avx512_vpermi2var_hi_512; 1244 else if (VecWidth == 128 && EltWidth == 8) 1245 IID = Intrinsic::x86_avx512_vpermi2var_qi_128; 1246 else if (VecWidth == 256 && EltWidth == 8) 1247 IID = Intrinsic::x86_avx512_vpermi2var_qi_256; 1248 else if (VecWidth == 512 && EltWidth == 8) 1249 IID = Intrinsic::x86_avx512_vpermi2var_qi_512; 1250 else 1251 llvm_unreachable("Unexpected intrinsic"); 1252 1253 Value *Args[] = { CI.getArgOperand(0) , CI.getArgOperand(1), 1254 CI.getArgOperand(2) }; 1255 1256 // If this isn't index form we need to swap operand 0 and 1. 1257 if (!IndexForm) 1258 std::swap(Args[0], Args[1]); 1259 1260 Value *V = Builder.CreateCall(Intrinsic::getDeclaration(CI.getModule(), IID), 1261 Args); 1262 Value *PassThru = ZeroMask ? ConstantAggregateZero::get(Ty) 1263 : Builder.CreateBitCast(CI.getArgOperand(1), 1264 Ty); 1265 return EmitX86Select(Builder, CI.getArgOperand(3), V, PassThru); 1266 } 1267 1268 static Value *UpgradeX86BinaryIntrinsics(IRBuilder<> &Builder, CallInst &CI, 1269 Intrinsic::ID IID) { 1270 Type *Ty = CI.getType(); 1271 Value *Op0 = CI.getOperand(0); 1272 Value *Op1 = CI.getOperand(1); 1273 Function *Intrin = Intrinsic::getDeclaration(CI.getModule(), IID, Ty); 1274 Value *Res = Builder.CreateCall(Intrin, {Op0, Op1}); 1275 1276 if (CI.getNumArgOperands() == 4) { // For masked intrinsics. 1277 Value *VecSrc = CI.getOperand(2); 1278 Value *Mask = CI.getOperand(3); 1279 Res = EmitX86Select(Builder, Mask, Res, VecSrc); 1280 } 1281 return Res; 1282 } 1283 1284 static Value *upgradeX86Rotate(IRBuilder<> &Builder, CallInst &CI, 1285 bool IsRotateRight) { 1286 Type *Ty = CI.getType(); 1287 Value *Src = CI.getArgOperand(0); 1288 Value *Amt = CI.getArgOperand(1); 1289 1290 // Amount may be scalar immediate, in which case create a splat vector. 1291 // Funnel shifts amounts are treated as modulo and types are all power-of-2 so 1292 // we only care about the lowest log2 bits anyway. 1293 if (Amt->getType() != Ty) { 1294 unsigned NumElts = cast<FixedVectorType>(Ty)->getNumElements(); 1295 Amt = Builder.CreateIntCast(Amt, Ty->getScalarType(), false); 1296 Amt = Builder.CreateVectorSplat(NumElts, Amt); 1297 } 1298 1299 Intrinsic::ID IID = IsRotateRight ? Intrinsic::fshr : Intrinsic::fshl; 1300 Function *Intrin = Intrinsic::getDeclaration(CI.getModule(), IID, Ty); 1301 Value *Res = Builder.CreateCall(Intrin, {Src, Src, Amt}); 1302 1303 if (CI.getNumArgOperands() == 4) { // For masked intrinsics. 1304 Value *VecSrc = CI.getOperand(2); 1305 Value *Mask = CI.getOperand(3); 1306 Res = EmitX86Select(Builder, Mask, Res, VecSrc); 1307 } 1308 return Res; 1309 } 1310 1311 static Value *upgradeX86vpcom(IRBuilder<> &Builder, CallInst &CI, unsigned Imm, 1312 bool IsSigned) { 1313 Type *Ty = CI.getType(); 1314 Value *LHS = CI.getArgOperand(0); 1315 Value *RHS = CI.getArgOperand(1); 1316 1317 CmpInst::Predicate Pred; 1318 switch (Imm) { 1319 case 0x0: 1320 Pred = IsSigned ? ICmpInst::ICMP_SLT : ICmpInst::ICMP_ULT; 1321 break; 1322 case 0x1: 1323 Pred = IsSigned ? ICmpInst::ICMP_SLE : ICmpInst::ICMP_ULE; 1324 break; 1325 case 0x2: 1326 Pred = IsSigned ? ICmpInst::ICMP_SGT : ICmpInst::ICMP_UGT; 1327 break; 1328 case 0x3: 1329 Pred = IsSigned ? ICmpInst::ICMP_SGE : ICmpInst::ICMP_UGE; 1330 break; 1331 case 0x4: 1332 Pred = ICmpInst::ICMP_EQ; 1333 break; 1334 case 0x5: 1335 Pred = ICmpInst::ICMP_NE; 1336 break; 1337 case 0x6: 1338 return Constant::getNullValue(Ty); // FALSE 1339 case 0x7: 1340 return Constant::getAllOnesValue(Ty); // TRUE 1341 default: 1342 llvm_unreachable("Unknown XOP vpcom/vpcomu predicate"); 1343 } 1344 1345 Value *Cmp = Builder.CreateICmp(Pred, LHS, RHS); 1346 Value *Ext = Builder.CreateSExt(Cmp, Ty); 1347 return Ext; 1348 } 1349 1350 static Value *upgradeX86ConcatShift(IRBuilder<> &Builder, CallInst &CI, 1351 bool IsShiftRight, bool ZeroMask) { 1352 Type *Ty = CI.getType(); 1353 Value *Op0 = CI.getArgOperand(0); 1354 Value *Op1 = CI.getArgOperand(1); 1355 Value *Amt = CI.getArgOperand(2); 1356 1357 if (IsShiftRight) 1358 std::swap(Op0, Op1); 1359 1360 // Amount may be scalar immediate, in which case create a splat vector. 1361 // Funnel shifts amounts are treated as modulo and types are all power-of-2 so 1362 // we only care about the lowest log2 bits anyway. 1363 if (Amt->getType() != Ty) { 1364 unsigned NumElts = cast<FixedVectorType>(Ty)->getNumElements(); 1365 Amt = Builder.CreateIntCast(Amt, Ty->getScalarType(), false); 1366 Amt = Builder.CreateVectorSplat(NumElts, Amt); 1367 } 1368 1369 Intrinsic::ID IID = IsShiftRight ? Intrinsic::fshr : Intrinsic::fshl; 1370 Function *Intrin = Intrinsic::getDeclaration(CI.getModule(), IID, Ty); 1371 Value *Res = Builder.CreateCall(Intrin, {Op0, Op1, Amt}); 1372 1373 unsigned NumArgs = CI.getNumArgOperands(); 1374 if (NumArgs >= 4) { // For masked intrinsics. 1375 Value *VecSrc = NumArgs == 5 ? CI.getArgOperand(3) : 1376 ZeroMask ? ConstantAggregateZero::get(CI.getType()) : 1377 CI.getArgOperand(0); 1378 Value *Mask = CI.getOperand(NumArgs - 1); 1379 Res = EmitX86Select(Builder, Mask, Res, VecSrc); 1380 } 1381 return Res; 1382 } 1383 1384 static Value *UpgradeMaskedStore(IRBuilder<> &Builder, 1385 Value *Ptr, Value *Data, Value *Mask, 1386 bool Aligned) { 1387 // Cast the pointer to the right type. 1388 Ptr = Builder.CreateBitCast(Ptr, 1389 llvm::PointerType::getUnqual(Data->getType())); 1390 const Align Alignment = 1391 Aligned 1392 ? Align(Data->getType()->getPrimitiveSizeInBits().getFixedSize() / 8) 1393 : Align(1); 1394 1395 // If the mask is all ones just emit a regular store. 1396 if (const auto *C = dyn_cast<Constant>(Mask)) 1397 if (C->isAllOnesValue()) 1398 return Builder.CreateAlignedStore(Data, Ptr, Alignment); 1399 1400 // Convert the mask from an integer type to a vector of i1. 1401 unsigned NumElts = cast<FixedVectorType>(Data->getType())->getNumElements(); 1402 Mask = getX86MaskVec(Builder, Mask, NumElts); 1403 return Builder.CreateMaskedStore(Data, Ptr, Alignment, Mask); 1404 } 1405 1406 static Value *UpgradeMaskedLoad(IRBuilder<> &Builder, 1407 Value *Ptr, Value *Passthru, Value *Mask, 1408 bool Aligned) { 1409 Type *ValTy = Passthru->getType(); 1410 // Cast the pointer to the right type. 1411 Ptr = Builder.CreateBitCast(Ptr, llvm::PointerType::getUnqual(ValTy)); 1412 const Align Alignment = 1413 Aligned 1414 ? Align(Passthru->getType()->getPrimitiveSizeInBits().getFixedSize() / 1415 8) 1416 : Align(1); 1417 1418 // If the mask is all ones just emit a regular store. 1419 if (const auto *C = dyn_cast<Constant>(Mask)) 1420 if (C->isAllOnesValue()) 1421 return Builder.CreateAlignedLoad(ValTy, Ptr, Alignment); 1422 1423 // Convert the mask from an integer type to a vector of i1. 1424 unsigned NumElts = cast<FixedVectorType>(ValTy)->getNumElements(); 1425 Mask = getX86MaskVec(Builder, Mask, NumElts); 1426 return Builder.CreateMaskedLoad(ValTy, Ptr, Alignment, Mask, Passthru); 1427 } 1428 1429 static Value *upgradeAbs(IRBuilder<> &Builder, CallInst &CI) { 1430 Type *Ty = CI.getType(); 1431 Value *Op0 = CI.getArgOperand(0); 1432 Function *F = Intrinsic::getDeclaration(CI.getModule(), Intrinsic::abs, Ty); 1433 Value *Res = Builder.CreateCall(F, {Op0, Builder.getInt1(false)}); 1434 if (CI.getNumArgOperands() == 3) 1435 Res = EmitX86Select(Builder, CI.getArgOperand(2), Res, CI.getArgOperand(1)); 1436 return Res; 1437 } 1438 1439 static Value *upgradePMULDQ(IRBuilder<> &Builder, CallInst &CI, bool IsSigned) { 1440 Type *Ty = CI.getType(); 1441 1442 // Arguments have a vXi32 type so cast to vXi64. 1443 Value *LHS = Builder.CreateBitCast(CI.getArgOperand(0), Ty); 1444 Value *RHS = Builder.CreateBitCast(CI.getArgOperand(1), Ty); 1445 1446 if (IsSigned) { 1447 // Shift left then arithmetic shift right. 1448 Constant *ShiftAmt = ConstantInt::get(Ty, 32); 1449 LHS = Builder.CreateShl(LHS, ShiftAmt); 1450 LHS = Builder.CreateAShr(LHS, ShiftAmt); 1451 RHS = Builder.CreateShl(RHS, ShiftAmt); 1452 RHS = Builder.CreateAShr(RHS, ShiftAmt); 1453 } else { 1454 // Clear the upper bits. 1455 Constant *Mask = ConstantInt::get(Ty, 0xffffffff); 1456 LHS = Builder.CreateAnd(LHS, Mask); 1457 RHS = Builder.CreateAnd(RHS, Mask); 1458 } 1459 1460 Value *Res = Builder.CreateMul(LHS, RHS); 1461 1462 if (CI.getNumArgOperands() == 4) 1463 Res = EmitX86Select(Builder, CI.getArgOperand(3), Res, CI.getArgOperand(2)); 1464 1465 return Res; 1466 } 1467 1468 // Applying mask on vector of i1's and make sure result is at least 8 bits wide. 1469 static Value *ApplyX86MaskOn1BitsVec(IRBuilder<> &Builder, Value *Vec, 1470 Value *Mask) { 1471 unsigned NumElts = cast<FixedVectorType>(Vec->getType())->getNumElements(); 1472 if (Mask) { 1473 const auto *C = dyn_cast<Constant>(Mask); 1474 if (!C || !C->isAllOnesValue()) 1475 Vec = Builder.CreateAnd(Vec, getX86MaskVec(Builder, Mask, NumElts)); 1476 } 1477 1478 if (NumElts < 8) { 1479 int Indices[8]; 1480 for (unsigned i = 0; i != NumElts; ++i) 1481 Indices[i] = i; 1482 for (unsigned i = NumElts; i != 8; ++i) 1483 Indices[i] = NumElts + i % NumElts; 1484 Vec = Builder.CreateShuffleVector(Vec, 1485 Constant::getNullValue(Vec->getType()), 1486 Indices); 1487 } 1488 return Builder.CreateBitCast(Vec, Builder.getIntNTy(std::max(NumElts, 8U))); 1489 } 1490 1491 static Value *upgradeMaskedCompare(IRBuilder<> &Builder, CallInst &CI, 1492 unsigned CC, bool Signed) { 1493 Value *Op0 = CI.getArgOperand(0); 1494 unsigned NumElts = cast<FixedVectorType>(Op0->getType())->getNumElements(); 1495 1496 Value *Cmp; 1497 if (CC == 3) { 1498 Cmp = Constant::getNullValue( 1499 FixedVectorType::get(Builder.getInt1Ty(), NumElts)); 1500 } else if (CC == 7) { 1501 Cmp = Constant::getAllOnesValue( 1502 FixedVectorType::get(Builder.getInt1Ty(), NumElts)); 1503 } else { 1504 ICmpInst::Predicate Pred; 1505 switch (CC) { 1506 default: llvm_unreachable("Unknown condition code"); 1507 case 0: Pred = ICmpInst::ICMP_EQ; break; 1508 case 1: Pred = Signed ? ICmpInst::ICMP_SLT : ICmpInst::ICMP_ULT; break; 1509 case 2: Pred = Signed ? ICmpInst::ICMP_SLE : ICmpInst::ICMP_ULE; break; 1510 case 4: Pred = ICmpInst::ICMP_NE; break; 1511 case 5: Pred = Signed ? ICmpInst::ICMP_SGE : ICmpInst::ICMP_UGE; break; 1512 case 6: Pred = Signed ? ICmpInst::ICMP_SGT : ICmpInst::ICMP_UGT; break; 1513 } 1514 Cmp = Builder.CreateICmp(Pred, Op0, CI.getArgOperand(1)); 1515 } 1516 1517 Value *Mask = CI.getArgOperand(CI.getNumArgOperands() - 1); 1518 1519 return ApplyX86MaskOn1BitsVec(Builder, Cmp, Mask); 1520 } 1521 1522 // Replace a masked intrinsic with an older unmasked intrinsic. 1523 static Value *UpgradeX86MaskedShift(IRBuilder<> &Builder, CallInst &CI, 1524 Intrinsic::ID IID) { 1525 Function *Intrin = Intrinsic::getDeclaration(CI.getModule(), IID); 1526 Value *Rep = Builder.CreateCall(Intrin, 1527 { CI.getArgOperand(0), CI.getArgOperand(1) }); 1528 return EmitX86Select(Builder, CI.getArgOperand(3), Rep, CI.getArgOperand(2)); 1529 } 1530 1531 static Value* upgradeMaskedMove(IRBuilder<> &Builder, CallInst &CI) { 1532 Value* A = CI.getArgOperand(0); 1533 Value* B = CI.getArgOperand(1); 1534 Value* Src = CI.getArgOperand(2); 1535 Value* Mask = CI.getArgOperand(3); 1536 1537 Value* AndNode = Builder.CreateAnd(Mask, APInt(8, 1)); 1538 Value* Cmp = Builder.CreateIsNotNull(AndNode); 1539 Value* Extract1 = Builder.CreateExtractElement(B, (uint64_t)0); 1540 Value* Extract2 = Builder.CreateExtractElement(Src, (uint64_t)0); 1541 Value* Select = Builder.CreateSelect(Cmp, Extract1, Extract2); 1542 return Builder.CreateInsertElement(A, Select, (uint64_t)0); 1543 } 1544 1545 1546 static Value* UpgradeMaskToInt(IRBuilder<> &Builder, CallInst &CI) { 1547 Value* Op = CI.getArgOperand(0); 1548 Type* ReturnOp = CI.getType(); 1549 unsigned NumElts = cast<FixedVectorType>(CI.getType())->getNumElements(); 1550 Value *Mask = getX86MaskVec(Builder, Op, NumElts); 1551 return Builder.CreateSExt(Mask, ReturnOp, "vpmovm2"); 1552 } 1553 1554 // Replace intrinsic with unmasked version and a select. 1555 static bool upgradeAVX512MaskToSelect(StringRef Name, IRBuilder<> &Builder, 1556 CallInst &CI, Value *&Rep) { 1557 Name = Name.substr(12); // Remove avx512.mask. 1558 1559 unsigned VecWidth = CI.getType()->getPrimitiveSizeInBits(); 1560 unsigned EltWidth = CI.getType()->getScalarSizeInBits(); 1561 Intrinsic::ID IID; 1562 if (Name.startswith("max.p")) { 1563 if (VecWidth == 128 && EltWidth == 32) 1564 IID = Intrinsic::x86_sse_max_ps; 1565 else if (VecWidth == 128 && EltWidth == 64) 1566 IID = Intrinsic::x86_sse2_max_pd; 1567 else if (VecWidth == 256 && EltWidth == 32) 1568 IID = Intrinsic::x86_avx_max_ps_256; 1569 else if (VecWidth == 256 && EltWidth == 64) 1570 IID = Intrinsic::x86_avx_max_pd_256; 1571 else 1572 llvm_unreachable("Unexpected intrinsic"); 1573 } else if (Name.startswith("min.p")) { 1574 if (VecWidth == 128 && EltWidth == 32) 1575 IID = Intrinsic::x86_sse_min_ps; 1576 else if (VecWidth == 128 && EltWidth == 64) 1577 IID = Intrinsic::x86_sse2_min_pd; 1578 else if (VecWidth == 256 && EltWidth == 32) 1579 IID = Intrinsic::x86_avx_min_ps_256; 1580 else if (VecWidth == 256 && EltWidth == 64) 1581 IID = Intrinsic::x86_avx_min_pd_256; 1582 else 1583 llvm_unreachable("Unexpected intrinsic"); 1584 } else if (Name.startswith("pshuf.b.")) { 1585 if (VecWidth == 128) 1586 IID = Intrinsic::x86_ssse3_pshuf_b_128; 1587 else if (VecWidth == 256) 1588 IID = Intrinsic::x86_avx2_pshuf_b; 1589 else if (VecWidth == 512) 1590 IID = Intrinsic::x86_avx512_pshuf_b_512; 1591 else 1592 llvm_unreachable("Unexpected intrinsic"); 1593 } else if (Name.startswith("pmul.hr.sw.")) { 1594 if (VecWidth == 128) 1595 IID = Intrinsic::x86_ssse3_pmul_hr_sw_128; 1596 else if (VecWidth == 256) 1597 IID = Intrinsic::x86_avx2_pmul_hr_sw; 1598 else if (VecWidth == 512) 1599 IID = Intrinsic::x86_avx512_pmul_hr_sw_512; 1600 else 1601 llvm_unreachable("Unexpected intrinsic"); 1602 } else if (Name.startswith("pmulh.w.")) { 1603 if (VecWidth == 128) 1604 IID = Intrinsic::x86_sse2_pmulh_w; 1605 else if (VecWidth == 256) 1606 IID = Intrinsic::x86_avx2_pmulh_w; 1607 else if (VecWidth == 512) 1608 IID = Intrinsic::x86_avx512_pmulh_w_512; 1609 else 1610 llvm_unreachable("Unexpected intrinsic"); 1611 } else if (Name.startswith("pmulhu.w.")) { 1612 if (VecWidth == 128) 1613 IID = Intrinsic::x86_sse2_pmulhu_w; 1614 else if (VecWidth == 256) 1615 IID = Intrinsic::x86_avx2_pmulhu_w; 1616 else if (VecWidth == 512) 1617 IID = Intrinsic::x86_avx512_pmulhu_w_512; 1618 else 1619 llvm_unreachable("Unexpected intrinsic"); 1620 } else if (Name.startswith("pmaddw.d.")) { 1621 if (VecWidth == 128) 1622 IID = Intrinsic::x86_sse2_pmadd_wd; 1623 else if (VecWidth == 256) 1624 IID = Intrinsic::x86_avx2_pmadd_wd; 1625 else if (VecWidth == 512) 1626 IID = Intrinsic::x86_avx512_pmaddw_d_512; 1627 else 1628 llvm_unreachable("Unexpected intrinsic"); 1629 } else if (Name.startswith("pmaddubs.w.")) { 1630 if (VecWidth == 128) 1631 IID = Intrinsic::x86_ssse3_pmadd_ub_sw_128; 1632 else if (VecWidth == 256) 1633 IID = Intrinsic::x86_avx2_pmadd_ub_sw; 1634 else if (VecWidth == 512) 1635 IID = Intrinsic::x86_avx512_pmaddubs_w_512; 1636 else 1637 llvm_unreachable("Unexpected intrinsic"); 1638 } else if (Name.startswith("packsswb.")) { 1639 if (VecWidth == 128) 1640 IID = Intrinsic::x86_sse2_packsswb_128; 1641 else if (VecWidth == 256) 1642 IID = Intrinsic::x86_avx2_packsswb; 1643 else if (VecWidth == 512) 1644 IID = Intrinsic::x86_avx512_packsswb_512; 1645 else 1646 llvm_unreachable("Unexpected intrinsic"); 1647 } else if (Name.startswith("packssdw.")) { 1648 if (VecWidth == 128) 1649 IID = Intrinsic::x86_sse2_packssdw_128; 1650 else if (VecWidth == 256) 1651 IID = Intrinsic::x86_avx2_packssdw; 1652 else if (VecWidth == 512) 1653 IID = Intrinsic::x86_avx512_packssdw_512; 1654 else 1655 llvm_unreachable("Unexpected intrinsic"); 1656 } else if (Name.startswith("packuswb.")) { 1657 if (VecWidth == 128) 1658 IID = Intrinsic::x86_sse2_packuswb_128; 1659 else if (VecWidth == 256) 1660 IID = Intrinsic::x86_avx2_packuswb; 1661 else if (VecWidth == 512) 1662 IID = Intrinsic::x86_avx512_packuswb_512; 1663 else 1664 llvm_unreachable("Unexpected intrinsic"); 1665 } else if (Name.startswith("packusdw.")) { 1666 if (VecWidth == 128) 1667 IID = Intrinsic::x86_sse41_packusdw; 1668 else if (VecWidth == 256) 1669 IID = Intrinsic::x86_avx2_packusdw; 1670 else if (VecWidth == 512) 1671 IID = Intrinsic::x86_avx512_packusdw_512; 1672 else 1673 llvm_unreachable("Unexpected intrinsic"); 1674 } else if (Name.startswith("vpermilvar.")) { 1675 if (VecWidth == 128 && EltWidth == 32) 1676 IID = Intrinsic::x86_avx_vpermilvar_ps; 1677 else if (VecWidth == 128 && EltWidth == 64) 1678 IID = Intrinsic::x86_avx_vpermilvar_pd; 1679 else if (VecWidth == 256 && EltWidth == 32) 1680 IID = Intrinsic::x86_avx_vpermilvar_ps_256; 1681 else if (VecWidth == 256 && EltWidth == 64) 1682 IID = Intrinsic::x86_avx_vpermilvar_pd_256; 1683 else if (VecWidth == 512 && EltWidth == 32) 1684 IID = Intrinsic::x86_avx512_vpermilvar_ps_512; 1685 else if (VecWidth == 512 && EltWidth == 64) 1686 IID = Intrinsic::x86_avx512_vpermilvar_pd_512; 1687 else 1688 llvm_unreachable("Unexpected intrinsic"); 1689 } else if (Name == "cvtpd2dq.256") { 1690 IID = Intrinsic::x86_avx_cvt_pd2dq_256; 1691 } else if (Name == "cvtpd2ps.256") { 1692 IID = Intrinsic::x86_avx_cvt_pd2_ps_256; 1693 } else if (Name == "cvttpd2dq.256") { 1694 IID = Intrinsic::x86_avx_cvtt_pd2dq_256; 1695 } else if (Name == "cvttps2dq.128") { 1696 IID = Intrinsic::x86_sse2_cvttps2dq; 1697 } else if (Name == "cvttps2dq.256") { 1698 IID = Intrinsic::x86_avx_cvtt_ps2dq_256; 1699 } else if (Name.startswith("permvar.")) { 1700 bool IsFloat = CI.getType()->isFPOrFPVectorTy(); 1701 if (VecWidth == 256 && EltWidth == 32 && IsFloat) 1702 IID = Intrinsic::x86_avx2_permps; 1703 else if (VecWidth == 256 && EltWidth == 32 && !IsFloat) 1704 IID = Intrinsic::x86_avx2_permd; 1705 else if (VecWidth == 256 && EltWidth == 64 && IsFloat) 1706 IID = Intrinsic::x86_avx512_permvar_df_256; 1707 else if (VecWidth == 256 && EltWidth == 64 && !IsFloat) 1708 IID = Intrinsic::x86_avx512_permvar_di_256; 1709 else if (VecWidth == 512 && EltWidth == 32 && IsFloat) 1710 IID = Intrinsic::x86_avx512_permvar_sf_512; 1711 else if (VecWidth == 512 && EltWidth == 32 && !IsFloat) 1712 IID = Intrinsic::x86_avx512_permvar_si_512; 1713 else if (VecWidth == 512 && EltWidth == 64 && IsFloat) 1714 IID = Intrinsic::x86_avx512_permvar_df_512; 1715 else if (VecWidth == 512 && EltWidth == 64 && !IsFloat) 1716 IID = Intrinsic::x86_avx512_permvar_di_512; 1717 else if (VecWidth == 128 && EltWidth == 16) 1718 IID = Intrinsic::x86_avx512_permvar_hi_128; 1719 else if (VecWidth == 256 && EltWidth == 16) 1720 IID = Intrinsic::x86_avx512_permvar_hi_256; 1721 else if (VecWidth == 512 && EltWidth == 16) 1722 IID = Intrinsic::x86_avx512_permvar_hi_512; 1723 else if (VecWidth == 128 && EltWidth == 8) 1724 IID = Intrinsic::x86_avx512_permvar_qi_128; 1725 else if (VecWidth == 256 && EltWidth == 8) 1726 IID = Intrinsic::x86_avx512_permvar_qi_256; 1727 else if (VecWidth == 512 && EltWidth == 8) 1728 IID = Intrinsic::x86_avx512_permvar_qi_512; 1729 else 1730 llvm_unreachable("Unexpected intrinsic"); 1731 } else if (Name.startswith("dbpsadbw.")) { 1732 if (VecWidth == 128) 1733 IID = Intrinsic::x86_avx512_dbpsadbw_128; 1734 else if (VecWidth == 256) 1735 IID = Intrinsic::x86_avx512_dbpsadbw_256; 1736 else if (VecWidth == 512) 1737 IID = Intrinsic::x86_avx512_dbpsadbw_512; 1738 else 1739 llvm_unreachable("Unexpected intrinsic"); 1740 } else if (Name.startswith("pmultishift.qb.")) { 1741 if (VecWidth == 128) 1742 IID = Intrinsic::x86_avx512_pmultishift_qb_128; 1743 else if (VecWidth == 256) 1744 IID = Intrinsic::x86_avx512_pmultishift_qb_256; 1745 else if (VecWidth == 512) 1746 IID = Intrinsic::x86_avx512_pmultishift_qb_512; 1747 else 1748 llvm_unreachable("Unexpected intrinsic"); 1749 } else if (Name.startswith("conflict.")) { 1750 if (Name[9] == 'd' && VecWidth == 128) 1751 IID = Intrinsic::x86_avx512_conflict_d_128; 1752 else if (Name[9] == 'd' && VecWidth == 256) 1753 IID = Intrinsic::x86_avx512_conflict_d_256; 1754 else if (Name[9] == 'd' && VecWidth == 512) 1755 IID = Intrinsic::x86_avx512_conflict_d_512; 1756 else if (Name[9] == 'q' && VecWidth == 128) 1757 IID = Intrinsic::x86_avx512_conflict_q_128; 1758 else if (Name[9] == 'q' && VecWidth == 256) 1759 IID = Intrinsic::x86_avx512_conflict_q_256; 1760 else if (Name[9] == 'q' && VecWidth == 512) 1761 IID = Intrinsic::x86_avx512_conflict_q_512; 1762 else 1763 llvm_unreachable("Unexpected intrinsic"); 1764 } else if (Name.startswith("pavg.")) { 1765 if (Name[5] == 'b' && VecWidth == 128) 1766 IID = Intrinsic::x86_sse2_pavg_b; 1767 else if (Name[5] == 'b' && VecWidth == 256) 1768 IID = Intrinsic::x86_avx2_pavg_b; 1769 else if (Name[5] == 'b' && VecWidth == 512) 1770 IID = Intrinsic::x86_avx512_pavg_b_512; 1771 else if (Name[5] == 'w' && VecWidth == 128) 1772 IID = Intrinsic::x86_sse2_pavg_w; 1773 else if (Name[5] == 'w' && VecWidth == 256) 1774 IID = Intrinsic::x86_avx2_pavg_w; 1775 else if (Name[5] == 'w' && VecWidth == 512) 1776 IID = Intrinsic::x86_avx512_pavg_w_512; 1777 else 1778 llvm_unreachable("Unexpected intrinsic"); 1779 } else 1780 return false; 1781 1782 SmallVector<Value *, 4> Args(CI.args()); 1783 Args.pop_back(); 1784 Args.pop_back(); 1785 Rep = Builder.CreateCall(Intrinsic::getDeclaration(CI.getModule(), IID), 1786 Args); 1787 unsigned NumArgs = CI.getNumArgOperands(); 1788 Rep = EmitX86Select(Builder, CI.getArgOperand(NumArgs - 1), Rep, 1789 CI.getArgOperand(NumArgs - 2)); 1790 return true; 1791 } 1792 1793 /// Upgrade comment in call to inline asm that represents an objc retain release 1794 /// marker. 1795 void llvm::UpgradeInlineAsmString(std::string *AsmStr) { 1796 size_t Pos; 1797 if (AsmStr->find("mov\tfp") == 0 && 1798 AsmStr->find("objc_retainAutoreleaseReturnValue") != std::string::npos && 1799 (Pos = AsmStr->find("# marker")) != std::string::npos) { 1800 AsmStr->replace(Pos, 1, ";"); 1801 } 1802 } 1803 1804 /// Upgrade a call to an old intrinsic. All argument and return casting must be 1805 /// provided to seamlessly integrate with existing context. 1806 void llvm::UpgradeIntrinsicCall(CallInst *CI, Function *NewFn) { 1807 Function *F = CI->getCalledFunction(); 1808 LLVMContext &C = CI->getContext(); 1809 IRBuilder<> Builder(C); 1810 Builder.SetInsertPoint(CI->getParent(), CI->getIterator()); 1811 1812 assert(F && "Intrinsic call is not direct?"); 1813 1814 if (!NewFn) { 1815 // Get the Function's name. 1816 StringRef Name = F->getName(); 1817 1818 assert(Name.startswith("llvm.") && "Intrinsic doesn't start with 'llvm.'"); 1819 Name = Name.substr(5); 1820 1821 bool IsX86 = Name.startswith("x86."); 1822 if (IsX86) 1823 Name = Name.substr(4); 1824 bool IsNVVM = Name.startswith("nvvm."); 1825 if (IsNVVM) 1826 Name = Name.substr(5); 1827 1828 if (IsX86 && Name.startswith("sse4a.movnt.")) { 1829 Module *M = F->getParent(); 1830 SmallVector<Metadata *, 1> Elts; 1831 Elts.push_back( 1832 ConstantAsMetadata::get(ConstantInt::get(Type::getInt32Ty(C), 1))); 1833 MDNode *Node = MDNode::get(C, Elts); 1834 1835 Value *Arg0 = CI->getArgOperand(0); 1836 Value *Arg1 = CI->getArgOperand(1); 1837 1838 // Nontemporal (unaligned) store of the 0'th element of the float/double 1839 // vector. 1840 Type *SrcEltTy = cast<VectorType>(Arg1->getType())->getElementType(); 1841 PointerType *EltPtrTy = PointerType::getUnqual(SrcEltTy); 1842 Value *Addr = Builder.CreateBitCast(Arg0, EltPtrTy, "cast"); 1843 Value *Extract = 1844 Builder.CreateExtractElement(Arg1, (uint64_t)0, "extractelement"); 1845 1846 StoreInst *SI = Builder.CreateAlignedStore(Extract, Addr, Align(1)); 1847 SI->setMetadata(M->getMDKindID("nontemporal"), Node); 1848 1849 // Remove intrinsic. 1850 CI->eraseFromParent(); 1851 return; 1852 } 1853 1854 if (IsX86 && (Name.startswith("avx.movnt.") || 1855 Name.startswith("avx512.storent."))) { 1856 Module *M = F->getParent(); 1857 SmallVector<Metadata *, 1> Elts; 1858 Elts.push_back( 1859 ConstantAsMetadata::get(ConstantInt::get(Type::getInt32Ty(C), 1))); 1860 MDNode *Node = MDNode::get(C, Elts); 1861 1862 Value *Arg0 = CI->getArgOperand(0); 1863 Value *Arg1 = CI->getArgOperand(1); 1864 1865 // Convert the type of the pointer to a pointer to the stored type. 1866 Value *BC = Builder.CreateBitCast(Arg0, 1867 PointerType::getUnqual(Arg1->getType()), 1868 "cast"); 1869 StoreInst *SI = Builder.CreateAlignedStore( 1870 Arg1, BC, 1871 Align(Arg1->getType()->getPrimitiveSizeInBits().getFixedSize() / 8)); 1872 SI->setMetadata(M->getMDKindID("nontemporal"), Node); 1873 1874 // Remove intrinsic. 1875 CI->eraseFromParent(); 1876 return; 1877 } 1878 1879 if (IsX86 && Name == "sse2.storel.dq") { 1880 Value *Arg0 = CI->getArgOperand(0); 1881 Value *Arg1 = CI->getArgOperand(1); 1882 1883 auto *NewVecTy = FixedVectorType::get(Type::getInt64Ty(C), 2); 1884 Value *BC0 = Builder.CreateBitCast(Arg1, NewVecTy, "cast"); 1885 Value *Elt = Builder.CreateExtractElement(BC0, (uint64_t)0); 1886 Value *BC = Builder.CreateBitCast(Arg0, 1887 PointerType::getUnqual(Elt->getType()), 1888 "cast"); 1889 Builder.CreateAlignedStore(Elt, BC, Align(1)); 1890 1891 // Remove intrinsic. 1892 CI->eraseFromParent(); 1893 return; 1894 } 1895 1896 if (IsX86 && (Name.startswith("sse.storeu.") || 1897 Name.startswith("sse2.storeu.") || 1898 Name.startswith("avx.storeu."))) { 1899 Value *Arg0 = CI->getArgOperand(0); 1900 Value *Arg1 = CI->getArgOperand(1); 1901 1902 Arg0 = Builder.CreateBitCast(Arg0, 1903 PointerType::getUnqual(Arg1->getType()), 1904 "cast"); 1905 Builder.CreateAlignedStore(Arg1, Arg0, Align(1)); 1906 1907 // Remove intrinsic. 1908 CI->eraseFromParent(); 1909 return; 1910 } 1911 1912 if (IsX86 && Name == "avx512.mask.store.ss") { 1913 Value *Mask = Builder.CreateAnd(CI->getArgOperand(2), Builder.getInt8(1)); 1914 UpgradeMaskedStore(Builder, CI->getArgOperand(0), CI->getArgOperand(1), 1915 Mask, false); 1916 1917 // Remove intrinsic. 1918 CI->eraseFromParent(); 1919 return; 1920 } 1921 1922 if (IsX86 && (Name.startswith("avx512.mask.store"))) { 1923 // "avx512.mask.storeu." or "avx512.mask.store." 1924 bool Aligned = Name[17] != 'u'; // "avx512.mask.storeu". 1925 UpgradeMaskedStore(Builder, CI->getArgOperand(0), CI->getArgOperand(1), 1926 CI->getArgOperand(2), Aligned); 1927 1928 // Remove intrinsic. 1929 CI->eraseFromParent(); 1930 return; 1931 } 1932 1933 Value *Rep; 1934 // Upgrade packed integer vector compare intrinsics to compare instructions. 1935 if (IsX86 && (Name.startswith("sse2.pcmp") || 1936 Name.startswith("avx2.pcmp"))) { 1937 // "sse2.pcpmpeq." "sse2.pcmpgt." "avx2.pcmpeq." or "avx2.pcmpgt." 1938 bool CmpEq = Name[9] == 'e'; 1939 Rep = Builder.CreateICmp(CmpEq ? ICmpInst::ICMP_EQ : ICmpInst::ICMP_SGT, 1940 CI->getArgOperand(0), CI->getArgOperand(1)); 1941 Rep = Builder.CreateSExt(Rep, CI->getType(), ""); 1942 } else if (IsX86 && (Name.startswith("avx512.broadcastm"))) { 1943 Type *ExtTy = Type::getInt32Ty(C); 1944 if (CI->getOperand(0)->getType()->isIntegerTy(8)) 1945 ExtTy = Type::getInt64Ty(C); 1946 unsigned NumElts = CI->getType()->getPrimitiveSizeInBits() / 1947 ExtTy->getPrimitiveSizeInBits(); 1948 Rep = Builder.CreateZExt(CI->getArgOperand(0), ExtTy); 1949 Rep = Builder.CreateVectorSplat(NumElts, Rep); 1950 } else if (IsX86 && (Name == "sse.sqrt.ss" || 1951 Name == "sse2.sqrt.sd")) { 1952 Value *Vec = CI->getArgOperand(0); 1953 Value *Elt0 = Builder.CreateExtractElement(Vec, (uint64_t)0); 1954 Function *Intr = Intrinsic::getDeclaration(F->getParent(), 1955 Intrinsic::sqrt, Elt0->getType()); 1956 Elt0 = Builder.CreateCall(Intr, Elt0); 1957 Rep = Builder.CreateInsertElement(Vec, Elt0, (uint64_t)0); 1958 } else if (IsX86 && (Name.startswith("avx.sqrt.p") || 1959 Name.startswith("sse2.sqrt.p") || 1960 Name.startswith("sse.sqrt.p"))) { 1961 Rep = Builder.CreateCall(Intrinsic::getDeclaration(F->getParent(), 1962 Intrinsic::sqrt, 1963 CI->getType()), 1964 {CI->getArgOperand(0)}); 1965 } else if (IsX86 && (Name.startswith("avx512.mask.sqrt.p"))) { 1966 if (CI->getNumArgOperands() == 4 && 1967 (!isa<ConstantInt>(CI->getArgOperand(3)) || 1968 cast<ConstantInt>(CI->getArgOperand(3))->getZExtValue() != 4)) { 1969 Intrinsic::ID IID = Name[18] == 's' ? Intrinsic::x86_avx512_sqrt_ps_512 1970 : Intrinsic::x86_avx512_sqrt_pd_512; 1971 1972 Value *Args[] = { CI->getArgOperand(0), CI->getArgOperand(3) }; 1973 Rep = Builder.CreateCall(Intrinsic::getDeclaration(CI->getModule(), 1974 IID), Args); 1975 } else { 1976 Rep = Builder.CreateCall(Intrinsic::getDeclaration(F->getParent(), 1977 Intrinsic::sqrt, 1978 CI->getType()), 1979 {CI->getArgOperand(0)}); 1980 } 1981 Rep = EmitX86Select(Builder, CI->getArgOperand(2), Rep, 1982 CI->getArgOperand(1)); 1983 } else if (IsX86 && (Name.startswith("avx512.ptestm") || 1984 Name.startswith("avx512.ptestnm"))) { 1985 Value *Op0 = CI->getArgOperand(0); 1986 Value *Op1 = CI->getArgOperand(1); 1987 Value *Mask = CI->getArgOperand(2); 1988 Rep = Builder.CreateAnd(Op0, Op1); 1989 llvm::Type *Ty = Op0->getType(); 1990 Value *Zero = llvm::Constant::getNullValue(Ty); 1991 ICmpInst::Predicate Pred = 1992 Name.startswith("avx512.ptestm") ? ICmpInst::ICMP_NE : ICmpInst::ICMP_EQ; 1993 Rep = Builder.CreateICmp(Pred, Rep, Zero); 1994 Rep = ApplyX86MaskOn1BitsVec(Builder, Rep, Mask); 1995 } else if (IsX86 && (Name.startswith("avx512.mask.pbroadcast"))){ 1996 unsigned NumElts = cast<FixedVectorType>(CI->getArgOperand(1)->getType()) 1997 ->getNumElements(); 1998 Rep = Builder.CreateVectorSplat(NumElts, CI->getArgOperand(0)); 1999 Rep = EmitX86Select(Builder, CI->getArgOperand(2), Rep, 2000 CI->getArgOperand(1)); 2001 } else if (IsX86 && (Name.startswith("avx512.kunpck"))) { 2002 unsigned NumElts = CI->getType()->getScalarSizeInBits(); 2003 Value *LHS = getX86MaskVec(Builder, CI->getArgOperand(0), NumElts); 2004 Value *RHS = getX86MaskVec(Builder, CI->getArgOperand(1), NumElts); 2005 int Indices[64]; 2006 for (unsigned i = 0; i != NumElts; ++i) 2007 Indices[i] = i; 2008 2009 // First extract half of each vector. This gives better codegen than 2010 // doing it in a single shuffle. 2011 LHS = Builder.CreateShuffleVector(LHS, LHS, 2012 makeArrayRef(Indices, NumElts / 2)); 2013 RHS = Builder.CreateShuffleVector(RHS, RHS, 2014 makeArrayRef(Indices, NumElts / 2)); 2015 // Concat the vectors. 2016 // NOTE: Operands have to be swapped to match intrinsic definition. 2017 Rep = Builder.CreateShuffleVector(RHS, LHS, 2018 makeArrayRef(Indices, NumElts)); 2019 Rep = Builder.CreateBitCast(Rep, CI->getType()); 2020 } else if (IsX86 && Name == "avx512.kand.w") { 2021 Value *LHS = getX86MaskVec(Builder, CI->getArgOperand(0), 16); 2022 Value *RHS = getX86MaskVec(Builder, CI->getArgOperand(1), 16); 2023 Rep = Builder.CreateAnd(LHS, RHS); 2024 Rep = Builder.CreateBitCast(Rep, CI->getType()); 2025 } else if (IsX86 && Name == "avx512.kandn.w") { 2026 Value *LHS = getX86MaskVec(Builder, CI->getArgOperand(0), 16); 2027 Value *RHS = getX86MaskVec(Builder, CI->getArgOperand(1), 16); 2028 LHS = Builder.CreateNot(LHS); 2029 Rep = Builder.CreateAnd(LHS, RHS); 2030 Rep = Builder.CreateBitCast(Rep, CI->getType()); 2031 } else if (IsX86 && Name == "avx512.kor.w") { 2032 Value *LHS = getX86MaskVec(Builder, CI->getArgOperand(0), 16); 2033 Value *RHS = getX86MaskVec(Builder, CI->getArgOperand(1), 16); 2034 Rep = Builder.CreateOr(LHS, RHS); 2035 Rep = Builder.CreateBitCast(Rep, CI->getType()); 2036 } else if (IsX86 && Name == "avx512.kxor.w") { 2037 Value *LHS = getX86MaskVec(Builder, CI->getArgOperand(0), 16); 2038 Value *RHS = getX86MaskVec(Builder, CI->getArgOperand(1), 16); 2039 Rep = Builder.CreateXor(LHS, RHS); 2040 Rep = Builder.CreateBitCast(Rep, CI->getType()); 2041 } else if (IsX86 && Name == "avx512.kxnor.w") { 2042 Value *LHS = getX86MaskVec(Builder, CI->getArgOperand(0), 16); 2043 Value *RHS = getX86MaskVec(Builder, CI->getArgOperand(1), 16); 2044 LHS = Builder.CreateNot(LHS); 2045 Rep = Builder.CreateXor(LHS, RHS); 2046 Rep = Builder.CreateBitCast(Rep, CI->getType()); 2047 } else if (IsX86 && Name == "avx512.knot.w") { 2048 Rep = getX86MaskVec(Builder, CI->getArgOperand(0), 16); 2049 Rep = Builder.CreateNot(Rep); 2050 Rep = Builder.CreateBitCast(Rep, CI->getType()); 2051 } else if (IsX86 && 2052 (Name == "avx512.kortestz.w" || Name == "avx512.kortestc.w")) { 2053 Value *LHS = getX86MaskVec(Builder, CI->getArgOperand(0), 16); 2054 Value *RHS = getX86MaskVec(Builder, CI->getArgOperand(1), 16); 2055 Rep = Builder.CreateOr(LHS, RHS); 2056 Rep = Builder.CreateBitCast(Rep, Builder.getInt16Ty()); 2057 Value *C; 2058 if (Name[14] == 'c') 2059 C = ConstantInt::getAllOnesValue(Builder.getInt16Ty()); 2060 else 2061 C = ConstantInt::getNullValue(Builder.getInt16Ty()); 2062 Rep = Builder.CreateICmpEQ(Rep, C); 2063 Rep = Builder.CreateZExt(Rep, Builder.getInt32Ty()); 2064 } else if (IsX86 && (Name == "sse.add.ss" || Name == "sse2.add.sd" || 2065 Name == "sse.sub.ss" || Name == "sse2.sub.sd" || 2066 Name == "sse.mul.ss" || Name == "sse2.mul.sd" || 2067 Name == "sse.div.ss" || Name == "sse2.div.sd")) { 2068 Type *I32Ty = Type::getInt32Ty(C); 2069 Value *Elt0 = Builder.CreateExtractElement(CI->getArgOperand(0), 2070 ConstantInt::get(I32Ty, 0)); 2071 Value *Elt1 = Builder.CreateExtractElement(CI->getArgOperand(1), 2072 ConstantInt::get(I32Ty, 0)); 2073 Value *EltOp; 2074 if (Name.contains(".add.")) 2075 EltOp = Builder.CreateFAdd(Elt0, Elt1); 2076 else if (Name.contains(".sub.")) 2077 EltOp = Builder.CreateFSub(Elt0, Elt1); 2078 else if (Name.contains(".mul.")) 2079 EltOp = Builder.CreateFMul(Elt0, Elt1); 2080 else 2081 EltOp = Builder.CreateFDiv(Elt0, Elt1); 2082 Rep = Builder.CreateInsertElement(CI->getArgOperand(0), EltOp, 2083 ConstantInt::get(I32Ty, 0)); 2084 } else if (IsX86 && Name.startswith("avx512.mask.pcmp")) { 2085 // "avx512.mask.pcmpeq." or "avx512.mask.pcmpgt." 2086 bool CmpEq = Name[16] == 'e'; 2087 Rep = upgradeMaskedCompare(Builder, *CI, CmpEq ? 0 : 6, true); 2088 } else if (IsX86 && Name.startswith("avx512.mask.vpshufbitqmb.")) { 2089 Type *OpTy = CI->getArgOperand(0)->getType(); 2090 unsigned VecWidth = OpTy->getPrimitiveSizeInBits(); 2091 Intrinsic::ID IID; 2092 switch (VecWidth) { 2093 default: llvm_unreachable("Unexpected intrinsic"); 2094 case 128: IID = Intrinsic::x86_avx512_vpshufbitqmb_128; break; 2095 case 256: IID = Intrinsic::x86_avx512_vpshufbitqmb_256; break; 2096 case 512: IID = Intrinsic::x86_avx512_vpshufbitqmb_512; break; 2097 } 2098 2099 Rep = Builder.CreateCall(Intrinsic::getDeclaration(F->getParent(), IID), 2100 { CI->getOperand(0), CI->getArgOperand(1) }); 2101 Rep = ApplyX86MaskOn1BitsVec(Builder, Rep, CI->getArgOperand(2)); 2102 } else if (IsX86 && Name.startswith("avx512.mask.fpclass.p")) { 2103 Type *OpTy = CI->getArgOperand(0)->getType(); 2104 unsigned VecWidth = OpTy->getPrimitiveSizeInBits(); 2105 unsigned EltWidth = OpTy->getScalarSizeInBits(); 2106 Intrinsic::ID IID; 2107 if (VecWidth == 128 && EltWidth == 32) 2108 IID = Intrinsic::x86_avx512_fpclass_ps_128; 2109 else if (VecWidth == 256 && EltWidth == 32) 2110 IID = Intrinsic::x86_avx512_fpclass_ps_256; 2111 else if (VecWidth == 512 && EltWidth == 32) 2112 IID = Intrinsic::x86_avx512_fpclass_ps_512; 2113 else if (VecWidth == 128 && EltWidth == 64) 2114 IID = Intrinsic::x86_avx512_fpclass_pd_128; 2115 else if (VecWidth == 256 && EltWidth == 64) 2116 IID = Intrinsic::x86_avx512_fpclass_pd_256; 2117 else if (VecWidth == 512 && EltWidth == 64) 2118 IID = Intrinsic::x86_avx512_fpclass_pd_512; 2119 else 2120 llvm_unreachable("Unexpected intrinsic"); 2121 2122 Rep = Builder.CreateCall(Intrinsic::getDeclaration(F->getParent(), IID), 2123 { CI->getOperand(0), CI->getArgOperand(1) }); 2124 Rep = ApplyX86MaskOn1BitsVec(Builder, Rep, CI->getArgOperand(2)); 2125 } else if (IsX86 && Name.startswith("avx512.cmp.p")) { 2126 SmallVector<Value *, 4> Args(CI->args()); 2127 Type *OpTy = Args[0]->getType(); 2128 unsigned VecWidth = OpTy->getPrimitiveSizeInBits(); 2129 unsigned EltWidth = OpTy->getScalarSizeInBits(); 2130 Intrinsic::ID IID; 2131 if (VecWidth == 128 && EltWidth == 32) 2132 IID = Intrinsic::x86_avx512_mask_cmp_ps_128; 2133 else if (VecWidth == 256 && EltWidth == 32) 2134 IID = Intrinsic::x86_avx512_mask_cmp_ps_256; 2135 else if (VecWidth == 512 && EltWidth == 32) 2136 IID = Intrinsic::x86_avx512_mask_cmp_ps_512; 2137 else if (VecWidth == 128 && EltWidth == 64) 2138 IID = Intrinsic::x86_avx512_mask_cmp_pd_128; 2139 else if (VecWidth == 256 && EltWidth == 64) 2140 IID = Intrinsic::x86_avx512_mask_cmp_pd_256; 2141 else if (VecWidth == 512 && EltWidth == 64) 2142 IID = Intrinsic::x86_avx512_mask_cmp_pd_512; 2143 else 2144 llvm_unreachable("Unexpected intrinsic"); 2145 2146 Value *Mask = Constant::getAllOnesValue(CI->getType()); 2147 if (VecWidth == 512) 2148 std::swap(Mask, Args.back()); 2149 Args.push_back(Mask); 2150 2151 Rep = Builder.CreateCall(Intrinsic::getDeclaration(F->getParent(), IID), 2152 Args); 2153 } else if (IsX86 && Name.startswith("avx512.mask.cmp.")) { 2154 // Integer compare intrinsics. 2155 unsigned Imm = cast<ConstantInt>(CI->getArgOperand(2))->getZExtValue(); 2156 Rep = upgradeMaskedCompare(Builder, *CI, Imm, true); 2157 } else if (IsX86 && Name.startswith("avx512.mask.ucmp.")) { 2158 unsigned Imm = cast<ConstantInt>(CI->getArgOperand(2))->getZExtValue(); 2159 Rep = upgradeMaskedCompare(Builder, *CI, Imm, false); 2160 } else if (IsX86 && (Name.startswith("avx512.cvtb2mask.") || 2161 Name.startswith("avx512.cvtw2mask.") || 2162 Name.startswith("avx512.cvtd2mask.") || 2163 Name.startswith("avx512.cvtq2mask."))) { 2164 Value *Op = CI->getArgOperand(0); 2165 Value *Zero = llvm::Constant::getNullValue(Op->getType()); 2166 Rep = Builder.CreateICmp(ICmpInst::ICMP_SLT, Op, Zero); 2167 Rep = ApplyX86MaskOn1BitsVec(Builder, Rep, nullptr); 2168 } else if(IsX86 && (Name == "ssse3.pabs.b.128" || 2169 Name == "ssse3.pabs.w.128" || 2170 Name == "ssse3.pabs.d.128" || 2171 Name.startswith("avx2.pabs") || 2172 Name.startswith("avx512.mask.pabs"))) { 2173 Rep = upgradeAbs(Builder, *CI); 2174 } else if (IsX86 && (Name == "sse41.pmaxsb" || 2175 Name == "sse2.pmaxs.w" || 2176 Name == "sse41.pmaxsd" || 2177 Name.startswith("avx2.pmaxs") || 2178 Name.startswith("avx512.mask.pmaxs"))) { 2179 Rep = UpgradeX86BinaryIntrinsics(Builder, *CI, Intrinsic::smax); 2180 } else if (IsX86 && (Name == "sse2.pmaxu.b" || 2181 Name == "sse41.pmaxuw" || 2182 Name == "sse41.pmaxud" || 2183 Name.startswith("avx2.pmaxu") || 2184 Name.startswith("avx512.mask.pmaxu"))) { 2185 Rep = UpgradeX86BinaryIntrinsics(Builder, *CI, Intrinsic::umax); 2186 } else if (IsX86 && (Name == "sse41.pminsb" || 2187 Name == "sse2.pmins.w" || 2188 Name == "sse41.pminsd" || 2189 Name.startswith("avx2.pmins") || 2190 Name.startswith("avx512.mask.pmins"))) { 2191 Rep = UpgradeX86BinaryIntrinsics(Builder, *CI, Intrinsic::smin); 2192 } else if (IsX86 && (Name == "sse2.pminu.b" || 2193 Name == "sse41.pminuw" || 2194 Name == "sse41.pminud" || 2195 Name.startswith("avx2.pminu") || 2196 Name.startswith("avx512.mask.pminu"))) { 2197 Rep = UpgradeX86BinaryIntrinsics(Builder, *CI, Intrinsic::umin); 2198 } else if (IsX86 && (Name == "sse2.pmulu.dq" || 2199 Name == "avx2.pmulu.dq" || 2200 Name == "avx512.pmulu.dq.512" || 2201 Name.startswith("avx512.mask.pmulu.dq."))) { 2202 Rep = upgradePMULDQ(Builder, *CI, /*Signed*/false); 2203 } else if (IsX86 && (Name == "sse41.pmuldq" || 2204 Name == "avx2.pmul.dq" || 2205 Name == "avx512.pmul.dq.512" || 2206 Name.startswith("avx512.mask.pmul.dq."))) { 2207 Rep = upgradePMULDQ(Builder, *CI, /*Signed*/true); 2208 } else if (IsX86 && (Name == "sse.cvtsi2ss" || 2209 Name == "sse2.cvtsi2sd" || 2210 Name == "sse.cvtsi642ss" || 2211 Name == "sse2.cvtsi642sd")) { 2212 Rep = Builder.CreateSIToFP( 2213 CI->getArgOperand(1), 2214 cast<VectorType>(CI->getType())->getElementType()); 2215 Rep = Builder.CreateInsertElement(CI->getArgOperand(0), Rep, (uint64_t)0); 2216 } else if (IsX86 && Name == "avx512.cvtusi2sd") { 2217 Rep = Builder.CreateUIToFP( 2218 CI->getArgOperand(1), 2219 cast<VectorType>(CI->getType())->getElementType()); 2220 Rep = Builder.CreateInsertElement(CI->getArgOperand(0), Rep, (uint64_t)0); 2221 } else if (IsX86 && Name == "sse2.cvtss2sd") { 2222 Rep = Builder.CreateExtractElement(CI->getArgOperand(1), (uint64_t)0); 2223 Rep = Builder.CreateFPExt( 2224 Rep, cast<VectorType>(CI->getType())->getElementType()); 2225 Rep = Builder.CreateInsertElement(CI->getArgOperand(0), Rep, (uint64_t)0); 2226 } else if (IsX86 && (Name == "sse2.cvtdq2pd" || 2227 Name == "sse2.cvtdq2ps" || 2228 Name == "avx.cvtdq2.pd.256" || 2229 Name == "avx.cvtdq2.ps.256" || 2230 Name.startswith("avx512.mask.cvtdq2pd.") || 2231 Name.startswith("avx512.mask.cvtudq2pd.") || 2232 Name.startswith("avx512.mask.cvtdq2ps.") || 2233 Name.startswith("avx512.mask.cvtudq2ps.") || 2234 Name.startswith("avx512.mask.cvtqq2pd.") || 2235 Name.startswith("avx512.mask.cvtuqq2pd.") || 2236 Name == "avx512.mask.cvtqq2ps.256" || 2237 Name == "avx512.mask.cvtqq2ps.512" || 2238 Name == "avx512.mask.cvtuqq2ps.256" || 2239 Name == "avx512.mask.cvtuqq2ps.512" || 2240 Name == "sse2.cvtps2pd" || 2241 Name == "avx.cvt.ps2.pd.256" || 2242 Name == "avx512.mask.cvtps2pd.128" || 2243 Name == "avx512.mask.cvtps2pd.256")) { 2244 auto *DstTy = cast<FixedVectorType>(CI->getType()); 2245 Rep = CI->getArgOperand(0); 2246 auto *SrcTy = cast<FixedVectorType>(Rep->getType()); 2247 2248 unsigned NumDstElts = DstTy->getNumElements(); 2249 if (NumDstElts < SrcTy->getNumElements()) { 2250 assert(NumDstElts == 2 && "Unexpected vector size"); 2251 Rep = Builder.CreateShuffleVector(Rep, Rep, ArrayRef<int>{0, 1}); 2252 } 2253 2254 bool IsPS2PD = SrcTy->getElementType()->isFloatTy(); 2255 bool IsUnsigned = (StringRef::npos != Name.find("cvtu")); 2256 if (IsPS2PD) 2257 Rep = Builder.CreateFPExt(Rep, DstTy, "cvtps2pd"); 2258 else if (CI->getNumArgOperands() == 4 && 2259 (!isa<ConstantInt>(CI->getArgOperand(3)) || 2260 cast<ConstantInt>(CI->getArgOperand(3))->getZExtValue() != 4)) { 2261 Intrinsic::ID IID = IsUnsigned ? Intrinsic::x86_avx512_uitofp_round 2262 : Intrinsic::x86_avx512_sitofp_round; 2263 Function *F = Intrinsic::getDeclaration(CI->getModule(), IID, 2264 { DstTy, SrcTy }); 2265 Rep = Builder.CreateCall(F, { Rep, CI->getArgOperand(3) }); 2266 } else { 2267 Rep = IsUnsigned ? Builder.CreateUIToFP(Rep, DstTy, "cvt") 2268 : Builder.CreateSIToFP(Rep, DstTy, "cvt"); 2269 } 2270 2271 if (CI->getNumArgOperands() >= 3) 2272 Rep = EmitX86Select(Builder, CI->getArgOperand(2), Rep, 2273 CI->getArgOperand(1)); 2274 } else if (IsX86 && (Name.startswith("avx512.mask.vcvtph2ps.") || 2275 Name.startswith("vcvtph2ps."))) { 2276 auto *DstTy = cast<FixedVectorType>(CI->getType()); 2277 Rep = CI->getArgOperand(0); 2278 auto *SrcTy = cast<FixedVectorType>(Rep->getType()); 2279 unsigned NumDstElts = DstTy->getNumElements(); 2280 if (NumDstElts != SrcTy->getNumElements()) { 2281 assert(NumDstElts == 4 && "Unexpected vector size"); 2282 Rep = Builder.CreateShuffleVector(Rep, Rep, ArrayRef<int>{0, 1, 2, 3}); 2283 } 2284 Rep = Builder.CreateBitCast( 2285 Rep, FixedVectorType::get(Type::getHalfTy(C), NumDstElts)); 2286 Rep = Builder.CreateFPExt(Rep, DstTy, "cvtph2ps"); 2287 if (CI->getNumArgOperands() >= 3) 2288 Rep = EmitX86Select(Builder, CI->getArgOperand(2), Rep, 2289 CI->getArgOperand(1)); 2290 } else if (IsX86 && (Name.startswith("avx512.mask.loadu."))) { 2291 Rep = UpgradeMaskedLoad(Builder, CI->getArgOperand(0), 2292 CI->getArgOperand(1), CI->getArgOperand(2), 2293 /*Aligned*/false); 2294 } else if (IsX86 && (Name.startswith("avx512.mask.load."))) { 2295 Rep = UpgradeMaskedLoad(Builder, CI->getArgOperand(0), 2296 CI->getArgOperand(1),CI->getArgOperand(2), 2297 /*Aligned*/true); 2298 } else if (IsX86 && Name.startswith("avx512.mask.expand.load.")) { 2299 auto *ResultTy = cast<FixedVectorType>(CI->getType()); 2300 Type *PtrTy = ResultTy->getElementType(); 2301 2302 // Cast the pointer to element type. 2303 Value *Ptr = Builder.CreateBitCast(CI->getOperand(0), 2304 llvm::PointerType::getUnqual(PtrTy)); 2305 2306 Value *MaskVec = getX86MaskVec(Builder, CI->getArgOperand(2), 2307 ResultTy->getNumElements()); 2308 2309 Function *ELd = Intrinsic::getDeclaration(F->getParent(), 2310 Intrinsic::masked_expandload, 2311 ResultTy); 2312 Rep = Builder.CreateCall(ELd, { Ptr, MaskVec, CI->getOperand(1) }); 2313 } else if (IsX86 && Name.startswith("avx512.mask.compress.store.")) { 2314 auto *ResultTy = cast<VectorType>(CI->getArgOperand(1)->getType()); 2315 Type *PtrTy = ResultTy->getElementType(); 2316 2317 // Cast the pointer to element type. 2318 Value *Ptr = Builder.CreateBitCast(CI->getOperand(0), 2319 llvm::PointerType::getUnqual(PtrTy)); 2320 2321 Value *MaskVec = 2322 getX86MaskVec(Builder, CI->getArgOperand(2), 2323 cast<FixedVectorType>(ResultTy)->getNumElements()); 2324 2325 Function *CSt = Intrinsic::getDeclaration(F->getParent(), 2326 Intrinsic::masked_compressstore, 2327 ResultTy); 2328 Rep = Builder.CreateCall(CSt, { CI->getArgOperand(1), Ptr, MaskVec }); 2329 } else if (IsX86 && (Name.startswith("avx512.mask.compress.") || 2330 Name.startswith("avx512.mask.expand."))) { 2331 auto *ResultTy = cast<FixedVectorType>(CI->getType()); 2332 2333 Value *MaskVec = getX86MaskVec(Builder, CI->getArgOperand(2), 2334 ResultTy->getNumElements()); 2335 2336 bool IsCompress = Name[12] == 'c'; 2337 Intrinsic::ID IID = IsCompress ? Intrinsic::x86_avx512_mask_compress 2338 : Intrinsic::x86_avx512_mask_expand; 2339 Function *Intr = Intrinsic::getDeclaration(F->getParent(), IID, ResultTy); 2340 Rep = Builder.CreateCall(Intr, { CI->getOperand(0), CI->getOperand(1), 2341 MaskVec }); 2342 } else if (IsX86 && Name.startswith("xop.vpcom")) { 2343 bool IsSigned; 2344 if (Name.endswith("ub") || Name.endswith("uw") || Name.endswith("ud") || 2345 Name.endswith("uq")) 2346 IsSigned = false; 2347 else if (Name.endswith("b") || Name.endswith("w") || Name.endswith("d") || 2348 Name.endswith("q")) 2349 IsSigned = true; 2350 else 2351 llvm_unreachable("Unknown suffix"); 2352 2353 unsigned Imm; 2354 if (CI->getNumArgOperands() == 3) { 2355 Imm = cast<ConstantInt>(CI->getArgOperand(2))->getZExtValue(); 2356 } else { 2357 Name = Name.substr(9); // strip off "xop.vpcom" 2358 if (Name.startswith("lt")) 2359 Imm = 0; 2360 else if (Name.startswith("le")) 2361 Imm = 1; 2362 else if (Name.startswith("gt")) 2363 Imm = 2; 2364 else if (Name.startswith("ge")) 2365 Imm = 3; 2366 else if (Name.startswith("eq")) 2367 Imm = 4; 2368 else if (Name.startswith("ne")) 2369 Imm = 5; 2370 else if (Name.startswith("false")) 2371 Imm = 6; 2372 else if (Name.startswith("true")) 2373 Imm = 7; 2374 else 2375 llvm_unreachable("Unknown condition"); 2376 } 2377 2378 Rep = upgradeX86vpcom(Builder, *CI, Imm, IsSigned); 2379 } else if (IsX86 && Name.startswith("xop.vpcmov")) { 2380 Value *Sel = CI->getArgOperand(2); 2381 Value *NotSel = Builder.CreateNot(Sel); 2382 Value *Sel0 = Builder.CreateAnd(CI->getArgOperand(0), Sel); 2383 Value *Sel1 = Builder.CreateAnd(CI->getArgOperand(1), NotSel); 2384 Rep = Builder.CreateOr(Sel0, Sel1); 2385 } else if (IsX86 && (Name.startswith("xop.vprot") || 2386 Name.startswith("avx512.prol") || 2387 Name.startswith("avx512.mask.prol"))) { 2388 Rep = upgradeX86Rotate(Builder, *CI, false); 2389 } else if (IsX86 && (Name.startswith("avx512.pror") || 2390 Name.startswith("avx512.mask.pror"))) { 2391 Rep = upgradeX86Rotate(Builder, *CI, true); 2392 } else if (IsX86 && (Name.startswith("avx512.vpshld.") || 2393 Name.startswith("avx512.mask.vpshld") || 2394 Name.startswith("avx512.maskz.vpshld"))) { 2395 bool ZeroMask = Name[11] == 'z'; 2396 Rep = upgradeX86ConcatShift(Builder, *CI, false, ZeroMask); 2397 } else if (IsX86 && (Name.startswith("avx512.vpshrd.") || 2398 Name.startswith("avx512.mask.vpshrd") || 2399 Name.startswith("avx512.maskz.vpshrd"))) { 2400 bool ZeroMask = Name[11] == 'z'; 2401 Rep = upgradeX86ConcatShift(Builder, *CI, true, ZeroMask); 2402 } else if (IsX86 && Name == "sse42.crc32.64.8") { 2403 Function *CRC32 = Intrinsic::getDeclaration(F->getParent(), 2404 Intrinsic::x86_sse42_crc32_32_8); 2405 Value *Trunc0 = Builder.CreateTrunc(CI->getArgOperand(0), Type::getInt32Ty(C)); 2406 Rep = Builder.CreateCall(CRC32, {Trunc0, CI->getArgOperand(1)}); 2407 Rep = Builder.CreateZExt(Rep, CI->getType(), ""); 2408 } else if (IsX86 && (Name.startswith("avx.vbroadcast.s") || 2409 Name.startswith("avx512.vbroadcast.s"))) { 2410 // Replace broadcasts with a series of insertelements. 2411 auto *VecTy = cast<FixedVectorType>(CI->getType()); 2412 Type *EltTy = VecTy->getElementType(); 2413 unsigned EltNum = VecTy->getNumElements(); 2414 Value *Cast = Builder.CreateBitCast(CI->getArgOperand(0), 2415 EltTy->getPointerTo()); 2416 Value *Load = Builder.CreateLoad(EltTy, Cast); 2417 Type *I32Ty = Type::getInt32Ty(C); 2418 Rep = UndefValue::get(VecTy); 2419 for (unsigned I = 0; I < EltNum; ++I) 2420 Rep = Builder.CreateInsertElement(Rep, Load, 2421 ConstantInt::get(I32Ty, I)); 2422 } else if (IsX86 && (Name.startswith("sse41.pmovsx") || 2423 Name.startswith("sse41.pmovzx") || 2424 Name.startswith("avx2.pmovsx") || 2425 Name.startswith("avx2.pmovzx") || 2426 Name.startswith("avx512.mask.pmovsx") || 2427 Name.startswith("avx512.mask.pmovzx"))) { 2428 auto *DstTy = cast<FixedVectorType>(CI->getType()); 2429 unsigned NumDstElts = DstTy->getNumElements(); 2430 2431 // Extract a subvector of the first NumDstElts lanes and sign/zero extend. 2432 SmallVector<int, 8> ShuffleMask(NumDstElts); 2433 for (unsigned i = 0; i != NumDstElts; ++i) 2434 ShuffleMask[i] = i; 2435 2436 Value *SV = 2437 Builder.CreateShuffleVector(CI->getArgOperand(0), ShuffleMask); 2438 2439 bool DoSext = (StringRef::npos != Name.find("pmovsx")); 2440 Rep = DoSext ? Builder.CreateSExt(SV, DstTy) 2441 : Builder.CreateZExt(SV, DstTy); 2442 // If there are 3 arguments, it's a masked intrinsic so we need a select. 2443 if (CI->getNumArgOperands() == 3) 2444 Rep = EmitX86Select(Builder, CI->getArgOperand(2), Rep, 2445 CI->getArgOperand(1)); 2446 } else if (Name == "avx512.mask.pmov.qd.256" || 2447 Name == "avx512.mask.pmov.qd.512" || 2448 Name == "avx512.mask.pmov.wb.256" || 2449 Name == "avx512.mask.pmov.wb.512") { 2450 Type *Ty = CI->getArgOperand(1)->getType(); 2451 Rep = Builder.CreateTrunc(CI->getArgOperand(0), Ty); 2452 Rep = EmitX86Select(Builder, CI->getArgOperand(2), Rep, 2453 CI->getArgOperand(1)); 2454 } else if (IsX86 && (Name.startswith("avx.vbroadcastf128") || 2455 Name == "avx2.vbroadcasti128")) { 2456 // Replace vbroadcastf128/vbroadcasti128 with a vector load+shuffle. 2457 Type *EltTy = cast<VectorType>(CI->getType())->getElementType(); 2458 unsigned NumSrcElts = 128 / EltTy->getPrimitiveSizeInBits(); 2459 auto *VT = FixedVectorType::get(EltTy, NumSrcElts); 2460 Value *Op = Builder.CreatePointerCast(CI->getArgOperand(0), 2461 PointerType::getUnqual(VT)); 2462 Value *Load = Builder.CreateAlignedLoad(VT, Op, Align(1)); 2463 if (NumSrcElts == 2) 2464 Rep = Builder.CreateShuffleVector(Load, ArrayRef<int>{0, 1, 0, 1}); 2465 else 2466 Rep = Builder.CreateShuffleVector( 2467 Load, ArrayRef<int>{0, 1, 2, 3, 0, 1, 2, 3}); 2468 } else if (IsX86 && (Name.startswith("avx512.mask.shuf.i") || 2469 Name.startswith("avx512.mask.shuf.f"))) { 2470 unsigned Imm = cast<ConstantInt>(CI->getArgOperand(2))->getZExtValue(); 2471 Type *VT = CI->getType(); 2472 unsigned NumLanes = VT->getPrimitiveSizeInBits() / 128; 2473 unsigned NumElementsInLane = 128 / VT->getScalarSizeInBits(); 2474 unsigned ControlBitsMask = NumLanes - 1; 2475 unsigned NumControlBits = NumLanes / 2; 2476 SmallVector<int, 8> ShuffleMask(0); 2477 2478 for (unsigned l = 0; l != NumLanes; ++l) { 2479 unsigned LaneMask = (Imm >> (l * NumControlBits)) & ControlBitsMask; 2480 // We actually need the other source. 2481 if (l >= NumLanes / 2) 2482 LaneMask += NumLanes; 2483 for (unsigned i = 0; i != NumElementsInLane; ++i) 2484 ShuffleMask.push_back(LaneMask * NumElementsInLane + i); 2485 } 2486 Rep = Builder.CreateShuffleVector(CI->getArgOperand(0), 2487 CI->getArgOperand(1), ShuffleMask); 2488 Rep = EmitX86Select(Builder, CI->getArgOperand(4), Rep, 2489 CI->getArgOperand(3)); 2490 }else if (IsX86 && (Name.startswith("avx512.mask.broadcastf") || 2491 Name.startswith("avx512.mask.broadcasti"))) { 2492 unsigned NumSrcElts = 2493 cast<FixedVectorType>(CI->getArgOperand(0)->getType()) 2494 ->getNumElements(); 2495 unsigned NumDstElts = 2496 cast<FixedVectorType>(CI->getType())->getNumElements(); 2497 2498 SmallVector<int, 8> ShuffleMask(NumDstElts); 2499 for (unsigned i = 0; i != NumDstElts; ++i) 2500 ShuffleMask[i] = i % NumSrcElts; 2501 2502 Rep = Builder.CreateShuffleVector(CI->getArgOperand(0), 2503 CI->getArgOperand(0), 2504 ShuffleMask); 2505 Rep = EmitX86Select(Builder, CI->getArgOperand(2), Rep, 2506 CI->getArgOperand(1)); 2507 } else if (IsX86 && (Name.startswith("avx2.pbroadcast") || 2508 Name.startswith("avx2.vbroadcast") || 2509 Name.startswith("avx512.pbroadcast") || 2510 Name.startswith("avx512.mask.broadcast.s"))) { 2511 // Replace vp?broadcasts with a vector shuffle. 2512 Value *Op = CI->getArgOperand(0); 2513 ElementCount EC = cast<VectorType>(CI->getType())->getElementCount(); 2514 Type *MaskTy = VectorType::get(Type::getInt32Ty(C), EC); 2515 SmallVector<int, 8> M; 2516 ShuffleVectorInst::getShuffleMask(Constant::getNullValue(MaskTy), M); 2517 Rep = Builder.CreateShuffleVector(Op, M); 2518 2519 if (CI->getNumArgOperands() == 3) 2520 Rep = EmitX86Select(Builder, CI->getArgOperand(2), Rep, 2521 CI->getArgOperand(1)); 2522 } else if (IsX86 && (Name.startswith("sse2.padds.") || 2523 Name.startswith("avx2.padds.") || 2524 Name.startswith("avx512.padds.") || 2525 Name.startswith("avx512.mask.padds."))) { 2526 Rep = UpgradeX86BinaryIntrinsics(Builder, *CI, Intrinsic::sadd_sat); 2527 } else if (IsX86 && (Name.startswith("sse2.psubs.") || 2528 Name.startswith("avx2.psubs.") || 2529 Name.startswith("avx512.psubs.") || 2530 Name.startswith("avx512.mask.psubs."))) { 2531 Rep = UpgradeX86BinaryIntrinsics(Builder, *CI, Intrinsic::ssub_sat); 2532 } else if (IsX86 && (Name.startswith("sse2.paddus.") || 2533 Name.startswith("avx2.paddus.") || 2534 Name.startswith("avx512.mask.paddus."))) { 2535 Rep = UpgradeX86BinaryIntrinsics(Builder, *CI, Intrinsic::uadd_sat); 2536 } else if (IsX86 && (Name.startswith("sse2.psubus.") || 2537 Name.startswith("avx2.psubus.") || 2538 Name.startswith("avx512.mask.psubus."))) { 2539 Rep = UpgradeX86BinaryIntrinsics(Builder, *CI, Intrinsic::usub_sat); 2540 } else if (IsX86 && Name.startswith("avx512.mask.palignr.")) { 2541 Rep = UpgradeX86ALIGNIntrinsics(Builder, CI->getArgOperand(0), 2542 CI->getArgOperand(1), 2543 CI->getArgOperand(2), 2544 CI->getArgOperand(3), 2545 CI->getArgOperand(4), 2546 false); 2547 } else if (IsX86 && Name.startswith("avx512.mask.valign.")) { 2548 Rep = UpgradeX86ALIGNIntrinsics(Builder, CI->getArgOperand(0), 2549 CI->getArgOperand(1), 2550 CI->getArgOperand(2), 2551 CI->getArgOperand(3), 2552 CI->getArgOperand(4), 2553 true); 2554 } else if (IsX86 && (Name == "sse2.psll.dq" || 2555 Name == "avx2.psll.dq")) { 2556 // 128/256-bit shift left specified in bits. 2557 unsigned Shift = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue(); 2558 Rep = UpgradeX86PSLLDQIntrinsics(Builder, CI->getArgOperand(0), 2559 Shift / 8); // Shift is in bits. 2560 } else if (IsX86 && (Name == "sse2.psrl.dq" || 2561 Name == "avx2.psrl.dq")) { 2562 // 128/256-bit shift right specified in bits. 2563 unsigned Shift = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue(); 2564 Rep = UpgradeX86PSRLDQIntrinsics(Builder, CI->getArgOperand(0), 2565 Shift / 8); // Shift is in bits. 2566 } else if (IsX86 && (Name == "sse2.psll.dq.bs" || 2567 Name == "avx2.psll.dq.bs" || 2568 Name == "avx512.psll.dq.512")) { 2569 // 128/256/512-bit shift left specified in bytes. 2570 unsigned Shift = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue(); 2571 Rep = UpgradeX86PSLLDQIntrinsics(Builder, CI->getArgOperand(0), Shift); 2572 } else if (IsX86 && (Name == "sse2.psrl.dq.bs" || 2573 Name == "avx2.psrl.dq.bs" || 2574 Name == "avx512.psrl.dq.512")) { 2575 // 128/256/512-bit shift right specified in bytes. 2576 unsigned Shift = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue(); 2577 Rep = UpgradeX86PSRLDQIntrinsics(Builder, CI->getArgOperand(0), Shift); 2578 } else if (IsX86 && (Name == "sse41.pblendw" || 2579 Name.startswith("sse41.blendp") || 2580 Name.startswith("avx.blend.p") || 2581 Name == "avx2.pblendw" || 2582 Name.startswith("avx2.pblendd."))) { 2583 Value *Op0 = CI->getArgOperand(0); 2584 Value *Op1 = CI->getArgOperand(1); 2585 unsigned Imm = cast <ConstantInt>(CI->getArgOperand(2))->getZExtValue(); 2586 auto *VecTy = cast<FixedVectorType>(CI->getType()); 2587 unsigned NumElts = VecTy->getNumElements(); 2588 2589 SmallVector<int, 16> Idxs(NumElts); 2590 for (unsigned i = 0; i != NumElts; ++i) 2591 Idxs[i] = ((Imm >> (i%8)) & 1) ? i + NumElts : i; 2592 2593 Rep = Builder.CreateShuffleVector(Op0, Op1, Idxs); 2594 } else if (IsX86 && (Name.startswith("avx.vinsertf128.") || 2595 Name == "avx2.vinserti128" || 2596 Name.startswith("avx512.mask.insert"))) { 2597 Value *Op0 = CI->getArgOperand(0); 2598 Value *Op1 = CI->getArgOperand(1); 2599 unsigned Imm = cast<ConstantInt>(CI->getArgOperand(2))->getZExtValue(); 2600 unsigned DstNumElts = 2601 cast<FixedVectorType>(CI->getType())->getNumElements(); 2602 unsigned SrcNumElts = 2603 cast<FixedVectorType>(Op1->getType())->getNumElements(); 2604 unsigned Scale = DstNumElts / SrcNumElts; 2605 2606 // Mask off the high bits of the immediate value; hardware ignores those. 2607 Imm = Imm % Scale; 2608 2609 // Extend the second operand into a vector the size of the destination. 2610 SmallVector<int, 8> Idxs(DstNumElts); 2611 for (unsigned i = 0; i != SrcNumElts; ++i) 2612 Idxs[i] = i; 2613 for (unsigned i = SrcNumElts; i != DstNumElts; ++i) 2614 Idxs[i] = SrcNumElts; 2615 Rep = Builder.CreateShuffleVector(Op1, Idxs); 2616 2617 // Insert the second operand into the first operand. 2618 2619 // Note that there is no guarantee that instruction lowering will actually 2620 // produce a vinsertf128 instruction for the created shuffles. In 2621 // particular, the 0 immediate case involves no lane changes, so it can 2622 // be handled as a blend. 2623 2624 // Example of shuffle mask for 32-bit elements: 2625 // Imm = 1 <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11> 2626 // Imm = 0 <i32 8, i32 9, i32 10, i32 11, i32 4, i32 5, i32 6, i32 7 > 2627 2628 // First fill with identify mask. 2629 for (unsigned i = 0; i != DstNumElts; ++i) 2630 Idxs[i] = i; 2631 // Then replace the elements where we need to insert. 2632 for (unsigned i = 0; i != SrcNumElts; ++i) 2633 Idxs[i + Imm * SrcNumElts] = i + DstNumElts; 2634 Rep = Builder.CreateShuffleVector(Op0, Rep, Idxs); 2635 2636 // If the intrinsic has a mask operand, handle that. 2637 if (CI->getNumArgOperands() == 5) 2638 Rep = EmitX86Select(Builder, CI->getArgOperand(4), Rep, 2639 CI->getArgOperand(3)); 2640 } else if (IsX86 && (Name.startswith("avx.vextractf128.") || 2641 Name == "avx2.vextracti128" || 2642 Name.startswith("avx512.mask.vextract"))) { 2643 Value *Op0 = CI->getArgOperand(0); 2644 unsigned Imm = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue(); 2645 unsigned DstNumElts = 2646 cast<FixedVectorType>(CI->getType())->getNumElements(); 2647 unsigned SrcNumElts = 2648 cast<FixedVectorType>(Op0->getType())->getNumElements(); 2649 unsigned Scale = SrcNumElts / DstNumElts; 2650 2651 // Mask off the high bits of the immediate value; hardware ignores those. 2652 Imm = Imm % Scale; 2653 2654 // Get indexes for the subvector of the input vector. 2655 SmallVector<int, 8> Idxs(DstNumElts); 2656 for (unsigned i = 0; i != DstNumElts; ++i) { 2657 Idxs[i] = i + (Imm * DstNumElts); 2658 } 2659 Rep = Builder.CreateShuffleVector(Op0, Op0, Idxs); 2660 2661 // If the intrinsic has a mask operand, handle that. 2662 if (CI->getNumArgOperands() == 4) 2663 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 2664 CI->getArgOperand(2)); 2665 } else if (!IsX86 && Name == "stackprotectorcheck") { 2666 Rep = nullptr; 2667 } else if (IsX86 && (Name.startswith("avx512.mask.perm.df.") || 2668 Name.startswith("avx512.mask.perm.di."))) { 2669 Value *Op0 = CI->getArgOperand(0); 2670 unsigned Imm = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue(); 2671 auto *VecTy = cast<FixedVectorType>(CI->getType()); 2672 unsigned NumElts = VecTy->getNumElements(); 2673 2674 SmallVector<int, 8> Idxs(NumElts); 2675 for (unsigned i = 0; i != NumElts; ++i) 2676 Idxs[i] = (i & ~0x3) + ((Imm >> (2 * (i & 0x3))) & 3); 2677 2678 Rep = Builder.CreateShuffleVector(Op0, Op0, Idxs); 2679 2680 if (CI->getNumArgOperands() == 4) 2681 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 2682 CI->getArgOperand(2)); 2683 } else if (IsX86 && (Name.startswith("avx.vperm2f128.") || 2684 Name == "avx2.vperm2i128")) { 2685 // The immediate permute control byte looks like this: 2686 // [1:0] - select 128 bits from sources for low half of destination 2687 // [2] - ignore 2688 // [3] - zero low half of destination 2689 // [5:4] - select 128 bits from sources for high half of destination 2690 // [6] - ignore 2691 // [7] - zero high half of destination 2692 2693 uint8_t Imm = cast<ConstantInt>(CI->getArgOperand(2))->getZExtValue(); 2694 2695 unsigned NumElts = cast<FixedVectorType>(CI->getType())->getNumElements(); 2696 unsigned HalfSize = NumElts / 2; 2697 SmallVector<int, 8> ShuffleMask(NumElts); 2698 2699 // Determine which operand(s) are actually in use for this instruction. 2700 Value *V0 = (Imm & 0x02) ? CI->getArgOperand(1) : CI->getArgOperand(0); 2701 Value *V1 = (Imm & 0x20) ? CI->getArgOperand(1) : CI->getArgOperand(0); 2702 2703 // If needed, replace operands based on zero mask. 2704 V0 = (Imm & 0x08) ? ConstantAggregateZero::get(CI->getType()) : V0; 2705 V1 = (Imm & 0x80) ? ConstantAggregateZero::get(CI->getType()) : V1; 2706 2707 // Permute low half of result. 2708 unsigned StartIndex = (Imm & 0x01) ? HalfSize : 0; 2709 for (unsigned i = 0; i < HalfSize; ++i) 2710 ShuffleMask[i] = StartIndex + i; 2711 2712 // Permute high half of result. 2713 StartIndex = (Imm & 0x10) ? HalfSize : 0; 2714 for (unsigned i = 0; i < HalfSize; ++i) 2715 ShuffleMask[i + HalfSize] = NumElts + StartIndex + i; 2716 2717 Rep = Builder.CreateShuffleVector(V0, V1, ShuffleMask); 2718 2719 } else if (IsX86 && (Name.startswith("avx.vpermil.") || 2720 Name == "sse2.pshuf.d" || 2721 Name.startswith("avx512.mask.vpermil.p") || 2722 Name.startswith("avx512.mask.pshuf.d."))) { 2723 Value *Op0 = CI->getArgOperand(0); 2724 unsigned Imm = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue(); 2725 auto *VecTy = cast<FixedVectorType>(CI->getType()); 2726 unsigned NumElts = VecTy->getNumElements(); 2727 // Calculate the size of each index in the immediate. 2728 unsigned IdxSize = 64 / VecTy->getScalarSizeInBits(); 2729 unsigned IdxMask = ((1 << IdxSize) - 1); 2730 2731 SmallVector<int, 8> Idxs(NumElts); 2732 // Lookup the bits for this element, wrapping around the immediate every 2733 // 8-bits. Elements are grouped into sets of 2 or 4 elements so we need 2734 // to offset by the first index of each group. 2735 for (unsigned i = 0; i != NumElts; ++i) 2736 Idxs[i] = ((Imm >> ((i * IdxSize) % 8)) & IdxMask) | (i & ~IdxMask); 2737 2738 Rep = Builder.CreateShuffleVector(Op0, Op0, Idxs); 2739 2740 if (CI->getNumArgOperands() == 4) 2741 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 2742 CI->getArgOperand(2)); 2743 } else if (IsX86 && (Name == "sse2.pshufl.w" || 2744 Name.startswith("avx512.mask.pshufl.w."))) { 2745 Value *Op0 = CI->getArgOperand(0); 2746 unsigned Imm = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue(); 2747 unsigned NumElts = cast<FixedVectorType>(CI->getType())->getNumElements(); 2748 2749 SmallVector<int, 16> Idxs(NumElts); 2750 for (unsigned l = 0; l != NumElts; l += 8) { 2751 for (unsigned i = 0; i != 4; ++i) 2752 Idxs[i + l] = ((Imm >> (2 * i)) & 0x3) + l; 2753 for (unsigned i = 4; i != 8; ++i) 2754 Idxs[i + l] = i + l; 2755 } 2756 2757 Rep = Builder.CreateShuffleVector(Op0, Op0, Idxs); 2758 2759 if (CI->getNumArgOperands() == 4) 2760 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 2761 CI->getArgOperand(2)); 2762 } else if (IsX86 && (Name == "sse2.pshufh.w" || 2763 Name.startswith("avx512.mask.pshufh.w."))) { 2764 Value *Op0 = CI->getArgOperand(0); 2765 unsigned Imm = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue(); 2766 unsigned NumElts = cast<FixedVectorType>(CI->getType())->getNumElements(); 2767 2768 SmallVector<int, 16> Idxs(NumElts); 2769 for (unsigned l = 0; l != NumElts; l += 8) { 2770 for (unsigned i = 0; i != 4; ++i) 2771 Idxs[i + l] = i + l; 2772 for (unsigned i = 0; i != 4; ++i) 2773 Idxs[i + l + 4] = ((Imm >> (2 * i)) & 0x3) + 4 + l; 2774 } 2775 2776 Rep = Builder.CreateShuffleVector(Op0, Op0, Idxs); 2777 2778 if (CI->getNumArgOperands() == 4) 2779 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 2780 CI->getArgOperand(2)); 2781 } else if (IsX86 && Name.startswith("avx512.mask.shuf.p")) { 2782 Value *Op0 = CI->getArgOperand(0); 2783 Value *Op1 = CI->getArgOperand(1); 2784 unsigned Imm = cast<ConstantInt>(CI->getArgOperand(2))->getZExtValue(); 2785 unsigned NumElts = cast<FixedVectorType>(CI->getType())->getNumElements(); 2786 2787 unsigned NumLaneElts = 128/CI->getType()->getScalarSizeInBits(); 2788 unsigned HalfLaneElts = NumLaneElts / 2; 2789 2790 SmallVector<int, 16> Idxs(NumElts); 2791 for (unsigned i = 0; i != NumElts; ++i) { 2792 // Base index is the starting element of the lane. 2793 Idxs[i] = i - (i % NumLaneElts); 2794 // If we are half way through the lane switch to the other source. 2795 if ((i % NumLaneElts) >= HalfLaneElts) 2796 Idxs[i] += NumElts; 2797 // Now select the specific element. By adding HalfLaneElts bits from 2798 // the immediate. Wrapping around the immediate every 8-bits. 2799 Idxs[i] += (Imm >> ((i * HalfLaneElts) % 8)) & ((1 << HalfLaneElts) - 1); 2800 } 2801 2802 Rep = Builder.CreateShuffleVector(Op0, Op1, Idxs); 2803 2804 Rep = EmitX86Select(Builder, CI->getArgOperand(4), Rep, 2805 CI->getArgOperand(3)); 2806 } else if (IsX86 && (Name.startswith("avx512.mask.movddup") || 2807 Name.startswith("avx512.mask.movshdup") || 2808 Name.startswith("avx512.mask.movsldup"))) { 2809 Value *Op0 = CI->getArgOperand(0); 2810 unsigned NumElts = cast<FixedVectorType>(CI->getType())->getNumElements(); 2811 unsigned NumLaneElts = 128/CI->getType()->getScalarSizeInBits(); 2812 2813 unsigned Offset = 0; 2814 if (Name.startswith("avx512.mask.movshdup.")) 2815 Offset = 1; 2816 2817 SmallVector<int, 16> Idxs(NumElts); 2818 for (unsigned l = 0; l != NumElts; l += NumLaneElts) 2819 for (unsigned i = 0; i != NumLaneElts; i += 2) { 2820 Idxs[i + l + 0] = i + l + Offset; 2821 Idxs[i + l + 1] = i + l + Offset; 2822 } 2823 2824 Rep = Builder.CreateShuffleVector(Op0, Op0, Idxs); 2825 2826 Rep = EmitX86Select(Builder, CI->getArgOperand(2), Rep, 2827 CI->getArgOperand(1)); 2828 } else if (IsX86 && (Name.startswith("avx512.mask.punpckl") || 2829 Name.startswith("avx512.mask.unpckl."))) { 2830 Value *Op0 = CI->getArgOperand(0); 2831 Value *Op1 = CI->getArgOperand(1); 2832 int NumElts = cast<FixedVectorType>(CI->getType())->getNumElements(); 2833 int NumLaneElts = 128/CI->getType()->getScalarSizeInBits(); 2834 2835 SmallVector<int, 64> Idxs(NumElts); 2836 for (int l = 0; l != NumElts; l += NumLaneElts) 2837 for (int i = 0; i != NumLaneElts; ++i) 2838 Idxs[i + l] = l + (i / 2) + NumElts * (i % 2); 2839 2840 Rep = Builder.CreateShuffleVector(Op0, Op1, Idxs); 2841 2842 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 2843 CI->getArgOperand(2)); 2844 } else if (IsX86 && (Name.startswith("avx512.mask.punpckh") || 2845 Name.startswith("avx512.mask.unpckh."))) { 2846 Value *Op0 = CI->getArgOperand(0); 2847 Value *Op1 = CI->getArgOperand(1); 2848 int NumElts = cast<FixedVectorType>(CI->getType())->getNumElements(); 2849 int NumLaneElts = 128/CI->getType()->getScalarSizeInBits(); 2850 2851 SmallVector<int, 64> Idxs(NumElts); 2852 for (int l = 0; l != NumElts; l += NumLaneElts) 2853 for (int i = 0; i != NumLaneElts; ++i) 2854 Idxs[i + l] = (NumLaneElts / 2) + l + (i / 2) + NumElts * (i % 2); 2855 2856 Rep = Builder.CreateShuffleVector(Op0, Op1, Idxs); 2857 2858 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 2859 CI->getArgOperand(2)); 2860 } else if (IsX86 && (Name.startswith("avx512.mask.and.") || 2861 Name.startswith("avx512.mask.pand."))) { 2862 VectorType *FTy = cast<VectorType>(CI->getType()); 2863 VectorType *ITy = VectorType::getInteger(FTy); 2864 Rep = Builder.CreateAnd(Builder.CreateBitCast(CI->getArgOperand(0), ITy), 2865 Builder.CreateBitCast(CI->getArgOperand(1), ITy)); 2866 Rep = Builder.CreateBitCast(Rep, FTy); 2867 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 2868 CI->getArgOperand(2)); 2869 } else if (IsX86 && (Name.startswith("avx512.mask.andn.") || 2870 Name.startswith("avx512.mask.pandn."))) { 2871 VectorType *FTy = cast<VectorType>(CI->getType()); 2872 VectorType *ITy = VectorType::getInteger(FTy); 2873 Rep = Builder.CreateNot(Builder.CreateBitCast(CI->getArgOperand(0), ITy)); 2874 Rep = Builder.CreateAnd(Rep, 2875 Builder.CreateBitCast(CI->getArgOperand(1), ITy)); 2876 Rep = Builder.CreateBitCast(Rep, FTy); 2877 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 2878 CI->getArgOperand(2)); 2879 } else if (IsX86 && (Name.startswith("avx512.mask.or.") || 2880 Name.startswith("avx512.mask.por."))) { 2881 VectorType *FTy = cast<VectorType>(CI->getType()); 2882 VectorType *ITy = VectorType::getInteger(FTy); 2883 Rep = Builder.CreateOr(Builder.CreateBitCast(CI->getArgOperand(0), ITy), 2884 Builder.CreateBitCast(CI->getArgOperand(1), ITy)); 2885 Rep = Builder.CreateBitCast(Rep, FTy); 2886 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 2887 CI->getArgOperand(2)); 2888 } else if (IsX86 && (Name.startswith("avx512.mask.xor.") || 2889 Name.startswith("avx512.mask.pxor."))) { 2890 VectorType *FTy = cast<VectorType>(CI->getType()); 2891 VectorType *ITy = VectorType::getInteger(FTy); 2892 Rep = Builder.CreateXor(Builder.CreateBitCast(CI->getArgOperand(0), ITy), 2893 Builder.CreateBitCast(CI->getArgOperand(1), ITy)); 2894 Rep = Builder.CreateBitCast(Rep, FTy); 2895 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 2896 CI->getArgOperand(2)); 2897 } else if (IsX86 && Name.startswith("avx512.mask.padd.")) { 2898 Rep = Builder.CreateAdd(CI->getArgOperand(0), CI->getArgOperand(1)); 2899 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 2900 CI->getArgOperand(2)); 2901 } else if (IsX86 && Name.startswith("avx512.mask.psub.")) { 2902 Rep = Builder.CreateSub(CI->getArgOperand(0), CI->getArgOperand(1)); 2903 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 2904 CI->getArgOperand(2)); 2905 } else if (IsX86 && Name.startswith("avx512.mask.pmull.")) { 2906 Rep = Builder.CreateMul(CI->getArgOperand(0), CI->getArgOperand(1)); 2907 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 2908 CI->getArgOperand(2)); 2909 } else if (IsX86 && Name.startswith("avx512.mask.add.p")) { 2910 if (Name.endswith(".512")) { 2911 Intrinsic::ID IID; 2912 if (Name[17] == 's') 2913 IID = Intrinsic::x86_avx512_add_ps_512; 2914 else 2915 IID = Intrinsic::x86_avx512_add_pd_512; 2916 2917 Rep = Builder.CreateCall(Intrinsic::getDeclaration(F->getParent(), IID), 2918 { CI->getArgOperand(0), CI->getArgOperand(1), 2919 CI->getArgOperand(4) }); 2920 } else { 2921 Rep = Builder.CreateFAdd(CI->getArgOperand(0), CI->getArgOperand(1)); 2922 } 2923 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 2924 CI->getArgOperand(2)); 2925 } else if (IsX86 && Name.startswith("avx512.mask.div.p")) { 2926 if (Name.endswith(".512")) { 2927 Intrinsic::ID IID; 2928 if (Name[17] == 's') 2929 IID = Intrinsic::x86_avx512_div_ps_512; 2930 else 2931 IID = Intrinsic::x86_avx512_div_pd_512; 2932 2933 Rep = Builder.CreateCall(Intrinsic::getDeclaration(F->getParent(), IID), 2934 { CI->getArgOperand(0), CI->getArgOperand(1), 2935 CI->getArgOperand(4) }); 2936 } else { 2937 Rep = Builder.CreateFDiv(CI->getArgOperand(0), CI->getArgOperand(1)); 2938 } 2939 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 2940 CI->getArgOperand(2)); 2941 } else if (IsX86 && Name.startswith("avx512.mask.mul.p")) { 2942 if (Name.endswith(".512")) { 2943 Intrinsic::ID IID; 2944 if (Name[17] == 's') 2945 IID = Intrinsic::x86_avx512_mul_ps_512; 2946 else 2947 IID = Intrinsic::x86_avx512_mul_pd_512; 2948 2949 Rep = Builder.CreateCall(Intrinsic::getDeclaration(F->getParent(), IID), 2950 { CI->getArgOperand(0), CI->getArgOperand(1), 2951 CI->getArgOperand(4) }); 2952 } else { 2953 Rep = Builder.CreateFMul(CI->getArgOperand(0), CI->getArgOperand(1)); 2954 } 2955 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 2956 CI->getArgOperand(2)); 2957 } else if (IsX86 && Name.startswith("avx512.mask.sub.p")) { 2958 if (Name.endswith(".512")) { 2959 Intrinsic::ID IID; 2960 if (Name[17] == 's') 2961 IID = Intrinsic::x86_avx512_sub_ps_512; 2962 else 2963 IID = Intrinsic::x86_avx512_sub_pd_512; 2964 2965 Rep = Builder.CreateCall(Intrinsic::getDeclaration(F->getParent(), IID), 2966 { CI->getArgOperand(0), CI->getArgOperand(1), 2967 CI->getArgOperand(4) }); 2968 } else { 2969 Rep = Builder.CreateFSub(CI->getArgOperand(0), CI->getArgOperand(1)); 2970 } 2971 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 2972 CI->getArgOperand(2)); 2973 } else if (IsX86 && (Name.startswith("avx512.mask.max.p") || 2974 Name.startswith("avx512.mask.min.p")) && 2975 Name.drop_front(18) == ".512") { 2976 bool IsDouble = Name[17] == 'd'; 2977 bool IsMin = Name[13] == 'i'; 2978 static const Intrinsic::ID MinMaxTbl[2][2] = { 2979 { Intrinsic::x86_avx512_max_ps_512, Intrinsic::x86_avx512_max_pd_512 }, 2980 { Intrinsic::x86_avx512_min_ps_512, Intrinsic::x86_avx512_min_pd_512 } 2981 }; 2982 Intrinsic::ID IID = MinMaxTbl[IsMin][IsDouble]; 2983 2984 Rep = Builder.CreateCall(Intrinsic::getDeclaration(F->getParent(), IID), 2985 { CI->getArgOperand(0), CI->getArgOperand(1), 2986 CI->getArgOperand(4) }); 2987 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 2988 CI->getArgOperand(2)); 2989 } else if (IsX86 && Name.startswith("avx512.mask.lzcnt.")) { 2990 Rep = Builder.CreateCall(Intrinsic::getDeclaration(F->getParent(), 2991 Intrinsic::ctlz, 2992 CI->getType()), 2993 { CI->getArgOperand(0), Builder.getInt1(false) }); 2994 Rep = EmitX86Select(Builder, CI->getArgOperand(2), Rep, 2995 CI->getArgOperand(1)); 2996 } else if (IsX86 && Name.startswith("avx512.mask.psll")) { 2997 bool IsImmediate = Name[16] == 'i' || 2998 (Name.size() > 18 && Name[18] == 'i'); 2999 bool IsVariable = Name[16] == 'v'; 3000 char Size = Name[16] == '.' ? Name[17] : 3001 Name[17] == '.' ? Name[18] : 3002 Name[18] == '.' ? Name[19] : 3003 Name[20]; 3004 3005 Intrinsic::ID IID; 3006 if (IsVariable && Name[17] != '.') { 3007 if (Size == 'd' && Name[17] == '2') // avx512.mask.psllv2.di 3008 IID = Intrinsic::x86_avx2_psllv_q; 3009 else if (Size == 'd' && Name[17] == '4') // avx512.mask.psllv4.di 3010 IID = Intrinsic::x86_avx2_psllv_q_256; 3011 else if (Size == 's' && Name[17] == '4') // avx512.mask.psllv4.si 3012 IID = Intrinsic::x86_avx2_psllv_d; 3013 else if (Size == 's' && Name[17] == '8') // avx512.mask.psllv8.si 3014 IID = Intrinsic::x86_avx2_psllv_d_256; 3015 else if (Size == 'h' && Name[17] == '8') // avx512.mask.psllv8.hi 3016 IID = Intrinsic::x86_avx512_psllv_w_128; 3017 else if (Size == 'h' && Name[17] == '1') // avx512.mask.psllv16.hi 3018 IID = Intrinsic::x86_avx512_psllv_w_256; 3019 else if (Name[17] == '3' && Name[18] == '2') // avx512.mask.psllv32hi 3020 IID = Intrinsic::x86_avx512_psllv_w_512; 3021 else 3022 llvm_unreachable("Unexpected size"); 3023 } else if (Name.endswith(".128")) { 3024 if (Size == 'd') // avx512.mask.psll.d.128, avx512.mask.psll.di.128 3025 IID = IsImmediate ? Intrinsic::x86_sse2_pslli_d 3026 : Intrinsic::x86_sse2_psll_d; 3027 else if (Size == 'q') // avx512.mask.psll.q.128, avx512.mask.psll.qi.128 3028 IID = IsImmediate ? Intrinsic::x86_sse2_pslli_q 3029 : Intrinsic::x86_sse2_psll_q; 3030 else if (Size == 'w') // avx512.mask.psll.w.128, avx512.mask.psll.wi.128 3031 IID = IsImmediate ? Intrinsic::x86_sse2_pslli_w 3032 : Intrinsic::x86_sse2_psll_w; 3033 else 3034 llvm_unreachable("Unexpected size"); 3035 } else if (Name.endswith(".256")) { 3036 if (Size == 'd') // avx512.mask.psll.d.256, avx512.mask.psll.di.256 3037 IID = IsImmediate ? Intrinsic::x86_avx2_pslli_d 3038 : Intrinsic::x86_avx2_psll_d; 3039 else if (Size == 'q') // avx512.mask.psll.q.256, avx512.mask.psll.qi.256 3040 IID = IsImmediate ? Intrinsic::x86_avx2_pslli_q 3041 : Intrinsic::x86_avx2_psll_q; 3042 else if (Size == 'w') // avx512.mask.psll.w.256, avx512.mask.psll.wi.256 3043 IID = IsImmediate ? Intrinsic::x86_avx2_pslli_w 3044 : Intrinsic::x86_avx2_psll_w; 3045 else 3046 llvm_unreachable("Unexpected size"); 3047 } else { 3048 if (Size == 'd') // psll.di.512, pslli.d, psll.d, psllv.d.512 3049 IID = IsImmediate ? Intrinsic::x86_avx512_pslli_d_512 : 3050 IsVariable ? Intrinsic::x86_avx512_psllv_d_512 : 3051 Intrinsic::x86_avx512_psll_d_512; 3052 else if (Size == 'q') // psll.qi.512, pslli.q, psll.q, psllv.q.512 3053 IID = IsImmediate ? Intrinsic::x86_avx512_pslli_q_512 : 3054 IsVariable ? Intrinsic::x86_avx512_psllv_q_512 : 3055 Intrinsic::x86_avx512_psll_q_512; 3056 else if (Size == 'w') // psll.wi.512, pslli.w, psll.w 3057 IID = IsImmediate ? Intrinsic::x86_avx512_pslli_w_512 3058 : Intrinsic::x86_avx512_psll_w_512; 3059 else 3060 llvm_unreachable("Unexpected size"); 3061 } 3062 3063 Rep = UpgradeX86MaskedShift(Builder, *CI, IID); 3064 } else if (IsX86 && Name.startswith("avx512.mask.psrl")) { 3065 bool IsImmediate = Name[16] == 'i' || 3066 (Name.size() > 18 && Name[18] == 'i'); 3067 bool IsVariable = Name[16] == 'v'; 3068 char Size = Name[16] == '.' ? Name[17] : 3069 Name[17] == '.' ? Name[18] : 3070 Name[18] == '.' ? Name[19] : 3071 Name[20]; 3072 3073 Intrinsic::ID IID; 3074 if (IsVariable && Name[17] != '.') { 3075 if (Size == 'd' && Name[17] == '2') // avx512.mask.psrlv2.di 3076 IID = Intrinsic::x86_avx2_psrlv_q; 3077 else if (Size == 'd' && Name[17] == '4') // avx512.mask.psrlv4.di 3078 IID = Intrinsic::x86_avx2_psrlv_q_256; 3079 else if (Size == 's' && Name[17] == '4') // avx512.mask.psrlv4.si 3080 IID = Intrinsic::x86_avx2_psrlv_d; 3081 else if (Size == 's' && Name[17] == '8') // avx512.mask.psrlv8.si 3082 IID = Intrinsic::x86_avx2_psrlv_d_256; 3083 else if (Size == 'h' && Name[17] == '8') // avx512.mask.psrlv8.hi 3084 IID = Intrinsic::x86_avx512_psrlv_w_128; 3085 else if (Size == 'h' && Name[17] == '1') // avx512.mask.psrlv16.hi 3086 IID = Intrinsic::x86_avx512_psrlv_w_256; 3087 else if (Name[17] == '3' && Name[18] == '2') // avx512.mask.psrlv32hi 3088 IID = Intrinsic::x86_avx512_psrlv_w_512; 3089 else 3090 llvm_unreachable("Unexpected size"); 3091 } else if (Name.endswith(".128")) { 3092 if (Size == 'd') // avx512.mask.psrl.d.128, avx512.mask.psrl.di.128 3093 IID = IsImmediate ? Intrinsic::x86_sse2_psrli_d 3094 : Intrinsic::x86_sse2_psrl_d; 3095 else if (Size == 'q') // avx512.mask.psrl.q.128, avx512.mask.psrl.qi.128 3096 IID = IsImmediate ? Intrinsic::x86_sse2_psrli_q 3097 : Intrinsic::x86_sse2_psrl_q; 3098 else if (Size == 'w') // avx512.mask.psrl.w.128, avx512.mask.psrl.wi.128 3099 IID = IsImmediate ? Intrinsic::x86_sse2_psrli_w 3100 : Intrinsic::x86_sse2_psrl_w; 3101 else 3102 llvm_unreachable("Unexpected size"); 3103 } else if (Name.endswith(".256")) { 3104 if (Size == 'd') // avx512.mask.psrl.d.256, avx512.mask.psrl.di.256 3105 IID = IsImmediate ? Intrinsic::x86_avx2_psrli_d 3106 : Intrinsic::x86_avx2_psrl_d; 3107 else if (Size == 'q') // avx512.mask.psrl.q.256, avx512.mask.psrl.qi.256 3108 IID = IsImmediate ? Intrinsic::x86_avx2_psrli_q 3109 : Intrinsic::x86_avx2_psrl_q; 3110 else if (Size == 'w') // avx512.mask.psrl.w.256, avx512.mask.psrl.wi.256 3111 IID = IsImmediate ? Intrinsic::x86_avx2_psrli_w 3112 : Intrinsic::x86_avx2_psrl_w; 3113 else 3114 llvm_unreachable("Unexpected size"); 3115 } else { 3116 if (Size == 'd') // psrl.di.512, psrli.d, psrl.d, psrl.d.512 3117 IID = IsImmediate ? Intrinsic::x86_avx512_psrli_d_512 : 3118 IsVariable ? Intrinsic::x86_avx512_psrlv_d_512 : 3119 Intrinsic::x86_avx512_psrl_d_512; 3120 else if (Size == 'q') // psrl.qi.512, psrli.q, psrl.q, psrl.q.512 3121 IID = IsImmediate ? Intrinsic::x86_avx512_psrli_q_512 : 3122 IsVariable ? Intrinsic::x86_avx512_psrlv_q_512 : 3123 Intrinsic::x86_avx512_psrl_q_512; 3124 else if (Size == 'w') // psrl.wi.512, psrli.w, psrl.w) 3125 IID = IsImmediate ? Intrinsic::x86_avx512_psrli_w_512 3126 : Intrinsic::x86_avx512_psrl_w_512; 3127 else 3128 llvm_unreachable("Unexpected size"); 3129 } 3130 3131 Rep = UpgradeX86MaskedShift(Builder, *CI, IID); 3132 } else if (IsX86 && Name.startswith("avx512.mask.psra")) { 3133 bool IsImmediate = Name[16] == 'i' || 3134 (Name.size() > 18 && Name[18] == 'i'); 3135 bool IsVariable = Name[16] == 'v'; 3136 char Size = Name[16] == '.' ? Name[17] : 3137 Name[17] == '.' ? Name[18] : 3138 Name[18] == '.' ? Name[19] : 3139 Name[20]; 3140 3141 Intrinsic::ID IID; 3142 if (IsVariable && Name[17] != '.') { 3143 if (Size == 's' && Name[17] == '4') // avx512.mask.psrav4.si 3144 IID = Intrinsic::x86_avx2_psrav_d; 3145 else if (Size == 's' && Name[17] == '8') // avx512.mask.psrav8.si 3146 IID = Intrinsic::x86_avx2_psrav_d_256; 3147 else if (Size == 'h' && Name[17] == '8') // avx512.mask.psrav8.hi 3148 IID = Intrinsic::x86_avx512_psrav_w_128; 3149 else if (Size == 'h' && Name[17] == '1') // avx512.mask.psrav16.hi 3150 IID = Intrinsic::x86_avx512_psrav_w_256; 3151 else if (Name[17] == '3' && Name[18] == '2') // avx512.mask.psrav32hi 3152 IID = Intrinsic::x86_avx512_psrav_w_512; 3153 else 3154 llvm_unreachable("Unexpected size"); 3155 } else if (Name.endswith(".128")) { 3156 if (Size == 'd') // avx512.mask.psra.d.128, avx512.mask.psra.di.128 3157 IID = IsImmediate ? Intrinsic::x86_sse2_psrai_d 3158 : Intrinsic::x86_sse2_psra_d; 3159 else if (Size == 'q') // avx512.mask.psra.q.128, avx512.mask.psra.qi.128 3160 IID = IsImmediate ? Intrinsic::x86_avx512_psrai_q_128 : 3161 IsVariable ? Intrinsic::x86_avx512_psrav_q_128 : 3162 Intrinsic::x86_avx512_psra_q_128; 3163 else if (Size == 'w') // avx512.mask.psra.w.128, avx512.mask.psra.wi.128 3164 IID = IsImmediate ? Intrinsic::x86_sse2_psrai_w 3165 : Intrinsic::x86_sse2_psra_w; 3166 else 3167 llvm_unreachable("Unexpected size"); 3168 } else if (Name.endswith(".256")) { 3169 if (Size == 'd') // avx512.mask.psra.d.256, avx512.mask.psra.di.256 3170 IID = IsImmediate ? Intrinsic::x86_avx2_psrai_d 3171 : Intrinsic::x86_avx2_psra_d; 3172 else if (Size == 'q') // avx512.mask.psra.q.256, avx512.mask.psra.qi.256 3173 IID = IsImmediate ? Intrinsic::x86_avx512_psrai_q_256 : 3174 IsVariable ? Intrinsic::x86_avx512_psrav_q_256 : 3175 Intrinsic::x86_avx512_psra_q_256; 3176 else if (Size == 'w') // avx512.mask.psra.w.256, avx512.mask.psra.wi.256 3177 IID = IsImmediate ? Intrinsic::x86_avx2_psrai_w 3178 : Intrinsic::x86_avx2_psra_w; 3179 else 3180 llvm_unreachable("Unexpected size"); 3181 } else { 3182 if (Size == 'd') // psra.di.512, psrai.d, psra.d, psrav.d.512 3183 IID = IsImmediate ? Intrinsic::x86_avx512_psrai_d_512 : 3184 IsVariable ? Intrinsic::x86_avx512_psrav_d_512 : 3185 Intrinsic::x86_avx512_psra_d_512; 3186 else if (Size == 'q') // psra.qi.512, psrai.q, psra.q 3187 IID = IsImmediate ? Intrinsic::x86_avx512_psrai_q_512 : 3188 IsVariable ? Intrinsic::x86_avx512_psrav_q_512 : 3189 Intrinsic::x86_avx512_psra_q_512; 3190 else if (Size == 'w') // psra.wi.512, psrai.w, psra.w 3191 IID = IsImmediate ? Intrinsic::x86_avx512_psrai_w_512 3192 : Intrinsic::x86_avx512_psra_w_512; 3193 else 3194 llvm_unreachable("Unexpected size"); 3195 } 3196 3197 Rep = UpgradeX86MaskedShift(Builder, *CI, IID); 3198 } else if (IsX86 && Name.startswith("avx512.mask.move.s")) { 3199 Rep = upgradeMaskedMove(Builder, *CI); 3200 } else if (IsX86 && Name.startswith("avx512.cvtmask2")) { 3201 Rep = UpgradeMaskToInt(Builder, *CI); 3202 } else if (IsX86 && Name.endswith(".movntdqa")) { 3203 Module *M = F->getParent(); 3204 MDNode *Node = MDNode::get( 3205 C, ConstantAsMetadata::get(ConstantInt::get(Type::getInt32Ty(C), 1))); 3206 3207 Value *Ptr = CI->getArgOperand(0); 3208 3209 // Convert the type of the pointer to a pointer to the stored type. 3210 Value *BC = Builder.CreateBitCast( 3211 Ptr, PointerType::getUnqual(CI->getType()), "cast"); 3212 LoadInst *LI = Builder.CreateAlignedLoad( 3213 CI->getType(), BC, 3214 Align(CI->getType()->getPrimitiveSizeInBits().getFixedSize() / 8)); 3215 LI->setMetadata(M->getMDKindID("nontemporal"), Node); 3216 Rep = LI; 3217 } else if (IsX86 && (Name.startswith("fma.vfmadd.") || 3218 Name.startswith("fma.vfmsub.") || 3219 Name.startswith("fma.vfnmadd.") || 3220 Name.startswith("fma.vfnmsub."))) { 3221 bool NegMul = Name[6] == 'n'; 3222 bool NegAcc = NegMul ? Name[8] == 's' : Name[7] == 's'; 3223 bool IsScalar = NegMul ? Name[12] == 's' : Name[11] == 's'; 3224 3225 Value *Ops[] = { CI->getArgOperand(0), CI->getArgOperand(1), 3226 CI->getArgOperand(2) }; 3227 3228 if (IsScalar) { 3229 Ops[0] = Builder.CreateExtractElement(Ops[0], (uint64_t)0); 3230 Ops[1] = Builder.CreateExtractElement(Ops[1], (uint64_t)0); 3231 Ops[2] = Builder.CreateExtractElement(Ops[2], (uint64_t)0); 3232 } 3233 3234 if (NegMul && !IsScalar) 3235 Ops[0] = Builder.CreateFNeg(Ops[0]); 3236 if (NegMul && IsScalar) 3237 Ops[1] = Builder.CreateFNeg(Ops[1]); 3238 if (NegAcc) 3239 Ops[2] = Builder.CreateFNeg(Ops[2]); 3240 3241 Rep = Builder.CreateCall(Intrinsic::getDeclaration(CI->getModule(), 3242 Intrinsic::fma, 3243 Ops[0]->getType()), 3244 Ops); 3245 3246 if (IsScalar) 3247 Rep = Builder.CreateInsertElement(CI->getArgOperand(0), Rep, 3248 (uint64_t)0); 3249 } else if (IsX86 && Name.startswith("fma4.vfmadd.s")) { 3250 Value *Ops[] = { CI->getArgOperand(0), CI->getArgOperand(1), 3251 CI->getArgOperand(2) }; 3252 3253 Ops[0] = Builder.CreateExtractElement(Ops[0], (uint64_t)0); 3254 Ops[1] = Builder.CreateExtractElement(Ops[1], (uint64_t)0); 3255 Ops[2] = Builder.CreateExtractElement(Ops[2], (uint64_t)0); 3256 3257 Rep = Builder.CreateCall(Intrinsic::getDeclaration(CI->getModule(), 3258 Intrinsic::fma, 3259 Ops[0]->getType()), 3260 Ops); 3261 3262 Rep = Builder.CreateInsertElement(Constant::getNullValue(CI->getType()), 3263 Rep, (uint64_t)0); 3264 } else if (IsX86 && (Name.startswith("avx512.mask.vfmadd.s") || 3265 Name.startswith("avx512.maskz.vfmadd.s") || 3266 Name.startswith("avx512.mask3.vfmadd.s") || 3267 Name.startswith("avx512.mask3.vfmsub.s") || 3268 Name.startswith("avx512.mask3.vfnmsub.s"))) { 3269 bool IsMask3 = Name[11] == '3'; 3270 bool IsMaskZ = Name[11] == 'z'; 3271 // Drop the "avx512.mask." to make it easier. 3272 Name = Name.drop_front(IsMask3 || IsMaskZ ? 13 : 12); 3273 bool NegMul = Name[2] == 'n'; 3274 bool NegAcc = NegMul ? Name[4] == 's' : Name[3] == 's'; 3275 3276 Value *A = CI->getArgOperand(0); 3277 Value *B = CI->getArgOperand(1); 3278 Value *C = CI->getArgOperand(2); 3279 3280 if (NegMul && (IsMask3 || IsMaskZ)) 3281 A = Builder.CreateFNeg(A); 3282 if (NegMul && !(IsMask3 || IsMaskZ)) 3283 B = Builder.CreateFNeg(B); 3284 if (NegAcc) 3285 C = Builder.CreateFNeg(C); 3286 3287 A = Builder.CreateExtractElement(A, (uint64_t)0); 3288 B = Builder.CreateExtractElement(B, (uint64_t)0); 3289 C = Builder.CreateExtractElement(C, (uint64_t)0); 3290 3291 if (!isa<ConstantInt>(CI->getArgOperand(4)) || 3292 cast<ConstantInt>(CI->getArgOperand(4))->getZExtValue() != 4) { 3293 Value *Ops[] = { A, B, C, CI->getArgOperand(4) }; 3294 3295 Intrinsic::ID IID; 3296 if (Name.back() == 'd') 3297 IID = Intrinsic::x86_avx512_vfmadd_f64; 3298 else 3299 IID = Intrinsic::x86_avx512_vfmadd_f32; 3300 Function *FMA = Intrinsic::getDeclaration(CI->getModule(), IID); 3301 Rep = Builder.CreateCall(FMA, Ops); 3302 } else { 3303 Function *FMA = Intrinsic::getDeclaration(CI->getModule(), 3304 Intrinsic::fma, 3305 A->getType()); 3306 Rep = Builder.CreateCall(FMA, { A, B, C }); 3307 } 3308 3309 Value *PassThru = IsMaskZ ? Constant::getNullValue(Rep->getType()) : 3310 IsMask3 ? C : A; 3311 3312 // For Mask3 with NegAcc, we need to create a new extractelement that 3313 // avoids the negation above. 3314 if (NegAcc && IsMask3) 3315 PassThru = Builder.CreateExtractElement(CI->getArgOperand(2), 3316 (uint64_t)0); 3317 3318 Rep = EmitX86ScalarSelect(Builder, CI->getArgOperand(3), 3319 Rep, PassThru); 3320 Rep = Builder.CreateInsertElement(CI->getArgOperand(IsMask3 ? 2 : 0), 3321 Rep, (uint64_t)0); 3322 } else if (IsX86 && (Name.startswith("avx512.mask.vfmadd.p") || 3323 Name.startswith("avx512.mask.vfnmadd.p") || 3324 Name.startswith("avx512.mask.vfnmsub.p") || 3325 Name.startswith("avx512.mask3.vfmadd.p") || 3326 Name.startswith("avx512.mask3.vfmsub.p") || 3327 Name.startswith("avx512.mask3.vfnmsub.p") || 3328 Name.startswith("avx512.maskz.vfmadd.p"))) { 3329 bool IsMask3 = Name[11] == '3'; 3330 bool IsMaskZ = Name[11] == 'z'; 3331 // Drop the "avx512.mask." to make it easier. 3332 Name = Name.drop_front(IsMask3 || IsMaskZ ? 13 : 12); 3333 bool NegMul = Name[2] == 'n'; 3334 bool NegAcc = NegMul ? Name[4] == 's' : Name[3] == 's'; 3335 3336 Value *A = CI->getArgOperand(0); 3337 Value *B = CI->getArgOperand(1); 3338 Value *C = CI->getArgOperand(2); 3339 3340 if (NegMul && (IsMask3 || IsMaskZ)) 3341 A = Builder.CreateFNeg(A); 3342 if (NegMul && !(IsMask3 || IsMaskZ)) 3343 B = Builder.CreateFNeg(B); 3344 if (NegAcc) 3345 C = Builder.CreateFNeg(C); 3346 3347 if (CI->getNumArgOperands() == 5 && 3348 (!isa<ConstantInt>(CI->getArgOperand(4)) || 3349 cast<ConstantInt>(CI->getArgOperand(4))->getZExtValue() != 4)) { 3350 Intrinsic::ID IID; 3351 // Check the character before ".512" in string. 3352 if (Name[Name.size()-5] == 's') 3353 IID = Intrinsic::x86_avx512_vfmadd_ps_512; 3354 else 3355 IID = Intrinsic::x86_avx512_vfmadd_pd_512; 3356 3357 Rep = Builder.CreateCall(Intrinsic::getDeclaration(F->getParent(), IID), 3358 { A, B, C, CI->getArgOperand(4) }); 3359 } else { 3360 Function *FMA = Intrinsic::getDeclaration(CI->getModule(), 3361 Intrinsic::fma, 3362 A->getType()); 3363 Rep = Builder.CreateCall(FMA, { A, B, C }); 3364 } 3365 3366 Value *PassThru = IsMaskZ ? llvm::Constant::getNullValue(CI->getType()) : 3367 IsMask3 ? CI->getArgOperand(2) : 3368 CI->getArgOperand(0); 3369 3370 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, PassThru); 3371 } else if (IsX86 && Name.startswith("fma.vfmsubadd.p")) { 3372 unsigned VecWidth = CI->getType()->getPrimitiveSizeInBits(); 3373 unsigned EltWidth = CI->getType()->getScalarSizeInBits(); 3374 Intrinsic::ID IID; 3375 if (VecWidth == 128 && EltWidth == 32) 3376 IID = Intrinsic::x86_fma_vfmaddsub_ps; 3377 else if (VecWidth == 256 && EltWidth == 32) 3378 IID = Intrinsic::x86_fma_vfmaddsub_ps_256; 3379 else if (VecWidth == 128 && EltWidth == 64) 3380 IID = Intrinsic::x86_fma_vfmaddsub_pd; 3381 else if (VecWidth == 256 && EltWidth == 64) 3382 IID = Intrinsic::x86_fma_vfmaddsub_pd_256; 3383 else 3384 llvm_unreachable("Unexpected intrinsic"); 3385 3386 Value *Ops[] = { CI->getArgOperand(0), CI->getArgOperand(1), 3387 CI->getArgOperand(2) }; 3388 Ops[2] = Builder.CreateFNeg(Ops[2]); 3389 Rep = Builder.CreateCall(Intrinsic::getDeclaration(F->getParent(), IID), 3390 Ops); 3391 } else if (IsX86 && (Name.startswith("avx512.mask.vfmaddsub.p") || 3392 Name.startswith("avx512.mask3.vfmaddsub.p") || 3393 Name.startswith("avx512.maskz.vfmaddsub.p") || 3394 Name.startswith("avx512.mask3.vfmsubadd.p"))) { 3395 bool IsMask3 = Name[11] == '3'; 3396 bool IsMaskZ = Name[11] == 'z'; 3397 // Drop the "avx512.mask." to make it easier. 3398 Name = Name.drop_front(IsMask3 || IsMaskZ ? 13 : 12); 3399 bool IsSubAdd = Name[3] == 's'; 3400 if (CI->getNumArgOperands() == 5) { 3401 Intrinsic::ID IID; 3402 // Check the character before ".512" in string. 3403 if (Name[Name.size()-5] == 's') 3404 IID = Intrinsic::x86_avx512_vfmaddsub_ps_512; 3405 else 3406 IID = Intrinsic::x86_avx512_vfmaddsub_pd_512; 3407 3408 Value *Ops[] = { CI->getArgOperand(0), CI->getArgOperand(1), 3409 CI->getArgOperand(2), CI->getArgOperand(4) }; 3410 if (IsSubAdd) 3411 Ops[2] = Builder.CreateFNeg(Ops[2]); 3412 3413 Rep = Builder.CreateCall(Intrinsic::getDeclaration(F->getParent(), IID), 3414 Ops); 3415 } else { 3416 int NumElts = cast<FixedVectorType>(CI->getType())->getNumElements(); 3417 3418 Value *Ops[] = { CI->getArgOperand(0), CI->getArgOperand(1), 3419 CI->getArgOperand(2) }; 3420 3421 Function *FMA = Intrinsic::getDeclaration(CI->getModule(), Intrinsic::fma, 3422 Ops[0]->getType()); 3423 Value *Odd = Builder.CreateCall(FMA, Ops); 3424 Ops[2] = Builder.CreateFNeg(Ops[2]); 3425 Value *Even = Builder.CreateCall(FMA, Ops); 3426 3427 if (IsSubAdd) 3428 std::swap(Even, Odd); 3429 3430 SmallVector<int, 32> Idxs(NumElts); 3431 for (int i = 0; i != NumElts; ++i) 3432 Idxs[i] = i + (i % 2) * NumElts; 3433 3434 Rep = Builder.CreateShuffleVector(Even, Odd, Idxs); 3435 } 3436 3437 Value *PassThru = IsMaskZ ? llvm::Constant::getNullValue(CI->getType()) : 3438 IsMask3 ? CI->getArgOperand(2) : 3439 CI->getArgOperand(0); 3440 3441 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, PassThru); 3442 } else if (IsX86 && (Name.startswith("avx512.mask.pternlog.") || 3443 Name.startswith("avx512.maskz.pternlog."))) { 3444 bool ZeroMask = Name[11] == 'z'; 3445 unsigned VecWidth = CI->getType()->getPrimitiveSizeInBits(); 3446 unsigned EltWidth = CI->getType()->getScalarSizeInBits(); 3447 Intrinsic::ID IID; 3448 if (VecWidth == 128 && EltWidth == 32) 3449 IID = Intrinsic::x86_avx512_pternlog_d_128; 3450 else if (VecWidth == 256 && EltWidth == 32) 3451 IID = Intrinsic::x86_avx512_pternlog_d_256; 3452 else if (VecWidth == 512 && EltWidth == 32) 3453 IID = Intrinsic::x86_avx512_pternlog_d_512; 3454 else if (VecWidth == 128 && EltWidth == 64) 3455 IID = Intrinsic::x86_avx512_pternlog_q_128; 3456 else if (VecWidth == 256 && EltWidth == 64) 3457 IID = Intrinsic::x86_avx512_pternlog_q_256; 3458 else if (VecWidth == 512 && EltWidth == 64) 3459 IID = Intrinsic::x86_avx512_pternlog_q_512; 3460 else 3461 llvm_unreachable("Unexpected intrinsic"); 3462 3463 Value *Args[] = { CI->getArgOperand(0) , CI->getArgOperand(1), 3464 CI->getArgOperand(2), CI->getArgOperand(3) }; 3465 Rep = Builder.CreateCall(Intrinsic::getDeclaration(CI->getModule(), IID), 3466 Args); 3467 Value *PassThru = ZeroMask ? ConstantAggregateZero::get(CI->getType()) 3468 : CI->getArgOperand(0); 3469 Rep = EmitX86Select(Builder, CI->getArgOperand(4), Rep, PassThru); 3470 } else if (IsX86 && (Name.startswith("avx512.mask.vpmadd52") || 3471 Name.startswith("avx512.maskz.vpmadd52"))) { 3472 bool ZeroMask = Name[11] == 'z'; 3473 bool High = Name[20] == 'h' || Name[21] == 'h'; 3474 unsigned VecWidth = CI->getType()->getPrimitiveSizeInBits(); 3475 Intrinsic::ID IID; 3476 if (VecWidth == 128 && !High) 3477 IID = Intrinsic::x86_avx512_vpmadd52l_uq_128; 3478 else if (VecWidth == 256 && !High) 3479 IID = Intrinsic::x86_avx512_vpmadd52l_uq_256; 3480 else if (VecWidth == 512 && !High) 3481 IID = Intrinsic::x86_avx512_vpmadd52l_uq_512; 3482 else if (VecWidth == 128 && High) 3483 IID = Intrinsic::x86_avx512_vpmadd52h_uq_128; 3484 else if (VecWidth == 256 && High) 3485 IID = Intrinsic::x86_avx512_vpmadd52h_uq_256; 3486 else if (VecWidth == 512 && High) 3487 IID = Intrinsic::x86_avx512_vpmadd52h_uq_512; 3488 else 3489 llvm_unreachable("Unexpected intrinsic"); 3490 3491 Value *Args[] = { CI->getArgOperand(0) , CI->getArgOperand(1), 3492 CI->getArgOperand(2) }; 3493 Rep = Builder.CreateCall(Intrinsic::getDeclaration(CI->getModule(), IID), 3494 Args); 3495 Value *PassThru = ZeroMask ? ConstantAggregateZero::get(CI->getType()) 3496 : CI->getArgOperand(0); 3497 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, PassThru); 3498 } else if (IsX86 && (Name.startswith("avx512.mask.vpermi2var.") || 3499 Name.startswith("avx512.mask.vpermt2var.") || 3500 Name.startswith("avx512.maskz.vpermt2var."))) { 3501 bool ZeroMask = Name[11] == 'z'; 3502 bool IndexForm = Name[17] == 'i'; 3503 Rep = UpgradeX86VPERMT2Intrinsics(Builder, *CI, ZeroMask, IndexForm); 3504 } else if (IsX86 && (Name.startswith("avx512.mask.vpdpbusd.") || 3505 Name.startswith("avx512.maskz.vpdpbusd.") || 3506 Name.startswith("avx512.mask.vpdpbusds.") || 3507 Name.startswith("avx512.maskz.vpdpbusds."))) { 3508 bool ZeroMask = Name[11] == 'z'; 3509 bool IsSaturating = Name[ZeroMask ? 21 : 20] == 's'; 3510 unsigned VecWidth = CI->getType()->getPrimitiveSizeInBits(); 3511 Intrinsic::ID IID; 3512 if (VecWidth == 128 && !IsSaturating) 3513 IID = Intrinsic::x86_avx512_vpdpbusd_128; 3514 else if (VecWidth == 256 && !IsSaturating) 3515 IID = Intrinsic::x86_avx512_vpdpbusd_256; 3516 else if (VecWidth == 512 && !IsSaturating) 3517 IID = Intrinsic::x86_avx512_vpdpbusd_512; 3518 else if (VecWidth == 128 && IsSaturating) 3519 IID = Intrinsic::x86_avx512_vpdpbusds_128; 3520 else if (VecWidth == 256 && IsSaturating) 3521 IID = Intrinsic::x86_avx512_vpdpbusds_256; 3522 else if (VecWidth == 512 && IsSaturating) 3523 IID = Intrinsic::x86_avx512_vpdpbusds_512; 3524 else 3525 llvm_unreachable("Unexpected intrinsic"); 3526 3527 Value *Args[] = { CI->getArgOperand(0), CI->getArgOperand(1), 3528 CI->getArgOperand(2) }; 3529 Rep = Builder.CreateCall(Intrinsic::getDeclaration(CI->getModule(), IID), 3530 Args); 3531 Value *PassThru = ZeroMask ? ConstantAggregateZero::get(CI->getType()) 3532 : CI->getArgOperand(0); 3533 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, PassThru); 3534 } else if (IsX86 && (Name.startswith("avx512.mask.vpdpwssd.") || 3535 Name.startswith("avx512.maskz.vpdpwssd.") || 3536 Name.startswith("avx512.mask.vpdpwssds.") || 3537 Name.startswith("avx512.maskz.vpdpwssds."))) { 3538 bool ZeroMask = Name[11] == 'z'; 3539 bool IsSaturating = Name[ZeroMask ? 21 : 20] == 's'; 3540 unsigned VecWidth = CI->getType()->getPrimitiveSizeInBits(); 3541 Intrinsic::ID IID; 3542 if (VecWidth == 128 && !IsSaturating) 3543 IID = Intrinsic::x86_avx512_vpdpwssd_128; 3544 else if (VecWidth == 256 && !IsSaturating) 3545 IID = Intrinsic::x86_avx512_vpdpwssd_256; 3546 else if (VecWidth == 512 && !IsSaturating) 3547 IID = Intrinsic::x86_avx512_vpdpwssd_512; 3548 else if (VecWidth == 128 && IsSaturating) 3549 IID = Intrinsic::x86_avx512_vpdpwssds_128; 3550 else if (VecWidth == 256 && IsSaturating) 3551 IID = Intrinsic::x86_avx512_vpdpwssds_256; 3552 else if (VecWidth == 512 && IsSaturating) 3553 IID = Intrinsic::x86_avx512_vpdpwssds_512; 3554 else 3555 llvm_unreachable("Unexpected intrinsic"); 3556 3557 Value *Args[] = { CI->getArgOperand(0), CI->getArgOperand(1), 3558 CI->getArgOperand(2) }; 3559 Rep = Builder.CreateCall(Intrinsic::getDeclaration(CI->getModule(), IID), 3560 Args); 3561 Value *PassThru = ZeroMask ? ConstantAggregateZero::get(CI->getType()) 3562 : CI->getArgOperand(0); 3563 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, PassThru); 3564 } else if (IsX86 && (Name == "addcarryx.u32" || Name == "addcarryx.u64" || 3565 Name == "addcarry.u32" || Name == "addcarry.u64" || 3566 Name == "subborrow.u32" || Name == "subborrow.u64")) { 3567 Intrinsic::ID IID; 3568 if (Name[0] == 'a' && Name.back() == '2') 3569 IID = Intrinsic::x86_addcarry_32; 3570 else if (Name[0] == 'a' && Name.back() == '4') 3571 IID = Intrinsic::x86_addcarry_64; 3572 else if (Name[0] == 's' && Name.back() == '2') 3573 IID = Intrinsic::x86_subborrow_32; 3574 else if (Name[0] == 's' && Name.back() == '4') 3575 IID = Intrinsic::x86_subborrow_64; 3576 else 3577 llvm_unreachable("Unexpected intrinsic"); 3578 3579 // Make a call with 3 operands. 3580 Value *Args[] = { CI->getArgOperand(0), CI->getArgOperand(1), 3581 CI->getArgOperand(2)}; 3582 Value *NewCall = Builder.CreateCall( 3583 Intrinsic::getDeclaration(CI->getModule(), IID), 3584 Args); 3585 3586 // Extract the second result and store it. 3587 Value *Data = Builder.CreateExtractValue(NewCall, 1); 3588 // Cast the pointer to the right type. 3589 Value *Ptr = Builder.CreateBitCast(CI->getArgOperand(3), 3590 llvm::PointerType::getUnqual(Data->getType())); 3591 Builder.CreateAlignedStore(Data, Ptr, Align(1)); 3592 // Replace the original call result with the first result of the new call. 3593 Value *CF = Builder.CreateExtractValue(NewCall, 0); 3594 3595 CI->replaceAllUsesWith(CF); 3596 Rep = nullptr; 3597 } else if (IsX86 && Name.startswith("avx512.mask.") && 3598 upgradeAVX512MaskToSelect(Name, Builder, *CI, Rep)) { 3599 // Rep will be updated by the call in the condition. 3600 } else if (IsNVVM && (Name == "abs.i" || Name == "abs.ll")) { 3601 Value *Arg = CI->getArgOperand(0); 3602 Value *Neg = Builder.CreateNeg(Arg, "neg"); 3603 Value *Cmp = Builder.CreateICmpSGE( 3604 Arg, llvm::Constant::getNullValue(Arg->getType()), "abs.cond"); 3605 Rep = Builder.CreateSelect(Cmp, Arg, Neg, "abs"); 3606 } else if (IsNVVM && (Name.startswith("atomic.load.add.f32.p") || 3607 Name.startswith("atomic.load.add.f64.p"))) { 3608 Value *Ptr = CI->getArgOperand(0); 3609 Value *Val = CI->getArgOperand(1); 3610 Rep = Builder.CreateAtomicRMW(AtomicRMWInst::FAdd, Ptr, Val, MaybeAlign(), 3611 AtomicOrdering::SequentiallyConsistent); 3612 } else if (IsNVVM && (Name == "max.i" || Name == "max.ll" || 3613 Name == "max.ui" || Name == "max.ull")) { 3614 Value *Arg0 = CI->getArgOperand(0); 3615 Value *Arg1 = CI->getArgOperand(1); 3616 Value *Cmp = Name.endswith(".ui") || Name.endswith(".ull") 3617 ? Builder.CreateICmpUGE(Arg0, Arg1, "max.cond") 3618 : Builder.CreateICmpSGE(Arg0, Arg1, "max.cond"); 3619 Rep = Builder.CreateSelect(Cmp, Arg0, Arg1, "max"); 3620 } else if (IsNVVM && (Name == "min.i" || Name == "min.ll" || 3621 Name == "min.ui" || Name == "min.ull")) { 3622 Value *Arg0 = CI->getArgOperand(0); 3623 Value *Arg1 = CI->getArgOperand(1); 3624 Value *Cmp = Name.endswith(".ui") || Name.endswith(".ull") 3625 ? Builder.CreateICmpULE(Arg0, Arg1, "min.cond") 3626 : Builder.CreateICmpSLE(Arg0, Arg1, "min.cond"); 3627 Rep = Builder.CreateSelect(Cmp, Arg0, Arg1, "min"); 3628 } else if (IsNVVM && Name == "clz.ll") { 3629 // llvm.nvvm.clz.ll returns an i32, but llvm.ctlz.i64 and returns an i64. 3630 Value *Arg = CI->getArgOperand(0); 3631 Value *Ctlz = Builder.CreateCall( 3632 Intrinsic::getDeclaration(F->getParent(), Intrinsic::ctlz, 3633 {Arg->getType()}), 3634 {Arg, Builder.getFalse()}, "ctlz"); 3635 Rep = Builder.CreateTrunc(Ctlz, Builder.getInt32Ty(), "ctlz.trunc"); 3636 } else if (IsNVVM && Name == "popc.ll") { 3637 // llvm.nvvm.popc.ll returns an i32, but llvm.ctpop.i64 and returns an 3638 // i64. 3639 Value *Arg = CI->getArgOperand(0); 3640 Value *Popc = Builder.CreateCall( 3641 Intrinsic::getDeclaration(F->getParent(), Intrinsic::ctpop, 3642 {Arg->getType()}), 3643 Arg, "ctpop"); 3644 Rep = Builder.CreateTrunc(Popc, Builder.getInt32Ty(), "ctpop.trunc"); 3645 } else if (IsNVVM && Name == "h2f") { 3646 Rep = Builder.CreateCall(Intrinsic::getDeclaration( 3647 F->getParent(), Intrinsic::convert_from_fp16, 3648 {Builder.getFloatTy()}), 3649 CI->getArgOperand(0), "h2f"); 3650 } else { 3651 llvm_unreachable("Unknown function for CallInst upgrade."); 3652 } 3653 3654 if (Rep) 3655 CI->replaceAllUsesWith(Rep); 3656 CI->eraseFromParent(); 3657 return; 3658 } 3659 3660 const auto &DefaultCase = [&NewFn, &CI]() -> void { 3661 // Handle generic mangling change, but nothing else 3662 assert( 3663 (CI->getCalledFunction()->getName() != NewFn->getName()) && 3664 "Unknown function for CallInst upgrade and isn't just a name change"); 3665 CI->setCalledFunction(NewFn); 3666 }; 3667 CallInst *NewCall = nullptr; 3668 switch (NewFn->getIntrinsicID()) { 3669 default: { 3670 DefaultCase(); 3671 return; 3672 } 3673 case Intrinsic::arm_neon_vld1: 3674 case Intrinsic::arm_neon_vld2: 3675 case Intrinsic::arm_neon_vld3: 3676 case Intrinsic::arm_neon_vld4: 3677 case Intrinsic::arm_neon_vld2lane: 3678 case Intrinsic::arm_neon_vld3lane: 3679 case Intrinsic::arm_neon_vld4lane: 3680 case Intrinsic::arm_neon_vst1: 3681 case Intrinsic::arm_neon_vst2: 3682 case Intrinsic::arm_neon_vst3: 3683 case Intrinsic::arm_neon_vst4: 3684 case Intrinsic::arm_neon_vst2lane: 3685 case Intrinsic::arm_neon_vst3lane: 3686 case Intrinsic::arm_neon_vst4lane: { 3687 SmallVector<Value *, 4> Args(CI->args()); 3688 NewCall = Builder.CreateCall(NewFn, Args); 3689 break; 3690 } 3691 3692 case Intrinsic::arm_neon_bfdot: 3693 case Intrinsic::arm_neon_bfmmla: 3694 case Intrinsic::arm_neon_bfmlalb: 3695 case Intrinsic::arm_neon_bfmlalt: 3696 case Intrinsic::aarch64_neon_bfdot: 3697 case Intrinsic::aarch64_neon_bfmmla: 3698 case Intrinsic::aarch64_neon_bfmlalb: 3699 case Intrinsic::aarch64_neon_bfmlalt: { 3700 SmallVector<Value *, 3> Args; 3701 assert(CI->getNumArgOperands() == 3 && 3702 "Mismatch between function args and call args"); 3703 size_t OperandWidth = 3704 CI->getArgOperand(1)->getType()->getPrimitiveSizeInBits(); 3705 assert((OperandWidth == 64 || OperandWidth == 128) && 3706 "Unexpected operand width"); 3707 Type *NewTy = FixedVectorType::get(Type::getBFloatTy(C), OperandWidth / 16); 3708 auto Iter = CI->arg_operands().begin(); 3709 Args.push_back(*Iter++); 3710 Args.push_back(Builder.CreateBitCast(*Iter++, NewTy)); 3711 Args.push_back(Builder.CreateBitCast(*Iter++, NewTy)); 3712 NewCall = Builder.CreateCall(NewFn, Args); 3713 break; 3714 } 3715 3716 case Intrinsic::bitreverse: 3717 NewCall = Builder.CreateCall(NewFn, {CI->getArgOperand(0)}); 3718 break; 3719 3720 case Intrinsic::ctlz: 3721 case Intrinsic::cttz: 3722 assert(CI->getNumArgOperands() == 1 && 3723 "Mismatch between function args and call args"); 3724 NewCall = 3725 Builder.CreateCall(NewFn, {CI->getArgOperand(0), Builder.getFalse()}); 3726 break; 3727 3728 case Intrinsic::objectsize: { 3729 Value *NullIsUnknownSize = CI->getNumArgOperands() == 2 3730 ? Builder.getFalse() 3731 : CI->getArgOperand(2); 3732 Value *Dynamic = 3733 CI->getNumArgOperands() < 4 ? Builder.getFalse() : CI->getArgOperand(3); 3734 NewCall = Builder.CreateCall( 3735 NewFn, {CI->getArgOperand(0), CI->getArgOperand(1), NullIsUnknownSize, Dynamic}); 3736 break; 3737 } 3738 3739 case Intrinsic::ctpop: 3740 NewCall = Builder.CreateCall(NewFn, {CI->getArgOperand(0)}); 3741 break; 3742 3743 case Intrinsic::convert_from_fp16: 3744 NewCall = Builder.CreateCall(NewFn, {CI->getArgOperand(0)}); 3745 break; 3746 3747 case Intrinsic::dbg_value: 3748 // Upgrade from the old version that had an extra offset argument. 3749 assert(CI->getNumArgOperands() == 4); 3750 // Drop nonzero offsets instead of attempting to upgrade them. 3751 if (auto *Offset = dyn_cast_or_null<Constant>(CI->getArgOperand(1))) 3752 if (Offset->isZeroValue()) { 3753 NewCall = Builder.CreateCall( 3754 NewFn, 3755 {CI->getArgOperand(0), CI->getArgOperand(2), CI->getArgOperand(3)}); 3756 break; 3757 } 3758 CI->eraseFromParent(); 3759 return; 3760 3761 case Intrinsic::ptr_annotation: 3762 // Upgrade from versions that lacked the annotation attribute argument. 3763 assert(CI->getNumArgOperands() == 4 && 3764 "Before LLVM 12.0 this intrinsic took four arguments"); 3765 // Create a new call with an added null annotation attribute argument. 3766 NewCall = Builder.CreateCall( 3767 NewFn, 3768 {CI->getArgOperand(0), CI->getArgOperand(1), CI->getArgOperand(2), 3769 CI->getArgOperand(3), Constant::getNullValue(Builder.getInt8PtrTy())}); 3770 NewCall->takeName(CI); 3771 CI->replaceAllUsesWith(NewCall); 3772 CI->eraseFromParent(); 3773 return; 3774 3775 case Intrinsic::var_annotation: 3776 // Upgrade from versions that lacked the annotation attribute argument. 3777 assert(CI->getNumArgOperands() == 4 && 3778 "Before LLVM 12.0 this intrinsic took four arguments"); 3779 // Create a new call with an added null annotation attribute argument. 3780 NewCall = Builder.CreateCall( 3781 NewFn, 3782 {CI->getArgOperand(0), CI->getArgOperand(1), CI->getArgOperand(2), 3783 CI->getArgOperand(3), Constant::getNullValue(Builder.getInt8PtrTy())}); 3784 CI->eraseFromParent(); 3785 return; 3786 3787 case Intrinsic::x86_xop_vfrcz_ss: 3788 case Intrinsic::x86_xop_vfrcz_sd: 3789 NewCall = Builder.CreateCall(NewFn, {CI->getArgOperand(1)}); 3790 break; 3791 3792 case Intrinsic::x86_xop_vpermil2pd: 3793 case Intrinsic::x86_xop_vpermil2ps: 3794 case Intrinsic::x86_xop_vpermil2pd_256: 3795 case Intrinsic::x86_xop_vpermil2ps_256: { 3796 SmallVector<Value *, 4> Args(CI->args()); 3797 VectorType *FltIdxTy = cast<VectorType>(Args[2]->getType()); 3798 VectorType *IntIdxTy = VectorType::getInteger(FltIdxTy); 3799 Args[2] = Builder.CreateBitCast(Args[2], IntIdxTy); 3800 NewCall = Builder.CreateCall(NewFn, Args); 3801 break; 3802 } 3803 3804 case Intrinsic::x86_sse41_ptestc: 3805 case Intrinsic::x86_sse41_ptestz: 3806 case Intrinsic::x86_sse41_ptestnzc: { 3807 // The arguments for these intrinsics used to be v4f32, and changed 3808 // to v2i64. This is purely a nop, since those are bitwise intrinsics. 3809 // So, the only thing required is a bitcast for both arguments. 3810 // First, check the arguments have the old type. 3811 Value *Arg0 = CI->getArgOperand(0); 3812 if (Arg0->getType() != FixedVectorType::get(Type::getFloatTy(C), 4)) 3813 return; 3814 3815 // Old intrinsic, add bitcasts 3816 Value *Arg1 = CI->getArgOperand(1); 3817 3818 auto *NewVecTy = FixedVectorType::get(Type::getInt64Ty(C), 2); 3819 3820 Value *BC0 = Builder.CreateBitCast(Arg0, NewVecTy, "cast"); 3821 Value *BC1 = Builder.CreateBitCast(Arg1, NewVecTy, "cast"); 3822 3823 NewCall = Builder.CreateCall(NewFn, {BC0, BC1}); 3824 break; 3825 } 3826 3827 case Intrinsic::x86_rdtscp: { 3828 // This used to take 1 arguments. If we have no arguments, it is already 3829 // upgraded. 3830 if (CI->getNumOperands() == 0) 3831 return; 3832 3833 NewCall = Builder.CreateCall(NewFn); 3834 // Extract the second result and store it. 3835 Value *Data = Builder.CreateExtractValue(NewCall, 1); 3836 // Cast the pointer to the right type. 3837 Value *Ptr = Builder.CreateBitCast(CI->getArgOperand(0), 3838 llvm::PointerType::getUnqual(Data->getType())); 3839 Builder.CreateAlignedStore(Data, Ptr, Align(1)); 3840 // Replace the original call result with the first result of the new call. 3841 Value *TSC = Builder.CreateExtractValue(NewCall, 0); 3842 3843 NewCall->takeName(CI); 3844 CI->replaceAllUsesWith(TSC); 3845 CI->eraseFromParent(); 3846 return; 3847 } 3848 3849 case Intrinsic::x86_sse41_insertps: 3850 case Intrinsic::x86_sse41_dppd: 3851 case Intrinsic::x86_sse41_dpps: 3852 case Intrinsic::x86_sse41_mpsadbw: 3853 case Intrinsic::x86_avx_dp_ps_256: 3854 case Intrinsic::x86_avx2_mpsadbw: { 3855 // Need to truncate the last argument from i32 to i8 -- this argument models 3856 // an inherently 8-bit immediate operand to these x86 instructions. 3857 SmallVector<Value *, 4> Args(CI->args()); 3858 3859 // Replace the last argument with a trunc. 3860 Args.back() = Builder.CreateTrunc(Args.back(), Type::getInt8Ty(C), "trunc"); 3861 NewCall = Builder.CreateCall(NewFn, Args); 3862 break; 3863 } 3864 3865 case Intrinsic::x86_avx512_mask_cmp_pd_128: 3866 case Intrinsic::x86_avx512_mask_cmp_pd_256: 3867 case Intrinsic::x86_avx512_mask_cmp_pd_512: 3868 case Intrinsic::x86_avx512_mask_cmp_ps_128: 3869 case Intrinsic::x86_avx512_mask_cmp_ps_256: 3870 case Intrinsic::x86_avx512_mask_cmp_ps_512: { 3871 SmallVector<Value *, 4> Args(CI->args()); 3872 unsigned NumElts = 3873 cast<FixedVectorType>(Args[0]->getType())->getNumElements(); 3874 Args[3] = getX86MaskVec(Builder, Args[3], NumElts); 3875 3876 NewCall = Builder.CreateCall(NewFn, Args); 3877 Value *Res = ApplyX86MaskOn1BitsVec(Builder, NewCall, nullptr); 3878 3879 NewCall->takeName(CI); 3880 CI->replaceAllUsesWith(Res); 3881 CI->eraseFromParent(); 3882 return; 3883 } 3884 3885 case Intrinsic::thread_pointer: { 3886 NewCall = Builder.CreateCall(NewFn, {}); 3887 break; 3888 } 3889 3890 case Intrinsic::invariant_start: 3891 case Intrinsic::invariant_end: { 3892 SmallVector<Value *, 4> Args(CI->args()); 3893 NewCall = Builder.CreateCall(NewFn, Args); 3894 break; 3895 } 3896 case Intrinsic::masked_load: 3897 case Intrinsic::masked_store: 3898 case Intrinsic::masked_gather: 3899 case Intrinsic::masked_scatter: { 3900 SmallVector<Value *, 4> Args(CI->args()); 3901 NewCall = Builder.CreateCall(NewFn, Args); 3902 NewCall->copyMetadata(*CI); 3903 break; 3904 } 3905 3906 case Intrinsic::memcpy: 3907 case Intrinsic::memmove: 3908 case Intrinsic::memset: { 3909 // We have to make sure that the call signature is what we're expecting. 3910 // We only want to change the old signatures by removing the alignment arg: 3911 // @llvm.mem[cpy|move]...(i8*, i8*, i[32|i64], i32, i1) 3912 // -> @llvm.mem[cpy|move]...(i8*, i8*, i[32|i64], i1) 3913 // @llvm.memset...(i8*, i8, i[32|64], i32, i1) 3914 // -> @llvm.memset...(i8*, i8, i[32|64], i1) 3915 // Note: i8*'s in the above can be any pointer type 3916 if (CI->getNumArgOperands() != 5) { 3917 DefaultCase(); 3918 return; 3919 } 3920 // Remove alignment argument (3), and add alignment attributes to the 3921 // dest/src pointers. 3922 Value *Args[4] = {CI->getArgOperand(0), CI->getArgOperand(1), 3923 CI->getArgOperand(2), CI->getArgOperand(4)}; 3924 NewCall = Builder.CreateCall(NewFn, Args); 3925 auto *MemCI = cast<MemIntrinsic>(NewCall); 3926 // All mem intrinsics support dest alignment. 3927 const ConstantInt *Align = cast<ConstantInt>(CI->getArgOperand(3)); 3928 MemCI->setDestAlignment(Align->getMaybeAlignValue()); 3929 // Memcpy/Memmove also support source alignment. 3930 if (auto *MTI = dyn_cast<MemTransferInst>(MemCI)) 3931 MTI->setSourceAlignment(Align->getMaybeAlignValue()); 3932 break; 3933 } 3934 } 3935 assert(NewCall && "Should have either set this variable or returned through " 3936 "the default case"); 3937 NewCall->takeName(CI); 3938 CI->replaceAllUsesWith(NewCall); 3939 CI->eraseFromParent(); 3940 } 3941 3942 void llvm::UpgradeCallsToIntrinsic(Function *F) { 3943 assert(F && "Illegal attempt to upgrade a non-existent intrinsic."); 3944 3945 // Check if this function should be upgraded and get the replacement function 3946 // if there is one. 3947 Function *NewFn; 3948 if (UpgradeIntrinsicFunction(F, NewFn)) { 3949 // Replace all users of the old function with the new function or new 3950 // instructions. This is not a range loop because the call is deleted. 3951 for (User *U : make_early_inc_range(F->users())) 3952 if (CallInst *CI = dyn_cast<CallInst>(U)) 3953 UpgradeIntrinsicCall(CI, NewFn); 3954 3955 // Remove old function, no longer used, from the module. 3956 F->eraseFromParent(); 3957 } 3958 } 3959 3960 MDNode *llvm::UpgradeTBAANode(MDNode &MD) { 3961 // Check if the tag uses struct-path aware TBAA format. 3962 if (isa<MDNode>(MD.getOperand(0)) && MD.getNumOperands() >= 3) 3963 return &MD; 3964 3965 auto &Context = MD.getContext(); 3966 if (MD.getNumOperands() == 3) { 3967 Metadata *Elts[] = {MD.getOperand(0), MD.getOperand(1)}; 3968 MDNode *ScalarType = MDNode::get(Context, Elts); 3969 // Create a MDNode <ScalarType, ScalarType, offset 0, const> 3970 Metadata *Elts2[] = {ScalarType, ScalarType, 3971 ConstantAsMetadata::get( 3972 Constant::getNullValue(Type::getInt64Ty(Context))), 3973 MD.getOperand(2)}; 3974 return MDNode::get(Context, Elts2); 3975 } 3976 // Create a MDNode <MD, MD, offset 0> 3977 Metadata *Elts[] = {&MD, &MD, ConstantAsMetadata::get(Constant::getNullValue( 3978 Type::getInt64Ty(Context)))}; 3979 return MDNode::get(Context, Elts); 3980 } 3981 3982 Instruction *llvm::UpgradeBitCastInst(unsigned Opc, Value *V, Type *DestTy, 3983 Instruction *&Temp) { 3984 if (Opc != Instruction::BitCast) 3985 return nullptr; 3986 3987 Temp = nullptr; 3988 Type *SrcTy = V->getType(); 3989 if (SrcTy->isPtrOrPtrVectorTy() && DestTy->isPtrOrPtrVectorTy() && 3990 SrcTy->getPointerAddressSpace() != DestTy->getPointerAddressSpace()) { 3991 LLVMContext &Context = V->getContext(); 3992 3993 // We have no information about target data layout, so we assume that 3994 // the maximum pointer size is 64bit. 3995 Type *MidTy = Type::getInt64Ty(Context); 3996 Temp = CastInst::Create(Instruction::PtrToInt, V, MidTy); 3997 3998 return CastInst::Create(Instruction::IntToPtr, Temp, DestTy); 3999 } 4000 4001 return nullptr; 4002 } 4003 4004 Value *llvm::UpgradeBitCastExpr(unsigned Opc, Constant *C, Type *DestTy) { 4005 if (Opc != Instruction::BitCast) 4006 return nullptr; 4007 4008 Type *SrcTy = C->getType(); 4009 if (SrcTy->isPtrOrPtrVectorTy() && DestTy->isPtrOrPtrVectorTy() && 4010 SrcTy->getPointerAddressSpace() != DestTy->getPointerAddressSpace()) { 4011 LLVMContext &Context = C->getContext(); 4012 4013 // We have no information about target data layout, so we assume that 4014 // the maximum pointer size is 64bit. 4015 Type *MidTy = Type::getInt64Ty(Context); 4016 4017 return ConstantExpr::getIntToPtr(ConstantExpr::getPtrToInt(C, MidTy), 4018 DestTy); 4019 } 4020 4021 return nullptr; 4022 } 4023 4024 /// Check the debug info version number, if it is out-dated, drop the debug 4025 /// info. Return true if module is modified. 4026 bool llvm::UpgradeDebugInfo(Module &M) { 4027 unsigned Version = getDebugMetadataVersionFromModule(M); 4028 if (Version == DEBUG_METADATA_VERSION) { 4029 bool BrokenDebugInfo = false; 4030 if (verifyModule(M, &llvm::errs(), &BrokenDebugInfo)) 4031 report_fatal_error("Broken module found, compilation aborted!"); 4032 if (!BrokenDebugInfo) 4033 // Everything is ok. 4034 return false; 4035 else { 4036 // Diagnose malformed debug info. 4037 DiagnosticInfoIgnoringInvalidDebugMetadata Diag(M); 4038 M.getContext().diagnose(Diag); 4039 } 4040 } 4041 bool Modified = StripDebugInfo(M); 4042 if (Modified && Version != DEBUG_METADATA_VERSION) { 4043 // Diagnose a version mismatch. 4044 DiagnosticInfoDebugMetadataVersion DiagVersion(M, Version); 4045 M.getContext().diagnose(DiagVersion); 4046 } 4047 return Modified; 4048 } 4049 4050 /// This checks for objc retain release marker which should be upgraded. It 4051 /// returns true if module is modified. 4052 static bool UpgradeRetainReleaseMarker(Module &M) { 4053 bool Changed = false; 4054 const char *MarkerKey = "clang.arc.retainAutoreleasedReturnValueMarker"; 4055 NamedMDNode *ModRetainReleaseMarker = M.getNamedMetadata(MarkerKey); 4056 if (ModRetainReleaseMarker) { 4057 MDNode *Op = ModRetainReleaseMarker->getOperand(0); 4058 if (Op) { 4059 MDString *ID = dyn_cast_or_null<MDString>(Op->getOperand(0)); 4060 if (ID) { 4061 SmallVector<StringRef, 4> ValueComp; 4062 ID->getString().split(ValueComp, "#"); 4063 if (ValueComp.size() == 2) { 4064 std::string NewValue = ValueComp[0].str() + ";" + ValueComp[1].str(); 4065 ID = MDString::get(M.getContext(), NewValue); 4066 } 4067 M.addModuleFlag(Module::Error, MarkerKey, ID); 4068 M.eraseNamedMetadata(ModRetainReleaseMarker); 4069 Changed = true; 4070 } 4071 } 4072 } 4073 return Changed; 4074 } 4075 4076 void llvm::UpgradeARCRuntime(Module &M) { 4077 // This lambda converts normal function calls to ARC runtime functions to 4078 // intrinsic calls. 4079 auto UpgradeToIntrinsic = [&](const char *OldFunc, 4080 llvm::Intrinsic::ID IntrinsicFunc) { 4081 Function *Fn = M.getFunction(OldFunc); 4082 4083 if (!Fn) 4084 return; 4085 4086 Function *NewFn = llvm::Intrinsic::getDeclaration(&M, IntrinsicFunc); 4087 4088 for (User *U : make_early_inc_range(Fn->users())) { 4089 CallInst *CI = dyn_cast<CallInst>(U); 4090 if (!CI || CI->getCalledFunction() != Fn) 4091 continue; 4092 4093 IRBuilder<> Builder(CI->getParent(), CI->getIterator()); 4094 FunctionType *NewFuncTy = NewFn->getFunctionType(); 4095 SmallVector<Value *, 2> Args; 4096 4097 // Don't upgrade the intrinsic if it's not valid to bitcast the return 4098 // value to the return type of the old function. 4099 if (NewFuncTy->getReturnType() != CI->getType() && 4100 !CastInst::castIsValid(Instruction::BitCast, CI, 4101 NewFuncTy->getReturnType())) 4102 continue; 4103 4104 bool InvalidCast = false; 4105 4106 for (unsigned I = 0, E = CI->getNumArgOperands(); I != E; ++I) { 4107 Value *Arg = CI->getArgOperand(I); 4108 4109 // Bitcast argument to the parameter type of the new function if it's 4110 // not a variadic argument. 4111 if (I < NewFuncTy->getNumParams()) { 4112 // Don't upgrade the intrinsic if it's not valid to bitcast the argument 4113 // to the parameter type of the new function. 4114 if (!CastInst::castIsValid(Instruction::BitCast, Arg, 4115 NewFuncTy->getParamType(I))) { 4116 InvalidCast = true; 4117 break; 4118 } 4119 Arg = Builder.CreateBitCast(Arg, NewFuncTy->getParamType(I)); 4120 } 4121 Args.push_back(Arg); 4122 } 4123 4124 if (InvalidCast) 4125 continue; 4126 4127 // Create a call instruction that calls the new function. 4128 CallInst *NewCall = Builder.CreateCall(NewFuncTy, NewFn, Args); 4129 NewCall->setTailCallKind(cast<CallInst>(CI)->getTailCallKind()); 4130 NewCall->takeName(CI); 4131 4132 // Bitcast the return value back to the type of the old call. 4133 Value *NewRetVal = Builder.CreateBitCast(NewCall, CI->getType()); 4134 4135 if (!CI->use_empty()) 4136 CI->replaceAllUsesWith(NewRetVal); 4137 CI->eraseFromParent(); 4138 } 4139 4140 if (Fn->use_empty()) 4141 Fn->eraseFromParent(); 4142 }; 4143 4144 // Unconditionally convert a call to "clang.arc.use" to a call to 4145 // "llvm.objc.clang.arc.use". 4146 UpgradeToIntrinsic("clang.arc.use", llvm::Intrinsic::objc_clang_arc_use); 4147 4148 // Upgrade the retain release marker. If there is no need to upgrade 4149 // the marker, that means either the module is already new enough to contain 4150 // new intrinsics or it is not ARC. There is no need to upgrade runtime call. 4151 if (!UpgradeRetainReleaseMarker(M)) 4152 return; 4153 4154 std::pair<const char *, llvm::Intrinsic::ID> RuntimeFuncs[] = { 4155 {"objc_autorelease", llvm::Intrinsic::objc_autorelease}, 4156 {"objc_autoreleasePoolPop", llvm::Intrinsic::objc_autoreleasePoolPop}, 4157 {"objc_autoreleasePoolPush", llvm::Intrinsic::objc_autoreleasePoolPush}, 4158 {"objc_autoreleaseReturnValue", 4159 llvm::Intrinsic::objc_autoreleaseReturnValue}, 4160 {"objc_copyWeak", llvm::Intrinsic::objc_copyWeak}, 4161 {"objc_destroyWeak", llvm::Intrinsic::objc_destroyWeak}, 4162 {"objc_initWeak", llvm::Intrinsic::objc_initWeak}, 4163 {"objc_loadWeak", llvm::Intrinsic::objc_loadWeak}, 4164 {"objc_loadWeakRetained", llvm::Intrinsic::objc_loadWeakRetained}, 4165 {"objc_moveWeak", llvm::Intrinsic::objc_moveWeak}, 4166 {"objc_release", llvm::Intrinsic::objc_release}, 4167 {"objc_retain", llvm::Intrinsic::objc_retain}, 4168 {"objc_retainAutorelease", llvm::Intrinsic::objc_retainAutorelease}, 4169 {"objc_retainAutoreleaseReturnValue", 4170 llvm::Intrinsic::objc_retainAutoreleaseReturnValue}, 4171 {"objc_retainAutoreleasedReturnValue", 4172 llvm::Intrinsic::objc_retainAutoreleasedReturnValue}, 4173 {"objc_retainBlock", llvm::Intrinsic::objc_retainBlock}, 4174 {"objc_storeStrong", llvm::Intrinsic::objc_storeStrong}, 4175 {"objc_storeWeak", llvm::Intrinsic::objc_storeWeak}, 4176 {"objc_unsafeClaimAutoreleasedReturnValue", 4177 llvm::Intrinsic::objc_unsafeClaimAutoreleasedReturnValue}, 4178 {"objc_retainedObject", llvm::Intrinsic::objc_retainedObject}, 4179 {"objc_unretainedObject", llvm::Intrinsic::objc_unretainedObject}, 4180 {"objc_unretainedPointer", llvm::Intrinsic::objc_unretainedPointer}, 4181 {"objc_retain_autorelease", llvm::Intrinsic::objc_retain_autorelease}, 4182 {"objc_sync_enter", llvm::Intrinsic::objc_sync_enter}, 4183 {"objc_sync_exit", llvm::Intrinsic::objc_sync_exit}, 4184 {"objc_arc_annotation_topdown_bbstart", 4185 llvm::Intrinsic::objc_arc_annotation_topdown_bbstart}, 4186 {"objc_arc_annotation_topdown_bbend", 4187 llvm::Intrinsic::objc_arc_annotation_topdown_bbend}, 4188 {"objc_arc_annotation_bottomup_bbstart", 4189 llvm::Intrinsic::objc_arc_annotation_bottomup_bbstart}, 4190 {"objc_arc_annotation_bottomup_bbend", 4191 llvm::Intrinsic::objc_arc_annotation_bottomup_bbend}}; 4192 4193 for (auto &I : RuntimeFuncs) 4194 UpgradeToIntrinsic(I.first, I.second); 4195 } 4196 4197 bool llvm::UpgradeModuleFlags(Module &M) { 4198 NamedMDNode *ModFlags = M.getModuleFlagsMetadata(); 4199 if (!ModFlags) 4200 return false; 4201 4202 bool HasObjCFlag = false, HasClassProperties = false, Changed = false; 4203 bool HasSwiftVersionFlag = false; 4204 uint8_t SwiftMajorVersion, SwiftMinorVersion; 4205 uint32_t SwiftABIVersion; 4206 auto Int8Ty = Type::getInt8Ty(M.getContext()); 4207 auto Int32Ty = Type::getInt32Ty(M.getContext()); 4208 4209 for (unsigned I = 0, E = ModFlags->getNumOperands(); I != E; ++I) { 4210 MDNode *Op = ModFlags->getOperand(I); 4211 if (Op->getNumOperands() != 3) 4212 continue; 4213 MDString *ID = dyn_cast_or_null<MDString>(Op->getOperand(1)); 4214 if (!ID) 4215 continue; 4216 if (ID->getString() == "Objective-C Image Info Version") 4217 HasObjCFlag = true; 4218 if (ID->getString() == "Objective-C Class Properties") 4219 HasClassProperties = true; 4220 // Upgrade PIC/PIE Module Flags. The module flag behavior for these two 4221 // field was Error and now they are Max. 4222 if (ID->getString() == "PIC Level" || ID->getString() == "PIE Level") { 4223 if (auto *Behavior = 4224 mdconst::dyn_extract_or_null<ConstantInt>(Op->getOperand(0))) { 4225 if (Behavior->getLimitedValue() == Module::Error) { 4226 Type *Int32Ty = Type::getInt32Ty(M.getContext()); 4227 Metadata *Ops[3] = { 4228 ConstantAsMetadata::get(ConstantInt::get(Int32Ty, Module::Max)), 4229 MDString::get(M.getContext(), ID->getString()), 4230 Op->getOperand(2)}; 4231 ModFlags->setOperand(I, MDNode::get(M.getContext(), Ops)); 4232 Changed = true; 4233 } 4234 } 4235 } 4236 // Upgrade Objective-C Image Info Section. Removed the whitespce in the 4237 // section name so that llvm-lto will not complain about mismatching 4238 // module flags that is functionally the same. 4239 if (ID->getString() == "Objective-C Image Info Section") { 4240 if (auto *Value = dyn_cast_or_null<MDString>(Op->getOperand(2))) { 4241 SmallVector<StringRef, 4> ValueComp; 4242 Value->getString().split(ValueComp, " "); 4243 if (ValueComp.size() != 1) { 4244 std::string NewValue; 4245 for (auto &S : ValueComp) 4246 NewValue += S.str(); 4247 Metadata *Ops[3] = {Op->getOperand(0), Op->getOperand(1), 4248 MDString::get(M.getContext(), NewValue)}; 4249 ModFlags->setOperand(I, MDNode::get(M.getContext(), Ops)); 4250 Changed = true; 4251 } 4252 } 4253 } 4254 4255 // IRUpgrader turns a i32 type "Objective-C Garbage Collection" into i8 value. 4256 // If the higher bits are set, it adds new module flag for swift info. 4257 if (ID->getString() == "Objective-C Garbage Collection") { 4258 auto Md = dyn_cast<ConstantAsMetadata>(Op->getOperand(2)); 4259 if (Md) { 4260 assert(Md->getValue() && "Expected non-empty metadata"); 4261 auto Type = Md->getValue()->getType(); 4262 if (Type == Int8Ty) 4263 continue; 4264 unsigned Val = Md->getValue()->getUniqueInteger().getZExtValue(); 4265 if ((Val & 0xff) != Val) { 4266 HasSwiftVersionFlag = true; 4267 SwiftABIVersion = (Val & 0xff00) >> 8; 4268 SwiftMajorVersion = (Val & 0xff000000) >> 24; 4269 SwiftMinorVersion = (Val & 0xff0000) >> 16; 4270 } 4271 Metadata *Ops[3] = { 4272 ConstantAsMetadata::get(ConstantInt::get(Int32Ty,Module::Error)), 4273 Op->getOperand(1), 4274 ConstantAsMetadata::get(ConstantInt::get(Int8Ty,Val & 0xff))}; 4275 ModFlags->setOperand(I, MDNode::get(M.getContext(), Ops)); 4276 Changed = true; 4277 } 4278 } 4279 } 4280 4281 // "Objective-C Class Properties" is recently added for Objective-C. We 4282 // upgrade ObjC bitcodes to contain a "Objective-C Class Properties" module 4283 // flag of value 0, so we can correclty downgrade this flag when trying to 4284 // link an ObjC bitcode without this module flag with an ObjC bitcode with 4285 // this module flag. 4286 if (HasObjCFlag && !HasClassProperties) { 4287 M.addModuleFlag(llvm::Module::Override, "Objective-C Class Properties", 4288 (uint32_t)0); 4289 Changed = true; 4290 } 4291 4292 if (HasSwiftVersionFlag) { 4293 M.addModuleFlag(Module::Error, "Swift ABI Version", 4294 SwiftABIVersion); 4295 M.addModuleFlag(Module::Error, "Swift Major Version", 4296 ConstantInt::get(Int8Ty, SwiftMajorVersion)); 4297 M.addModuleFlag(Module::Error, "Swift Minor Version", 4298 ConstantInt::get(Int8Ty, SwiftMinorVersion)); 4299 Changed = true; 4300 } 4301 4302 return Changed; 4303 } 4304 4305 void llvm::UpgradeSectionAttributes(Module &M) { 4306 auto TrimSpaces = [](StringRef Section) -> std::string { 4307 SmallVector<StringRef, 5> Components; 4308 Section.split(Components, ','); 4309 4310 SmallString<32> Buffer; 4311 raw_svector_ostream OS(Buffer); 4312 4313 for (auto Component : Components) 4314 OS << ',' << Component.trim(); 4315 4316 return std::string(OS.str().substr(1)); 4317 }; 4318 4319 for (auto &GV : M.globals()) { 4320 if (!GV.hasSection()) 4321 continue; 4322 4323 StringRef Section = GV.getSection(); 4324 4325 if (!Section.startswith("__DATA, __objc_catlist")) 4326 continue; 4327 4328 // __DATA, __objc_catlist, regular, no_dead_strip 4329 // __DATA,__objc_catlist,regular,no_dead_strip 4330 GV.setSection(TrimSpaces(Section)); 4331 } 4332 } 4333 4334 namespace { 4335 // Prior to LLVM 10.0, the strictfp attribute could be used on individual 4336 // callsites within a function that did not also have the strictfp attribute. 4337 // Since 10.0, if strict FP semantics are needed within a function, the 4338 // function must have the strictfp attribute and all calls within the function 4339 // must also have the strictfp attribute. This latter restriction is 4340 // necessary to prevent unwanted libcall simplification when a function is 4341 // being cloned (such as for inlining). 4342 // 4343 // The "dangling" strictfp attribute usage was only used to prevent constant 4344 // folding and other libcall simplification. The nobuiltin attribute on the 4345 // callsite has the same effect. 4346 struct StrictFPUpgradeVisitor : public InstVisitor<StrictFPUpgradeVisitor> { 4347 StrictFPUpgradeVisitor() {} 4348 4349 void visitCallBase(CallBase &Call) { 4350 if (!Call.isStrictFP()) 4351 return; 4352 if (isa<ConstrainedFPIntrinsic>(&Call)) 4353 return; 4354 // If we get here, the caller doesn't have the strictfp attribute 4355 // but this callsite does. Replace the strictfp attribute with nobuiltin. 4356 Call.removeFnAttr(Attribute::StrictFP); 4357 Call.addFnAttr(Attribute::NoBuiltin); 4358 } 4359 }; 4360 } // namespace 4361 4362 void llvm::UpgradeFunctionAttributes(Function &F) { 4363 // If a function definition doesn't have the strictfp attribute, 4364 // convert any callsite strictfp attributes to nobuiltin. 4365 if (!F.isDeclaration() && !F.hasFnAttribute(Attribute::StrictFP)) { 4366 StrictFPUpgradeVisitor SFPV; 4367 SFPV.visit(F); 4368 } 4369 4370 if (F.getCallingConv() == CallingConv::X86_INTR && 4371 !F.arg_empty() && !F.hasParamAttribute(0, Attribute::ByVal)) { 4372 Type *ByValTy = cast<PointerType>(F.getArg(0)->getType())->getElementType(); 4373 Attribute NewAttr = Attribute::getWithByValType(F.getContext(), ByValTy); 4374 F.addParamAttr(0, NewAttr); 4375 } 4376 4377 // Remove all incompatibile attributes from function. 4378 F.removeRetAttrs(AttributeFuncs::typeIncompatible(F.getReturnType())); 4379 for (auto &Arg : F.args()) 4380 Arg.removeAttrs(AttributeFuncs::typeIncompatible(Arg.getType())); 4381 } 4382 4383 static bool isOldLoopArgument(Metadata *MD) { 4384 auto *T = dyn_cast_or_null<MDTuple>(MD); 4385 if (!T) 4386 return false; 4387 if (T->getNumOperands() < 1) 4388 return false; 4389 auto *S = dyn_cast_or_null<MDString>(T->getOperand(0)); 4390 if (!S) 4391 return false; 4392 return S->getString().startswith("llvm.vectorizer."); 4393 } 4394 4395 static MDString *upgradeLoopTag(LLVMContext &C, StringRef OldTag) { 4396 StringRef OldPrefix = "llvm.vectorizer."; 4397 assert(OldTag.startswith(OldPrefix) && "Expected old prefix"); 4398 4399 if (OldTag == "llvm.vectorizer.unroll") 4400 return MDString::get(C, "llvm.loop.interleave.count"); 4401 4402 return MDString::get( 4403 C, (Twine("llvm.loop.vectorize.") + OldTag.drop_front(OldPrefix.size())) 4404 .str()); 4405 } 4406 4407 static Metadata *upgradeLoopArgument(Metadata *MD) { 4408 auto *T = dyn_cast_or_null<MDTuple>(MD); 4409 if (!T) 4410 return MD; 4411 if (T->getNumOperands() < 1) 4412 return MD; 4413 auto *OldTag = dyn_cast_or_null<MDString>(T->getOperand(0)); 4414 if (!OldTag) 4415 return MD; 4416 if (!OldTag->getString().startswith("llvm.vectorizer.")) 4417 return MD; 4418 4419 // This has an old tag. Upgrade it. 4420 SmallVector<Metadata *, 8> Ops; 4421 Ops.reserve(T->getNumOperands()); 4422 Ops.push_back(upgradeLoopTag(T->getContext(), OldTag->getString())); 4423 for (unsigned I = 1, E = T->getNumOperands(); I != E; ++I) 4424 Ops.push_back(T->getOperand(I)); 4425 4426 return MDTuple::get(T->getContext(), Ops); 4427 } 4428 4429 MDNode *llvm::upgradeInstructionLoopAttachment(MDNode &N) { 4430 auto *T = dyn_cast<MDTuple>(&N); 4431 if (!T) 4432 return &N; 4433 4434 if (none_of(T->operands(), isOldLoopArgument)) 4435 return &N; 4436 4437 SmallVector<Metadata *, 8> Ops; 4438 Ops.reserve(T->getNumOperands()); 4439 for (Metadata *MD : T->operands()) 4440 Ops.push_back(upgradeLoopArgument(MD)); 4441 4442 return MDTuple::get(T->getContext(), Ops); 4443 } 4444 4445 std::string llvm::UpgradeDataLayoutString(StringRef DL, StringRef TT) { 4446 Triple T(TT); 4447 // For AMDGPU we uprgrade older DataLayouts to include the default globals 4448 // address space of 1. 4449 if (T.isAMDGPU() && !DL.contains("-G") && !DL.startswith("G")) { 4450 return DL.empty() ? std::string("G1") : (DL + "-G1").str(); 4451 } 4452 4453 std::string AddrSpaces = "-p270:32:32-p271:32:32-p272:64:64"; 4454 // If X86, and the datalayout matches the expected format, add pointer size 4455 // address spaces to the datalayout. 4456 if (!T.isX86() || DL.contains(AddrSpaces)) 4457 return std::string(DL); 4458 4459 SmallVector<StringRef, 4> Groups; 4460 Regex R("(e-m:[a-z](-p:32:32)?)(-[if]64:.*$)"); 4461 if (!R.match(DL, &Groups)) 4462 return std::string(DL); 4463 4464 return (Groups[1] + AddrSpaces + Groups[3]).str(); 4465 } 4466 4467 void llvm::UpgradeAttributes(AttrBuilder &B) { 4468 StringRef FramePointer; 4469 if (B.contains("no-frame-pointer-elim")) { 4470 // The value can be "true" or "false". 4471 for (const auto &I : B.td_attrs()) 4472 if (I.first == "no-frame-pointer-elim") 4473 FramePointer = I.second == "true" ? "all" : "none"; 4474 B.removeAttribute("no-frame-pointer-elim"); 4475 } 4476 if (B.contains("no-frame-pointer-elim-non-leaf")) { 4477 // The value is ignored. "no-frame-pointer-elim"="true" takes priority. 4478 if (FramePointer != "all") 4479 FramePointer = "non-leaf"; 4480 B.removeAttribute("no-frame-pointer-elim-non-leaf"); 4481 } 4482 if (!FramePointer.empty()) 4483 B.addAttribute("frame-pointer", FramePointer); 4484 4485 if (B.contains("null-pointer-is-valid")) { 4486 // The value can be "true" or "false". 4487 bool NullPointerIsValid = false; 4488 for (const auto &I : B.td_attrs()) 4489 if (I.first == "null-pointer-is-valid") 4490 NullPointerIsValid = I.second == "true"; 4491 B.removeAttribute("null-pointer-is-valid"); 4492 if (NullPointerIsValid) 4493 B.addAttribute(Attribute::NullPointerIsValid); 4494 } 4495 } 4496