1 //===-- AutoUpgrade.cpp - Implement auto-upgrade helper functions ---------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements the auto-upgrade helper functions. 11 // This is where deprecated IR intrinsics and other IR features are updated to 12 // current specifications. 13 // 14 //===----------------------------------------------------------------------===// 15 16 #include "llvm/IR/AutoUpgrade.h" 17 #include "llvm/ADT/StringSwitch.h" 18 #include "llvm/IR/Constants.h" 19 #include "llvm/IR/DIBuilder.h" 20 #include "llvm/IR/DebugInfo.h" 21 #include "llvm/IR/DiagnosticInfo.h" 22 #include "llvm/IR/Function.h" 23 #include "llvm/IR/IRBuilder.h" 24 #include "llvm/IR/Instruction.h" 25 #include "llvm/IR/IntrinsicInst.h" 26 #include "llvm/IR/LLVMContext.h" 27 #include "llvm/IR/Module.h" 28 #include "llvm/IR/Verifier.h" 29 #include "llvm/Support/ErrorHandling.h" 30 #include "llvm/Support/Regex.h" 31 #include <cstring> 32 using namespace llvm; 33 34 static void rename(GlobalValue *GV) { GV->setName(GV->getName() + ".old"); } 35 36 // Upgrade the declarations of the SSE4.1 ptest intrinsics whose arguments have 37 // changed their type from v4f32 to v2i64. 38 static bool UpgradePTESTIntrinsic(Function* F, Intrinsic::ID IID, 39 Function *&NewFn) { 40 // Check whether this is an old version of the function, which received 41 // v4f32 arguments. 42 Type *Arg0Type = F->getFunctionType()->getParamType(0); 43 if (Arg0Type != VectorType::get(Type::getFloatTy(F->getContext()), 4)) 44 return false; 45 46 // Yes, it's old, replace it with new version. 47 rename(F); 48 NewFn = Intrinsic::getDeclaration(F->getParent(), IID); 49 return true; 50 } 51 52 // Upgrade the declarations of intrinsic functions whose 8-bit immediate mask 53 // arguments have changed their type from i32 to i8. 54 static bool UpgradeX86IntrinsicsWith8BitMask(Function *F, Intrinsic::ID IID, 55 Function *&NewFn) { 56 // Check that the last argument is an i32. 57 Type *LastArgType = F->getFunctionType()->getParamType( 58 F->getFunctionType()->getNumParams() - 1); 59 if (!LastArgType->isIntegerTy(32)) 60 return false; 61 62 // Move this function aside and map down. 63 rename(F); 64 NewFn = Intrinsic::getDeclaration(F->getParent(), IID); 65 return true; 66 } 67 68 // Upgrade the declaration of fp compare intrinsics that change return type 69 // from scalar to vXi1 mask. 70 static bool UpgradeX86MaskedFPCompare(Function *F, Intrinsic::ID IID, 71 Function *&NewFn) { 72 // Check if the return type is a vector. 73 if (F->getReturnType()->isVectorTy()) 74 return false; 75 76 rename(F); 77 NewFn = Intrinsic::getDeclaration(F->getParent(), IID); 78 return true; 79 } 80 81 static bool ShouldUpgradeX86Intrinsic(Function *F, StringRef Name) { 82 // All of the intrinsics matches below should be marked with which llvm 83 // version started autoupgrading them. At some point in the future we would 84 // like to use this information to remove upgrade code for some older 85 // intrinsics. It is currently undecided how we will determine that future 86 // point. 87 if (Name=="ssse3.pabs.b.128" || // Added in 6.0 88 Name=="ssse3.pabs.w.128" || // Added in 6.0 89 Name=="ssse3.pabs.d.128" || // Added in 6.0 90 Name.startswith("avx512.mask.shuf.i") || // Added in 6.0 91 Name.startswith("avx512.mask.shuf.f") || // Added in 6.0 92 Name.startswith("avx512.kunpck") || //added in 6.0 93 Name.startswith("avx2.pabs.") || // Added in 6.0 94 Name.startswith("avx512.mask.pabs.") || // Added in 6.0 95 Name.startswith("avx512.broadcastm") || // Added in 6.0 96 Name.startswith("avx512.mask.pbroadcast") || // Added in 6.0 97 Name.startswith("sse2.pcmpeq.") || // Added in 3.1 98 Name.startswith("sse2.pcmpgt.") || // Added in 3.1 99 Name.startswith("avx2.pcmpeq.") || // Added in 3.1 100 Name.startswith("avx2.pcmpgt.") || // Added in 3.1 101 Name.startswith("avx512.mask.pcmpeq.") || // Added in 3.9 102 Name.startswith("avx512.mask.pcmpgt.") || // Added in 3.9 103 Name.startswith("avx.vperm2f128.") || // Added in 6.0 104 Name == "avx2.vperm2i128" || // Added in 6.0 105 Name == "sse.add.ss" || // Added in 4.0 106 Name == "sse2.add.sd" || // Added in 4.0 107 Name == "sse.sub.ss" || // Added in 4.0 108 Name == "sse2.sub.sd" || // Added in 4.0 109 Name == "sse.mul.ss" || // Added in 4.0 110 Name == "sse2.mul.sd" || // Added in 4.0 111 Name == "sse.div.ss" || // Added in 4.0 112 Name == "sse2.div.sd" || // Added in 4.0 113 Name == "sse41.pmaxsb" || // Added in 3.9 114 Name == "sse2.pmaxs.w" || // Added in 3.9 115 Name == "sse41.pmaxsd" || // Added in 3.9 116 Name == "sse2.pmaxu.b" || // Added in 3.9 117 Name == "sse41.pmaxuw" || // Added in 3.9 118 Name == "sse41.pmaxud" || // Added in 3.9 119 Name == "sse41.pminsb" || // Added in 3.9 120 Name == "sse2.pmins.w" || // Added in 3.9 121 Name == "sse41.pminsd" || // Added in 3.9 122 Name == "sse2.pminu.b" || // Added in 3.9 123 Name == "sse41.pminuw" || // Added in 3.9 124 Name == "sse41.pminud" || // Added in 3.9 125 Name == "avx512.kand.w" || // Added in 7.0 126 Name == "avx512.kandn.w" || // Added in 7.0 127 Name == "avx512.knot.w" || // Added in 7.0 128 Name == "avx512.kor.w" || // Added in 7.0 129 Name == "avx512.kxor.w" || // Added in 7.0 130 Name == "avx512.kxnor.w" || // Added in 7.0 131 Name == "avx512.kortestc.w" || // Added in 7.0 132 Name == "avx512.kortestz.w" || // Added in 7.0 133 Name.startswith("avx512.mask.pshuf.b.") || // Added in 4.0 134 Name.startswith("avx2.pmax") || // Added in 3.9 135 Name.startswith("avx2.pmin") || // Added in 3.9 136 Name.startswith("avx512.mask.pmax") || // Added in 4.0 137 Name.startswith("avx512.mask.pmin") || // Added in 4.0 138 Name.startswith("avx2.vbroadcast") || // Added in 3.8 139 Name.startswith("avx2.pbroadcast") || // Added in 3.8 140 Name.startswith("avx.vpermil.") || // Added in 3.1 141 Name.startswith("sse2.pshuf") || // Added in 3.9 142 Name.startswith("avx512.pbroadcast") || // Added in 3.9 143 Name.startswith("avx512.mask.broadcast.s") || // Added in 3.9 144 Name.startswith("avx512.mask.movddup") || // Added in 3.9 145 Name.startswith("avx512.mask.movshdup") || // Added in 3.9 146 Name.startswith("avx512.mask.movsldup") || // Added in 3.9 147 Name.startswith("avx512.mask.pshuf.d.") || // Added in 3.9 148 Name.startswith("avx512.mask.pshufl.w.") || // Added in 3.9 149 Name.startswith("avx512.mask.pshufh.w.") || // Added in 3.9 150 Name.startswith("avx512.mask.shuf.p") || // Added in 4.0 151 Name.startswith("avx512.mask.vpermil.p") || // Added in 3.9 152 Name.startswith("avx512.mask.perm.df.") || // Added in 3.9 153 Name.startswith("avx512.mask.perm.di.") || // Added in 3.9 154 Name.startswith("avx512.mask.punpckl") || // Added in 3.9 155 Name.startswith("avx512.mask.punpckh") || // Added in 3.9 156 Name.startswith("avx512.mask.unpckl.") || // Added in 3.9 157 Name.startswith("avx512.mask.unpckh.") || // Added in 3.9 158 Name.startswith("avx512.mask.pand.") || // Added in 3.9 159 Name.startswith("avx512.mask.pandn.") || // Added in 3.9 160 Name.startswith("avx512.mask.por.") || // Added in 3.9 161 Name.startswith("avx512.mask.pxor.") || // Added in 3.9 162 Name.startswith("avx512.mask.and.") || // Added in 3.9 163 Name.startswith("avx512.mask.andn.") || // Added in 3.9 164 Name.startswith("avx512.mask.or.") || // Added in 3.9 165 Name.startswith("avx512.mask.xor.") || // Added in 3.9 166 Name.startswith("avx512.mask.padd.") || // Added in 4.0 167 Name.startswith("avx512.mask.psub.") || // Added in 4.0 168 Name.startswith("avx512.mask.pmull.") || // Added in 4.0 169 Name.startswith("avx512.mask.cvtdq2pd.") || // Added in 4.0 170 Name.startswith("avx512.mask.cvtudq2pd.") || // Added in 4.0 171 Name == "sse2.pmulu.dq" || // Added in 7.0 172 Name == "sse41.pmuldq" || // Added in 7.0 173 Name == "avx2.pmulu.dq" || // Added in 7.0 174 Name == "avx2.pmul.dq" || // Added in 7.0 175 Name == "avx512.pmulu.dq.512" || // Added in 7.0 176 Name == "avx512.pmul.dq.512" || // Added in 7.0 177 Name.startswith("avx512.mask.pmul.dq.") || // Added in 4.0 178 Name.startswith("avx512.mask.pmulu.dq.") || // Added in 4.0 179 Name.startswith("avx512.mask.pmul.hr.sw.") || // Added in 7.0 180 Name.startswith("avx512.mask.pmulh.w.") || // Added in 7.0 181 Name.startswith("avx512.mask.pmulhu.w.") || // Added in 7.0 182 Name.startswith("avx512.mask.pmaddw.d.") || // Added in 7.0 183 Name.startswith("avx512.mask.pmaddubs.w.") || // Added in 7.0 184 Name.startswith("avx512.mask.packsswb.") || // Added in 5.0 185 Name.startswith("avx512.mask.packssdw.") || // Added in 5.0 186 Name.startswith("avx512.mask.packuswb.") || // Added in 5.0 187 Name.startswith("avx512.mask.packusdw.") || // Added in 5.0 188 Name.startswith("avx512.mask.cmp.b") || // Added in 5.0 189 Name.startswith("avx512.mask.cmp.d") || // Added in 5.0 190 Name.startswith("avx512.mask.cmp.q") || // Added in 5.0 191 Name.startswith("avx512.mask.cmp.w") || // Added in 5.0 192 Name.startswith("avx512.mask.ucmp.") || // Added in 5.0 193 Name.startswith("avx512.cvtb2mask.") || // Added in 7.0 194 Name.startswith("avx512.cvtw2mask.") || // Added in 7.0 195 Name.startswith("avx512.cvtd2mask.") || // Added in 7.0 196 Name.startswith("avx512.cvtq2mask.") || // Added in 7.0 197 Name == "avx512.mask.add.pd.128" || // Added in 4.0 198 Name == "avx512.mask.add.pd.256" || // Added in 4.0 199 Name == "avx512.mask.add.ps.128" || // Added in 4.0 200 Name == "avx512.mask.add.ps.256" || // Added in 4.0 201 Name == "avx512.mask.div.pd.128" || // Added in 4.0 202 Name == "avx512.mask.div.pd.256" || // Added in 4.0 203 Name == "avx512.mask.div.ps.128" || // Added in 4.0 204 Name == "avx512.mask.div.ps.256" || // Added in 4.0 205 Name == "avx512.mask.mul.pd.128" || // Added in 4.0 206 Name == "avx512.mask.mul.pd.256" || // Added in 4.0 207 Name == "avx512.mask.mul.ps.128" || // Added in 4.0 208 Name == "avx512.mask.mul.ps.256" || // Added in 4.0 209 Name == "avx512.mask.sub.pd.128" || // Added in 4.0 210 Name == "avx512.mask.sub.pd.256" || // Added in 4.0 211 Name == "avx512.mask.sub.ps.128" || // Added in 4.0 212 Name == "avx512.mask.sub.ps.256" || // Added in 4.0 213 Name == "avx512.mask.max.pd.128" || // Added in 5.0 214 Name == "avx512.mask.max.pd.256" || // Added in 5.0 215 Name == "avx512.mask.max.ps.128" || // Added in 5.0 216 Name == "avx512.mask.max.ps.256" || // Added in 5.0 217 Name == "avx512.mask.min.pd.128" || // Added in 5.0 218 Name == "avx512.mask.min.pd.256" || // Added in 5.0 219 Name == "avx512.mask.min.ps.128" || // Added in 5.0 220 Name == "avx512.mask.min.ps.256" || // Added in 5.0 221 Name.startswith("avx512.mask.vpermilvar.") || // Added in 4.0 222 Name.startswith("avx512.mask.psll.d") || // Added in 4.0 223 Name.startswith("avx512.mask.psll.q") || // Added in 4.0 224 Name.startswith("avx512.mask.psll.w") || // Added in 4.0 225 Name.startswith("avx512.mask.psra.d") || // Added in 4.0 226 Name.startswith("avx512.mask.psra.q") || // Added in 4.0 227 Name.startswith("avx512.mask.psra.w") || // Added in 4.0 228 Name.startswith("avx512.mask.psrl.d") || // Added in 4.0 229 Name.startswith("avx512.mask.psrl.q") || // Added in 4.0 230 Name.startswith("avx512.mask.psrl.w") || // Added in 4.0 231 Name.startswith("avx512.mask.pslli") || // Added in 4.0 232 Name.startswith("avx512.mask.psrai") || // Added in 4.0 233 Name.startswith("avx512.mask.psrli") || // Added in 4.0 234 Name.startswith("avx512.mask.psllv") || // Added in 4.0 235 Name.startswith("avx512.mask.psrav") || // Added in 4.0 236 Name.startswith("avx512.mask.psrlv") || // Added in 4.0 237 Name.startswith("sse41.pmovsx") || // Added in 3.8 238 Name.startswith("sse41.pmovzx") || // Added in 3.9 239 Name.startswith("avx2.pmovsx") || // Added in 3.9 240 Name.startswith("avx2.pmovzx") || // Added in 3.9 241 Name.startswith("avx512.mask.pmovsx") || // Added in 4.0 242 Name.startswith("avx512.mask.pmovzx") || // Added in 4.0 243 Name.startswith("avx512.mask.lzcnt.") || // Added in 5.0 244 Name == "sse2.cvtdq2pd" || // Added in 3.9 245 Name == "sse2.cvtps2pd" || // Added in 3.9 246 Name == "avx.cvtdq2.pd.256" || // Added in 3.9 247 Name == "avx.cvt.ps2.pd.256" || // Added in 3.9 248 Name.startswith("avx.vinsertf128.") || // Added in 3.7 249 Name == "avx2.vinserti128" || // Added in 3.7 250 Name.startswith("avx512.mask.insert") || // Added in 4.0 251 Name.startswith("avx.vextractf128.") || // Added in 3.7 252 Name == "avx2.vextracti128" || // Added in 3.7 253 Name.startswith("avx512.mask.vextract") || // Added in 4.0 254 Name.startswith("sse4a.movnt.") || // Added in 3.9 255 Name.startswith("avx.movnt.") || // Added in 3.2 256 Name.startswith("avx512.storent.") || // Added in 3.9 257 Name == "sse41.movntdqa" || // Added in 5.0 258 Name == "avx2.movntdqa" || // Added in 5.0 259 Name == "avx512.movntdqa" || // Added in 5.0 260 Name == "sse2.storel.dq" || // Added in 3.9 261 Name.startswith("sse.storeu.") || // Added in 3.9 262 Name.startswith("sse2.storeu.") || // Added in 3.9 263 Name.startswith("avx.storeu.") || // Added in 3.9 264 Name.startswith("avx512.mask.storeu.") || // Added in 3.9 265 Name.startswith("avx512.mask.store.p") || // Added in 3.9 266 Name.startswith("avx512.mask.store.b.") || // Added in 3.9 267 Name.startswith("avx512.mask.store.w.") || // Added in 3.9 268 Name.startswith("avx512.mask.store.d.") || // Added in 3.9 269 Name.startswith("avx512.mask.store.q.") || // Added in 3.9 270 Name.startswith("avx512.mask.loadu.") || // Added in 3.9 271 Name.startswith("avx512.mask.load.") || // Added in 3.9 272 Name == "sse42.crc32.64.8" || // Added in 3.4 273 Name.startswith("avx.vbroadcast.s") || // Added in 3.5 274 Name.startswith("avx512.mask.palignr.") || // Added in 3.9 275 Name.startswith("avx512.mask.valign.") || // Added in 4.0 276 Name.startswith("sse2.psll.dq") || // Added in 3.7 277 Name.startswith("sse2.psrl.dq") || // Added in 3.7 278 Name.startswith("avx2.psll.dq") || // Added in 3.7 279 Name.startswith("avx2.psrl.dq") || // Added in 3.7 280 Name.startswith("avx512.psll.dq") || // Added in 3.9 281 Name.startswith("avx512.psrl.dq") || // Added in 3.9 282 Name == "sse41.pblendw" || // Added in 3.7 283 Name.startswith("sse41.blendp") || // Added in 3.7 284 Name.startswith("avx.blend.p") || // Added in 3.7 285 Name == "avx2.pblendw" || // Added in 3.7 286 Name.startswith("avx2.pblendd.") || // Added in 3.7 287 Name.startswith("avx.vbroadcastf128") || // Added in 4.0 288 Name == "avx2.vbroadcasti128" || // Added in 3.7 289 Name.startswith("avx512.mask.broadcastf") || // Added in 6.0 290 Name.startswith("avx512.mask.broadcasti") || // Added in 6.0 291 Name == "xop.vpcmov" || // Added in 3.8 292 Name == "xop.vpcmov.256" || // Added in 5.0 293 Name.startswith("avx512.mask.move.s") || // Added in 4.0 294 Name.startswith("avx512.cvtmask2") || // Added in 5.0 295 (Name.startswith("xop.vpcom") && // Added in 3.2 296 F->arg_size() == 2) || 297 Name.startswith("avx512.ptestm") || //Added in 6.0 298 Name.startswith("avx512.ptestnm") || //Added in 6.0 299 Name.startswith("sse2.pavg") || // Added in 6.0 300 Name.startswith("avx2.pavg") || // Added in 6.0 301 Name.startswith("avx512.mask.pavg")) // Added in 6.0 302 return true; 303 304 return false; 305 } 306 307 static bool UpgradeX86IntrinsicFunction(Function *F, StringRef Name, 308 Function *&NewFn) { 309 // Only handle intrinsics that start with "x86.". 310 if (!Name.startswith("x86.")) 311 return false; 312 // Remove "x86." prefix. 313 Name = Name.substr(4); 314 315 if (ShouldUpgradeX86Intrinsic(F, Name)) { 316 NewFn = nullptr; 317 return true; 318 } 319 320 // SSE4.1 ptest functions may have an old signature. 321 if (Name.startswith("sse41.ptest")) { // Added in 3.2 322 if (Name.substr(11) == "c") 323 return UpgradePTESTIntrinsic(F, Intrinsic::x86_sse41_ptestc, NewFn); 324 if (Name.substr(11) == "z") 325 return UpgradePTESTIntrinsic(F, Intrinsic::x86_sse41_ptestz, NewFn); 326 if (Name.substr(11) == "nzc") 327 return UpgradePTESTIntrinsic(F, Intrinsic::x86_sse41_ptestnzc, NewFn); 328 } 329 // Several blend and other instructions with masks used the wrong number of 330 // bits. 331 if (Name == "sse41.insertps") // Added in 3.6 332 return UpgradeX86IntrinsicsWith8BitMask(F, Intrinsic::x86_sse41_insertps, 333 NewFn); 334 if (Name == "sse41.dppd") // Added in 3.6 335 return UpgradeX86IntrinsicsWith8BitMask(F, Intrinsic::x86_sse41_dppd, 336 NewFn); 337 if (Name == "sse41.dpps") // Added in 3.6 338 return UpgradeX86IntrinsicsWith8BitMask(F, Intrinsic::x86_sse41_dpps, 339 NewFn); 340 if (Name == "sse41.mpsadbw") // Added in 3.6 341 return UpgradeX86IntrinsicsWith8BitMask(F, Intrinsic::x86_sse41_mpsadbw, 342 NewFn); 343 if (Name == "avx.dp.ps.256") // Added in 3.6 344 return UpgradeX86IntrinsicsWith8BitMask(F, Intrinsic::x86_avx_dp_ps_256, 345 NewFn); 346 if (Name == "avx2.mpsadbw") // Added in 3.6 347 return UpgradeX86IntrinsicsWith8BitMask(F, Intrinsic::x86_avx2_mpsadbw, 348 NewFn); 349 if (Name == "avx512.mask.cmp.pd.128") // Added in 7.0 350 return UpgradeX86MaskedFPCompare(F, Intrinsic::x86_avx512_mask_cmp_pd_128, 351 NewFn); 352 if (Name == "avx512.mask.cmp.pd.256") // Added in 7.0 353 return UpgradeX86MaskedFPCompare(F, Intrinsic::x86_avx512_mask_cmp_pd_256, 354 NewFn); 355 if (Name == "avx512.mask.cmp.pd.512") // Added in 7.0 356 return UpgradeX86MaskedFPCompare(F, Intrinsic::x86_avx512_mask_cmp_pd_512, 357 NewFn); 358 if (Name == "avx512.mask.cmp.ps.128") // Added in 7.0 359 return UpgradeX86MaskedFPCompare(F, Intrinsic::x86_avx512_mask_cmp_ps_128, 360 NewFn); 361 if (Name == "avx512.mask.cmp.ps.256") // Added in 7.0 362 return UpgradeX86MaskedFPCompare(F, Intrinsic::x86_avx512_mask_cmp_ps_256, 363 NewFn); 364 if (Name == "avx512.mask.cmp.ps.512") // Added in 7.0 365 return UpgradeX86MaskedFPCompare(F, Intrinsic::x86_avx512_mask_cmp_ps_512, 366 NewFn); 367 368 // frcz.ss/sd may need to have an argument dropped. Added in 3.2 369 if (Name.startswith("xop.vfrcz.ss") && F->arg_size() == 2) { 370 rename(F); 371 NewFn = Intrinsic::getDeclaration(F->getParent(), 372 Intrinsic::x86_xop_vfrcz_ss); 373 return true; 374 } 375 if (Name.startswith("xop.vfrcz.sd") && F->arg_size() == 2) { 376 rename(F); 377 NewFn = Intrinsic::getDeclaration(F->getParent(), 378 Intrinsic::x86_xop_vfrcz_sd); 379 return true; 380 } 381 // Upgrade any XOP PERMIL2 index operand still using a float/double vector. 382 if (Name.startswith("xop.vpermil2")) { // Added in 3.9 383 auto Idx = F->getFunctionType()->getParamType(2); 384 if (Idx->isFPOrFPVectorTy()) { 385 rename(F); 386 unsigned IdxSize = Idx->getPrimitiveSizeInBits(); 387 unsigned EltSize = Idx->getScalarSizeInBits(); 388 Intrinsic::ID Permil2ID; 389 if (EltSize == 64 && IdxSize == 128) 390 Permil2ID = Intrinsic::x86_xop_vpermil2pd; 391 else if (EltSize == 32 && IdxSize == 128) 392 Permil2ID = Intrinsic::x86_xop_vpermil2ps; 393 else if (EltSize == 64 && IdxSize == 256) 394 Permil2ID = Intrinsic::x86_xop_vpermil2pd_256; 395 else 396 Permil2ID = Intrinsic::x86_xop_vpermil2ps_256; 397 NewFn = Intrinsic::getDeclaration(F->getParent(), Permil2ID); 398 return true; 399 } 400 } 401 402 return false; 403 } 404 405 static bool UpgradeIntrinsicFunction1(Function *F, Function *&NewFn) { 406 assert(F && "Illegal to upgrade a non-existent Function."); 407 408 // Quickly eliminate it, if it's not a candidate. 409 StringRef Name = F->getName(); 410 if (Name.size() <= 8 || !Name.startswith("llvm.")) 411 return false; 412 Name = Name.substr(5); // Strip off "llvm." 413 414 switch (Name[0]) { 415 default: break; 416 case 'a': { 417 if (Name.startswith("arm.rbit") || Name.startswith("aarch64.rbit")) { 418 NewFn = Intrinsic::getDeclaration(F->getParent(), Intrinsic::bitreverse, 419 F->arg_begin()->getType()); 420 return true; 421 } 422 if (Name.startswith("arm.neon.vclz")) { 423 Type* args[2] = { 424 F->arg_begin()->getType(), 425 Type::getInt1Ty(F->getContext()) 426 }; 427 // Can't use Intrinsic::getDeclaration here as it adds a ".i1" to 428 // the end of the name. Change name from llvm.arm.neon.vclz.* to 429 // llvm.ctlz.* 430 FunctionType* fType = FunctionType::get(F->getReturnType(), args, false); 431 NewFn = Function::Create(fType, F->getLinkage(), 432 "llvm.ctlz." + Name.substr(14), F->getParent()); 433 return true; 434 } 435 if (Name.startswith("arm.neon.vcnt")) { 436 NewFn = Intrinsic::getDeclaration(F->getParent(), Intrinsic::ctpop, 437 F->arg_begin()->getType()); 438 return true; 439 } 440 Regex vldRegex("^arm\\.neon\\.vld([1234]|[234]lane)\\.v[a-z0-9]*$"); 441 if (vldRegex.match(Name)) { 442 auto fArgs = F->getFunctionType()->params(); 443 SmallVector<Type *, 4> Tys(fArgs.begin(), fArgs.end()); 444 // Can't use Intrinsic::getDeclaration here as the return types might 445 // then only be structurally equal. 446 FunctionType* fType = FunctionType::get(F->getReturnType(), Tys, false); 447 NewFn = Function::Create(fType, F->getLinkage(), 448 "llvm." + Name + ".p0i8", F->getParent()); 449 return true; 450 } 451 Regex vstRegex("^arm\\.neon\\.vst([1234]|[234]lane)\\.v[a-z0-9]*$"); 452 if (vstRegex.match(Name)) { 453 static const Intrinsic::ID StoreInts[] = {Intrinsic::arm_neon_vst1, 454 Intrinsic::arm_neon_vst2, 455 Intrinsic::arm_neon_vst3, 456 Intrinsic::arm_neon_vst4}; 457 458 static const Intrinsic::ID StoreLaneInts[] = { 459 Intrinsic::arm_neon_vst2lane, Intrinsic::arm_neon_vst3lane, 460 Intrinsic::arm_neon_vst4lane 461 }; 462 463 auto fArgs = F->getFunctionType()->params(); 464 Type *Tys[] = {fArgs[0], fArgs[1]}; 465 if (Name.find("lane") == StringRef::npos) 466 NewFn = Intrinsic::getDeclaration(F->getParent(), 467 StoreInts[fArgs.size() - 3], Tys); 468 else 469 NewFn = Intrinsic::getDeclaration(F->getParent(), 470 StoreLaneInts[fArgs.size() - 5], Tys); 471 return true; 472 } 473 if (Name == "aarch64.thread.pointer" || Name == "arm.thread.pointer") { 474 NewFn = Intrinsic::getDeclaration(F->getParent(), Intrinsic::thread_pointer); 475 return true; 476 } 477 break; 478 } 479 480 case 'c': { 481 if (Name.startswith("ctlz.") && F->arg_size() == 1) { 482 rename(F); 483 NewFn = Intrinsic::getDeclaration(F->getParent(), Intrinsic::ctlz, 484 F->arg_begin()->getType()); 485 return true; 486 } 487 if (Name.startswith("cttz.") && F->arg_size() == 1) { 488 rename(F); 489 NewFn = Intrinsic::getDeclaration(F->getParent(), Intrinsic::cttz, 490 F->arg_begin()->getType()); 491 return true; 492 } 493 break; 494 } 495 case 'd': { 496 if (Name == "dbg.value" && F->arg_size() == 4) { 497 rename(F); 498 NewFn = Intrinsic::getDeclaration(F->getParent(), Intrinsic::dbg_value); 499 return true; 500 } 501 break; 502 } 503 case 'i': 504 case 'l': { 505 bool IsLifetimeStart = Name.startswith("lifetime.start"); 506 if (IsLifetimeStart || Name.startswith("invariant.start")) { 507 Intrinsic::ID ID = IsLifetimeStart ? 508 Intrinsic::lifetime_start : Intrinsic::invariant_start; 509 auto Args = F->getFunctionType()->params(); 510 Type* ObjectPtr[1] = {Args[1]}; 511 if (F->getName() != Intrinsic::getName(ID, ObjectPtr)) { 512 rename(F); 513 NewFn = Intrinsic::getDeclaration(F->getParent(), ID, ObjectPtr); 514 return true; 515 } 516 } 517 518 bool IsLifetimeEnd = Name.startswith("lifetime.end"); 519 if (IsLifetimeEnd || Name.startswith("invariant.end")) { 520 Intrinsic::ID ID = IsLifetimeEnd ? 521 Intrinsic::lifetime_end : Intrinsic::invariant_end; 522 523 auto Args = F->getFunctionType()->params(); 524 Type* ObjectPtr[1] = {Args[IsLifetimeEnd ? 1 : 2]}; 525 if (F->getName() != Intrinsic::getName(ID, ObjectPtr)) { 526 rename(F); 527 NewFn = Intrinsic::getDeclaration(F->getParent(), ID, ObjectPtr); 528 return true; 529 } 530 } 531 break; 532 } 533 case 'm': { 534 if (Name.startswith("masked.load.")) { 535 Type *Tys[] = { F->getReturnType(), F->arg_begin()->getType() }; 536 if (F->getName() != Intrinsic::getName(Intrinsic::masked_load, Tys)) { 537 rename(F); 538 NewFn = Intrinsic::getDeclaration(F->getParent(), 539 Intrinsic::masked_load, 540 Tys); 541 return true; 542 } 543 } 544 if (Name.startswith("masked.store.")) { 545 auto Args = F->getFunctionType()->params(); 546 Type *Tys[] = { Args[0], Args[1] }; 547 if (F->getName() != Intrinsic::getName(Intrinsic::masked_store, Tys)) { 548 rename(F); 549 NewFn = Intrinsic::getDeclaration(F->getParent(), 550 Intrinsic::masked_store, 551 Tys); 552 return true; 553 } 554 } 555 // Renaming gather/scatter intrinsics with no address space overloading 556 // to the new overload which includes an address space 557 if (Name.startswith("masked.gather.")) { 558 Type *Tys[] = {F->getReturnType(), F->arg_begin()->getType()}; 559 if (F->getName() != Intrinsic::getName(Intrinsic::masked_gather, Tys)) { 560 rename(F); 561 NewFn = Intrinsic::getDeclaration(F->getParent(), 562 Intrinsic::masked_gather, Tys); 563 return true; 564 } 565 } 566 if (Name.startswith("masked.scatter.")) { 567 auto Args = F->getFunctionType()->params(); 568 Type *Tys[] = {Args[0], Args[1]}; 569 if (F->getName() != Intrinsic::getName(Intrinsic::masked_scatter, Tys)) { 570 rename(F); 571 NewFn = Intrinsic::getDeclaration(F->getParent(), 572 Intrinsic::masked_scatter, Tys); 573 return true; 574 } 575 } 576 // Updating the memory intrinsics (memcpy/memmove/memset) that have an 577 // alignment parameter to embedding the alignment as an attribute of 578 // the pointer args. 579 if (Name.startswith("memcpy.") && F->arg_size() == 5) { 580 rename(F); 581 // Get the types of dest, src, and len 582 ArrayRef<Type *> ParamTypes = F->getFunctionType()->params().slice(0, 3); 583 NewFn = Intrinsic::getDeclaration(F->getParent(), Intrinsic::memcpy, 584 ParamTypes); 585 return true; 586 } 587 if (Name.startswith("memmove.") && F->arg_size() == 5) { 588 rename(F); 589 // Get the types of dest, src, and len 590 ArrayRef<Type *> ParamTypes = F->getFunctionType()->params().slice(0, 3); 591 NewFn = Intrinsic::getDeclaration(F->getParent(), Intrinsic::memmove, 592 ParamTypes); 593 return true; 594 } 595 if (Name.startswith("memset.") && F->arg_size() == 5) { 596 rename(F); 597 // Get the types of dest, and len 598 const auto *FT = F->getFunctionType(); 599 Type *ParamTypes[2] = { 600 FT->getParamType(0), // Dest 601 FT->getParamType(2) // len 602 }; 603 NewFn = Intrinsic::getDeclaration(F->getParent(), Intrinsic::memset, 604 ParamTypes); 605 return true; 606 } 607 break; 608 } 609 case 'n': { 610 if (Name.startswith("nvvm.")) { 611 Name = Name.substr(5); 612 613 // The following nvvm intrinsics correspond exactly to an LLVM intrinsic. 614 Intrinsic::ID IID = StringSwitch<Intrinsic::ID>(Name) 615 .Cases("brev32", "brev64", Intrinsic::bitreverse) 616 .Case("clz.i", Intrinsic::ctlz) 617 .Case("popc.i", Intrinsic::ctpop) 618 .Default(Intrinsic::not_intrinsic); 619 if (IID != Intrinsic::not_intrinsic && F->arg_size() == 1) { 620 NewFn = Intrinsic::getDeclaration(F->getParent(), IID, 621 {F->getReturnType()}); 622 return true; 623 } 624 625 // The following nvvm intrinsics correspond exactly to an LLVM idiom, but 626 // not to an intrinsic alone. We expand them in UpgradeIntrinsicCall. 627 // 628 // TODO: We could add lohi.i2d. 629 bool Expand = StringSwitch<bool>(Name) 630 .Cases("abs.i", "abs.ll", true) 631 .Cases("clz.ll", "popc.ll", "h2f", true) 632 .Cases("max.i", "max.ll", "max.ui", "max.ull", true) 633 .Cases("min.i", "min.ll", "min.ui", "min.ull", true) 634 .Default(false); 635 if (Expand) { 636 NewFn = nullptr; 637 return true; 638 } 639 } 640 break; 641 } 642 case 'o': 643 // We only need to change the name to match the mangling including the 644 // address space. 645 if (Name.startswith("objectsize.")) { 646 Type *Tys[2] = { F->getReturnType(), F->arg_begin()->getType() }; 647 if (F->arg_size() == 2 || 648 F->getName() != Intrinsic::getName(Intrinsic::objectsize, Tys)) { 649 rename(F); 650 NewFn = Intrinsic::getDeclaration(F->getParent(), Intrinsic::objectsize, 651 Tys); 652 return true; 653 } 654 } 655 break; 656 657 case 's': 658 if (Name == "stackprotectorcheck") { 659 NewFn = nullptr; 660 return true; 661 } 662 break; 663 664 case 'x': 665 if (UpgradeX86IntrinsicFunction(F, Name, NewFn)) 666 return true; 667 } 668 // Remangle our intrinsic since we upgrade the mangling 669 auto Result = llvm::Intrinsic::remangleIntrinsicFunction(F); 670 if (Result != None) { 671 NewFn = Result.getValue(); 672 return true; 673 } 674 675 // This may not belong here. This function is effectively being overloaded 676 // to both detect an intrinsic which needs upgrading, and to provide the 677 // upgraded form of the intrinsic. We should perhaps have two separate 678 // functions for this. 679 return false; 680 } 681 682 bool llvm::UpgradeIntrinsicFunction(Function *F, Function *&NewFn) { 683 NewFn = nullptr; 684 bool Upgraded = UpgradeIntrinsicFunction1(F, NewFn); 685 assert(F != NewFn && "Intrinsic function upgraded to the same function"); 686 687 // Upgrade intrinsic attributes. This does not change the function. 688 if (NewFn) 689 F = NewFn; 690 if (Intrinsic::ID id = F->getIntrinsicID()) 691 F->setAttributes(Intrinsic::getAttributes(F->getContext(), id)); 692 return Upgraded; 693 } 694 695 bool llvm::UpgradeGlobalVariable(GlobalVariable *GV) { 696 // Nothing to do yet. 697 return false; 698 } 699 700 // Handles upgrading SSE2/AVX2/AVX512BW PSLLDQ intrinsics by converting them 701 // to byte shuffles. 702 static Value *UpgradeX86PSLLDQIntrinsics(IRBuilder<> &Builder, 703 Value *Op, unsigned Shift) { 704 Type *ResultTy = Op->getType(); 705 unsigned NumElts = ResultTy->getVectorNumElements() * 8; 706 707 // Bitcast from a 64-bit element type to a byte element type. 708 Type *VecTy = VectorType::get(Builder.getInt8Ty(), NumElts); 709 Op = Builder.CreateBitCast(Op, VecTy, "cast"); 710 711 // We'll be shuffling in zeroes. 712 Value *Res = Constant::getNullValue(VecTy); 713 714 // If shift is less than 16, emit a shuffle to move the bytes. Otherwise, 715 // we'll just return the zero vector. 716 if (Shift < 16) { 717 uint32_t Idxs[64]; 718 // 256/512-bit version is split into 2/4 16-byte lanes. 719 for (unsigned l = 0; l != NumElts; l += 16) 720 for (unsigned i = 0; i != 16; ++i) { 721 unsigned Idx = NumElts + i - Shift; 722 if (Idx < NumElts) 723 Idx -= NumElts - 16; // end of lane, switch operand. 724 Idxs[l + i] = Idx + l; 725 } 726 727 Res = Builder.CreateShuffleVector(Res, Op, makeArrayRef(Idxs, NumElts)); 728 } 729 730 // Bitcast back to a 64-bit element type. 731 return Builder.CreateBitCast(Res, ResultTy, "cast"); 732 } 733 734 // Handles upgrading SSE2/AVX2/AVX512BW PSRLDQ intrinsics by converting them 735 // to byte shuffles. 736 static Value *UpgradeX86PSRLDQIntrinsics(IRBuilder<> &Builder, Value *Op, 737 unsigned Shift) { 738 Type *ResultTy = Op->getType(); 739 unsigned NumElts = ResultTy->getVectorNumElements() * 8; 740 741 // Bitcast from a 64-bit element type to a byte element type. 742 Type *VecTy = VectorType::get(Builder.getInt8Ty(), NumElts); 743 Op = Builder.CreateBitCast(Op, VecTy, "cast"); 744 745 // We'll be shuffling in zeroes. 746 Value *Res = Constant::getNullValue(VecTy); 747 748 // If shift is less than 16, emit a shuffle to move the bytes. Otherwise, 749 // we'll just return the zero vector. 750 if (Shift < 16) { 751 uint32_t Idxs[64]; 752 // 256/512-bit version is split into 2/4 16-byte lanes. 753 for (unsigned l = 0; l != NumElts; l += 16) 754 for (unsigned i = 0; i != 16; ++i) { 755 unsigned Idx = i + Shift; 756 if (Idx >= 16) 757 Idx += NumElts - 16; // end of lane, switch operand. 758 Idxs[l + i] = Idx + l; 759 } 760 761 Res = Builder.CreateShuffleVector(Op, Res, makeArrayRef(Idxs, NumElts)); 762 } 763 764 // Bitcast back to a 64-bit element type. 765 return Builder.CreateBitCast(Res, ResultTy, "cast"); 766 } 767 768 static Value *getX86MaskVec(IRBuilder<> &Builder, Value *Mask, 769 unsigned NumElts) { 770 llvm::VectorType *MaskTy = llvm::VectorType::get(Builder.getInt1Ty(), 771 cast<IntegerType>(Mask->getType())->getBitWidth()); 772 Mask = Builder.CreateBitCast(Mask, MaskTy); 773 774 // If we have less than 8 elements, then the starting mask was an i8 and 775 // we need to extract down to the right number of elements. 776 if (NumElts < 8) { 777 uint32_t Indices[4]; 778 for (unsigned i = 0; i != NumElts; ++i) 779 Indices[i] = i; 780 Mask = Builder.CreateShuffleVector(Mask, Mask, 781 makeArrayRef(Indices, NumElts), 782 "extract"); 783 } 784 785 return Mask; 786 } 787 788 static Value *EmitX86Select(IRBuilder<> &Builder, Value *Mask, 789 Value *Op0, Value *Op1) { 790 // If the mask is all ones just emit the align operation. 791 if (const auto *C = dyn_cast<Constant>(Mask)) 792 if (C->isAllOnesValue()) 793 return Op0; 794 795 Mask = getX86MaskVec(Builder, Mask, Op0->getType()->getVectorNumElements()); 796 return Builder.CreateSelect(Mask, Op0, Op1); 797 } 798 799 // Handle autoupgrade for masked PALIGNR and VALIGND/Q intrinsics. 800 // PALIGNR handles large immediates by shifting while VALIGN masks the immediate 801 // so we need to handle both cases. VALIGN also doesn't have 128-bit lanes. 802 static Value *UpgradeX86ALIGNIntrinsics(IRBuilder<> &Builder, Value *Op0, 803 Value *Op1, Value *Shift, 804 Value *Passthru, Value *Mask, 805 bool IsVALIGN) { 806 unsigned ShiftVal = cast<llvm::ConstantInt>(Shift)->getZExtValue(); 807 808 unsigned NumElts = Op0->getType()->getVectorNumElements(); 809 assert((IsVALIGN || NumElts % 16 == 0) && "Illegal NumElts for PALIGNR!"); 810 assert((!IsVALIGN || NumElts <= 16) && "NumElts too large for VALIGN!"); 811 assert(isPowerOf2_32(NumElts) && "NumElts not a power of 2!"); 812 813 // Mask the immediate for VALIGN. 814 if (IsVALIGN) 815 ShiftVal &= (NumElts - 1); 816 817 // If palignr is shifting the pair of vectors more than the size of two 818 // lanes, emit zero. 819 if (ShiftVal >= 32) 820 return llvm::Constant::getNullValue(Op0->getType()); 821 822 // If palignr is shifting the pair of input vectors more than one lane, 823 // but less than two lanes, convert to shifting in zeroes. 824 if (ShiftVal > 16) { 825 ShiftVal -= 16; 826 Op1 = Op0; 827 Op0 = llvm::Constant::getNullValue(Op0->getType()); 828 } 829 830 uint32_t Indices[64]; 831 // 256-bit palignr operates on 128-bit lanes so we need to handle that 832 for (unsigned l = 0; l < NumElts; l += 16) { 833 for (unsigned i = 0; i != 16; ++i) { 834 unsigned Idx = ShiftVal + i; 835 if (!IsVALIGN && Idx >= 16) // Disable wrap for VALIGN. 836 Idx += NumElts - 16; // End of lane, switch operand. 837 Indices[l + i] = Idx + l; 838 } 839 } 840 841 Value *Align = Builder.CreateShuffleVector(Op1, Op0, 842 makeArrayRef(Indices, NumElts), 843 "palignr"); 844 845 return EmitX86Select(Builder, Mask, Align, Passthru); 846 } 847 848 static Value *UpgradeMaskedStore(IRBuilder<> &Builder, 849 Value *Ptr, Value *Data, Value *Mask, 850 bool Aligned) { 851 // Cast the pointer to the right type. 852 Ptr = Builder.CreateBitCast(Ptr, 853 llvm::PointerType::getUnqual(Data->getType())); 854 unsigned Align = 855 Aligned ? cast<VectorType>(Data->getType())->getBitWidth() / 8 : 1; 856 857 // If the mask is all ones just emit a regular store. 858 if (const auto *C = dyn_cast<Constant>(Mask)) 859 if (C->isAllOnesValue()) 860 return Builder.CreateAlignedStore(Data, Ptr, Align); 861 862 // Convert the mask from an integer type to a vector of i1. 863 unsigned NumElts = Data->getType()->getVectorNumElements(); 864 Mask = getX86MaskVec(Builder, Mask, NumElts); 865 return Builder.CreateMaskedStore(Data, Ptr, Align, Mask); 866 } 867 868 static Value *UpgradeMaskedLoad(IRBuilder<> &Builder, 869 Value *Ptr, Value *Passthru, Value *Mask, 870 bool Aligned) { 871 // Cast the pointer to the right type. 872 Ptr = Builder.CreateBitCast(Ptr, 873 llvm::PointerType::getUnqual(Passthru->getType())); 874 unsigned Align = 875 Aligned ? cast<VectorType>(Passthru->getType())->getBitWidth() / 8 : 1; 876 877 // If the mask is all ones just emit a regular store. 878 if (const auto *C = dyn_cast<Constant>(Mask)) 879 if (C->isAllOnesValue()) 880 return Builder.CreateAlignedLoad(Ptr, Align); 881 882 // Convert the mask from an integer type to a vector of i1. 883 unsigned NumElts = Passthru->getType()->getVectorNumElements(); 884 Mask = getX86MaskVec(Builder, Mask, NumElts); 885 return Builder.CreateMaskedLoad(Ptr, Align, Mask, Passthru); 886 } 887 888 static Value *upgradeAbs(IRBuilder<> &Builder, CallInst &CI) { 889 Value *Op0 = CI.getArgOperand(0); 890 llvm::Type *Ty = Op0->getType(); 891 Value *Zero = llvm::Constant::getNullValue(Ty); 892 Value *Cmp = Builder.CreateICmp(ICmpInst::ICMP_SGT, Op0, Zero); 893 Value *Neg = Builder.CreateNeg(Op0); 894 Value *Res = Builder.CreateSelect(Cmp, Op0, Neg); 895 896 if (CI.getNumArgOperands() == 3) 897 Res = EmitX86Select(Builder,CI.getArgOperand(2), Res, CI.getArgOperand(1)); 898 899 return Res; 900 } 901 902 static Value *upgradeIntMinMax(IRBuilder<> &Builder, CallInst &CI, 903 ICmpInst::Predicate Pred) { 904 Value *Op0 = CI.getArgOperand(0); 905 Value *Op1 = CI.getArgOperand(1); 906 Value *Cmp = Builder.CreateICmp(Pred, Op0, Op1); 907 Value *Res = Builder.CreateSelect(Cmp, Op0, Op1); 908 909 if (CI.getNumArgOperands() == 4) 910 Res = EmitX86Select(Builder, CI.getArgOperand(3), Res, CI.getArgOperand(2)); 911 912 return Res; 913 } 914 915 static Value *upgradePMULDQ(IRBuilder<> &Builder, CallInst &CI, bool IsSigned) { 916 Type *Ty = CI.getType(); 917 918 // Arguments have a vXi32 type so cast to vXi64. 919 Value *LHS = Builder.CreateBitCast(CI.getArgOperand(0), Ty); 920 Value *RHS = Builder.CreateBitCast(CI.getArgOperand(1), Ty); 921 922 if (IsSigned) { 923 // Shift left then arithmetic shift right. 924 Constant *ShiftAmt = ConstantInt::get(Ty, 32); 925 LHS = Builder.CreateShl(LHS, ShiftAmt); 926 LHS = Builder.CreateAShr(LHS, ShiftAmt); 927 RHS = Builder.CreateShl(RHS, ShiftAmt); 928 RHS = Builder.CreateAShr(RHS, ShiftAmt); 929 } else { 930 // Clear the upper bits. 931 Constant *Mask = ConstantInt::get(Ty, 0xffffffff); 932 LHS = Builder.CreateAnd(LHS, Mask); 933 RHS = Builder.CreateAnd(RHS, Mask); 934 } 935 936 Value *Res = Builder.CreateMul(LHS, RHS); 937 938 if (CI.getNumArgOperands() == 4) 939 Res = EmitX86Select(Builder, CI.getArgOperand(3), Res, CI.getArgOperand(2)); 940 941 return Res; 942 } 943 944 // Applying mask on vector of i1's and make sure result is at least 8 bits wide. 945 static Value *ApplyX86MaskOn1BitsVec(IRBuilder<> &Builder,Value *Vec, Value *Mask, 946 unsigned NumElts) { 947 if (Mask) { 948 const auto *C = dyn_cast<Constant>(Mask); 949 if (!C || !C->isAllOnesValue()) 950 Vec = Builder.CreateAnd(Vec, getX86MaskVec(Builder, Mask, NumElts)); 951 } 952 953 if (NumElts < 8) { 954 uint32_t Indices[8]; 955 for (unsigned i = 0; i != NumElts; ++i) 956 Indices[i] = i; 957 for (unsigned i = NumElts; i != 8; ++i) 958 Indices[i] = NumElts + i % NumElts; 959 Vec = Builder.CreateShuffleVector(Vec, 960 Constant::getNullValue(Vec->getType()), 961 Indices); 962 } 963 return Builder.CreateBitCast(Vec, Builder.getIntNTy(std::max(NumElts, 8U))); 964 } 965 966 static Value *upgradeMaskedCompare(IRBuilder<> &Builder, CallInst &CI, 967 unsigned CC, bool Signed) { 968 Value *Op0 = CI.getArgOperand(0); 969 unsigned NumElts = Op0->getType()->getVectorNumElements(); 970 971 Value *Cmp; 972 if (CC == 3) { 973 Cmp = Constant::getNullValue(llvm::VectorType::get(Builder.getInt1Ty(), NumElts)); 974 } else if (CC == 7) { 975 Cmp = Constant::getAllOnesValue(llvm::VectorType::get(Builder.getInt1Ty(), NumElts)); 976 } else { 977 ICmpInst::Predicate Pred; 978 switch (CC) { 979 default: llvm_unreachable("Unknown condition code"); 980 case 0: Pred = ICmpInst::ICMP_EQ; break; 981 case 1: Pred = Signed ? ICmpInst::ICMP_SLT : ICmpInst::ICMP_ULT; break; 982 case 2: Pred = Signed ? ICmpInst::ICMP_SLE : ICmpInst::ICMP_ULE; break; 983 case 4: Pred = ICmpInst::ICMP_NE; break; 984 case 5: Pred = Signed ? ICmpInst::ICMP_SGE : ICmpInst::ICMP_UGE; break; 985 case 6: Pred = Signed ? ICmpInst::ICMP_SGT : ICmpInst::ICMP_UGT; break; 986 } 987 Cmp = Builder.CreateICmp(Pred, Op0, CI.getArgOperand(1)); 988 } 989 990 Value *Mask = CI.getArgOperand(CI.getNumArgOperands() - 1); 991 992 return ApplyX86MaskOn1BitsVec(Builder, Cmp, Mask, NumElts); 993 } 994 995 // Replace a masked intrinsic with an older unmasked intrinsic. 996 static Value *UpgradeX86MaskedShift(IRBuilder<> &Builder, CallInst &CI, 997 Intrinsic::ID IID) { 998 Function *Intrin = Intrinsic::getDeclaration(CI.getModule(), IID); 999 Value *Rep = Builder.CreateCall(Intrin, 1000 { CI.getArgOperand(0), CI.getArgOperand(1) }); 1001 return EmitX86Select(Builder, CI.getArgOperand(3), Rep, CI.getArgOperand(2)); 1002 } 1003 1004 static Value* upgradeMaskedMove(IRBuilder<> &Builder, CallInst &CI) { 1005 Value* A = CI.getArgOperand(0); 1006 Value* B = CI.getArgOperand(1); 1007 Value* Src = CI.getArgOperand(2); 1008 Value* Mask = CI.getArgOperand(3); 1009 1010 Value* AndNode = Builder.CreateAnd(Mask, APInt(8, 1)); 1011 Value* Cmp = Builder.CreateIsNotNull(AndNode); 1012 Value* Extract1 = Builder.CreateExtractElement(B, (uint64_t)0); 1013 Value* Extract2 = Builder.CreateExtractElement(Src, (uint64_t)0); 1014 Value* Select = Builder.CreateSelect(Cmp, Extract1, Extract2); 1015 return Builder.CreateInsertElement(A, Select, (uint64_t)0); 1016 } 1017 1018 1019 static Value* UpgradeMaskToInt(IRBuilder<> &Builder, CallInst &CI) { 1020 Value* Op = CI.getArgOperand(0); 1021 Type* ReturnOp = CI.getType(); 1022 unsigned NumElts = CI.getType()->getVectorNumElements(); 1023 Value *Mask = getX86MaskVec(Builder, Op, NumElts); 1024 return Builder.CreateSExt(Mask, ReturnOp, "vpmovm2"); 1025 } 1026 1027 // Replace intrinsic with unmasked version and a select. 1028 static bool upgradeAVX512MaskToSelect(StringRef Name, IRBuilder<> &Builder, 1029 CallInst &CI, Value *&Rep) { 1030 Name = Name.substr(12); // Remove avx512.mask. 1031 1032 unsigned VecWidth = CI.getType()->getPrimitiveSizeInBits(); 1033 unsigned EltWidth = CI.getType()->getScalarSizeInBits(); 1034 Intrinsic::ID IID; 1035 if (Name.startswith("max.p")) { 1036 if (VecWidth == 128 && EltWidth == 32) 1037 IID = Intrinsic::x86_sse_max_ps; 1038 else if (VecWidth == 128 && EltWidth == 64) 1039 IID = Intrinsic::x86_sse2_max_pd; 1040 else if (VecWidth == 256 && EltWidth == 32) 1041 IID = Intrinsic::x86_avx_max_ps_256; 1042 else if (VecWidth == 256 && EltWidth == 64) 1043 IID = Intrinsic::x86_avx_max_pd_256; 1044 else 1045 llvm_unreachable("Unexpected intrinsic"); 1046 } else if (Name.startswith("min.p")) { 1047 if (VecWidth == 128 && EltWidth == 32) 1048 IID = Intrinsic::x86_sse_min_ps; 1049 else if (VecWidth == 128 && EltWidth == 64) 1050 IID = Intrinsic::x86_sse2_min_pd; 1051 else if (VecWidth == 256 && EltWidth == 32) 1052 IID = Intrinsic::x86_avx_min_ps_256; 1053 else if (VecWidth == 256 && EltWidth == 64) 1054 IID = Intrinsic::x86_avx_min_pd_256; 1055 else 1056 llvm_unreachable("Unexpected intrinsic"); 1057 } else if (Name.startswith("pshuf.b.")) { 1058 if (VecWidth == 128) 1059 IID = Intrinsic::x86_ssse3_pshuf_b_128; 1060 else if (VecWidth == 256) 1061 IID = Intrinsic::x86_avx2_pshuf_b; 1062 else if (VecWidth == 512) 1063 IID = Intrinsic::x86_avx512_pshuf_b_512; 1064 else 1065 llvm_unreachable("Unexpected intrinsic"); 1066 } else if (Name.startswith("pmul.hr.sw.")) { 1067 if (VecWidth == 128) 1068 IID = Intrinsic::x86_ssse3_pmul_hr_sw_128; 1069 else if (VecWidth == 256) 1070 IID = Intrinsic::x86_avx2_pmul_hr_sw; 1071 else if (VecWidth == 512) 1072 IID = Intrinsic::x86_avx512_pmul_hr_sw_512; 1073 else 1074 llvm_unreachable("Unexpected intrinsic"); 1075 } else if (Name.startswith("pmulh.w.")) { 1076 if (VecWidth == 128) 1077 IID = Intrinsic::x86_sse2_pmulh_w; 1078 else if (VecWidth == 256) 1079 IID = Intrinsic::x86_avx2_pmulh_w; 1080 else if (VecWidth == 512) 1081 IID = Intrinsic::x86_avx512_pmulh_w_512; 1082 else 1083 llvm_unreachable("Unexpected intrinsic"); 1084 } else if (Name.startswith("pmulhu.w.")) { 1085 if (VecWidth == 128) 1086 IID = Intrinsic::x86_sse2_pmulhu_w; 1087 else if (VecWidth == 256) 1088 IID = Intrinsic::x86_avx2_pmulhu_w; 1089 else if (VecWidth == 512) 1090 IID = Intrinsic::x86_avx512_pmulhu_w_512; 1091 else 1092 llvm_unreachable("Unexpected intrinsic"); 1093 } else if (Name.startswith("pmaddw.d.")) { 1094 if (VecWidth == 128) 1095 IID = Intrinsic::x86_sse2_pmadd_wd; 1096 else if (VecWidth == 256) 1097 IID = Intrinsic::x86_avx2_pmadd_wd; 1098 else if (VecWidth == 512) 1099 IID = Intrinsic::x86_avx512_pmaddw_d_512; 1100 else 1101 llvm_unreachable("Unexpected intrinsic"); 1102 } else if (Name.startswith("pmaddubs.w.")) { 1103 if (VecWidth == 128) 1104 IID = Intrinsic::x86_ssse3_pmadd_ub_sw_128; 1105 else if (VecWidth == 256) 1106 IID = Intrinsic::x86_avx2_pmadd_ub_sw; 1107 else if (VecWidth == 512) 1108 IID = Intrinsic::x86_avx512_pmaddubs_w_512; 1109 else 1110 llvm_unreachable("Unexpected intrinsic"); 1111 } else if (Name.startswith("packsswb.")) { 1112 if (VecWidth == 128) 1113 IID = Intrinsic::x86_sse2_packsswb_128; 1114 else if (VecWidth == 256) 1115 IID = Intrinsic::x86_avx2_packsswb; 1116 else if (VecWidth == 512) 1117 IID = Intrinsic::x86_avx512_packsswb_512; 1118 else 1119 llvm_unreachable("Unexpected intrinsic"); 1120 } else if (Name.startswith("packssdw.")) { 1121 if (VecWidth == 128) 1122 IID = Intrinsic::x86_sse2_packssdw_128; 1123 else if (VecWidth == 256) 1124 IID = Intrinsic::x86_avx2_packssdw; 1125 else if (VecWidth == 512) 1126 IID = Intrinsic::x86_avx512_packssdw_512; 1127 else 1128 llvm_unreachable("Unexpected intrinsic"); 1129 } else if (Name.startswith("packuswb.")) { 1130 if (VecWidth == 128) 1131 IID = Intrinsic::x86_sse2_packuswb_128; 1132 else if (VecWidth == 256) 1133 IID = Intrinsic::x86_avx2_packuswb; 1134 else if (VecWidth == 512) 1135 IID = Intrinsic::x86_avx512_packuswb_512; 1136 else 1137 llvm_unreachable("Unexpected intrinsic"); 1138 } else if (Name.startswith("packusdw.")) { 1139 if (VecWidth == 128) 1140 IID = Intrinsic::x86_sse41_packusdw; 1141 else if (VecWidth == 256) 1142 IID = Intrinsic::x86_avx2_packusdw; 1143 else if (VecWidth == 512) 1144 IID = Intrinsic::x86_avx512_packusdw_512; 1145 else 1146 llvm_unreachable("Unexpected intrinsic"); 1147 } else if (Name.startswith("vpermilvar.")) { 1148 if (VecWidth == 128 && EltWidth == 32) 1149 IID = Intrinsic::x86_avx_vpermilvar_ps; 1150 else if (VecWidth == 128 && EltWidth == 64) 1151 IID = Intrinsic::x86_avx_vpermilvar_pd; 1152 else if (VecWidth == 256 && EltWidth == 32) 1153 IID = Intrinsic::x86_avx_vpermilvar_ps_256; 1154 else if (VecWidth == 256 && EltWidth == 64) 1155 IID = Intrinsic::x86_avx_vpermilvar_pd_256; 1156 else if (VecWidth == 512 && EltWidth == 32) 1157 IID = Intrinsic::x86_avx512_vpermilvar_ps_512; 1158 else if (VecWidth == 512 && EltWidth == 64) 1159 IID = Intrinsic::x86_avx512_vpermilvar_pd_512; 1160 else 1161 llvm_unreachable("Unexpected intrinsic"); 1162 } else 1163 return false; 1164 1165 Rep = Builder.CreateCall(Intrinsic::getDeclaration(CI.getModule(), IID), 1166 { CI.getArgOperand(0), CI.getArgOperand(1) }); 1167 Rep = EmitX86Select(Builder, CI.getArgOperand(3), Rep, 1168 CI.getArgOperand(2)); 1169 return true; 1170 } 1171 1172 /// Upgrade comment in call to inline asm that represents an objc retain release 1173 /// marker. 1174 void llvm::UpgradeInlineAsmString(std::string *AsmStr) { 1175 size_t Pos; 1176 if (AsmStr->find("mov\tfp") == 0 && 1177 AsmStr->find("objc_retainAutoreleaseReturnValue") != std::string::npos && 1178 (Pos = AsmStr->find("# marker")) != std::string::npos) { 1179 AsmStr->replace(Pos, 1, ";"); 1180 } 1181 return; 1182 } 1183 1184 /// Upgrade a call to an old intrinsic. All argument and return casting must be 1185 /// provided to seamlessly integrate with existing context. 1186 void llvm::UpgradeIntrinsicCall(CallInst *CI, Function *NewFn) { 1187 Function *F = CI->getCalledFunction(); 1188 LLVMContext &C = CI->getContext(); 1189 IRBuilder<> Builder(C); 1190 Builder.SetInsertPoint(CI->getParent(), CI->getIterator()); 1191 1192 assert(F && "Intrinsic call is not direct?"); 1193 1194 if (!NewFn) { 1195 // Get the Function's name. 1196 StringRef Name = F->getName(); 1197 1198 assert(Name.startswith("llvm.") && "Intrinsic doesn't start with 'llvm.'"); 1199 Name = Name.substr(5); 1200 1201 bool IsX86 = Name.startswith("x86."); 1202 if (IsX86) 1203 Name = Name.substr(4); 1204 bool IsNVVM = Name.startswith("nvvm."); 1205 if (IsNVVM) 1206 Name = Name.substr(5); 1207 1208 if (IsX86 && Name.startswith("sse4a.movnt.")) { 1209 Module *M = F->getParent(); 1210 SmallVector<Metadata *, 1> Elts; 1211 Elts.push_back( 1212 ConstantAsMetadata::get(ConstantInt::get(Type::getInt32Ty(C), 1))); 1213 MDNode *Node = MDNode::get(C, Elts); 1214 1215 Value *Arg0 = CI->getArgOperand(0); 1216 Value *Arg1 = CI->getArgOperand(1); 1217 1218 // Nontemporal (unaligned) store of the 0'th element of the float/double 1219 // vector. 1220 Type *SrcEltTy = cast<VectorType>(Arg1->getType())->getElementType(); 1221 PointerType *EltPtrTy = PointerType::getUnqual(SrcEltTy); 1222 Value *Addr = Builder.CreateBitCast(Arg0, EltPtrTy, "cast"); 1223 Value *Extract = 1224 Builder.CreateExtractElement(Arg1, (uint64_t)0, "extractelement"); 1225 1226 StoreInst *SI = Builder.CreateAlignedStore(Extract, Addr, 1); 1227 SI->setMetadata(M->getMDKindID("nontemporal"), Node); 1228 1229 // Remove intrinsic. 1230 CI->eraseFromParent(); 1231 return; 1232 } 1233 1234 if (IsX86 && (Name.startswith("avx.movnt.") || 1235 Name.startswith("avx512.storent."))) { 1236 Module *M = F->getParent(); 1237 SmallVector<Metadata *, 1> Elts; 1238 Elts.push_back( 1239 ConstantAsMetadata::get(ConstantInt::get(Type::getInt32Ty(C), 1))); 1240 MDNode *Node = MDNode::get(C, Elts); 1241 1242 Value *Arg0 = CI->getArgOperand(0); 1243 Value *Arg1 = CI->getArgOperand(1); 1244 1245 // Convert the type of the pointer to a pointer to the stored type. 1246 Value *BC = Builder.CreateBitCast(Arg0, 1247 PointerType::getUnqual(Arg1->getType()), 1248 "cast"); 1249 VectorType *VTy = cast<VectorType>(Arg1->getType()); 1250 StoreInst *SI = Builder.CreateAlignedStore(Arg1, BC, 1251 VTy->getBitWidth() / 8); 1252 SI->setMetadata(M->getMDKindID("nontemporal"), Node); 1253 1254 // Remove intrinsic. 1255 CI->eraseFromParent(); 1256 return; 1257 } 1258 1259 if (IsX86 && Name == "sse2.storel.dq") { 1260 Value *Arg0 = CI->getArgOperand(0); 1261 Value *Arg1 = CI->getArgOperand(1); 1262 1263 Type *NewVecTy = VectorType::get(Type::getInt64Ty(C), 2); 1264 Value *BC0 = Builder.CreateBitCast(Arg1, NewVecTy, "cast"); 1265 Value *Elt = Builder.CreateExtractElement(BC0, (uint64_t)0); 1266 Value *BC = Builder.CreateBitCast(Arg0, 1267 PointerType::getUnqual(Elt->getType()), 1268 "cast"); 1269 Builder.CreateAlignedStore(Elt, BC, 1); 1270 1271 // Remove intrinsic. 1272 CI->eraseFromParent(); 1273 return; 1274 } 1275 1276 if (IsX86 && (Name.startswith("sse.storeu.") || 1277 Name.startswith("sse2.storeu.") || 1278 Name.startswith("avx.storeu."))) { 1279 Value *Arg0 = CI->getArgOperand(0); 1280 Value *Arg1 = CI->getArgOperand(1); 1281 1282 Arg0 = Builder.CreateBitCast(Arg0, 1283 PointerType::getUnqual(Arg1->getType()), 1284 "cast"); 1285 Builder.CreateAlignedStore(Arg1, Arg0, 1); 1286 1287 // Remove intrinsic. 1288 CI->eraseFromParent(); 1289 return; 1290 } 1291 1292 if (IsX86 && (Name.startswith("avx512.mask.store"))) { 1293 // "avx512.mask.storeu." or "avx512.mask.store." 1294 bool Aligned = Name[17] != 'u'; // "avx512.mask.storeu". 1295 UpgradeMaskedStore(Builder, CI->getArgOperand(0), CI->getArgOperand(1), 1296 CI->getArgOperand(2), Aligned); 1297 1298 // Remove intrinsic. 1299 CI->eraseFromParent(); 1300 return; 1301 } 1302 1303 Value *Rep; 1304 // Upgrade packed integer vector compare intrinsics to compare instructions. 1305 if (IsX86 && (Name.startswith("sse2.pcmp") || 1306 Name.startswith("avx2.pcmp"))) { 1307 // "sse2.pcpmpeq." "sse2.pcmpgt." "avx2.pcmpeq." or "avx2.pcmpgt." 1308 bool CmpEq = Name[9] == 'e'; 1309 Rep = Builder.CreateICmp(CmpEq ? ICmpInst::ICMP_EQ : ICmpInst::ICMP_SGT, 1310 CI->getArgOperand(0), CI->getArgOperand(1)); 1311 Rep = Builder.CreateSExt(Rep, CI->getType(), ""); 1312 } else if (IsX86 && (Name.startswith("avx512.broadcastm"))) { 1313 Type *ExtTy = Type::getInt32Ty(C); 1314 if (CI->getOperand(0)->getType()->isIntegerTy(8)) 1315 ExtTy = Type::getInt64Ty(C); 1316 unsigned NumElts = CI->getType()->getPrimitiveSizeInBits() / 1317 ExtTy->getPrimitiveSizeInBits(); 1318 Rep = Builder.CreateZExt(CI->getArgOperand(0), ExtTy); 1319 Rep = Builder.CreateVectorSplat(NumElts, Rep); 1320 } else if (IsX86 && (Name.startswith("avx512.ptestm") || 1321 Name.startswith("avx512.ptestnm"))) { 1322 Value *Op0 = CI->getArgOperand(0); 1323 Value *Op1 = CI->getArgOperand(1); 1324 Value *Mask = CI->getArgOperand(2); 1325 Rep = Builder.CreateAnd(Op0, Op1); 1326 llvm::Type *Ty = Op0->getType(); 1327 Value *Zero = llvm::Constant::getNullValue(Ty); 1328 ICmpInst::Predicate Pred = 1329 Name.startswith("avx512.ptestm") ? ICmpInst::ICMP_NE : ICmpInst::ICMP_EQ; 1330 Rep = Builder.CreateICmp(Pred, Rep, Zero); 1331 unsigned NumElts = Op0->getType()->getVectorNumElements(); 1332 Rep = ApplyX86MaskOn1BitsVec(Builder, Rep, Mask, NumElts); 1333 } else if (IsX86 && (Name.startswith("avx512.mask.pbroadcast"))){ 1334 unsigned NumElts = 1335 CI->getArgOperand(1)->getType()->getVectorNumElements(); 1336 Rep = Builder.CreateVectorSplat(NumElts, CI->getArgOperand(0)); 1337 Rep = EmitX86Select(Builder, CI->getArgOperand(2), Rep, 1338 CI->getArgOperand(1)); 1339 } else if (IsX86 && (Name.startswith("avx512.kunpck"))) { 1340 unsigned NumElts = CI->getType()->getScalarSizeInBits(); 1341 Value *LHS = getX86MaskVec(Builder, CI->getArgOperand(0), NumElts); 1342 Value *RHS = getX86MaskVec(Builder, CI->getArgOperand(1), NumElts); 1343 uint32_t Indices[64]; 1344 for (unsigned i = 0; i != NumElts; ++i) 1345 Indices[i] = i; 1346 1347 // First extract half of each vector. This gives better codegen than 1348 // doing it in a single shuffle. 1349 LHS = Builder.CreateShuffleVector(LHS, LHS, 1350 makeArrayRef(Indices, NumElts / 2)); 1351 RHS = Builder.CreateShuffleVector(RHS, RHS, 1352 makeArrayRef(Indices, NumElts / 2)); 1353 // Concat the vectors. 1354 // NOTE: Operands have to be swapped to match intrinsic definition. 1355 Rep = Builder.CreateShuffleVector(RHS, LHS, 1356 makeArrayRef(Indices, NumElts)); 1357 Rep = Builder.CreateBitCast(Rep, CI->getType()); 1358 } else if (IsX86 && Name == "avx512.kand.w") { 1359 Value *LHS = getX86MaskVec(Builder, CI->getArgOperand(0), 16); 1360 Value *RHS = getX86MaskVec(Builder, CI->getArgOperand(1), 16); 1361 Rep = Builder.CreateAnd(LHS, RHS); 1362 Rep = Builder.CreateBitCast(Rep, CI->getType()); 1363 } else if (IsX86 && Name == "avx512.kandn.w") { 1364 Value *LHS = getX86MaskVec(Builder, CI->getArgOperand(0), 16); 1365 Value *RHS = getX86MaskVec(Builder, CI->getArgOperand(1), 16); 1366 LHS = Builder.CreateNot(LHS); 1367 Rep = Builder.CreateAnd(LHS, RHS); 1368 Rep = Builder.CreateBitCast(Rep, CI->getType()); 1369 } else if (IsX86 && Name == "avx512.kor.w") { 1370 Value *LHS = getX86MaskVec(Builder, CI->getArgOperand(0), 16); 1371 Value *RHS = getX86MaskVec(Builder, CI->getArgOperand(1), 16); 1372 Rep = Builder.CreateOr(LHS, RHS); 1373 Rep = Builder.CreateBitCast(Rep, CI->getType()); 1374 } else if (IsX86 && Name == "avx512.kxor.w") { 1375 Value *LHS = getX86MaskVec(Builder, CI->getArgOperand(0), 16); 1376 Value *RHS = getX86MaskVec(Builder, CI->getArgOperand(1), 16); 1377 Rep = Builder.CreateXor(LHS, RHS); 1378 Rep = Builder.CreateBitCast(Rep, CI->getType()); 1379 } else if (IsX86 && Name == "avx512.kxnor.w") { 1380 Value *LHS = getX86MaskVec(Builder, CI->getArgOperand(0), 16); 1381 Value *RHS = getX86MaskVec(Builder, CI->getArgOperand(1), 16); 1382 LHS = Builder.CreateNot(LHS); 1383 Rep = Builder.CreateXor(LHS, RHS); 1384 Rep = Builder.CreateBitCast(Rep, CI->getType()); 1385 } else if (IsX86 && Name == "avx512.knot.w") { 1386 Rep = getX86MaskVec(Builder, CI->getArgOperand(0), 16); 1387 Rep = Builder.CreateNot(Rep); 1388 Rep = Builder.CreateBitCast(Rep, CI->getType()); 1389 } else if (IsX86 && 1390 (Name == "avx512.kortestz.w" || Name == "avx512.kortestc.w")) { 1391 Value *LHS = getX86MaskVec(Builder, CI->getArgOperand(0), 16); 1392 Value *RHS = getX86MaskVec(Builder, CI->getArgOperand(1), 16); 1393 Rep = Builder.CreateOr(LHS, RHS); 1394 Rep = Builder.CreateBitCast(Rep, Builder.getInt16Ty()); 1395 Value *C; 1396 if (Name[14] == 'c') 1397 C = ConstantInt::getAllOnesValue(Builder.getInt16Ty()); 1398 else 1399 C = ConstantInt::getNullValue(Builder.getInt16Ty()); 1400 Rep = Builder.CreateICmpEQ(Rep, C); 1401 Rep = Builder.CreateZExt(Rep, Builder.getInt32Ty()); 1402 } else if (IsX86 && (Name == "sse.add.ss" || Name == "sse2.add.sd")) { 1403 Type *I32Ty = Type::getInt32Ty(C); 1404 Value *Elt0 = Builder.CreateExtractElement(CI->getArgOperand(0), 1405 ConstantInt::get(I32Ty, 0)); 1406 Value *Elt1 = Builder.CreateExtractElement(CI->getArgOperand(1), 1407 ConstantInt::get(I32Ty, 0)); 1408 Rep = Builder.CreateInsertElement(CI->getArgOperand(0), 1409 Builder.CreateFAdd(Elt0, Elt1), 1410 ConstantInt::get(I32Ty, 0)); 1411 } else if (IsX86 && (Name == "sse.sub.ss" || Name == "sse2.sub.sd")) { 1412 Type *I32Ty = Type::getInt32Ty(C); 1413 Value *Elt0 = Builder.CreateExtractElement(CI->getArgOperand(0), 1414 ConstantInt::get(I32Ty, 0)); 1415 Value *Elt1 = Builder.CreateExtractElement(CI->getArgOperand(1), 1416 ConstantInt::get(I32Ty, 0)); 1417 Rep = Builder.CreateInsertElement(CI->getArgOperand(0), 1418 Builder.CreateFSub(Elt0, Elt1), 1419 ConstantInt::get(I32Ty, 0)); 1420 } else if (IsX86 && (Name == "sse.mul.ss" || Name == "sse2.mul.sd")) { 1421 Type *I32Ty = Type::getInt32Ty(C); 1422 Value *Elt0 = Builder.CreateExtractElement(CI->getArgOperand(0), 1423 ConstantInt::get(I32Ty, 0)); 1424 Value *Elt1 = Builder.CreateExtractElement(CI->getArgOperand(1), 1425 ConstantInt::get(I32Ty, 0)); 1426 Rep = Builder.CreateInsertElement(CI->getArgOperand(0), 1427 Builder.CreateFMul(Elt0, Elt1), 1428 ConstantInt::get(I32Ty, 0)); 1429 } else if (IsX86 && (Name == "sse.div.ss" || Name == "sse2.div.sd")) { 1430 Type *I32Ty = Type::getInt32Ty(C); 1431 Value *Elt0 = Builder.CreateExtractElement(CI->getArgOperand(0), 1432 ConstantInt::get(I32Ty, 0)); 1433 Value *Elt1 = Builder.CreateExtractElement(CI->getArgOperand(1), 1434 ConstantInt::get(I32Ty, 0)); 1435 Rep = Builder.CreateInsertElement(CI->getArgOperand(0), 1436 Builder.CreateFDiv(Elt0, Elt1), 1437 ConstantInt::get(I32Ty, 0)); 1438 } else if (IsX86 && Name.startswith("avx512.mask.pcmp")) { 1439 // "avx512.mask.pcmpeq." or "avx512.mask.pcmpgt." 1440 bool CmpEq = Name[16] == 'e'; 1441 Rep = upgradeMaskedCompare(Builder, *CI, CmpEq ? 0 : 6, true); 1442 } else if (IsX86 && Name.startswith("avx512.mask.cmp")) { 1443 unsigned Imm = cast<ConstantInt>(CI->getArgOperand(2))->getZExtValue(); 1444 Rep = upgradeMaskedCompare(Builder, *CI, Imm, true); 1445 } else if (IsX86 && Name.startswith("avx512.mask.ucmp")) { 1446 unsigned Imm = cast<ConstantInt>(CI->getArgOperand(2))->getZExtValue(); 1447 Rep = upgradeMaskedCompare(Builder, *CI, Imm, false); 1448 } else if (IsX86 && (Name.startswith("avx512.cvtb2mask.") || 1449 Name.startswith("avx512.cvtw2mask.") || 1450 Name.startswith("avx512.cvtd2mask.") || 1451 Name.startswith("avx512.cvtq2mask."))) { 1452 Value *Op = CI->getArgOperand(0); 1453 Value *Zero = llvm::Constant::getNullValue(Op->getType()); 1454 Rep = Builder.CreateICmp(ICmpInst::ICMP_SLT, Op, Zero); 1455 Rep = ApplyX86MaskOn1BitsVec(Builder, Rep, nullptr, 1456 Op->getType()->getVectorNumElements()); 1457 } else if(IsX86 && (Name == "ssse3.pabs.b.128" || 1458 Name == "ssse3.pabs.w.128" || 1459 Name == "ssse3.pabs.d.128" || 1460 Name.startswith("avx2.pabs") || 1461 Name.startswith("avx512.mask.pabs"))) { 1462 Rep = upgradeAbs(Builder, *CI); 1463 } else if (IsX86 && (Name == "sse41.pmaxsb" || 1464 Name == "sse2.pmaxs.w" || 1465 Name == "sse41.pmaxsd" || 1466 Name.startswith("avx2.pmaxs") || 1467 Name.startswith("avx512.mask.pmaxs"))) { 1468 Rep = upgradeIntMinMax(Builder, *CI, ICmpInst::ICMP_SGT); 1469 } else if (IsX86 && (Name == "sse2.pmaxu.b" || 1470 Name == "sse41.pmaxuw" || 1471 Name == "sse41.pmaxud" || 1472 Name.startswith("avx2.pmaxu") || 1473 Name.startswith("avx512.mask.pmaxu"))) { 1474 Rep = upgradeIntMinMax(Builder, *CI, ICmpInst::ICMP_UGT); 1475 } else if (IsX86 && (Name == "sse41.pminsb" || 1476 Name == "sse2.pmins.w" || 1477 Name == "sse41.pminsd" || 1478 Name.startswith("avx2.pmins") || 1479 Name.startswith("avx512.mask.pmins"))) { 1480 Rep = upgradeIntMinMax(Builder, *CI, ICmpInst::ICMP_SLT); 1481 } else if (IsX86 && (Name == "sse2.pminu.b" || 1482 Name == "sse41.pminuw" || 1483 Name == "sse41.pminud" || 1484 Name.startswith("avx2.pminu") || 1485 Name.startswith("avx512.mask.pminu"))) { 1486 Rep = upgradeIntMinMax(Builder, *CI, ICmpInst::ICMP_ULT); 1487 } else if (IsX86 && (Name == "sse2.pmulu.dq" || 1488 Name == "avx2.pmulu.dq" || 1489 Name == "avx512.pmulu.dq.512" || 1490 Name.startswith("avx512.mask.pmulu.dq."))) { 1491 Rep = upgradePMULDQ(Builder, *CI, /*Signed*/false); 1492 } else if (IsX86 && (Name == "sse41.pmuldq" || 1493 Name == "avx2.pmul.dq" || 1494 Name == "avx512.pmul.dq.512" || 1495 Name.startswith("avx512.mask.pmul.dq."))) { 1496 Rep = upgradePMULDQ(Builder, *CI, /*Signed*/true); 1497 } else if (IsX86 && (Name == "sse2.cvtdq2pd" || 1498 Name == "sse2.cvtps2pd" || 1499 Name == "avx.cvtdq2.pd.256" || 1500 Name == "avx.cvt.ps2.pd.256" || 1501 Name.startswith("avx512.mask.cvtdq2pd.") || 1502 Name.startswith("avx512.mask.cvtudq2pd."))) { 1503 // Lossless i32/float to double conversion. 1504 // Extract the bottom elements if necessary and convert to double vector. 1505 Value *Src = CI->getArgOperand(0); 1506 VectorType *SrcTy = cast<VectorType>(Src->getType()); 1507 VectorType *DstTy = cast<VectorType>(CI->getType()); 1508 Rep = CI->getArgOperand(0); 1509 1510 unsigned NumDstElts = DstTy->getNumElements(); 1511 if (NumDstElts < SrcTy->getNumElements()) { 1512 assert(NumDstElts == 2 && "Unexpected vector size"); 1513 uint32_t ShuffleMask[2] = { 0, 1 }; 1514 Rep = Builder.CreateShuffleVector(Rep, UndefValue::get(SrcTy), 1515 ShuffleMask); 1516 } 1517 1518 bool SInt2Double = (StringRef::npos != Name.find("cvtdq2")); 1519 bool UInt2Double = (StringRef::npos != Name.find("cvtudq2")); 1520 if (SInt2Double) 1521 Rep = Builder.CreateSIToFP(Rep, DstTy, "cvtdq2pd"); 1522 else if (UInt2Double) 1523 Rep = Builder.CreateUIToFP(Rep, DstTy, "cvtudq2pd"); 1524 else 1525 Rep = Builder.CreateFPExt(Rep, DstTy, "cvtps2pd"); 1526 1527 if (CI->getNumArgOperands() == 3) 1528 Rep = EmitX86Select(Builder, CI->getArgOperand(2), Rep, 1529 CI->getArgOperand(1)); 1530 } else if (IsX86 && (Name.startswith("avx512.mask.loadu."))) { 1531 Rep = UpgradeMaskedLoad(Builder, CI->getArgOperand(0), 1532 CI->getArgOperand(1), CI->getArgOperand(2), 1533 /*Aligned*/false); 1534 } else if (IsX86 && (Name.startswith("avx512.mask.load."))) { 1535 Rep = UpgradeMaskedLoad(Builder, CI->getArgOperand(0), 1536 CI->getArgOperand(1),CI->getArgOperand(2), 1537 /*Aligned*/true); 1538 } else if (IsX86 && Name.startswith("xop.vpcom")) { 1539 Intrinsic::ID intID; 1540 if (Name.endswith("ub")) 1541 intID = Intrinsic::x86_xop_vpcomub; 1542 else if (Name.endswith("uw")) 1543 intID = Intrinsic::x86_xop_vpcomuw; 1544 else if (Name.endswith("ud")) 1545 intID = Intrinsic::x86_xop_vpcomud; 1546 else if (Name.endswith("uq")) 1547 intID = Intrinsic::x86_xop_vpcomuq; 1548 else if (Name.endswith("b")) 1549 intID = Intrinsic::x86_xop_vpcomb; 1550 else if (Name.endswith("w")) 1551 intID = Intrinsic::x86_xop_vpcomw; 1552 else if (Name.endswith("d")) 1553 intID = Intrinsic::x86_xop_vpcomd; 1554 else if (Name.endswith("q")) 1555 intID = Intrinsic::x86_xop_vpcomq; 1556 else 1557 llvm_unreachable("Unknown suffix"); 1558 1559 Name = Name.substr(9); // strip off "xop.vpcom" 1560 unsigned Imm; 1561 if (Name.startswith("lt")) 1562 Imm = 0; 1563 else if (Name.startswith("le")) 1564 Imm = 1; 1565 else if (Name.startswith("gt")) 1566 Imm = 2; 1567 else if (Name.startswith("ge")) 1568 Imm = 3; 1569 else if (Name.startswith("eq")) 1570 Imm = 4; 1571 else if (Name.startswith("ne")) 1572 Imm = 5; 1573 else if (Name.startswith("false")) 1574 Imm = 6; 1575 else if (Name.startswith("true")) 1576 Imm = 7; 1577 else 1578 llvm_unreachable("Unknown condition"); 1579 1580 Function *VPCOM = Intrinsic::getDeclaration(F->getParent(), intID); 1581 Rep = 1582 Builder.CreateCall(VPCOM, {CI->getArgOperand(0), CI->getArgOperand(1), 1583 Builder.getInt8(Imm)}); 1584 } else if (IsX86 && Name.startswith("xop.vpcmov")) { 1585 Value *Sel = CI->getArgOperand(2); 1586 Value *NotSel = Builder.CreateNot(Sel); 1587 Value *Sel0 = Builder.CreateAnd(CI->getArgOperand(0), Sel); 1588 Value *Sel1 = Builder.CreateAnd(CI->getArgOperand(1), NotSel); 1589 Rep = Builder.CreateOr(Sel0, Sel1); 1590 } else if (IsX86 && Name == "sse42.crc32.64.8") { 1591 Function *CRC32 = Intrinsic::getDeclaration(F->getParent(), 1592 Intrinsic::x86_sse42_crc32_32_8); 1593 Value *Trunc0 = Builder.CreateTrunc(CI->getArgOperand(0), Type::getInt32Ty(C)); 1594 Rep = Builder.CreateCall(CRC32, {Trunc0, CI->getArgOperand(1)}); 1595 Rep = Builder.CreateZExt(Rep, CI->getType(), ""); 1596 } else if (IsX86 && Name.startswith("avx.vbroadcast.s")) { 1597 // Replace broadcasts with a series of insertelements. 1598 Type *VecTy = CI->getType(); 1599 Type *EltTy = VecTy->getVectorElementType(); 1600 unsigned EltNum = VecTy->getVectorNumElements(); 1601 Value *Cast = Builder.CreateBitCast(CI->getArgOperand(0), 1602 EltTy->getPointerTo()); 1603 Value *Load = Builder.CreateLoad(EltTy, Cast); 1604 Type *I32Ty = Type::getInt32Ty(C); 1605 Rep = UndefValue::get(VecTy); 1606 for (unsigned I = 0; I < EltNum; ++I) 1607 Rep = Builder.CreateInsertElement(Rep, Load, 1608 ConstantInt::get(I32Ty, I)); 1609 } else if (IsX86 && (Name.startswith("sse41.pmovsx") || 1610 Name.startswith("sse41.pmovzx") || 1611 Name.startswith("avx2.pmovsx") || 1612 Name.startswith("avx2.pmovzx") || 1613 Name.startswith("avx512.mask.pmovsx") || 1614 Name.startswith("avx512.mask.pmovzx"))) { 1615 VectorType *SrcTy = cast<VectorType>(CI->getArgOperand(0)->getType()); 1616 VectorType *DstTy = cast<VectorType>(CI->getType()); 1617 unsigned NumDstElts = DstTy->getNumElements(); 1618 1619 // Extract a subvector of the first NumDstElts lanes and sign/zero extend. 1620 SmallVector<uint32_t, 8> ShuffleMask(NumDstElts); 1621 for (unsigned i = 0; i != NumDstElts; ++i) 1622 ShuffleMask[i] = i; 1623 1624 Value *SV = Builder.CreateShuffleVector( 1625 CI->getArgOperand(0), UndefValue::get(SrcTy), ShuffleMask); 1626 1627 bool DoSext = (StringRef::npos != Name.find("pmovsx")); 1628 Rep = DoSext ? Builder.CreateSExt(SV, DstTy) 1629 : Builder.CreateZExt(SV, DstTy); 1630 // If there are 3 arguments, it's a masked intrinsic so we need a select. 1631 if (CI->getNumArgOperands() == 3) 1632 Rep = EmitX86Select(Builder, CI->getArgOperand(2), Rep, 1633 CI->getArgOperand(1)); 1634 } else if (IsX86 && (Name.startswith("avx.vbroadcastf128") || 1635 Name == "avx2.vbroadcasti128")) { 1636 // Replace vbroadcastf128/vbroadcasti128 with a vector load+shuffle. 1637 Type *EltTy = CI->getType()->getVectorElementType(); 1638 unsigned NumSrcElts = 128 / EltTy->getPrimitiveSizeInBits(); 1639 Type *VT = VectorType::get(EltTy, NumSrcElts); 1640 Value *Op = Builder.CreatePointerCast(CI->getArgOperand(0), 1641 PointerType::getUnqual(VT)); 1642 Value *Load = Builder.CreateAlignedLoad(Op, 1); 1643 if (NumSrcElts == 2) 1644 Rep = Builder.CreateShuffleVector(Load, UndefValue::get(Load->getType()), 1645 { 0, 1, 0, 1 }); 1646 else 1647 Rep = Builder.CreateShuffleVector(Load, UndefValue::get(Load->getType()), 1648 { 0, 1, 2, 3, 0, 1, 2, 3 }); 1649 } else if (IsX86 && (Name.startswith("avx512.mask.shuf.i") || 1650 Name.startswith("avx512.mask.shuf.f"))) { 1651 unsigned Imm = cast<ConstantInt>(CI->getArgOperand(2))->getZExtValue(); 1652 Type *VT = CI->getType(); 1653 unsigned NumLanes = VT->getPrimitiveSizeInBits() / 128; 1654 unsigned NumElementsInLane = 128 / VT->getScalarSizeInBits(); 1655 unsigned ControlBitsMask = NumLanes - 1; 1656 unsigned NumControlBits = NumLanes / 2; 1657 SmallVector<uint32_t, 8> ShuffleMask(0); 1658 1659 for (unsigned l = 0; l != NumLanes; ++l) { 1660 unsigned LaneMask = (Imm >> (l * NumControlBits)) & ControlBitsMask; 1661 // We actually need the other source. 1662 if (l >= NumLanes / 2) 1663 LaneMask += NumLanes; 1664 for (unsigned i = 0; i != NumElementsInLane; ++i) 1665 ShuffleMask.push_back(LaneMask * NumElementsInLane + i); 1666 } 1667 Rep = Builder.CreateShuffleVector(CI->getArgOperand(0), 1668 CI->getArgOperand(1), ShuffleMask); 1669 Rep = EmitX86Select(Builder, CI->getArgOperand(4), Rep, 1670 CI->getArgOperand(3)); 1671 }else if (IsX86 && (Name.startswith("avx512.mask.broadcastf") || 1672 Name.startswith("avx512.mask.broadcasti"))) { 1673 unsigned NumSrcElts = 1674 CI->getArgOperand(0)->getType()->getVectorNumElements(); 1675 unsigned NumDstElts = CI->getType()->getVectorNumElements(); 1676 1677 SmallVector<uint32_t, 8> ShuffleMask(NumDstElts); 1678 for (unsigned i = 0; i != NumDstElts; ++i) 1679 ShuffleMask[i] = i % NumSrcElts; 1680 1681 Rep = Builder.CreateShuffleVector(CI->getArgOperand(0), 1682 CI->getArgOperand(0), 1683 ShuffleMask); 1684 Rep = EmitX86Select(Builder, CI->getArgOperand(2), Rep, 1685 CI->getArgOperand(1)); 1686 } else if (IsX86 && (Name.startswith("avx2.pbroadcast") || 1687 Name.startswith("avx2.vbroadcast") || 1688 Name.startswith("avx512.pbroadcast") || 1689 Name.startswith("avx512.mask.broadcast.s"))) { 1690 // Replace vp?broadcasts with a vector shuffle. 1691 Value *Op = CI->getArgOperand(0); 1692 unsigned NumElts = CI->getType()->getVectorNumElements(); 1693 Type *MaskTy = VectorType::get(Type::getInt32Ty(C), NumElts); 1694 Rep = Builder.CreateShuffleVector(Op, UndefValue::get(Op->getType()), 1695 Constant::getNullValue(MaskTy)); 1696 1697 if (CI->getNumArgOperands() == 3) 1698 Rep = EmitX86Select(Builder, CI->getArgOperand(2), Rep, 1699 CI->getArgOperand(1)); 1700 } else if (IsX86 && Name.startswith("avx512.mask.palignr.")) { 1701 Rep = UpgradeX86ALIGNIntrinsics(Builder, CI->getArgOperand(0), 1702 CI->getArgOperand(1), 1703 CI->getArgOperand(2), 1704 CI->getArgOperand(3), 1705 CI->getArgOperand(4), 1706 false); 1707 } else if (IsX86 && Name.startswith("avx512.mask.valign.")) { 1708 Rep = UpgradeX86ALIGNIntrinsics(Builder, CI->getArgOperand(0), 1709 CI->getArgOperand(1), 1710 CI->getArgOperand(2), 1711 CI->getArgOperand(3), 1712 CI->getArgOperand(4), 1713 true); 1714 } else if (IsX86 && (Name == "sse2.psll.dq" || 1715 Name == "avx2.psll.dq")) { 1716 // 128/256-bit shift left specified in bits. 1717 unsigned Shift = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue(); 1718 Rep = UpgradeX86PSLLDQIntrinsics(Builder, CI->getArgOperand(0), 1719 Shift / 8); // Shift is in bits. 1720 } else if (IsX86 && (Name == "sse2.psrl.dq" || 1721 Name == "avx2.psrl.dq")) { 1722 // 128/256-bit shift right specified in bits. 1723 unsigned Shift = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue(); 1724 Rep = UpgradeX86PSRLDQIntrinsics(Builder, CI->getArgOperand(0), 1725 Shift / 8); // Shift is in bits. 1726 } else if (IsX86 && (Name == "sse2.psll.dq.bs" || 1727 Name == "avx2.psll.dq.bs" || 1728 Name == "avx512.psll.dq.512")) { 1729 // 128/256/512-bit shift left specified in bytes. 1730 unsigned Shift = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue(); 1731 Rep = UpgradeX86PSLLDQIntrinsics(Builder, CI->getArgOperand(0), Shift); 1732 } else if (IsX86 && (Name == "sse2.psrl.dq.bs" || 1733 Name == "avx2.psrl.dq.bs" || 1734 Name == "avx512.psrl.dq.512")) { 1735 // 128/256/512-bit shift right specified in bytes. 1736 unsigned Shift = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue(); 1737 Rep = UpgradeX86PSRLDQIntrinsics(Builder, CI->getArgOperand(0), Shift); 1738 } else if (IsX86 && (Name == "sse41.pblendw" || 1739 Name.startswith("sse41.blendp") || 1740 Name.startswith("avx.blend.p") || 1741 Name == "avx2.pblendw" || 1742 Name.startswith("avx2.pblendd."))) { 1743 Value *Op0 = CI->getArgOperand(0); 1744 Value *Op1 = CI->getArgOperand(1); 1745 unsigned Imm = cast <ConstantInt>(CI->getArgOperand(2))->getZExtValue(); 1746 VectorType *VecTy = cast<VectorType>(CI->getType()); 1747 unsigned NumElts = VecTy->getNumElements(); 1748 1749 SmallVector<uint32_t, 16> Idxs(NumElts); 1750 for (unsigned i = 0; i != NumElts; ++i) 1751 Idxs[i] = ((Imm >> (i%8)) & 1) ? i + NumElts : i; 1752 1753 Rep = Builder.CreateShuffleVector(Op0, Op1, Idxs); 1754 } else if (IsX86 && (Name.startswith("avx.vinsertf128.") || 1755 Name == "avx2.vinserti128" || 1756 Name.startswith("avx512.mask.insert"))) { 1757 Value *Op0 = CI->getArgOperand(0); 1758 Value *Op1 = CI->getArgOperand(1); 1759 unsigned Imm = cast<ConstantInt>(CI->getArgOperand(2))->getZExtValue(); 1760 unsigned DstNumElts = CI->getType()->getVectorNumElements(); 1761 unsigned SrcNumElts = Op1->getType()->getVectorNumElements(); 1762 unsigned Scale = DstNumElts / SrcNumElts; 1763 1764 // Mask off the high bits of the immediate value; hardware ignores those. 1765 Imm = Imm % Scale; 1766 1767 // Extend the second operand into a vector the size of the destination. 1768 Value *UndefV = UndefValue::get(Op1->getType()); 1769 SmallVector<uint32_t, 8> Idxs(DstNumElts); 1770 for (unsigned i = 0; i != SrcNumElts; ++i) 1771 Idxs[i] = i; 1772 for (unsigned i = SrcNumElts; i != DstNumElts; ++i) 1773 Idxs[i] = SrcNumElts; 1774 Rep = Builder.CreateShuffleVector(Op1, UndefV, Idxs); 1775 1776 // Insert the second operand into the first operand. 1777 1778 // Note that there is no guarantee that instruction lowering will actually 1779 // produce a vinsertf128 instruction for the created shuffles. In 1780 // particular, the 0 immediate case involves no lane changes, so it can 1781 // be handled as a blend. 1782 1783 // Example of shuffle mask for 32-bit elements: 1784 // Imm = 1 <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11> 1785 // Imm = 0 <i32 8, i32 9, i32 10, i32 11, i32 4, i32 5, i32 6, i32 7 > 1786 1787 // First fill with identify mask. 1788 for (unsigned i = 0; i != DstNumElts; ++i) 1789 Idxs[i] = i; 1790 // Then replace the elements where we need to insert. 1791 for (unsigned i = 0; i != SrcNumElts; ++i) 1792 Idxs[i + Imm * SrcNumElts] = i + DstNumElts; 1793 Rep = Builder.CreateShuffleVector(Op0, Rep, Idxs); 1794 1795 // If the intrinsic has a mask operand, handle that. 1796 if (CI->getNumArgOperands() == 5) 1797 Rep = EmitX86Select(Builder, CI->getArgOperand(4), Rep, 1798 CI->getArgOperand(3)); 1799 } else if (IsX86 && (Name.startswith("avx.vextractf128.") || 1800 Name == "avx2.vextracti128" || 1801 Name.startswith("avx512.mask.vextract"))) { 1802 Value *Op0 = CI->getArgOperand(0); 1803 unsigned Imm = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue(); 1804 unsigned DstNumElts = CI->getType()->getVectorNumElements(); 1805 unsigned SrcNumElts = Op0->getType()->getVectorNumElements(); 1806 unsigned Scale = SrcNumElts / DstNumElts; 1807 1808 // Mask off the high bits of the immediate value; hardware ignores those. 1809 Imm = Imm % Scale; 1810 1811 // Get indexes for the subvector of the input vector. 1812 SmallVector<uint32_t, 8> Idxs(DstNumElts); 1813 for (unsigned i = 0; i != DstNumElts; ++i) { 1814 Idxs[i] = i + (Imm * DstNumElts); 1815 } 1816 Rep = Builder.CreateShuffleVector(Op0, Op0, Idxs); 1817 1818 // If the intrinsic has a mask operand, handle that. 1819 if (CI->getNumArgOperands() == 4) 1820 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1821 CI->getArgOperand(2)); 1822 } else if (!IsX86 && Name == "stackprotectorcheck") { 1823 Rep = nullptr; 1824 } else if (IsX86 && (Name.startswith("avx512.mask.perm.df.") || 1825 Name.startswith("avx512.mask.perm.di."))) { 1826 Value *Op0 = CI->getArgOperand(0); 1827 unsigned Imm = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue(); 1828 VectorType *VecTy = cast<VectorType>(CI->getType()); 1829 unsigned NumElts = VecTy->getNumElements(); 1830 1831 SmallVector<uint32_t, 8> Idxs(NumElts); 1832 for (unsigned i = 0; i != NumElts; ++i) 1833 Idxs[i] = (i & ~0x3) + ((Imm >> (2 * (i & 0x3))) & 3); 1834 1835 Rep = Builder.CreateShuffleVector(Op0, Op0, Idxs); 1836 1837 if (CI->getNumArgOperands() == 4) 1838 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1839 CI->getArgOperand(2)); 1840 } else if (IsX86 && (Name.startswith("avx.vperm2f128.") || 1841 Name == "avx2.vperm2i128")) { 1842 // The immediate permute control byte looks like this: 1843 // [1:0] - select 128 bits from sources for low half of destination 1844 // [2] - ignore 1845 // [3] - zero low half of destination 1846 // [5:4] - select 128 bits from sources for high half of destination 1847 // [6] - ignore 1848 // [7] - zero high half of destination 1849 1850 uint8_t Imm = cast<ConstantInt>(CI->getArgOperand(2))->getZExtValue(); 1851 1852 unsigned NumElts = CI->getType()->getVectorNumElements(); 1853 unsigned HalfSize = NumElts / 2; 1854 SmallVector<uint32_t, 8> ShuffleMask(NumElts); 1855 1856 // Determine which operand(s) are actually in use for this instruction. 1857 Value *V0 = (Imm & 0x02) ? CI->getArgOperand(1) : CI->getArgOperand(0); 1858 Value *V1 = (Imm & 0x20) ? CI->getArgOperand(1) : CI->getArgOperand(0); 1859 1860 // If needed, replace operands based on zero mask. 1861 V0 = (Imm & 0x08) ? ConstantAggregateZero::get(CI->getType()) : V0; 1862 V1 = (Imm & 0x80) ? ConstantAggregateZero::get(CI->getType()) : V1; 1863 1864 // Permute low half of result. 1865 unsigned StartIndex = (Imm & 0x01) ? HalfSize : 0; 1866 for (unsigned i = 0; i < HalfSize; ++i) 1867 ShuffleMask[i] = StartIndex + i; 1868 1869 // Permute high half of result. 1870 StartIndex = (Imm & 0x10) ? HalfSize : 0; 1871 for (unsigned i = 0; i < HalfSize; ++i) 1872 ShuffleMask[i + HalfSize] = NumElts + StartIndex + i; 1873 1874 Rep = Builder.CreateShuffleVector(V0, V1, ShuffleMask); 1875 1876 } else if (IsX86 && (Name.startswith("avx.vpermil.") || 1877 Name == "sse2.pshuf.d" || 1878 Name.startswith("avx512.mask.vpermil.p") || 1879 Name.startswith("avx512.mask.pshuf.d."))) { 1880 Value *Op0 = CI->getArgOperand(0); 1881 unsigned Imm = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue(); 1882 VectorType *VecTy = cast<VectorType>(CI->getType()); 1883 unsigned NumElts = VecTy->getNumElements(); 1884 // Calculate the size of each index in the immediate. 1885 unsigned IdxSize = 64 / VecTy->getScalarSizeInBits(); 1886 unsigned IdxMask = ((1 << IdxSize) - 1); 1887 1888 SmallVector<uint32_t, 8> Idxs(NumElts); 1889 // Lookup the bits for this element, wrapping around the immediate every 1890 // 8-bits. Elements are grouped into sets of 2 or 4 elements so we need 1891 // to offset by the first index of each group. 1892 for (unsigned i = 0; i != NumElts; ++i) 1893 Idxs[i] = ((Imm >> ((i * IdxSize) % 8)) & IdxMask) | (i & ~IdxMask); 1894 1895 Rep = Builder.CreateShuffleVector(Op0, Op0, Idxs); 1896 1897 if (CI->getNumArgOperands() == 4) 1898 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1899 CI->getArgOperand(2)); 1900 } else if (IsX86 && (Name == "sse2.pshufl.w" || 1901 Name.startswith("avx512.mask.pshufl.w."))) { 1902 Value *Op0 = CI->getArgOperand(0); 1903 unsigned Imm = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue(); 1904 unsigned NumElts = CI->getType()->getVectorNumElements(); 1905 1906 SmallVector<uint32_t, 16> Idxs(NumElts); 1907 for (unsigned l = 0; l != NumElts; l += 8) { 1908 for (unsigned i = 0; i != 4; ++i) 1909 Idxs[i + l] = ((Imm >> (2 * i)) & 0x3) + l; 1910 for (unsigned i = 4; i != 8; ++i) 1911 Idxs[i + l] = i + l; 1912 } 1913 1914 Rep = Builder.CreateShuffleVector(Op0, Op0, Idxs); 1915 1916 if (CI->getNumArgOperands() == 4) 1917 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1918 CI->getArgOperand(2)); 1919 } else if (IsX86 && (Name == "sse2.pshufh.w" || 1920 Name.startswith("avx512.mask.pshufh.w."))) { 1921 Value *Op0 = CI->getArgOperand(0); 1922 unsigned Imm = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue(); 1923 unsigned NumElts = CI->getType()->getVectorNumElements(); 1924 1925 SmallVector<uint32_t, 16> Idxs(NumElts); 1926 for (unsigned l = 0; l != NumElts; l += 8) { 1927 for (unsigned i = 0; i != 4; ++i) 1928 Idxs[i + l] = i + l; 1929 for (unsigned i = 0; i != 4; ++i) 1930 Idxs[i + l + 4] = ((Imm >> (2 * i)) & 0x3) + 4 + l; 1931 } 1932 1933 Rep = Builder.CreateShuffleVector(Op0, Op0, Idxs); 1934 1935 if (CI->getNumArgOperands() == 4) 1936 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1937 CI->getArgOperand(2)); 1938 } else if (IsX86 && Name.startswith("avx512.mask.shuf.p")) { 1939 Value *Op0 = CI->getArgOperand(0); 1940 Value *Op1 = CI->getArgOperand(1); 1941 unsigned Imm = cast<ConstantInt>(CI->getArgOperand(2))->getZExtValue(); 1942 unsigned NumElts = CI->getType()->getVectorNumElements(); 1943 1944 unsigned NumLaneElts = 128/CI->getType()->getScalarSizeInBits(); 1945 unsigned HalfLaneElts = NumLaneElts / 2; 1946 1947 SmallVector<uint32_t, 16> Idxs(NumElts); 1948 for (unsigned i = 0; i != NumElts; ++i) { 1949 // Base index is the starting element of the lane. 1950 Idxs[i] = i - (i % NumLaneElts); 1951 // If we are half way through the lane switch to the other source. 1952 if ((i % NumLaneElts) >= HalfLaneElts) 1953 Idxs[i] += NumElts; 1954 // Now select the specific element. By adding HalfLaneElts bits from 1955 // the immediate. Wrapping around the immediate every 8-bits. 1956 Idxs[i] += (Imm >> ((i * HalfLaneElts) % 8)) & ((1 << HalfLaneElts) - 1); 1957 } 1958 1959 Rep = Builder.CreateShuffleVector(Op0, Op1, Idxs); 1960 1961 Rep = EmitX86Select(Builder, CI->getArgOperand(4), Rep, 1962 CI->getArgOperand(3)); 1963 } else if (IsX86 && (Name.startswith("avx512.mask.movddup") || 1964 Name.startswith("avx512.mask.movshdup") || 1965 Name.startswith("avx512.mask.movsldup"))) { 1966 Value *Op0 = CI->getArgOperand(0); 1967 unsigned NumElts = CI->getType()->getVectorNumElements(); 1968 unsigned NumLaneElts = 128/CI->getType()->getScalarSizeInBits(); 1969 1970 unsigned Offset = 0; 1971 if (Name.startswith("avx512.mask.movshdup.")) 1972 Offset = 1; 1973 1974 SmallVector<uint32_t, 16> Idxs(NumElts); 1975 for (unsigned l = 0; l != NumElts; l += NumLaneElts) 1976 for (unsigned i = 0; i != NumLaneElts; i += 2) { 1977 Idxs[i + l + 0] = i + l + Offset; 1978 Idxs[i + l + 1] = i + l + Offset; 1979 } 1980 1981 Rep = Builder.CreateShuffleVector(Op0, Op0, Idxs); 1982 1983 Rep = EmitX86Select(Builder, CI->getArgOperand(2), Rep, 1984 CI->getArgOperand(1)); 1985 } else if (IsX86 && (Name.startswith("avx512.mask.punpckl") || 1986 Name.startswith("avx512.mask.unpckl."))) { 1987 Value *Op0 = CI->getArgOperand(0); 1988 Value *Op1 = CI->getArgOperand(1); 1989 int NumElts = CI->getType()->getVectorNumElements(); 1990 int NumLaneElts = 128/CI->getType()->getScalarSizeInBits(); 1991 1992 SmallVector<uint32_t, 64> Idxs(NumElts); 1993 for (int l = 0; l != NumElts; l += NumLaneElts) 1994 for (int i = 0; i != NumLaneElts; ++i) 1995 Idxs[i + l] = l + (i / 2) + NumElts * (i % 2); 1996 1997 Rep = Builder.CreateShuffleVector(Op0, Op1, Idxs); 1998 1999 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 2000 CI->getArgOperand(2)); 2001 } else if (IsX86 && (Name.startswith("avx512.mask.punpckh") || 2002 Name.startswith("avx512.mask.unpckh."))) { 2003 Value *Op0 = CI->getArgOperand(0); 2004 Value *Op1 = CI->getArgOperand(1); 2005 int NumElts = CI->getType()->getVectorNumElements(); 2006 int NumLaneElts = 128/CI->getType()->getScalarSizeInBits(); 2007 2008 SmallVector<uint32_t, 64> Idxs(NumElts); 2009 for (int l = 0; l != NumElts; l += NumLaneElts) 2010 for (int i = 0; i != NumLaneElts; ++i) 2011 Idxs[i + l] = (NumLaneElts / 2) + l + (i / 2) + NumElts * (i % 2); 2012 2013 Rep = Builder.CreateShuffleVector(Op0, Op1, Idxs); 2014 2015 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 2016 CI->getArgOperand(2)); 2017 } else if (IsX86 && Name.startswith("avx512.mask.pand.")) { 2018 Rep = Builder.CreateAnd(CI->getArgOperand(0), CI->getArgOperand(1)); 2019 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 2020 CI->getArgOperand(2)); 2021 } else if (IsX86 && Name.startswith("avx512.mask.pandn.")) { 2022 Rep = Builder.CreateAnd(Builder.CreateNot(CI->getArgOperand(0)), 2023 CI->getArgOperand(1)); 2024 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 2025 CI->getArgOperand(2)); 2026 } else if (IsX86 && Name.startswith("avx512.mask.por.")) { 2027 Rep = Builder.CreateOr(CI->getArgOperand(0), CI->getArgOperand(1)); 2028 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 2029 CI->getArgOperand(2)); 2030 } else if (IsX86 && Name.startswith("avx512.mask.pxor.")) { 2031 Rep = Builder.CreateXor(CI->getArgOperand(0), CI->getArgOperand(1)); 2032 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 2033 CI->getArgOperand(2)); 2034 } else if (IsX86 && Name.startswith("avx512.mask.and.")) { 2035 VectorType *FTy = cast<VectorType>(CI->getType()); 2036 VectorType *ITy = VectorType::getInteger(FTy); 2037 Rep = Builder.CreateAnd(Builder.CreateBitCast(CI->getArgOperand(0), ITy), 2038 Builder.CreateBitCast(CI->getArgOperand(1), ITy)); 2039 Rep = Builder.CreateBitCast(Rep, FTy); 2040 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 2041 CI->getArgOperand(2)); 2042 } else if (IsX86 && Name.startswith("avx512.mask.andn.")) { 2043 VectorType *FTy = cast<VectorType>(CI->getType()); 2044 VectorType *ITy = VectorType::getInteger(FTy); 2045 Rep = Builder.CreateNot(Builder.CreateBitCast(CI->getArgOperand(0), ITy)); 2046 Rep = Builder.CreateAnd(Rep, 2047 Builder.CreateBitCast(CI->getArgOperand(1), ITy)); 2048 Rep = Builder.CreateBitCast(Rep, FTy); 2049 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 2050 CI->getArgOperand(2)); 2051 } else if (IsX86 && Name.startswith("avx512.mask.or.")) { 2052 VectorType *FTy = cast<VectorType>(CI->getType()); 2053 VectorType *ITy = VectorType::getInteger(FTy); 2054 Rep = Builder.CreateOr(Builder.CreateBitCast(CI->getArgOperand(0), ITy), 2055 Builder.CreateBitCast(CI->getArgOperand(1), ITy)); 2056 Rep = Builder.CreateBitCast(Rep, FTy); 2057 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 2058 CI->getArgOperand(2)); 2059 } else if (IsX86 && Name.startswith("avx512.mask.xor.")) { 2060 VectorType *FTy = cast<VectorType>(CI->getType()); 2061 VectorType *ITy = VectorType::getInteger(FTy); 2062 Rep = Builder.CreateXor(Builder.CreateBitCast(CI->getArgOperand(0), ITy), 2063 Builder.CreateBitCast(CI->getArgOperand(1), ITy)); 2064 Rep = Builder.CreateBitCast(Rep, FTy); 2065 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 2066 CI->getArgOperand(2)); 2067 } else if (IsX86 && Name.startswith("avx512.mask.padd.")) { 2068 Rep = Builder.CreateAdd(CI->getArgOperand(0), CI->getArgOperand(1)); 2069 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 2070 CI->getArgOperand(2)); 2071 } else if (IsX86 && Name.startswith("avx512.mask.psub.")) { 2072 Rep = Builder.CreateSub(CI->getArgOperand(0), CI->getArgOperand(1)); 2073 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 2074 CI->getArgOperand(2)); 2075 } else if (IsX86 && Name.startswith("avx512.mask.pmull.")) { 2076 Rep = Builder.CreateMul(CI->getArgOperand(0), CI->getArgOperand(1)); 2077 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 2078 CI->getArgOperand(2)); 2079 } else if (IsX86 && (Name.startswith("avx512.mask.add.p"))) { 2080 Rep = Builder.CreateFAdd(CI->getArgOperand(0), CI->getArgOperand(1)); 2081 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 2082 CI->getArgOperand(2)); 2083 } else if (IsX86 && Name.startswith("avx512.mask.div.p")) { 2084 Rep = Builder.CreateFDiv(CI->getArgOperand(0), CI->getArgOperand(1)); 2085 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 2086 CI->getArgOperand(2)); 2087 } else if (IsX86 && Name.startswith("avx512.mask.mul.p")) { 2088 Rep = Builder.CreateFMul(CI->getArgOperand(0), CI->getArgOperand(1)); 2089 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 2090 CI->getArgOperand(2)); 2091 } else if (IsX86 && Name.startswith("avx512.mask.sub.p")) { 2092 Rep = Builder.CreateFSub(CI->getArgOperand(0), CI->getArgOperand(1)); 2093 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 2094 CI->getArgOperand(2)); 2095 } else if (IsX86 && Name.startswith("avx512.mask.lzcnt.")) { 2096 Rep = Builder.CreateCall(Intrinsic::getDeclaration(F->getParent(), 2097 Intrinsic::ctlz, 2098 CI->getType()), 2099 { CI->getArgOperand(0), Builder.getInt1(false) }); 2100 Rep = EmitX86Select(Builder, CI->getArgOperand(2), Rep, 2101 CI->getArgOperand(1)); 2102 } else if (IsX86 && Name.startswith("avx512.mask.psll")) { 2103 bool IsImmediate = Name[16] == 'i' || 2104 (Name.size() > 18 && Name[18] == 'i'); 2105 bool IsVariable = Name[16] == 'v'; 2106 char Size = Name[16] == '.' ? Name[17] : 2107 Name[17] == '.' ? Name[18] : 2108 Name[18] == '.' ? Name[19] : 2109 Name[20]; 2110 2111 Intrinsic::ID IID; 2112 if (IsVariable && Name[17] != '.') { 2113 if (Size == 'd' && Name[17] == '2') // avx512.mask.psllv2.di 2114 IID = Intrinsic::x86_avx2_psllv_q; 2115 else if (Size == 'd' && Name[17] == '4') // avx512.mask.psllv4.di 2116 IID = Intrinsic::x86_avx2_psllv_q_256; 2117 else if (Size == 's' && Name[17] == '4') // avx512.mask.psllv4.si 2118 IID = Intrinsic::x86_avx2_psllv_d; 2119 else if (Size == 's' && Name[17] == '8') // avx512.mask.psllv8.si 2120 IID = Intrinsic::x86_avx2_psllv_d_256; 2121 else if (Size == 'h' && Name[17] == '8') // avx512.mask.psllv8.hi 2122 IID = Intrinsic::x86_avx512_psllv_w_128; 2123 else if (Size == 'h' && Name[17] == '1') // avx512.mask.psllv16.hi 2124 IID = Intrinsic::x86_avx512_psllv_w_256; 2125 else if (Name[17] == '3' && Name[18] == '2') // avx512.mask.psllv32hi 2126 IID = Intrinsic::x86_avx512_psllv_w_512; 2127 else 2128 llvm_unreachable("Unexpected size"); 2129 } else if (Name.endswith(".128")) { 2130 if (Size == 'd') // avx512.mask.psll.d.128, avx512.mask.psll.di.128 2131 IID = IsImmediate ? Intrinsic::x86_sse2_pslli_d 2132 : Intrinsic::x86_sse2_psll_d; 2133 else if (Size == 'q') // avx512.mask.psll.q.128, avx512.mask.psll.qi.128 2134 IID = IsImmediate ? Intrinsic::x86_sse2_pslli_q 2135 : Intrinsic::x86_sse2_psll_q; 2136 else if (Size == 'w') // avx512.mask.psll.w.128, avx512.mask.psll.wi.128 2137 IID = IsImmediate ? Intrinsic::x86_sse2_pslli_w 2138 : Intrinsic::x86_sse2_psll_w; 2139 else 2140 llvm_unreachable("Unexpected size"); 2141 } else if (Name.endswith(".256")) { 2142 if (Size == 'd') // avx512.mask.psll.d.256, avx512.mask.psll.di.256 2143 IID = IsImmediate ? Intrinsic::x86_avx2_pslli_d 2144 : Intrinsic::x86_avx2_psll_d; 2145 else if (Size == 'q') // avx512.mask.psll.q.256, avx512.mask.psll.qi.256 2146 IID = IsImmediate ? Intrinsic::x86_avx2_pslli_q 2147 : Intrinsic::x86_avx2_psll_q; 2148 else if (Size == 'w') // avx512.mask.psll.w.256, avx512.mask.psll.wi.256 2149 IID = IsImmediate ? Intrinsic::x86_avx2_pslli_w 2150 : Intrinsic::x86_avx2_psll_w; 2151 else 2152 llvm_unreachable("Unexpected size"); 2153 } else { 2154 if (Size == 'd') // psll.di.512, pslli.d, psll.d, psllv.d.512 2155 IID = IsImmediate ? Intrinsic::x86_avx512_pslli_d_512 : 2156 IsVariable ? Intrinsic::x86_avx512_psllv_d_512 : 2157 Intrinsic::x86_avx512_psll_d_512; 2158 else if (Size == 'q') // psll.qi.512, pslli.q, psll.q, psllv.q.512 2159 IID = IsImmediate ? Intrinsic::x86_avx512_pslli_q_512 : 2160 IsVariable ? Intrinsic::x86_avx512_psllv_q_512 : 2161 Intrinsic::x86_avx512_psll_q_512; 2162 else if (Size == 'w') // psll.wi.512, pslli.w, psll.w 2163 IID = IsImmediate ? Intrinsic::x86_avx512_pslli_w_512 2164 : Intrinsic::x86_avx512_psll_w_512; 2165 else 2166 llvm_unreachable("Unexpected size"); 2167 } 2168 2169 Rep = UpgradeX86MaskedShift(Builder, *CI, IID); 2170 } else if (IsX86 && Name.startswith("avx512.mask.psrl")) { 2171 bool IsImmediate = Name[16] == 'i' || 2172 (Name.size() > 18 && Name[18] == 'i'); 2173 bool IsVariable = Name[16] == 'v'; 2174 char Size = Name[16] == '.' ? Name[17] : 2175 Name[17] == '.' ? Name[18] : 2176 Name[18] == '.' ? Name[19] : 2177 Name[20]; 2178 2179 Intrinsic::ID IID; 2180 if (IsVariable && Name[17] != '.') { 2181 if (Size == 'd' && Name[17] == '2') // avx512.mask.psrlv2.di 2182 IID = Intrinsic::x86_avx2_psrlv_q; 2183 else if (Size == 'd' && Name[17] == '4') // avx512.mask.psrlv4.di 2184 IID = Intrinsic::x86_avx2_psrlv_q_256; 2185 else if (Size == 's' && Name[17] == '4') // avx512.mask.psrlv4.si 2186 IID = Intrinsic::x86_avx2_psrlv_d; 2187 else if (Size == 's' && Name[17] == '8') // avx512.mask.psrlv8.si 2188 IID = Intrinsic::x86_avx2_psrlv_d_256; 2189 else if (Size == 'h' && Name[17] == '8') // avx512.mask.psrlv8.hi 2190 IID = Intrinsic::x86_avx512_psrlv_w_128; 2191 else if (Size == 'h' && Name[17] == '1') // avx512.mask.psrlv16.hi 2192 IID = Intrinsic::x86_avx512_psrlv_w_256; 2193 else if (Name[17] == '3' && Name[18] == '2') // avx512.mask.psrlv32hi 2194 IID = Intrinsic::x86_avx512_psrlv_w_512; 2195 else 2196 llvm_unreachable("Unexpected size"); 2197 } else if (Name.endswith(".128")) { 2198 if (Size == 'd') // avx512.mask.psrl.d.128, avx512.mask.psrl.di.128 2199 IID = IsImmediate ? Intrinsic::x86_sse2_psrli_d 2200 : Intrinsic::x86_sse2_psrl_d; 2201 else if (Size == 'q') // avx512.mask.psrl.q.128, avx512.mask.psrl.qi.128 2202 IID = IsImmediate ? Intrinsic::x86_sse2_psrli_q 2203 : Intrinsic::x86_sse2_psrl_q; 2204 else if (Size == 'w') // avx512.mask.psrl.w.128, avx512.mask.psrl.wi.128 2205 IID = IsImmediate ? Intrinsic::x86_sse2_psrli_w 2206 : Intrinsic::x86_sse2_psrl_w; 2207 else 2208 llvm_unreachable("Unexpected size"); 2209 } else if (Name.endswith(".256")) { 2210 if (Size == 'd') // avx512.mask.psrl.d.256, avx512.mask.psrl.di.256 2211 IID = IsImmediate ? Intrinsic::x86_avx2_psrli_d 2212 : Intrinsic::x86_avx2_psrl_d; 2213 else if (Size == 'q') // avx512.mask.psrl.q.256, avx512.mask.psrl.qi.256 2214 IID = IsImmediate ? Intrinsic::x86_avx2_psrli_q 2215 : Intrinsic::x86_avx2_psrl_q; 2216 else if (Size == 'w') // avx512.mask.psrl.w.256, avx512.mask.psrl.wi.256 2217 IID = IsImmediate ? Intrinsic::x86_avx2_psrli_w 2218 : Intrinsic::x86_avx2_psrl_w; 2219 else 2220 llvm_unreachable("Unexpected size"); 2221 } else { 2222 if (Size == 'd') // psrl.di.512, psrli.d, psrl.d, psrl.d.512 2223 IID = IsImmediate ? Intrinsic::x86_avx512_psrli_d_512 : 2224 IsVariable ? Intrinsic::x86_avx512_psrlv_d_512 : 2225 Intrinsic::x86_avx512_psrl_d_512; 2226 else if (Size == 'q') // psrl.qi.512, psrli.q, psrl.q, psrl.q.512 2227 IID = IsImmediate ? Intrinsic::x86_avx512_psrli_q_512 : 2228 IsVariable ? Intrinsic::x86_avx512_psrlv_q_512 : 2229 Intrinsic::x86_avx512_psrl_q_512; 2230 else if (Size == 'w') // psrl.wi.512, psrli.w, psrl.w) 2231 IID = IsImmediate ? Intrinsic::x86_avx512_psrli_w_512 2232 : Intrinsic::x86_avx512_psrl_w_512; 2233 else 2234 llvm_unreachable("Unexpected size"); 2235 } 2236 2237 Rep = UpgradeX86MaskedShift(Builder, *CI, IID); 2238 } else if (IsX86 && Name.startswith("avx512.mask.psra")) { 2239 bool IsImmediate = Name[16] == 'i' || 2240 (Name.size() > 18 && Name[18] == 'i'); 2241 bool IsVariable = Name[16] == 'v'; 2242 char Size = Name[16] == '.' ? Name[17] : 2243 Name[17] == '.' ? Name[18] : 2244 Name[18] == '.' ? Name[19] : 2245 Name[20]; 2246 2247 Intrinsic::ID IID; 2248 if (IsVariable && Name[17] != '.') { 2249 if (Size == 's' && Name[17] == '4') // avx512.mask.psrav4.si 2250 IID = Intrinsic::x86_avx2_psrav_d; 2251 else if (Size == 's' && Name[17] == '8') // avx512.mask.psrav8.si 2252 IID = Intrinsic::x86_avx2_psrav_d_256; 2253 else if (Size == 'h' && Name[17] == '8') // avx512.mask.psrav8.hi 2254 IID = Intrinsic::x86_avx512_psrav_w_128; 2255 else if (Size == 'h' && Name[17] == '1') // avx512.mask.psrav16.hi 2256 IID = Intrinsic::x86_avx512_psrav_w_256; 2257 else if (Name[17] == '3' && Name[18] == '2') // avx512.mask.psrav32hi 2258 IID = Intrinsic::x86_avx512_psrav_w_512; 2259 else 2260 llvm_unreachable("Unexpected size"); 2261 } else if (Name.endswith(".128")) { 2262 if (Size == 'd') // avx512.mask.psra.d.128, avx512.mask.psra.di.128 2263 IID = IsImmediate ? Intrinsic::x86_sse2_psrai_d 2264 : Intrinsic::x86_sse2_psra_d; 2265 else if (Size == 'q') // avx512.mask.psra.q.128, avx512.mask.psra.qi.128 2266 IID = IsImmediate ? Intrinsic::x86_avx512_psrai_q_128 : 2267 IsVariable ? Intrinsic::x86_avx512_psrav_q_128 : 2268 Intrinsic::x86_avx512_psra_q_128; 2269 else if (Size == 'w') // avx512.mask.psra.w.128, avx512.mask.psra.wi.128 2270 IID = IsImmediate ? Intrinsic::x86_sse2_psrai_w 2271 : Intrinsic::x86_sse2_psra_w; 2272 else 2273 llvm_unreachable("Unexpected size"); 2274 } else if (Name.endswith(".256")) { 2275 if (Size == 'd') // avx512.mask.psra.d.256, avx512.mask.psra.di.256 2276 IID = IsImmediate ? Intrinsic::x86_avx2_psrai_d 2277 : Intrinsic::x86_avx2_psra_d; 2278 else if (Size == 'q') // avx512.mask.psra.q.256, avx512.mask.psra.qi.256 2279 IID = IsImmediate ? Intrinsic::x86_avx512_psrai_q_256 : 2280 IsVariable ? Intrinsic::x86_avx512_psrav_q_256 : 2281 Intrinsic::x86_avx512_psra_q_256; 2282 else if (Size == 'w') // avx512.mask.psra.w.256, avx512.mask.psra.wi.256 2283 IID = IsImmediate ? Intrinsic::x86_avx2_psrai_w 2284 : Intrinsic::x86_avx2_psra_w; 2285 else 2286 llvm_unreachable("Unexpected size"); 2287 } else { 2288 if (Size == 'd') // psra.di.512, psrai.d, psra.d, psrav.d.512 2289 IID = IsImmediate ? Intrinsic::x86_avx512_psrai_d_512 : 2290 IsVariable ? Intrinsic::x86_avx512_psrav_d_512 : 2291 Intrinsic::x86_avx512_psra_d_512; 2292 else if (Size == 'q') // psra.qi.512, psrai.q, psra.q 2293 IID = IsImmediate ? Intrinsic::x86_avx512_psrai_q_512 : 2294 IsVariable ? Intrinsic::x86_avx512_psrav_q_512 : 2295 Intrinsic::x86_avx512_psra_q_512; 2296 else if (Size == 'w') // psra.wi.512, psrai.w, psra.w 2297 IID = IsImmediate ? Intrinsic::x86_avx512_psrai_w_512 2298 : Intrinsic::x86_avx512_psra_w_512; 2299 else 2300 llvm_unreachable("Unexpected size"); 2301 } 2302 2303 Rep = UpgradeX86MaskedShift(Builder, *CI, IID); 2304 } else if (IsX86 && Name.startswith("avx512.mask.move.s")) { 2305 Rep = upgradeMaskedMove(Builder, *CI); 2306 } else if (IsX86 && Name.startswith("avx512.cvtmask2")) { 2307 Rep = UpgradeMaskToInt(Builder, *CI); 2308 } else if (IsX86 && Name.endswith(".movntdqa")) { 2309 Module *M = F->getParent(); 2310 MDNode *Node = MDNode::get( 2311 C, ConstantAsMetadata::get(ConstantInt::get(Type::getInt32Ty(C), 1))); 2312 2313 Value *Ptr = CI->getArgOperand(0); 2314 VectorType *VTy = cast<VectorType>(CI->getType()); 2315 2316 // Convert the type of the pointer to a pointer to the stored type. 2317 Value *BC = 2318 Builder.CreateBitCast(Ptr, PointerType::getUnqual(VTy), "cast"); 2319 LoadInst *LI = Builder.CreateAlignedLoad(BC, VTy->getBitWidth() / 8); 2320 LI->setMetadata(M->getMDKindID("nontemporal"), Node); 2321 Rep = LI; 2322 } else if (IsX86 && 2323 (Name.startswith("sse2.pavg") || Name.startswith("avx2.pavg") || 2324 Name.startswith("avx512.mask.pavg"))) { 2325 // llvm.x86.sse2.pavg.b/w, llvm.x86.avx2.pavg.b/w, 2326 // llvm.x86.avx512.mask.pavg.b/w 2327 Value *A = CI->getArgOperand(0); 2328 Value *B = CI->getArgOperand(1); 2329 VectorType *ZextType = VectorType::getExtendedElementVectorType( 2330 cast<VectorType>(A->getType())); 2331 Value *ExtendedA = Builder.CreateZExt(A, ZextType); 2332 Value *ExtendedB = Builder.CreateZExt(B, ZextType); 2333 Value *Sum = Builder.CreateAdd(ExtendedA, ExtendedB); 2334 Value *AddOne = Builder.CreateAdd(Sum, ConstantInt::get(ZextType, 1)); 2335 Value *ShiftR = Builder.CreateLShr(AddOne, ConstantInt::get(ZextType, 1)); 2336 Rep = Builder.CreateTrunc(ShiftR, A->getType()); 2337 if (CI->getNumArgOperands() > 2) { 2338 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 2339 CI->getArgOperand(2)); 2340 } 2341 } else if (IsX86 && Name.startswith("avx512.mask.") && 2342 upgradeAVX512MaskToSelect(Name, Builder, *CI, Rep)) { 2343 // Rep will be updated by the call in the condition. 2344 } else if (IsNVVM && (Name == "abs.i" || Name == "abs.ll")) { 2345 Value *Arg = CI->getArgOperand(0); 2346 Value *Neg = Builder.CreateNeg(Arg, "neg"); 2347 Value *Cmp = Builder.CreateICmpSGE( 2348 Arg, llvm::Constant::getNullValue(Arg->getType()), "abs.cond"); 2349 Rep = Builder.CreateSelect(Cmp, Arg, Neg, "abs"); 2350 } else if (IsNVVM && (Name == "max.i" || Name == "max.ll" || 2351 Name == "max.ui" || Name == "max.ull")) { 2352 Value *Arg0 = CI->getArgOperand(0); 2353 Value *Arg1 = CI->getArgOperand(1); 2354 Value *Cmp = Name.endswith(".ui") || Name.endswith(".ull") 2355 ? Builder.CreateICmpUGE(Arg0, Arg1, "max.cond") 2356 : Builder.CreateICmpSGE(Arg0, Arg1, "max.cond"); 2357 Rep = Builder.CreateSelect(Cmp, Arg0, Arg1, "max"); 2358 } else if (IsNVVM && (Name == "min.i" || Name == "min.ll" || 2359 Name == "min.ui" || Name == "min.ull")) { 2360 Value *Arg0 = CI->getArgOperand(0); 2361 Value *Arg1 = CI->getArgOperand(1); 2362 Value *Cmp = Name.endswith(".ui") || Name.endswith(".ull") 2363 ? Builder.CreateICmpULE(Arg0, Arg1, "min.cond") 2364 : Builder.CreateICmpSLE(Arg0, Arg1, "min.cond"); 2365 Rep = Builder.CreateSelect(Cmp, Arg0, Arg1, "min"); 2366 } else if (IsNVVM && Name == "clz.ll") { 2367 // llvm.nvvm.clz.ll returns an i32, but llvm.ctlz.i64 and returns an i64. 2368 Value *Arg = CI->getArgOperand(0); 2369 Value *Ctlz = Builder.CreateCall( 2370 Intrinsic::getDeclaration(F->getParent(), Intrinsic::ctlz, 2371 {Arg->getType()}), 2372 {Arg, Builder.getFalse()}, "ctlz"); 2373 Rep = Builder.CreateTrunc(Ctlz, Builder.getInt32Ty(), "ctlz.trunc"); 2374 } else if (IsNVVM && Name == "popc.ll") { 2375 // llvm.nvvm.popc.ll returns an i32, but llvm.ctpop.i64 and returns an 2376 // i64. 2377 Value *Arg = CI->getArgOperand(0); 2378 Value *Popc = Builder.CreateCall( 2379 Intrinsic::getDeclaration(F->getParent(), Intrinsic::ctpop, 2380 {Arg->getType()}), 2381 Arg, "ctpop"); 2382 Rep = Builder.CreateTrunc(Popc, Builder.getInt32Ty(), "ctpop.trunc"); 2383 } else if (IsNVVM && Name == "h2f") { 2384 Rep = Builder.CreateCall(Intrinsic::getDeclaration( 2385 F->getParent(), Intrinsic::convert_from_fp16, 2386 {Builder.getFloatTy()}), 2387 CI->getArgOperand(0), "h2f"); 2388 } else { 2389 llvm_unreachable("Unknown function for CallInst upgrade."); 2390 } 2391 2392 if (Rep) 2393 CI->replaceAllUsesWith(Rep); 2394 CI->eraseFromParent(); 2395 return; 2396 } 2397 2398 const auto &DefaultCase = [&NewFn, &CI]() -> void { 2399 // Handle generic mangling change, but nothing else 2400 assert( 2401 (CI->getCalledFunction()->getName() != NewFn->getName()) && 2402 "Unknown function for CallInst upgrade and isn't just a name change"); 2403 CI->setCalledFunction(NewFn); 2404 }; 2405 CallInst *NewCall = nullptr; 2406 switch (NewFn->getIntrinsicID()) { 2407 default: { 2408 DefaultCase(); 2409 return; 2410 } 2411 2412 case Intrinsic::arm_neon_vld1: 2413 case Intrinsic::arm_neon_vld2: 2414 case Intrinsic::arm_neon_vld3: 2415 case Intrinsic::arm_neon_vld4: 2416 case Intrinsic::arm_neon_vld2lane: 2417 case Intrinsic::arm_neon_vld3lane: 2418 case Intrinsic::arm_neon_vld4lane: 2419 case Intrinsic::arm_neon_vst1: 2420 case Intrinsic::arm_neon_vst2: 2421 case Intrinsic::arm_neon_vst3: 2422 case Intrinsic::arm_neon_vst4: 2423 case Intrinsic::arm_neon_vst2lane: 2424 case Intrinsic::arm_neon_vst3lane: 2425 case Intrinsic::arm_neon_vst4lane: { 2426 SmallVector<Value *, 4> Args(CI->arg_operands().begin(), 2427 CI->arg_operands().end()); 2428 NewCall = Builder.CreateCall(NewFn, Args); 2429 break; 2430 } 2431 2432 case Intrinsic::bitreverse: 2433 NewCall = Builder.CreateCall(NewFn, {CI->getArgOperand(0)}); 2434 break; 2435 2436 case Intrinsic::ctlz: 2437 case Intrinsic::cttz: 2438 assert(CI->getNumArgOperands() == 1 && 2439 "Mismatch between function args and call args"); 2440 NewCall = 2441 Builder.CreateCall(NewFn, {CI->getArgOperand(0), Builder.getFalse()}); 2442 break; 2443 2444 case Intrinsic::objectsize: { 2445 Value *NullIsUnknownSize = CI->getNumArgOperands() == 2 2446 ? Builder.getFalse() 2447 : CI->getArgOperand(2); 2448 NewCall = Builder.CreateCall( 2449 NewFn, {CI->getArgOperand(0), CI->getArgOperand(1), NullIsUnknownSize}); 2450 break; 2451 } 2452 2453 case Intrinsic::ctpop: 2454 NewCall = Builder.CreateCall(NewFn, {CI->getArgOperand(0)}); 2455 break; 2456 2457 case Intrinsic::convert_from_fp16: 2458 NewCall = Builder.CreateCall(NewFn, {CI->getArgOperand(0)}); 2459 break; 2460 2461 case Intrinsic::dbg_value: 2462 // Upgrade from the old version that had an extra offset argument. 2463 assert(CI->getNumArgOperands() == 4); 2464 // Drop nonzero offsets instead of attempting to upgrade them. 2465 if (auto *Offset = dyn_cast_or_null<Constant>(CI->getArgOperand(1))) 2466 if (Offset->isZeroValue()) { 2467 NewCall = Builder.CreateCall( 2468 NewFn, 2469 {CI->getArgOperand(0), CI->getArgOperand(2), CI->getArgOperand(3)}); 2470 break; 2471 } 2472 CI->eraseFromParent(); 2473 return; 2474 2475 case Intrinsic::x86_xop_vfrcz_ss: 2476 case Intrinsic::x86_xop_vfrcz_sd: 2477 NewCall = Builder.CreateCall(NewFn, {CI->getArgOperand(1)}); 2478 break; 2479 2480 case Intrinsic::x86_xop_vpermil2pd: 2481 case Intrinsic::x86_xop_vpermil2ps: 2482 case Intrinsic::x86_xop_vpermil2pd_256: 2483 case Intrinsic::x86_xop_vpermil2ps_256: { 2484 SmallVector<Value *, 4> Args(CI->arg_operands().begin(), 2485 CI->arg_operands().end()); 2486 VectorType *FltIdxTy = cast<VectorType>(Args[2]->getType()); 2487 VectorType *IntIdxTy = VectorType::getInteger(FltIdxTy); 2488 Args[2] = Builder.CreateBitCast(Args[2], IntIdxTy); 2489 NewCall = Builder.CreateCall(NewFn, Args); 2490 break; 2491 } 2492 2493 case Intrinsic::x86_sse41_ptestc: 2494 case Intrinsic::x86_sse41_ptestz: 2495 case Intrinsic::x86_sse41_ptestnzc: { 2496 // The arguments for these intrinsics used to be v4f32, and changed 2497 // to v2i64. This is purely a nop, since those are bitwise intrinsics. 2498 // So, the only thing required is a bitcast for both arguments. 2499 // First, check the arguments have the old type. 2500 Value *Arg0 = CI->getArgOperand(0); 2501 if (Arg0->getType() != VectorType::get(Type::getFloatTy(C), 4)) 2502 return; 2503 2504 // Old intrinsic, add bitcasts 2505 Value *Arg1 = CI->getArgOperand(1); 2506 2507 Type *NewVecTy = VectorType::get(Type::getInt64Ty(C), 2); 2508 2509 Value *BC0 = Builder.CreateBitCast(Arg0, NewVecTy, "cast"); 2510 Value *BC1 = Builder.CreateBitCast(Arg1, NewVecTy, "cast"); 2511 2512 NewCall = Builder.CreateCall(NewFn, {BC0, BC1}); 2513 break; 2514 } 2515 2516 case Intrinsic::x86_sse41_insertps: 2517 case Intrinsic::x86_sse41_dppd: 2518 case Intrinsic::x86_sse41_dpps: 2519 case Intrinsic::x86_sse41_mpsadbw: 2520 case Intrinsic::x86_avx_dp_ps_256: 2521 case Intrinsic::x86_avx2_mpsadbw: { 2522 // Need to truncate the last argument from i32 to i8 -- this argument models 2523 // an inherently 8-bit immediate operand to these x86 instructions. 2524 SmallVector<Value *, 4> Args(CI->arg_operands().begin(), 2525 CI->arg_operands().end()); 2526 2527 // Replace the last argument with a trunc. 2528 Args.back() = Builder.CreateTrunc(Args.back(), Type::getInt8Ty(C), "trunc"); 2529 NewCall = Builder.CreateCall(NewFn, Args); 2530 break; 2531 } 2532 2533 case Intrinsic::x86_avx512_mask_cmp_pd_128: 2534 case Intrinsic::x86_avx512_mask_cmp_pd_256: 2535 case Intrinsic::x86_avx512_mask_cmp_pd_512: 2536 case Intrinsic::x86_avx512_mask_cmp_ps_128: 2537 case Intrinsic::x86_avx512_mask_cmp_ps_256: 2538 case Intrinsic::x86_avx512_mask_cmp_ps_512: { 2539 SmallVector<Value *, 4> Args; 2540 Args.push_back(CI->getArgOperand(0)); 2541 Args.push_back(CI->getArgOperand(1)); 2542 Args.push_back(CI->getArgOperand(2)); 2543 if (CI->getNumArgOperands() == 5) 2544 Args.push_back(CI->getArgOperand(4)); 2545 2546 NewCall = Builder.CreateCall(NewFn, Args); 2547 unsigned NumElts = Args[0]->getType()->getVectorNumElements(); 2548 Value *Res = ApplyX86MaskOn1BitsVec(Builder, NewCall, CI->getArgOperand(3), 2549 NumElts); 2550 2551 std::string Name = CI->getName(); 2552 if (!Name.empty()) { 2553 CI->setName(Name + ".old"); 2554 NewCall->setName(Name); 2555 } 2556 CI->replaceAllUsesWith(Res); 2557 CI->eraseFromParent(); 2558 return; 2559 } 2560 2561 case Intrinsic::thread_pointer: { 2562 NewCall = Builder.CreateCall(NewFn, {}); 2563 break; 2564 } 2565 2566 case Intrinsic::invariant_start: 2567 case Intrinsic::invariant_end: 2568 case Intrinsic::masked_load: 2569 case Intrinsic::masked_store: 2570 case Intrinsic::masked_gather: 2571 case Intrinsic::masked_scatter: { 2572 SmallVector<Value *, 4> Args(CI->arg_operands().begin(), 2573 CI->arg_operands().end()); 2574 NewCall = Builder.CreateCall(NewFn, Args); 2575 break; 2576 } 2577 2578 case Intrinsic::memcpy: 2579 case Intrinsic::memmove: 2580 case Intrinsic::memset: { 2581 // We have to make sure that the call signature is what we're expecting. 2582 // We only want to change the old signatures by removing the alignment arg: 2583 // @llvm.mem[cpy|move]...(i8*, i8*, i[32|i64], i32, i1) 2584 // -> @llvm.mem[cpy|move]...(i8*, i8*, i[32|i64], i1) 2585 // @llvm.memset...(i8*, i8, i[32|64], i32, i1) 2586 // -> @llvm.memset...(i8*, i8, i[32|64], i1) 2587 // Note: i8*'s in the above can be any pointer type 2588 if (CI->getNumArgOperands() != 5) { 2589 DefaultCase(); 2590 return; 2591 } 2592 // Remove alignment argument (3), and add alignment attributes to the 2593 // dest/src pointers. 2594 Value *Args[4] = {CI->getArgOperand(0), CI->getArgOperand(1), 2595 CI->getArgOperand(2), CI->getArgOperand(4)}; 2596 NewCall = Builder.CreateCall(NewFn, Args); 2597 auto *MemCI = cast<MemIntrinsic>(NewCall); 2598 // All mem intrinsics support dest alignment. 2599 const ConstantInt *Align = cast<ConstantInt>(CI->getArgOperand(3)); 2600 MemCI->setDestAlignment(Align->getZExtValue()); 2601 // Memcpy/Memmove also support source alignment. 2602 if (auto *MTI = dyn_cast<MemTransferInst>(MemCI)) 2603 MTI->setSourceAlignment(Align->getZExtValue()); 2604 break; 2605 } 2606 } 2607 assert(NewCall && "Should have either set this variable or returned through " 2608 "the default case"); 2609 std::string Name = CI->getName(); 2610 if (!Name.empty()) { 2611 CI->setName(Name + ".old"); 2612 NewCall->setName(Name); 2613 } 2614 CI->replaceAllUsesWith(NewCall); 2615 CI->eraseFromParent(); 2616 } 2617 2618 void llvm::UpgradeCallsToIntrinsic(Function *F) { 2619 assert(F && "Illegal attempt to upgrade a non-existent intrinsic."); 2620 2621 // Check if this function should be upgraded and get the replacement function 2622 // if there is one. 2623 Function *NewFn; 2624 if (UpgradeIntrinsicFunction(F, NewFn)) { 2625 // Replace all users of the old function with the new function or new 2626 // instructions. This is not a range loop because the call is deleted. 2627 for (auto UI = F->user_begin(), UE = F->user_end(); UI != UE; ) 2628 if (CallInst *CI = dyn_cast<CallInst>(*UI++)) 2629 UpgradeIntrinsicCall(CI, NewFn); 2630 2631 // Remove old function, no longer used, from the module. 2632 F->eraseFromParent(); 2633 } 2634 } 2635 2636 MDNode *llvm::UpgradeTBAANode(MDNode &MD) { 2637 // Check if the tag uses struct-path aware TBAA format. 2638 if (isa<MDNode>(MD.getOperand(0)) && MD.getNumOperands() >= 3) 2639 return &MD; 2640 2641 auto &Context = MD.getContext(); 2642 if (MD.getNumOperands() == 3) { 2643 Metadata *Elts[] = {MD.getOperand(0), MD.getOperand(1)}; 2644 MDNode *ScalarType = MDNode::get(Context, Elts); 2645 // Create a MDNode <ScalarType, ScalarType, offset 0, const> 2646 Metadata *Elts2[] = {ScalarType, ScalarType, 2647 ConstantAsMetadata::get( 2648 Constant::getNullValue(Type::getInt64Ty(Context))), 2649 MD.getOperand(2)}; 2650 return MDNode::get(Context, Elts2); 2651 } 2652 // Create a MDNode <MD, MD, offset 0> 2653 Metadata *Elts[] = {&MD, &MD, ConstantAsMetadata::get(Constant::getNullValue( 2654 Type::getInt64Ty(Context)))}; 2655 return MDNode::get(Context, Elts); 2656 } 2657 2658 Instruction *llvm::UpgradeBitCastInst(unsigned Opc, Value *V, Type *DestTy, 2659 Instruction *&Temp) { 2660 if (Opc != Instruction::BitCast) 2661 return nullptr; 2662 2663 Temp = nullptr; 2664 Type *SrcTy = V->getType(); 2665 if (SrcTy->isPtrOrPtrVectorTy() && DestTy->isPtrOrPtrVectorTy() && 2666 SrcTy->getPointerAddressSpace() != DestTy->getPointerAddressSpace()) { 2667 LLVMContext &Context = V->getContext(); 2668 2669 // We have no information about target data layout, so we assume that 2670 // the maximum pointer size is 64bit. 2671 Type *MidTy = Type::getInt64Ty(Context); 2672 Temp = CastInst::Create(Instruction::PtrToInt, V, MidTy); 2673 2674 return CastInst::Create(Instruction::IntToPtr, Temp, DestTy); 2675 } 2676 2677 return nullptr; 2678 } 2679 2680 Value *llvm::UpgradeBitCastExpr(unsigned Opc, Constant *C, Type *DestTy) { 2681 if (Opc != Instruction::BitCast) 2682 return nullptr; 2683 2684 Type *SrcTy = C->getType(); 2685 if (SrcTy->isPtrOrPtrVectorTy() && DestTy->isPtrOrPtrVectorTy() && 2686 SrcTy->getPointerAddressSpace() != DestTy->getPointerAddressSpace()) { 2687 LLVMContext &Context = C->getContext(); 2688 2689 // We have no information about target data layout, so we assume that 2690 // the maximum pointer size is 64bit. 2691 Type *MidTy = Type::getInt64Ty(Context); 2692 2693 return ConstantExpr::getIntToPtr(ConstantExpr::getPtrToInt(C, MidTy), 2694 DestTy); 2695 } 2696 2697 return nullptr; 2698 } 2699 2700 /// Check the debug info version number, if it is out-dated, drop the debug 2701 /// info. Return true if module is modified. 2702 bool llvm::UpgradeDebugInfo(Module &M) { 2703 unsigned Version = getDebugMetadataVersionFromModule(M); 2704 if (Version == DEBUG_METADATA_VERSION) { 2705 bool BrokenDebugInfo = false; 2706 if (verifyModule(M, &llvm::errs(), &BrokenDebugInfo)) 2707 report_fatal_error("Broken module found, compilation aborted!"); 2708 if (!BrokenDebugInfo) 2709 // Everything is ok. 2710 return false; 2711 else { 2712 // Diagnose malformed debug info. 2713 DiagnosticInfoIgnoringInvalidDebugMetadata Diag(M); 2714 M.getContext().diagnose(Diag); 2715 } 2716 } 2717 bool Modified = StripDebugInfo(M); 2718 if (Modified && Version != DEBUG_METADATA_VERSION) { 2719 // Diagnose a version mismatch. 2720 DiagnosticInfoDebugMetadataVersion DiagVersion(M, Version); 2721 M.getContext().diagnose(DiagVersion); 2722 } 2723 return Modified; 2724 } 2725 2726 bool llvm::UpgradeRetainReleaseMarker(Module &M) { 2727 bool Changed = false; 2728 NamedMDNode *ModRetainReleaseMarker = 2729 M.getNamedMetadata("clang.arc.retainAutoreleasedReturnValueMarker"); 2730 if (ModRetainReleaseMarker) { 2731 MDNode *Op = ModRetainReleaseMarker->getOperand(0); 2732 if (Op) { 2733 MDString *ID = dyn_cast_or_null<MDString>(Op->getOperand(0)); 2734 if (ID) { 2735 SmallVector<StringRef, 4> ValueComp; 2736 ID->getString().split(ValueComp, "#"); 2737 if (ValueComp.size() == 2) { 2738 std::string NewValue = ValueComp[0].str() + ";" + ValueComp[1].str(); 2739 Metadata *Ops[1] = {MDString::get(M.getContext(), NewValue)}; 2740 ModRetainReleaseMarker->setOperand(0, 2741 MDNode::get(M.getContext(), Ops)); 2742 Changed = true; 2743 } 2744 } 2745 } 2746 } 2747 return Changed; 2748 } 2749 2750 bool llvm::UpgradeModuleFlags(Module &M) { 2751 NamedMDNode *ModFlags = M.getModuleFlagsMetadata(); 2752 if (!ModFlags) 2753 return false; 2754 2755 bool HasObjCFlag = false, HasClassProperties = false, Changed = false; 2756 for (unsigned I = 0, E = ModFlags->getNumOperands(); I != E; ++I) { 2757 MDNode *Op = ModFlags->getOperand(I); 2758 if (Op->getNumOperands() != 3) 2759 continue; 2760 MDString *ID = dyn_cast_or_null<MDString>(Op->getOperand(1)); 2761 if (!ID) 2762 continue; 2763 if (ID->getString() == "Objective-C Image Info Version") 2764 HasObjCFlag = true; 2765 if (ID->getString() == "Objective-C Class Properties") 2766 HasClassProperties = true; 2767 // Upgrade PIC/PIE Module Flags. The module flag behavior for these two 2768 // field was Error and now they are Max. 2769 if (ID->getString() == "PIC Level" || ID->getString() == "PIE Level") { 2770 if (auto *Behavior = 2771 mdconst::dyn_extract_or_null<ConstantInt>(Op->getOperand(0))) { 2772 if (Behavior->getLimitedValue() == Module::Error) { 2773 Type *Int32Ty = Type::getInt32Ty(M.getContext()); 2774 Metadata *Ops[3] = { 2775 ConstantAsMetadata::get(ConstantInt::get(Int32Ty, Module::Max)), 2776 MDString::get(M.getContext(), ID->getString()), 2777 Op->getOperand(2)}; 2778 ModFlags->setOperand(I, MDNode::get(M.getContext(), Ops)); 2779 Changed = true; 2780 } 2781 } 2782 } 2783 // Upgrade Objective-C Image Info Section. Removed the whitespce in the 2784 // section name so that llvm-lto will not complain about mismatching 2785 // module flags that is functionally the same. 2786 if (ID->getString() == "Objective-C Image Info Section") { 2787 if (auto *Value = dyn_cast_or_null<MDString>(Op->getOperand(2))) { 2788 SmallVector<StringRef, 4> ValueComp; 2789 Value->getString().split(ValueComp, " "); 2790 if (ValueComp.size() != 1) { 2791 std::string NewValue; 2792 for (auto &S : ValueComp) 2793 NewValue += S.str(); 2794 Metadata *Ops[3] = {Op->getOperand(0), Op->getOperand(1), 2795 MDString::get(M.getContext(), NewValue)}; 2796 ModFlags->setOperand(I, MDNode::get(M.getContext(), Ops)); 2797 Changed = true; 2798 } 2799 } 2800 } 2801 } 2802 2803 // "Objective-C Class Properties" is recently added for Objective-C. We 2804 // upgrade ObjC bitcodes to contain a "Objective-C Class Properties" module 2805 // flag of value 0, so we can correclty downgrade this flag when trying to 2806 // link an ObjC bitcode without this module flag with an ObjC bitcode with 2807 // this module flag. 2808 if (HasObjCFlag && !HasClassProperties) { 2809 M.addModuleFlag(llvm::Module::Override, "Objective-C Class Properties", 2810 (uint32_t)0); 2811 Changed = true; 2812 } 2813 2814 return Changed; 2815 } 2816 2817 void llvm::UpgradeSectionAttributes(Module &M) { 2818 auto TrimSpaces = [](StringRef Section) -> std::string { 2819 SmallVector<StringRef, 5> Components; 2820 Section.split(Components, ','); 2821 2822 SmallString<32> Buffer; 2823 raw_svector_ostream OS(Buffer); 2824 2825 for (auto Component : Components) 2826 OS << ',' << Component.trim(); 2827 2828 return OS.str().substr(1); 2829 }; 2830 2831 for (auto &GV : M.globals()) { 2832 if (!GV.hasSection()) 2833 continue; 2834 2835 StringRef Section = GV.getSection(); 2836 2837 if (!Section.startswith("__DATA, __objc_catlist")) 2838 continue; 2839 2840 // __DATA, __objc_catlist, regular, no_dead_strip 2841 // __DATA,__objc_catlist,regular,no_dead_strip 2842 GV.setSection(TrimSpaces(Section)); 2843 } 2844 } 2845 2846 static bool isOldLoopArgument(Metadata *MD) { 2847 auto *T = dyn_cast_or_null<MDTuple>(MD); 2848 if (!T) 2849 return false; 2850 if (T->getNumOperands() < 1) 2851 return false; 2852 auto *S = dyn_cast_or_null<MDString>(T->getOperand(0)); 2853 if (!S) 2854 return false; 2855 return S->getString().startswith("llvm.vectorizer."); 2856 } 2857 2858 static MDString *upgradeLoopTag(LLVMContext &C, StringRef OldTag) { 2859 StringRef OldPrefix = "llvm.vectorizer."; 2860 assert(OldTag.startswith(OldPrefix) && "Expected old prefix"); 2861 2862 if (OldTag == "llvm.vectorizer.unroll") 2863 return MDString::get(C, "llvm.loop.interleave.count"); 2864 2865 return MDString::get( 2866 C, (Twine("llvm.loop.vectorize.") + OldTag.drop_front(OldPrefix.size())) 2867 .str()); 2868 } 2869 2870 static Metadata *upgradeLoopArgument(Metadata *MD) { 2871 auto *T = dyn_cast_or_null<MDTuple>(MD); 2872 if (!T) 2873 return MD; 2874 if (T->getNumOperands() < 1) 2875 return MD; 2876 auto *OldTag = dyn_cast_or_null<MDString>(T->getOperand(0)); 2877 if (!OldTag) 2878 return MD; 2879 if (!OldTag->getString().startswith("llvm.vectorizer.")) 2880 return MD; 2881 2882 // This has an old tag. Upgrade it. 2883 SmallVector<Metadata *, 8> Ops; 2884 Ops.reserve(T->getNumOperands()); 2885 Ops.push_back(upgradeLoopTag(T->getContext(), OldTag->getString())); 2886 for (unsigned I = 1, E = T->getNumOperands(); I != E; ++I) 2887 Ops.push_back(T->getOperand(I)); 2888 2889 return MDTuple::get(T->getContext(), Ops); 2890 } 2891 2892 MDNode *llvm::upgradeInstructionLoopAttachment(MDNode &N) { 2893 auto *T = dyn_cast<MDTuple>(&N); 2894 if (!T) 2895 return &N; 2896 2897 if (none_of(T->operands(), isOldLoopArgument)) 2898 return &N; 2899 2900 SmallVector<Metadata *, 8> Ops; 2901 Ops.reserve(T->getNumOperands()); 2902 for (Metadata *MD : T->operands()) 2903 Ops.push_back(upgradeLoopArgument(MD)); 2904 2905 return MDTuple::get(T->getContext(), Ops); 2906 } 2907