1 //===-- AutoUpgrade.cpp - Implement auto-upgrade helper functions ---------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements the auto-upgrade helper functions. 11 // This is where deprecated IR intrinsics and other IR features are updated to 12 // current specifications. 13 // 14 //===----------------------------------------------------------------------===// 15 16 #include "llvm/IR/AutoUpgrade.h" 17 #include "llvm/ADT/StringSwitch.h" 18 #include "llvm/IR/Constants.h" 19 #include "llvm/IR/DIBuilder.h" 20 #include "llvm/IR/DebugInfo.h" 21 #include "llvm/IR/DiagnosticInfo.h" 22 #include "llvm/IR/Function.h" 23 #include "llvm/IR/IRBuilder.h" 24 #include "llvm/IR/Instruction.h" 25 #include "llvm/IR/IntrinsicInst.h" 26 #include "llvm/IR/LLVMContext.h" 27 #include "llvm/IR/Module.h" 28 #include "llvm/IR/Verifier.h" 29 #include "llvm/Support/ErrorHandling.h" 30 #include "llvm/Support/Regex.h" 31 #include <cstring> 32 using namespace llvm; 33 34 static void rename(GlobalValue *GV) { GV->setName(GV->getName() + ".old"); } 35 36 // Upgrade the declarations of the SSE4.1 ptest intrinsics whose arguments have 37 // changed their type from v4f32 to v2i64. 38 static bool UpgradePTESTIntrinsic(Function* F, Intrinsic::ID IID, 39 Function *&NewFn) { 40 // Check whether this is an old version of the function, which received 41 // v4f32 arguments. 42 Type *Arg0Type = F->getFunctionType()->getParamType(0); 43 if (Arg0Type != VectorType::get(Type::getFloatTy(F->getContext()), 4)) 44 return false; 45 46 // Yes, it's old, replace it with new version. 47 rename(F); 48 NewFn = Intrinsic::getDeclaration(F->getParent(), IID); 49 return true; 50 } 51 52 // Upgrade the declarations of intrinsic functions whose 8-bit immediate mask 53 // arguments have changed their type from i32 to i8. 54 static bool UpgradeX86IntrinsicsWith8BitMask(Function *F, Intrinsic::ID IID, 55 Function *&NewFn) { 56 // Check that the last argument is an i32. 57 Type *LastArgType = F->getFunctionType()->getParamType( 58 F->getFunctionType()->getNumParams() - 1); 59 if (!LastArgType->isIntegerTy(32)) 60 return false; 61 62 // Move this function aside and map down. 63 rename(F); 64 NewFn = Intrinsic::getDeclaration(F->getParent(), IID); 65 return true; 66 } 67 68 // Upgrade the declaration of fp compare intrinsics that change return type 69 // from scalar to vXi1 mask. 70 static bool UpgradeX86MaskedFPCompare(Function *F, Intrinsic::ID IID, 71 Function *&NewFn) { 72 // Check if the return type is a vector. 73 if (F->getReturnType()->isVectorTy()) 74 return false; 75 76 rename(F); 77 NewFn = Intrinsic::getDeclaration(F->getParent(), IID); 78 return true; 79 } 80 81 static bool ShouldUpgradeX86Intrinsic(Function *F, StringRef Name) { 82 // All of the intrinsics matches below should be marked with which llvm 83 // version started autoupgrading them. At some point in the future we would 84 // like to use this information to remove upgrade code for some older 85 // intrinsics. It is currently undecided how we will determine that future 86 // point. 87 if (Name=="ssse3.pabs.b.128" || // Added in 6.0 88 Name=="ssse3.pabs.w.128" || // Added in 6.0 89 Name=="ssse3.pabs.d.128" || // Added in 6.0 90 Name.startswith("avx512.mask.shuf.i") || // Added in 6.0 91 Name.startswith("avx512.mask.shuf.f") || // Added in 6.0 92 Name.startswith("avx512.kunpck") || //added in 6.0 93 Name.startswith("avx2.pabs.") || // Added in 6.0 94 Name.startswith("avx512.mask.pabs.") || // Added in 6.0 95 Name.startswith("avx512.broadcastm") || // Added in 6.0 96 Name.startswith("avx512.mask.pbroadcast") || // Added in 6.0 97 Name.startswith("sse2.pcmpeq.") || // Added in 3.1 98 Name.startswith("sse2.pcmpgt.") || // Added in 3.1 99 Name.startswith("avx2.pcmpeq.") || // Added in 3.1 100 Name.startswith("avx2.pcmpgt.") || // Added in 3.1 101 Name.startswith("avx512.mask.pcmpeq.") || // Added in 3.9 102 Name.startswith("avx512.mask.pcmpgt.") || // Added in 3.9 103 Name.startswith("avx.vperm2f128.") || // Added in 6.0 104 Name == "avx2.vperm2i128" || // Added in 6.0 105 Name == "sse.add.ss" || // Added in 4.0 106 Name == "sse2.add.sd" || // Added in 4.0 107 Name == "sse.sub.ss" || // Added in 4.0 108 Name == "sse2.sub.sd" || // Added in 4.0 109 Name == "sse.mul.ss" || // Added in 4.0 110 Name == "sse2.mul.sd" || // Added in 4.0 111 Name == "sse.div.ss" || // Added in 4.0 112 Name == "sse2.div.sd" || // Added in 4.0 113 Name == "sse41.pmaxsb" || // Added in 3.9 114 Name == "sse2.pmaxs.w" || // Added in 3.9 115 Name == "sse41.pmaxsd" || // Added in 3.9 116 Name == "sse2.pmaxu.b" || // Added in 3.9 117 Name == "sse41.pmaxuw" || // Added in 3.9 118 Name == "sse41.pmaxud" || // Added in 3.9 119 Name == "sse41.pminsb" || // Added in 3.9 120 Name == "sse2.pmins.w" || // Added in 3.9 121 Name == "sse41.pminsd" || // Added in 3.9 122 Name == "sse2.pminu.b" || // Added in 3.9 123 Name == "sse41.pminuw" || // Added in 3.9 124 Name == "sse41.pminud" || // Added in 3.9 125 Name == "avx512.kand.w" || // Added in 7.0 126 Name == "avx512.kandn.w" || // Added in 7.0 127 Name == "avx512.knot.w" || // Added in 7.0 128 Name == "avx512.kor.w" || // Added in 7.0 129 Name == "avx512.kxor.w" || // Added in 7.0 130 Name == "avx512.kxnor.w" || // Added in 7.0 131 Name == "avx512.kortestc.w" || // Added in 7.0 132 Name == "avx512.kortestz.w" || // Added in 7.0 133 Name.startswith("avx512.mask.pshuf.b.") || // Added in 4.0 134 Name.startswith("avx2.pmax") || // Added in 3.9 135 Name.startswith("avx2.pmin") || // Added in 3.9 136 Name.startswith("avx512.mask.pmax") || // Added in 4.0 137 Name.startswith("avx512.mask.pmin") || // Added in 4.0 138 Name.startswith("avx2.vbroadcast") || // Added in 3.8 139 Name.startswith("avx2.pbroadcast") || // Added in 3.8 140 Name.startswith("avx.vpermil.") || // Added in 3.1 141 Name.startswith("sse2.pshuf") || // Added in 3.9 142 Name.startswith("avx512.pbroadcast") || // Added in 3.9 143 Name.startswith("avx512.mask.broadcast.s") || // Added in 3.9 144 Name.startswith("avx512.mask.movddup") || // Added in 3.9 145 Name.startswith("avx512.mask.movshdup") || // Added in 3.9 146 Name.startswith("avx512.mask.movsldup") || // Added in 3.9 147 Name.startswith("avx512.mask.pshuf.d.") || // Added in 3.9 148 Name.startswith("avx512.mask.pshufl.w.") || // Added in 3.9 149 Name.startswith("avx512.mask.pshufh.w.") || // Added in 3.9 150 Name.startswith("avx512.mask.shuf.p") || // Added in 4.0 151 Name.startswith("avx512.mask.vpermil.p") || // Added in 3.9 152 Name.startswith("avx512.mask.perm.df.") || // Added in 3.9 153 Name.startswith("avx512.mask.perm.di.") || // Added in 3.9 154 Name.startswith("avx512.mask.punpckl") || // Added in 3.9 155 Name.startswith("avx512.mask.punpckh") || // Added in 3.9 156 Name.startswith("avx512.mask.unpckl.") || // Added in 3.9 157 Name.startswith("avx512.mask.unpckh.") || // Added in 3.9 158 Name.startswith("avx512.mask.pand.") || // Added in 3.9 159 Name.startswith("avx512.mask.pandn.") || // Added in 3.9 160 Name.startswith("avx512.mask.por.") || // Added in 3.9 161 Name.startswith("avx512.mask.pxor.") || // Added in 3.9 162 Name.startswith("avx512.mask.and.") || // Added in 3.9 163 Name.startswith("avx512.mask.andn.") || // Added in 3.9 164 Name.startswith("avx512.mask.or.") || // Added in 3.9 165 Name.startswith("avx512.mask.xor.") || // Added in 3.9 166 Name.startswith("avx512.mask.padd.") || // Added in 4.0 167 Name.startswith("avx512.mask.psub.") || // Added in 4.0 168 Name.startswith("avx512.mask.pmull.") || // Added in 4.0 169 Name.startswith("avx512.mask.cvtdq2pd.") || // Added in 4.0 170 Name.startswith("avx512.mask.cvtudq2pd.") || // Added in 4.0 171 Name.startswith("avx512.mask.pmul.dq.") || // Added in 4.0 172 Name.startswith("avx512.mask.pmulu.dq.") || // Added in 4.0 173 Name.startswith("avx512.mask.pmul.hr.sw.") || // Added in 7.0 174 Name.startswith("avx512.mask.pmulh.w.") || // Added in 7.0 175 Name.startswith("avx512.mask.pmulhu.w.") || // Added in 7.0 176 Name.startswith("avx512.mask.packsswb.") || // Added in 5.0 177 Name.startswith("avx512.mask.packssdw.") || // Added in 5.0 178 Name.startswith("avx512.mask.packuswb.") || // Added in 5.0 179 Name.startswith("avx512.mask.packusdw.") || // Added in 5.0 180 Name.startswith("avx512.mask.cmp.b") || // Added in 5.0 181 Name.startswith("avx512.mask.cmp.d") || // Added in 5.0 182 Name.startswith("avx512.mask.cmp.q") || // Added in 5.0 183 Name.startswith("avx512.mask.cmp.w") || // Added in 5.0 184 Name.startswith("avx512.mask.ucmp.") || // Added in 5.0 185 Name.startswith("avx512.cvtb2mask.") || // Added in 7.0 186 Name.startswith("avx512.cvtw2mask.") || // Added in 7.0 187 Name.startswith("avx512.cvtd2mask.") || // Added in 7.0 188 Name.startswith("avx512.cvtq2mask.") || // Added in 7.0 189 Name == "avx512.mask.add.pd.128" || // Added in 4.0 190 Name == "avx512.mask.add.pd.256" || // Added in 4.0 191 Name == "avx512.mask.add.ps.128" || // Added in 4.0 192 Name == "avx512.mask.add.ps.256" || // Added in 4.0 193 Name == "avx512.mask.div.pd.128" || // Added in 4.0 194 Name == "avx512.mask.div.pd.256" || // Added in 4.0 195 Name == "avx512.mask.div.ps.128" || // Added in 4.0 196 Name == "avx512.mask.div.ps.256" || // Added in 4.0 197 Name == "avx512.mask.mul.pd.128" || // Added in 4.0 198 Name == "avx512.mask.mul.pd.256" || // Added in 4.0 199 Name == "avx512.mask.mul.ps.128" || // Added in 4.0 200 Name == "avx512.mask.mul.ps.256" || // Added in 4.0 201 Name == "avx512.mask.sub.pd.128" || // Added in 4.0 202 Name == "avx512.mask.sub.pd.256" || // Added in 4.0 203 Name == "avx512.mask.sub.ps.128" || // Added in 4.0 204 Name == "avx512.mask.sub.ps.256" || // Added in 4.0 205 Name == "avx512.mask.max.pd.128" || // Added in 5.0 206 Name == "avx512.mask.max.pd.256" || // Added in 5.0 207 Name == "avx512.mask.max.ps.128" || // Added in 5.0 208 Name == "avx512.mask.max.ps.256" || // Added in 5.0 209 Name == "avx512.mask.min.pd.128" || // Added in 5.0 210 Name == "avx512.mask.min.pd.256" || // Added in 5.0 211 Name == "avx512.mask.min.ps.128" || // Added in 5.0 212 Name == "avx512.mask.min.ps.256" || // Added in 5.0 213 Name.startswith("avx512.mask.vpermilvar.") || // Added in 4.0 214 Name.startswith("avx512.mask.psll.d") || // Added in 4.0 215 Name.startswith("avx512.mask.psll.q") || // Added in 4.0 216 Name.startswith("avx512.mask.psll.w") || // Added in 4.0 217 Name.startswith("avx512.mask.psra.d") || // Added in 4.0 218 Name.startswith("avx512.mask.psra.q") || // Added in 4.0 219 Name.startswith("avx512.mask.psra.w") || // Added in 4.0 220 Name.startswith("avx512.mask.psrl.d") || // Added in 4.0 221 Name.startswith("avx512.mask.psrl.q") || // Added in 4.0 222 Name.startswith("avx512.mask.psrl.w") || // Added in 4.0 223 Name.startswith("avx512.mask.pslli") || // Added in 4.0 224 Name.startswith("avx512.mask.psrai") || // Added in 4.0 225 Name.startswith("avx512.mask.psrli") || // Added in 4.0 226 Name.startswith("avx512.mask.psllv") || // Added in 4.0 227 Name.startswith("avx512.mask.psrav") || // Added in 4.0 228 Name.startswith("avx512.mask.psrlv") || // Added in 4.0 229 Name.startswith("sse41.pmovsx") || // Added in 3.8 230 Name.startswith("sse41.pmovzx") || // Added in 3.9 231 Name.startswith("avx2.pmovsx") || // Added in 3.9 232 Name.startswith("avx2.pmovzx") || // Added in 3.9 233 Name.startswith("avx512.mask.pmovsx") || // Added in 4.0 234 Name.startswith("avx512.mask.pmovzx") || // Added in 4.0 235 Name.startswith("avx512.mask.lzcnt.") || // Added in 5.0 236 Name == "sse2.cvtdq2pd" || // Added in 3.9 237 Name == "sse2.cvtps2pd" || // Added in 3.9 238 Name == "avx.cvtdq2.pd.256" || // Added in 3.9 239 Name == "avx.cvt.ps2.pd.256" || // Added in 3.9 240 Name.startswith("avx.vinsertf128.") || // Added in 3.7 241 Name == "avx2.vinserti128" || // Added in 3.7 242 Name.startswith("avx512.mask.insert") || // Added in 4.0 243 Name.startswith("avx.vextractf128.") || // Added in 3.7 244 Name == "avx2.vextracti128" || // Added in 3.7 245 Name.startswith("avx512.mask.vextract") || // Added in 4.0 246 Name.startswith("sse4a.movnt.") || // Added in 3.9 247 Name.startswith("avx.movnt.") || // Added in 3.2 248 Name.startswith("avx512.storent.") || // Added in 3.9 249 Name == "sse41.movntdqa" || // Added in 5.0 250 Name == "avx2.movntdqa" || // Added in 5.0 251 Name == "avx512.movntdqa" || // Added in 5.0 252 Name == "sse2.storel.dq" || // Added in 3.9 253 Name.startswith("sse.storeu.") || // Added in 3.9 254 Name.startswith("sse2.storeu.") || // Added in 3.9 255 Name.startswith("avx.storeu.") || // Added in 3.9 256 Name.startswith("avx512.mask.storeu.") || // Added in 3.9 257 Name.startswith("avx512.mask.store.p") || // Added in 3.9 258 Name.startswith("avx512.mask.store.b.") || // Added in 3.9 259 Name.startswith("avx512.mask.store.w.") || // Added in 3.9 260 Name.startswith("avx512.mask.store.d.") || // Added in 3.9 261 Name.startswith("avx512.mask.store.q.") || // Added in 3.9 262 Name.startswith("avx512.mask.loadu.") || // Added in 3.9 263 Name.startswith("avx512.mask.load.") || // Added in 3.9 264 Name == "sse42.crc32.64.8" || // Added in 3.4 265 Name.startswith("avx.vbroadcast.s") || // Added in 3.5 266 Name.startswith("avx512.mask.palignr.") || // Added in 3.9 267 Name.startswith("avx512.mask.valign.") || // Added in 4.0 268 Name.startswith("sse2.psll.dq") || // Added in 3.7 269 Name.startswith("sse2.psrl.dq") || // Added in 3.7 270 Name.startswith("avx2.psll.dq") || // Added in 3.7 271 Name.startswith("avx2.psrl.dq") || // Added in 3.7 272 Name.startswith("avx512.psll.dq") || // Added in 3.9 273 Name.startswith("avx512.psrl.dq") || // Added in 3.9 274 Name == "sse41.pblendw" || // Added in 3.7 275 Name.startswith("sse41.blendp") || // Added in 3.7 276 Name.startswith("avx.blend.p") || // Added in 3.7 277 Name == "avx2.pblendw" || // Added in 3.7 278 Name.startswith("avx2.pblendd.") || // Added in 3.7 279 Name.startswith("avx.vbroadcastf128") || // Added in 4.0 280 Name == "avx2.vbroadcasti128" || // Added in 3.7 281 Name.startswith("avx512.mask.broadcastf") || // Added in 6.0 282 Name.startswith("avx512.mask.broadcasti") || // Added in 6.0 283 Name == "xop.vpcmov" || // Added in 3.8 284 Name == "xop.vpcmov.256" || // Added in 5.0 285 Name.startswith("avx512.mask.move.s") || // Added in 4.0 286 Name.startswith("avx512.cvtmask2") || // Added in 5.0 287 (Name.startswith("xop.vpcom") && // Added in 3.2 288 F->arg_size() == 2) || 289 Name.startswith("avx512.ptestm") || //Added in 6.0 290 Name.startswith("avx512.ptestnm") || //Added in 6.0 291 Name.startswith("sse2.pavg") || // Added in 6.0 292 Name.startswith("avx2.pavg") || // Added in 6.0 293 Name.startswith("avx512.mask.pavg")) // Added in 6.0 294 return true; 295 296 return false; 297 } 298 299 static bool UpgradeX86IntrinsicFunction(Function *F, StringRef Name, 300 Function *&NewFn) { 301 // Only handle intrinsics that start with "x86.". 302 if (!Name.startswith("x86.")) 303 return false; 304 // Remove "x86." prefix. 305 Name = Name.substr(4); 306 307 if (ShouldUpgradeX86Intrinsic(F, Name)) { 308 NewFn = nullptr; 309 return true; 310 } 311 312 // SSE4.1 ptest functions may have an old signature. 313 if (Name.startswith("sse41.ptest")) { // Added in 3.2 314 if (Name.substr(11) == "c") 315 return UpgradePTESTIntrinsic(F, Intrinsic::x86_sse41_ptestc, NewFn); 316 if (Name.substr(11) == "z") 317 return UpgradePTESTIntrinsic(F, Intrinsic::x86_sse41_ptestz, NewFn); 318 if (Name.substr(11) == "nzc") 319 return UpgradePTESTIntrinsic(F, Intrinsic::x86_sse41_ptestnzc, NewFn); 320 } 321 // Several blend and other instructions with masks used the wrong number of 322 // bits. 323 if (Name == "sse41.insertps") // Added in 3.6 324 return UpgradeX86IntrinsicsWith8BitMask(F, Intrinsic::x86_sse41_insertps, 325 NewFn); 326 if (Name == "sse41.dppd") // Added in 3.6 327 return UpgradeX86IntrinsicsWith8BitMask(F, Intrinsic::x86_sse41_dppd, 328 NewFn); 329 if (Name == "sse41.dpps") // Added in 3.6 330 return UpgradeX86IntrinsicsWith8BitMask(F, Intrinsic::x86_sse41_dpps, 331 NewFn); 332 if (Name == "sse41.mpsadbw") // Added in 3.6 333 return UpgradeX86IntrinsicsWith8BitMask(F, Intrinsic::x86_sse41_mpsadbw, 334 NewFn); 335 if (Name == "avx.dp.ps.256") // Added in 3.6 336 return UpgradeX86IntrinsicsWith8BitMask(F, Intrinsic::x86_avx_dp_ps_256, 337 NewFn); 338 if (Name == "avx2.mpsadbw") // Added in 3.6 339 return UpgradeX86IntrinsicsWith8BitMask(F, Intrinsic::x86_avx2_mpsadbw, 340 NewFn); 341 if (Name == "avx512.mask.cmp.pd.128") // Added in 7.0 342 return UpgradeX86MaskedFPCompare(F, Intrinsic::x86_avx512_mask_cmp_pd_128, 343 NewFn); 344 if (Name == "avx512.mask.cmp.pd.256") // Added in 7.0 345 return UpgradeX86MaskedFPCompare(F, Intrinsic::x86_avx512_mask_cmp_pd_256, 346 NewFn); 347 if (Name == "avx512.mask.cmp.pd.512") // Added in 7.0 348 return UpgradeX86MaskedFPCompare(F, Intrinsic::x86_avx512_mask_cmp_pd_512, 349 NewFn); 350 if (Name == "avx512.mask.cmp.ps.128") // Added in 7.0 351 return UpgradeX86MaskedFPCompare(F, Intrinsic::x86_avx512_mask_cmp_ps_128, 352 NewFn); 353 if (Name == "avx512.mask.cmp.ps.256") // Added in 7.0 354 return UpgradeX86MaskedFPCompare(F, Intrinsic::x86_avx512_mask_cmp_ps_256, 355 NewFn); 356 if (Name == "avx512.mask.cmp.ps.512") // Added in 7.0 357 return UpgradeX86MaskedFPCompare(F, Intrinsic::x86_avx512_mask_cmp_ps_512, 358 NewFn); 359 360 // frcz.ss/sd may need to have an argument dropped. Added in 3.2 361 if (Name.startswith("xop.vfrcz.ss") && F->arg_size() == 2) { 362 rename(F); 363 NewFn = Intrinsic::getDeclaration(F->getParent(), 364 Intrinsic::x86_xop_vfrcz_ss); 365 return true; 366 } 367 if (Name.startswith("xop.vfrcz.sd") && F->arg_size() == 2) { 368 rename(F); 369 NewFn = Intrinsic::getDeclaration(F->getParent(), 370 Intrinsic::x86_xop_vfrcz_sd); 371 return true; 372 } 373 // Upgrade any XOP PERMIL2 index operand still using a float/double vector. 374 if (Name.startswith("xop.vpermil2")) { // Added in 3.9 375 auto Idx = F->getFunctionType()->getParamType(2); 376 if (Idx->isFPOrFPVectorTy()) { 377 rename(F); 378 unsigned IdxSize = Idx->getPrimitiveSizeInBits(); 379 unsigned EltSize = Idx->getScalarSizeInBits(); 380 Intrinsic::ID Permil2ID; 381 if (EltSize == 64 && IdxSize == 128) 382 Permil2ID = Intrinsic::x86_xop_vpermil2pd; 383 else if (EltSize == 32 && IdxSize == 128) 384 Permil2ID = Intrinsic::x86_xop_vpermil2ps; 385 else if (EltSize == 64 && IdxSize == 256) 386 Permil2ID = Intrinsic::x86_xop_vpermil2pd_256; 387 else 388 Permil2ID = Intrinsic::x86_xop_vpermil2ps_256; 389 NewFn = Intrinsic::getDeclaration(F->getParent(), Permil2ID); 390 return true; 391 } 392 } 393 394 return false; 395 } 396 397 static bool UpgradeIntrinsicFunction1(Function *F, Function *&NewFn) { 398 assert(F && "Illegal to upgrade a non-existent Function."); 399 400 // Quickly eliminate it, if it's not a candidate. 401 StringRef Name = F->getName(); 402 if (Name.size() <= 8 || !Name.startswith("llvm.")) 403 return false; 404 Name = Name.substr(5); // Strip off "llvm." 405 406 switch (Name[0]) { 407 default: break; 408 case 'a': { 409 if (Name.startswith("arm.rbit") || Name.startswith("aarch64.rbit")) { 410 NewFn = Intrinsic::getDeclaration(F->getParent(), Intrinsic::bitreverse, 411 F->arg_begin()->getType()); 412 return true; 413 } 414 if (Name.startswith("arm.neon.vclz")) { 415 Type* args[2] = { 416 F->arg_begin()->getType(), 417 Type::getInt1Ty(F->getContext()) 418 }; 419 // Can't use Intrinsic::getDeclaration here as it adds a ".i1" to 420 // the end of the name. Change name from llvm.arm.neon.vclz.* to 421 // llvm.ctlz.* 422 FunctionType* fType = FunctionType::get(F->getReturnType(), args, false); 423 NewFn = Function::Create(fType, F->getLinkage(), 424 "llvm.ctlz." + Name.substr(14), F->getParent()); 425 return true; 426 } 427 if (Name.startswith("arm.neon.vcnt")) { 428 NewFn = Intrinsic::getDeclaration(F->getParent(), Intrinsic::ctpop, 429 F->arg_begin()->getType()); 430 return true; 431 } 432 Regex vldRegex("^arm\\.neon\\.vld([1234]|[234]lane)\\.v[a-z0-9]*$"); 433 if (vldRegex.match(Name)) { 434 auto fArgs = F->getFunctionType()->params(); 435 SmallVector<Type *, 4> Tys(fArgs.begin(), fArgs.end()); 436 // Can't use Intrinsic::getDeclaration here as the return types might 437 // then only be structurally equal. 438 FunctionType* fType = FunctionType::get(F->getReturnType(), Tys, false); 439 NewFn = Function::Create(fType, F->getLinkage(), 440 "llvm." + Name + ".p0i8", F->getParent()); 441 return true; 442 } 443 Regex vstRegex("^arm\\.neon\\.vst([1234]|[234]lane)\\.v[a-z0-9]*$"); 444 if (vstRegex.match(Name)) { 445 static const Intrinsic::ID StoreInts[] = {Intrinsic::arm_neon_vst1, 446 Intrinsic::arm_neon_vst2, 447 Intrinsic::arm_neon_vst3, 448 Intrinsic::arm_neon_vst4}; 449 450 static const Intrinsic::ID StoreLaneInts[] = { 451 Intrinsic::arm_neon_vst2lane, Intrinsic::arm_neon_vst3lane, 452 Intrinsic::arm_neon_vst4lane 453 }; 454 455 auto fArgs = F->getFunctionType()->params(); 456 Type *Tys[] = {fArgs[0], fArgs[1]}; 457 if (Name.find("lane") == StringRef::npos) 458 NewFn = Intrinsic::getDeclaration(F->getParent(), 459 StoreInts[fArgs.size() - 3], Tys); 460 else 461 NewFn = Intrinsic::getDeclaration(F->getParent(), 462 StoreLaneInts[fArgs.size() - 5], Tys); 463 return true; 464 } 465 if (Name == "aarch64.thread.pointer" || Name == "arm.thread.pointer") { 466 NewFn = Intrinsic::getDeclaration(F->getParent(), Intrinsic::thread_pointer); 467 return true; 468 } 469 break; 470 } 471 472 case 'c': { 473 if (Name.startswith("ctlz.") && F->arg_size() == 1) { 474 rename(F); 475 NewFn = Intrinsic::getDeclaration(F->getParent(), Intrinsic::ctlz, 476 F->arg_begin()->getType()); 477 return true; 478 } 479 if (Name.startswith("cttz.") && F->arg_size() == 1) { 480 rename(F); 481 NewFn = Intrinsic::getDeclaration(F->getParent(), Intrinsic::cttz, 482 F->arg_begin()->getType()); 483 return true; 484 } 485 break; 486 } 487 case 'd': { 488 if (Name == "dbg.value" && F->arg_size() == 4) { 489 rename(F); 490 NewFn = Intrinsic::getDeclaration(F->getParent(), Intrinsic::dbg_value); 491 return true; 492 } 493 break; 494 } 495 case 'i': 496 case 'l': { 497 bool IsLifetimeStart = Name.startswith("lifetime.start"); 498 if (IsLifetimeStart || Name.startswith("invariant.start")) { 499 Intrinsic::ID ID = IsLifetimeStart ? 500 Intrinsic::lifetime_start : Intrinsic::invariant_start; 501 auto Args = F->getFunctionType()->params(); 502 Type* ObjectPtr[1] = {Args[1]}; 503 if (F->getName() != Intrinsic::getName(ID, ObjectPtr)) { 504 rename(F); 505 NewFn = Intrinsic::getDeclaration(F->getParent(), ID, ObjectPtr); 506 return true; 507 } 508 } 509 510 bool IsLifetimeEnd = Name.startswith("lifetime.end"); 511 if (IsLifetimeEnd || Name.startswith("invariant.end")) { 512 Intrinsic::ID ID = IsLifetimeEnd ? 513 Intrinsic::lifetime_end : Intrinsic::invariant_end; 514 515 auto Args = F->getFunctionType()->params(); 516 Type* ObjectPtr[1] = {Args[IsLifetimeEnd ? 1 : 2]}; 517 if (F->getName() != Intrinsic::getName(ID, ObjectPtr)) { 518 rename(F); 519 NewFn = Intrinsic::getDeclaration(F->getParent(), ID, ObjectPtr); 520 return true; 521 } 522 } 523 break; 524 } 525 case 'm': { 526 if (Name.startswith("masked.load.")) { 527 Type *Tys[] = { F->getReturnType(), F->arg_begin()->getType() }; 528 if (F->getName() != Intrinsic::getName(Intrinsic::masked_load, Tys)) { 529 rename(F); 530 NewFn = Intrinsic::getDeclaration(F->getParent(), 531 Intrinsic::masked_load, 532 Tys); 533 return true; 534 } 535 } 536 if (Name.startswith("masked.store.")) { 537 auto Args = F->getFunctionType()->params(); 538 Type *Tys[] = { Args[0], Args[1] }; 539 if (F->getName() != Intrinsic::getName(Intrinsic::masked_store, Tys)) { 540 rename(F); 541 NewFn = Intrinsic::getDeclaration(F->getParent(), 542 Intrinsic::masked_store, 543 Tys); 544 return true; 545 } 546 } 547 // Renaming gather/scatter intrinsics with no address space overloading 548 // to the new overload which includes an address space 549 if (Name.startswith("masked.gather.")) { 550 Type *Tys[] = {F->getReturnType(), F->arg_begin()->getType()}; 551 if (F->getName() != Intrinsic::getName(Intrinsic::masked_gather, Tys)) { 552 rename(F); 553 NewFn = Intrinsic::getDeclaration(F->getParent(), 554 Intrinsic::masked_gather, Tys); 555 return true; 556 } 557 } 558 if (Name.startswith("masked.scatter.")) { 559 auto Args = F->getFunctionType()->params(); 560 Type *Tys[] = {Args[0], Args[1]}; 561 if (F->getName() != Intrinsic::getName(Intrinsic::masked_scatter, Tys)) { 562 rename(F); 563 NewFn = Intrinsic::getDeclaration(F->getParent(), 564 Intrinsic::masked_scatter, Tys); 565 return true; 566 } 567 } 568 // Updating the memory intrinsics (memcpy/memmove/memset) that have an 569 // alignment parameter to embedding the alignment as an attribute of 570 // the pointer args. 571 if (Name.startswith("memcpy.") && F->arg_size() == 5) { 572 rename(F); 573 // Get the types of dest, src, and len 574 ArrayRef<Type *> ParamTypes = F->getFunctionType()->params().slice(0, 3); 575 NewFn = Intrinsic::getDeclaration(F->getParent(), Intrinsic::memcpy, 576 ParamTypes); 577 return true; 578 } 579 if (Name.startswith("memmove.") && F->arg_size() == 5) { 580 rename(F); 581 // Get the types of dest, src, and len 582 ArrayRef<Type *> ParamTypes = F->getFunctionType()->params().slice(0, 3); 583 NewFn = Intrinsic::getDeclaration(F->getParent(), Intrinsic::memmove, 584 ParamTypes); 585 return true; 586 } 587 if (Name.startswith("memset.") && F->arg_size() == 5) { 588 rename(F); 589 // Get the types of dest, and len 590 const auto *FT = F->getFunctionType(); 591 Type *ParamTypes[2] = { 592 FT->getParamType(0), // Dest 593 FT->getParamType(2) // len 594 }; 595 NewFn = Intrinsic::getDeclaration(F->getParent(), Intrinsic::memset, 596 ParamTypes); 597 return true; 598 } 599 break; 600 } 601 case 'n': { 602 if (Name.startswith("nvvm.")) { 603 Name = Name.substr(5); 604 605 // The following nvvm intrinsics correspond exactly to an LLVM intrinsic. 606 Intrinsic::ID IID = StringSwitch<Intrinsic::ID>(Name) 607 .Cases("brev32", "brev64", Intrinsic::bitreverse) 608 .Case("clz.i", Intrinsic::ctlz) 609 .Case("popc.i", Intrinsic::ctpop) 610 .Default(Intrinsic::not_intrinsic); 611 if (IID != Intrinsic::not_intrinsic && F->arg_size() == 1) { 612 NewFn = Intrinsic::getDeclaration(F->getParent(), IID, 613 {F->getReturnType()}); 614 return true; 615 } 616 617 // The following nvvm intrinsics correspond exactly to an LLVM idiom, but 618 // not to an intrinsic alone. We expand them in UpgradeIntrinsicCall. 619 // 620 // TODO: We could add lohi.i2d. 621 bool Expand = StringSwitch<bool>(Name) 622 .Cases("abs.i", "abs.ll", true) 623 .Cases("clz.ll", "popc.ll", "h2f", true) 624 .Cases("max.i", "max.ll", "max.ui", "max.ull", true) 625 .Cases("min.i", "min.ll", "min.ui", "min.ull", true) 626 .Default(false); 627 if (Expand) { 628 NewFn = nullptr; 629 return true; 630 } 631 } 632 break; 633 } 634 case 'o': 635 // We only need to change the name to match the mangling including the 636 // address space. 637 if (Name.startswith("objectsize.")) { 638 Type *Tys[2] = { F->getReturnType(), F->arg_begin()->getType() }; 639 if (F->arg_size() == 2 || 640 F->getName() != Intrinsic::getName(Intrinsic::objectsize, Tys)) { 641 rename(F); 642 NewFn = Intrinsic::getDeclaration(F->getParent(), Intrinsic::objectsize, 643 Tys); 644 return true; 645 } 646 } 647 break; 648 649 case 's': 650 if (Name == "stackprotectorcheck") { 651 NewFn = nullptr; 652 return true; 653 } 654 break; 655 656 case 'x': 657 if (UpgradeX86IntrinsicFunction(F, Name, NewFn)) 658 return true; 659 } 660 // Remangle our intrinsic since we upgrade the mangling 661 auto Result = llvm::Intrinsic::remangleIntrinsicFunction(F); 662 if (Result != None) { 663 NewFn = Result.getValue(); 664 return true; 665 } 666 667 // This may not belong here. This function is effectively being overloaded 668 // to both detect an intrinsic which needs upgrading, and to provide the 669 // upgraded form of the intrinsic. We should perhaps have two separate 670 // functions for this. 671 return false; 672 } 673 674 bool llvm::UpgradeIntrinsicFunction(Function *F, Function *&NewFn) { 675 NewFn = nullptr; 676 bool Upgraded = UpgradeIntrinsicFunction1(F, NewFn); 677 assert(F != NewFn && "Intrinsic function upgraded to the same function"); 678 679 // Upgrade intrinsic attributes. This does not change the function. 680 if (NewFn) 681 F = NewFn; 682 if (Intrinsic::ID id = F->getIntrinsicID()) 683 F->setAttributes(Intrinsic::getAttributes(F->getContext(), id)); 684 return Upgraded; 685 } 686 687 bool llvm::UpgradeGlobalVariable(GlobalVariable *GV) { 688 // Nothing to do yet. 689 return false; 690 } 691 692 // Handles upgrading SSE2/AVX2/AVX512BW PSLLDQ intrinsics by converting them 693 // to byte shuffles. 694 static Value *UpgradeX86PSLLDQIntrinsics(IRBuilder<> &Builder, 695 Value *Op, unsigned Shift) { 696 Type *ResultTy = Op->getType(); 697 unsigned NumElts = ResultTy->getVectorNumElements() * 8; 698 699 // Bitcast from a 64-bit element type to a byte element type. 700 Type *VecTy = VectorType::get(Builder.getInt8Ty(), NumElts); 701 Op = Builder.CreateBitCast(Op, VecTy, "cast"); 702 703 // We'll be shuffling in zeroes. 704 Value *Res = Constant::getNullValue(VecTy); 705 706 // If shift is less than 16, emit a shuffle to move the bytes. Otherwise, 707 // we'll just return the zero vector. 708 if (Shift < 16) { 709 uint32_t Idxs[64]; 710 // 256/512-bit version is split into 2/4 16-byte lanes. 711 for (unsigned l = 0; l != NumElts; l += 16) 712 for (unsigned i = 0; i != 16; ++i) { 713 unsigned Idx = NumElts + i - Shift; 714 if (Idx < NumElts) 715 Idx -= NumElts - 16; // end of lane, switch operand. 716 Idxs[l + i] = Idx + l; 717 } 718 719 Res = Builder.CreateShuffleVector(Res, Op, makeArrayRef(Idxs, NumElts)); 720 } 721 722 // Bitcast back to a 64-bit element type. 723 return Builder.CreateBitCast(Res, ResultTy, "cast"); 724 } 725 726 // Handles upgrading SSE2/AVX2/AVX512BW PSRLDQ intrinsics by converting them 727 // to byte shuffles. 728 static Value *UpgradeX86PSRLDQIntrinsics(IRBuilder<> &Builder, Value *Op, 729 unsigned Shift) { 730 Type *ResultTy = Op->getType(); 731 unsigned NumElts = ResultTy->getVectorNumElements() * 8; 732 733 // Bitcast from a 64-bit element type to a byte element type. 734 Type *VecTy = VectorType::get(Builder.getInt8Ty(), NumElts); 735 Op = Builder.CreateBitCast(Op, VecTy, "cast"); 736 737 // We'll be shuffling in zeroes. 738 Value *Res = Constant::getNullValue(VecTy); 739 740 // If shift is less than 16, emit a shuffle to move the bytes. Otherwise, 741 // we'll just return the zero vector. 742 if (Shift < 16) { 743 uint32_t Idxs[64]; 744 // 256/512-bit version is split into 2/4 16-byte lanes. 745 for (unsigned l = 0; l != NumElts; l += 16) 746 for (unsigned i = 0; i != 16; ++i) { 747 unsigned Idx = i + Shift; 748 if (Idx >= 16) 749 Idx += NumElts - 16; // end of lane, switch operand. 750 Idxs[l + i] = Idx + l; 751 } 752 753 Res = Builder.CreateShuffleVector(Op, Res, makeArrayRef(Idxs, NumElts)); 754 } 755 756 // Bitcast back to a 64-bit element type. 757 return Builder.CreateBitCast(Res, ResultTy, "cast"); 758 } 759 760 static Value *getX86MaskVec(IRBuilder<> &Builder, Value *Mask, 761 unsigned NumElts) { 762 llvm::VectorType *MaskTy = llvm::VectorType::get(Builder.getInt1Ty(), 763 cast<IntegerType>(Mask->getType())->getBitWidth()); 764 Mask = Builder.CreateBitCast(Mask, MaskTy); 765 766 // If we have less than 8 elements, then the starting mask was an i8 and 767 // we need to extract down to the right number of elements. 768 if (NumElts < 8) { 769 uint32_t Indices[4]; 770 for (unsigned i = 0; i != NumElts; ++i) 771 Indices[i] = i; 772 Mask = Builder.CreateShuffleVector(Mask, Mask, 773 makeArrayRef(Indices, NumElts), 774 "extract"); 775 } 776 777 return Mask; 778 } 779 780 static Value *EmitX86Select(IRBuilder<> &Builder, Value *Mask, 781 Value *Op0, Value *Op1) { 782 // If the mask is all ones just emit the align operation. 783 if (const auto *C = dyn_cast<Constant>(Mask)) 784 if (C->isAllOnesValue()) 785 return Op0; 786 787 Mask = getX86MaskVec(Builder, Mask, Op0->getType()->getVectorNumElements()); 788 return Builder.CreateSelect(Mask, Op0, Op1); 789 } 790 791 // Handle autoupgrade for masked PALIGNR and VALIGND/Q intrinsics. 792 // PALIGNR handles large immediates by shifting while VALIGN masks the immediate 793 // so we need to handle both cases. VALIGN also doesn't have 128-bit lanes. 794 static Value *UpgradeX86ALIGNIntrinsics(IRBuilder<> &Builder, Value *Op0, 795 Value *Op1, Value *Shift, 796 Value *Passthru, Value *Mask, 797 bool IsVALIGN) { 798 unsigned ShiftVal = cast<llvm::ConstantInt>(Shift)->getZExtValue(); 799 800 unsigned NumElts = Op0->getType()->getVectorNumElements(); 801 assert((IsVALIGN || NumElts % 16 == 0) && "Illegal NumElts for PALIGNR!"); 802 assert((!IsVALIGN || NumElts <= 16) && "NumElts too large for VALIGN!"); 803 assert(isPowerOf2_32(NumElts) && "NumElts not a power of 2!"); 804 805 // Mask the immediate for VALIGN. 806 if (IsVALIGN) 807 ShiftVal &= (NumElts - 1); 808 809 // If palignr is shifting the pair of vectors more than the size of two 810 // lanes, emit zero. 811 if (ShiftVal >= 32) 812 return llvm::Constant::getNullValue(Op0->getType()); 813 814 // If palignr is shifting the pair of input vectors more than one lane, 815 // but less than two lanes, convert to shifting in zeroes. 816 if (ShiftVal > 16) { 817 ShiftVal -= 16; 818 Op1 = Op0; 819 Op0 = llvm::Constant::getNullValue(Op0->getType()); 820 } 821 822 uint32_t Indices[64]; 823 // 256-bit palignr operates on 128-bit lanes so we need to handle that 824 for (unsigned l = 0; l < NumElts; l += 16) { 825 for (unsigned i = 0; i != 16; ++i) { 826 unsigned Idx = ShiftVal + i; 827 if (!IsVALIGN && Idx >= 16) // Disable wrap for VALIGN. 828 Idx += NumElts - 16; // End of lane, switch operand. 829 Indices[l + i] = Idx + l; 830 } 831 } 832 833 Value *Align = Builder.CreateShuffleVector(Op1, Op0, 834 makeArrayRef(Indices, NumElts), 835 "palignr"); 836 837 return EmitX86Select(Builder, Mask, Align, Passthru); 838 } 839 840 static Value *UpgradeMaskedStore(IRBuilder<> &Builder, 841 Value *Ptr, Value *Data, Value *Mask, 842 bool Aligned) { 843 // Cast the pointer to the right type. 844 Ptr = Builder.CreateBitCast(Ptr, 845 llvm::PointerType::getUnqual(Data->getType())); 846 unsigned Align = 847 Aligned ? cast<VectorType>(Data->getType())->getBitWidth() / 8 : 1; 848 849 // If the mask is all ones just emit a regular store. 850 if (const auto *C = dyn_cast<Constant>(Mask)) 851 if (C->isAllOnesValue()) 852 return Builder.CreateAlignedStore(Data, Ptr, Align); 853 854 // Convert the mask from an integer type to a vector of i1. 855 unsigned NumElts = Data->getType()->getVectorNumElements(); 856 Mask = getX86MaskVec(Builder, Mask, NumElts); 857 return Builder.CreateMaskedStore(Data, Ptr, Align, Mask); 858 } 859 860 static Value *UpgradeMaskedLoad(IRBuilder<> &Builder, 861 Value *Ptr, Value *Passthru, Value *Mask, 862 bool Aligned) { 863 // Cast the pointer to the right type. 864 Ptr = Builder.CreateBitCast(Ptr, 865 llvm::PointerType::getUnqual(Passthru->getType())); 866 unsigned Align = 867 Aligned ? cast<VectorType>(Passthru->getType())->getBitWidth() / 8 : 1; 868 869 // If the mask is all ones just emit a regular store. 870 if (const auto *C = dyn_cast<Constant>(Mask)) 871 if (C->isAllOnesValue()) 872 return Builder.CreateAlignedLoad(Ptr, Align); 873 874 // Convert the mask from an integer type to a vector of i1. 875 unsigned NumElts = Passthru->getType()->getVectorNumElements(); 876 Mask = getX86MaskVec(Builder, Mask, NumElts); 877 return Builder.CreateMaskedLoad(Ptr, Align, Mask, Passthru); 878 } 879 880 static Value *upgradeAbs(IRBuilder<> &Builder, CallInst &CI) { 881 Value *Op0 = CI.getArgOperand(0); 882 llvm::Type *Ty = Op0->getType(); 883 Value *Zero = llvm::Constant::getNullValue(Ty); 884 Value *Cmp = Builder.CreateICmp(ICmpInst::ICMP_SGT, Op0, Zero); 885 Value *Neg = Builder.CreateNeg(Op0); 886 Value *Res = Builder.CreateSelect(Cmp, Op0, Neg); 887 888 if (CI.getNumArgOperands() == 3) 889 Res = EmitX86Select(Builder,CI.getArgOperand(2), Res, CI.getArgOperand(1)); 890 891 return Res; 892 } 893 894 static Value *upgradeIntMinMax(IRBuilder<> &Builder, CallInst &CI, 895 ICmpInst::Predicate Pred) { 896 Value *Op0 = CI.getArgOperand(0); 897 Value *Op1 = CI.getArgOperand(1); 898 Value *Cmp = Builder.CreateICmp(Pred, Op0, Op1); 899 Value *Res = Builder.CreateSelect(Cmp, Op0, Op1); 900 901 if (CI.getNumArgOperands() == 4) 902 Res = EmitX86Select(Builder, CI.getArgOperand(3), Res, CI.getArgOperand(2)); 903 904 return Res; 905 } 906 907 // Applying mask on vector of i1's and make sure result is at least 8 bits wide. 908 static Value *ApplyX86MaskOn1BitsVec(IRBuilder<> &Builder,Value *Vec, Value *Mask, 909 unsigned NumElts) { 910 if (Mask) { 911 const auto *C = dyn_cast<Constant>(Mask); 912 if (!C || !C->isAllOnesValue()) 913 Vec = Builder.CreateAnd(Vec, getX86MaskVec(Builder, Mask, NumElts)); 914 } 915 916 if (NumElts < 8) { 917 uint32_t Indices[8]; 918 for (unsigned i = 0; i != NumElts; ++i) 919 Indices[i] = i; 920 for (unsigned i = NumElts; i != 8; ++i) 921 Indices[i] = NumElts + i % NumElts; 922 Vec = Builder.CreateShuffleVector(Vec, 923 Constant::getNullValue(Vec->getType()), 924 Indices); 925 } 926 return Builder.CreateBitCast(Vec, Builder.getIntNTy(std::max(NumElts, 8U))); 927 } 928 929 static Value *upgradeMaskedCompare(IRBuilder<> &Builder, CallInst &CI, 930 unsigned CC, bool Signed) { 931 Value *Op0 = CI.getArgOperand(0); 932 unsigned NumElts = Op0->getType()->getVectorNumElements(); 933 934 Value *Cmp; 935 if (CC == 3) { 936 Cmp = Constant::getNullValue(llvm::VectorType::get(Builder.getInt1Ty(), NumElts)); 937 } else if (CC == 7) { 938 Cmp = Constant::getAllOnesValue(llvm::VectorType::get(Builder.getInt1Ty(), NumElts)); 939 } else { 940 ICmpInst::Predicate Pred; 941 switch (CC) { 942 default: llvm_unreachable("Unknown condition code"); 943 case 0: Pred = ICmpInst::ICMP_EQ; break; 944 case 1: Pred = Signed ? ICmpInst::ICMP_SLT : ICmpInst::ICMP_ULT; break; 945 case 2: Pred = Signed ? ICmpInst::ICMP_SLE : ICmpInst::ICMP_ULE; break; 946 case 4: Pred = ICmpInst::ICMP_NE; break; 947 case 5: Pred = Signed ? ICmpInst::ICMP_SGE : ICmpInst::ICMP_UGE; break; 948 case 6: Pred = Signed ? ICmpInst::ICMP_SGT : ICmpInst::ICMP_UGT; break; 949 } 950 Cmp = Builder.CreateICmp(Pred, Op0, CI.getArgOperand(1)); 951 } 952 953 Value *Mask = CI.getArgOperand(CI.getNumArgOperands() - 1); 954 955 return ApplyX86MaskOn1BitsVec(Builder, Cmp, Mask, NumElts); 956 } 957 958 // Replace a masked intrinsic with an older unmasked intrinsic. 959 static Value *UpgradeX86MaskedShift(IRBuilder<> &Builder, CallInst &CI, 960 Intrinsic::ID IID) { 961 Function *F = CI.getCalledFunction(); 962 Function *Intrin = Intrinsic::getDeclaration(F->getParent(), IID); 963 Value *Rep = Builder.CreateCall(Intrin, 964 { CI.getArgOperand(0), CI.getArgOperand(1) }); 965 return EmitX86Select(Builder, CI.getArgOperand(3), Rep, CI.getArgOperand(2)); 966 } 967 968 static Value* upgradeMaskedMove(IRBuilder<> &Builder, CallInst &CI) { 969 Value* A = CI.getArgOperand(0); 970 Value* B = CI.getArgOperand(1); 971 Value* Src = CI.getArgOperand(2); 972 Value* Mask = CI.getArgOperand(3); 973 974 Value* AndNode = Builder.CreateAnd(Mask, APInt(8, 1)); 975 Value* Cmp = Builder.CreateIsNotNull(AndNode); 976 Value* Extract1 = Builder.CreateExtractElement(B, (uint64_t)0); 977 Value* Extract2 = Builder.CreateExtractElement(Src, (uint64_t)0); 978 Value* Select = Builder.CreateSelect(Cmp, Extract1, Extract2); 979 return Builder.CreateInsertElement(A, Select, (uint64_t)0); 980 } 981 982 983 static Value* UpgradeMaskToInt(IRBuilder<> &Builder, CallInst &CI) { 984 Value* Op = CI.getArgOperand(0); 985 Type* ReturnOp = CI.getType(); 986 unsigned NumElts = CI.getType()->getVectorNumElements(); 987 Value *Mask = getX86MaskVec(Builder, Op, NumElts); 988 return Builder.CreateSExt(Mask, ReturnOp, "vpmovm2"); 989 } 990 991 /// Upgrade a call to an old intrinsic. All argument and return casting must be 992 /// provided to seamlessly integrate with existing context. 993 void llvm::UpgradeIntrinsicCall(CallInst *CI, Function *NewFn) { 994 Function *F = CI->getCalledFunction(); 995 LLVMContext &C = CI->getContext(); 996 IRBuilder<> Builder(C); 997 Builder.SetInsertPoint(CI->getParent(), CI->getIterator()); 998 999 assert(F && "Intrinsic call is not direct?"); 1000 1001 if (!NewFn) { 1002 // Get the Function's name. 1003 StringRef Name = F->getName(); 1004 1005 assert(Name.startswith("llvm.") && "Intrinsic doesn't start with 'llvm.'"); 1006 Name = Name.substr(5); 1007 1008 bool IsX86 = Name.startswith("x86."); 1009 if (IsX86) 1010 Name = Name.substr(4); 1011 bool IsNVVM = Name.startswith("nvvm."); 1012 if (IsNVVM) 1013 Name = Name.substr(5); 1014 1015 if (IsX86 && Name.startswith("sse4a.movnt.")) { 1016 Module *M = F->getParent(); 1017 SmallVector<Metadata *, 1> Elts; 1018 Elts.push_back( 1019 ConstantAsMetadata::get(ConstantInt::get(Type::getInt32Ty(C), 1))); 1020 MDNode *Node = MDNode::get(C, Elts); 1021 1022 Value *Arg0 = CI->getArgOperand(0); 1023 Value *Arg1 = CI->getArgOperand(1); 1024 1025 // Nontemporal (unaligned) store of the 0'th element of the float/double 1026 // vector. 1027 Type *SrcEltTy = cast<VectorType>(Arg1->getType())->getElementType(); 1028 PointerType *EltPtrTy = PointerType::getUnqual(SrcEltTy); 1029 Value *Addr = Builder.CreateBitCast(Arg0, EltPtrTy, "cast"); 1030 Value *Extract = 1031 Builder.CreateExtractElement(Arg1, (uint64_t)0, "extractelement"); 1032 1033 StoreInst *SI = Builder.CreateAlignedStore(Extract, Addr, 1); 1034 SI->setMetadata(M->getMDKindID("nontemporal"), Node); 1035 1036 // Remove intrinsic. 1037 CI->eraseFromParent(); 1038 return; 1039 } 1040 1041 if (IsX86 && (Name.startswith("avx.movnt.") || 1042 Name.startswith("avx512.storent."))) { 1043 Module *M = F->getParent(); 1044 SmallVector<Metadata *, 1> Elts; 1045 Elts.push_back( 1046 ConstantAsMetadata::get(ConstantInt::get(Type::getInt32Ty(C), 1))); 1047 MDNode *Node = MDNode::get(C, Elts); 1048 1049 Value *Arg0 = CI->getArgOperand(0); 1050 Value *Arg1 = CI->getArgOperand(1); 1051 1052 // Convert the type of the pointer to a pointer to the stored type. 1053 Value *BC = Builder.CreateBitCast(Arg0, 1054 PointerType::getUnqual(Arg1->getType()), 1055 "cast"); 1056 VectorType *VTy = cast<VectorType>(Arg1->getType()); 1057 StoreInst *SI = Builder.CreateAlignedStore(Arg1, BC, 1058 VTy->getBitWidth() / 8); 1059 SI->setMetadata(M->getMDKindID("nontemporal"), Node); 1060 1061 // Remove intrinsic. 1062 CI->eraseFromParent(); 1063 return; 1064 } 1065 1066 if (IsX86 && Name == "sse2.storel.dq") { 1067 Value *Arg0 = CI->getArgOperand(0); 1068 Value *Arg1 = CI->getArgOperand(1); 1069 1070 Type *NewVecTy = VectorType::get(Type::getInt64Ty(C), 2); 1071 Value *BC0 = Builder.CreateBitCast(Arg1, NewVecTy, "cast"); 1072 Value *Elt = Builder.CreateExtractElement(BC0, (uint64_t)0); 1073 Value *BC = Builder.CreateBitCast(Arg0, 1074 PointerType::getUnqual(Elt->getType()), 1075 "cast"); 1076 Builder.CreateAlignedStore(Elt, BC, 1); 1077 1078 // Remove intrinsic. 1079 CI->eraseFromParent(); 1080 return; 1081 } 1082 1083 if (IsX86 && (Name.startswith("sse.storeu.") || 1084 Name.startswith("sse2.storeu.") || 1085 Name.startswith("avx.storeu."))) { 1086 Value *Arg0 = CI->getArgOperand(0); 1087 Value *Arg1 = CI->getArgOperand(1); 1088 1089 Arg0 = Builder.CreateBitCast(Arg0, 1090 PointerType::getUnqual(Arg1->getType()), 1091 "cast"); 1092 Builder.CreateAlignedStore(Arg1, Arg0, 1); 1093 1094 // Remove intrinsic. 1095 CI->eraseFromParent(); 1096 return; 1097 } 1098 1099 if (IsX86 && (Name.startswith("avx512.mask.store"))) { 1100 // "avx512.mask.storeu." or "avx512.mask.store." 1101 bool Aligned = Name[17] != 'u'; // "avx512.mask.storeu". 1102 UpgradeMaskedStore(Builder, CI->getArgOperand(0), CI->getArgOperand(1), 1103 CI->getArgOperand(2), Aligned); 1104 1105 // Remove intrinsic. 1106 CI->eraseFromParent(); 1107 return; 1108 } 1109 1110 Value *Rep; 1111 // Upgrade packed integer vector compare intrinsics to compare instructions. 1112 if (IsX86 && (Name.startswith("sse2.pcmp") || 1113 Name.startswith("avx2.pcmp"))) { 1114 // "sse2.pcpmpeq." "sse2.pcmpgt." "avx2.pcmpeq." or "avx2.pcmpgt." 1115 bool CmpEq = Name[9] == 'e'; 1116 Rep = Builder.CreateICmp(CmpEq ? ICmpInst::ICMP_EQ : ICmpInst::ICMP_SGT, 1117 CI->getArgOperand(0), CI->getArgOperand(1)); 1118 Rep = Builder.CreateSExt(Rep, CI->getType(), ""); 1119 } else if (IsX86 && (Name.startswith("avx512.broadcastm"))) { 1120 Type *ExtTy = Type::getInt32Ty(C); 1121 if (CI->getOperand(0)->getType()->isIntegerTy(8)) 1122 ExtTy = Type::getInt64Ty(C); 1123 unsigned NumElts = CI->getType()->getPrimitiveSizeInBits() / 1124 ExtTy->getPrimitiveSizeInBits(); 1125 Rep = Builder.CreateZExt(CI->getArgOperand(0), ExtTy); 1126 Rep = Builder.CreateVectorSplat(NumElts, Rep); 1127 } else if (IsX86 && (Name.startswith("avx512.ptestm") || 1128 Name.startswith("avx512.ptestnm"))) { 1129 Value *Op0 = CI->getArgOperand(0); 1130 Value *Op1 = CI->getArgOperand(1); 1131 Value *Mask = CI->getArgOperand(2); 1132 Rep = Builder.CreateAnd(Op0, Op1); 1133 llvm::Type *Ty = Op0->getType(); 1134 Value *Zero = llvm::Constant::getNullValue(Ty); 1135 ICmpInst::Predicate Pred = 1136 Name.startswith("avx512.ptestm") ? ICmpInst::ICMP_NE : ICmpInst::ICMP_EQ; 1137 Rep = Builder.CreateICmp(Pred, Rep, Zero); 1138 unsigned NumElts = Op0->getType()->getVectorNumElements(); 1139 Rep = ApplyX86MaskOn1BitsVec(Builder, Rep, Mask, NumElts); 1140 } else if (IsX86 && (Name.startswith("avx512.mask.pbroadcast"))){ 1141 unsigned NumElts = 1142 CI->getArgOperand(1)->getType()->getVectorNumElements(); 1143 Rep = Builder.CreateVectorSplat(NumElts, CI->getArgOperand(0)); 1144 Rep = EmitX86Select(Builder, CI->getArgOperand(2), Rep, 1145 CI->getArgOperand(1)); 1146 } else if (IsX86 && (Name.startswith("avx512.kunpck"))) { 1147 unsigned NumElts = CI->getType()->getScalarSizeInBits(); 1148 Value *LHS = getX86MaskVec(Builder, CI->getArgOperand(0), NumElts); 1149 Value *RHS = getX86MaskVec(Builder, CI->getArgOperand(1), NumElts); 1150 uint32_t Indices[64]; 1151 for (unsigned i = 0; i != NumElts; ++i) 1152 Indices[i] = i; 1153 1154 // First extract half of each vector. This gives better codegen than 1155 // doing it in a single shuffle. 1156 LHS = Builder.CreateShuffleVector(LHS, LHS, 1157 makeArrayRef(Indices, NumElts / 2)); 1158 RHS = Builder.CreateShuffleVector(RHS, RHS, 1159 makeArrayRef(Indices, NumElts / 2)); 1160 // Concat the vectors. 1161 // NOTE: Operands have to be swapped to match intrinsic definition. 1162 Rep = Builder.CreateShuffleVector(RHS, LHS, 1163 makeArrayRef(Indices, NumElts)); 1164 Rep = Builder.CreateBitCast(Rep, CI->getType()); 1165 } else if (IsX86 && Name == "avx512.kand.w") { 1166 Value *LHS = getX86MaskVec(Builder, CI->getArgOperand(0), 16); 1167 Value *RHS = getX86MaskVec(Builder, CI->getArgOperand(1), 16); 1168 Rep = Builder.CreateAnd(LHS, RHS); 1169 Rep = Builder.CreateBitCast(Rep, CI->getType()); 1170 } else if (IsX86 && Name == "avx512.kandn.w") { 1171 Value *LHS = getX86MaskVec(Builder, CI->getArgOperand(0), 16); 1172 Value *RHS = getX86MaskVec(Builder, CI->getArgOperand(1), 16); 1173 LHS = Builder.CreateNot(LHS); 1174 Rep = Builder.CreateAnd(LHS, RHS); 1175 Rep = Builder.CreateBitCast(Rep, CI->getType()); 1176 } else if (IsX86 && Name == "avx512.kor.w") { 1177 Value *LHS = getX86MaskVec(Builder, CI->getArgOperand(0), 16); 1178 Value *RHS = getX86MaskVec(Builder, CI->getArgOperand(1), 16); 1179 Rep = Builder.CreateOr(LHS, RHS); 1180 Rep = Builder.CreateBitCast(Rep, CI->getType()); 1181 } else if (IsX86 && Name == "avx512.kxor.w") { 1182 Value *LHS = getX86MaskVec(Builder, CI->getArgOperand(0), 16); 1183 Value *RHS = getX86MaskVec(Builder, CI->getArgOperand(1), 16); 1184 Rep = Builder.CreateXor(LHS, RHS); 1185 Rep = Builder.CreateBitCast(Rep, CI->getType()); 1186 } else if (IsX86 && Name == "avx512.kxnor.w") { 1187 Value *LHS = getX86MaskVec(Builder, CI->getArgOperand(0), 16); 1188 Value *RHS = getX86MaskVec(Builder, CI->getArgOperand(1), 16); 1189 LHS = Builder.CreateNot(LHS); 1190 Rep = Builder.CreateXor(LHS, RHS); 1191 Rep = Builder.CreateBitCast(Rep, CI->getType()); 1192 } else if (IsX86 && Name == "avx512.knot.w") { 1193 Rep = getX86MaskVec(Builder, CI->getArgOperand(0), 16); 1194 Rep = Builder.CreateNot(Rep); 1195 Rep = Builder.CreateBitCast(Rep, CI->getType()); 1196 } else if (IsX86 && 1197 (Name == "avx512.kortestz.w" || Name == "avx512.kortestc.w")) { 1198 Value *LHS = getX86MaskVec(Builder, CI->getArgOperand(0), 16); 1199 Value *RHS = getX86MaskVec(Builder, CI->getArgOperand(1), 16); 1200 Rep = Builder.CreateOr(LHS, RHS); 1201 Rep = Builder.CreateBitCast(Rep, Builder.getInt16Ty()); 1202 Value *C; 1203 if (Name[14] == 'c') 1204 C = ConstantInt::getAllOnesValue(Builder.getInt16Ty()); 1205 else 1206 C = ConstantInt::getNullValue(Builder.getInt16Ty()); 1207 Rep = Builder.CreateICmpEQ(Rep, C); 1208 Rep = Builder.CreateZExt(Rep, Builder.getInt32Ty()); 1209 } else if (IsX86 && (Name == "sse.add.ss" || Name == "sse2.add.sd")) { 1210 Type *I32Ty = Type::getInt32Ty(C); 1211 Value *Elt0 = Builder.CreateExtractElement(CI->getArgOperand(0), 1212 ConstantInt::get(I32Ty, 0)); 1213 Value *Elt1 = Builder.CreateExtractElement(CI->getArgOperand(1), 1214 ConstantInt::get(I32Ty, 0)); 1215 Rep = Builder.CreateInsertElement(CI->getArgOperand(0), 1216 Builder.CreateFAdd(Elt0, Elt1), 1217 ConstantInt::get(I32Ty, 0)); 1218 } else if (IsX86 && (Name == "sse.sub.ss" || Name == "sse2.sub.sd")) { 1219 Type *I32Ty = Type::getInt32Ty(C); 1220 Value *Elt0 = Builder.CreateExtractElement(CI->getArgOperand(0), 1221 ConstantInt::get(I32Ty, 0)); 1222 Value *Elt1 = Builder.CreateExtractElement(CI->getArgOperand(1), 1223 ConstantInt::get(I32Ty, 0)); 1224 Rep = Builder.CreateInsertElement(CI->getArgOperand(0), 1225 Builder.CreateFSub(Elt0, Elt1), 1226 ConstantInt::get(I32Ty, 0)); 1227 } else if (IsX86 && (Name == "sse.mul.ss" || Name == "sse2.mul.sd")) { 1228 Type *I32Ty = Type::getInt32Ty(C); 1229 Value *Elt0 = Builder.CreateExtractElement(CI->getArgOperand(0), 1230 ConstantInt::get(I32Ty, 0)); 1231 Value *Elt1 = Builder.CreateExtractElement(CI->getArgOperand(1), 1232 ConstantInt::get(I32Ty, 0)); 1233 Rep = Builder.CreateInsertElement(CI->getArgOperand(0), 1234 Builder.CreateFMul(Elt0, Elt1), 1235 ConstantInt::get(I32Ty, 0)); 1236 } else if (IsX86 && (Name == "sse.div.ss" || Name == "sse2.div.sd")) { 1237 Type *I32Ty = Type::getInt32Ty(C); 1238 Value *Elt0 = Builder.CreateExtractElement(CI->getArgOperand(0), 1239 ConstantInt::get(I32Ty, 0)); 1240 Value *Elt1 = Builder.CreateExtractElement(CI->getArgOperand(1), 1241 ConstantInt::get(I32Ty, 0)); 1242 Rep = Builder.CreateInsertElement(CI->getArgOperand(0), 1243 Builder.CreateFDiv(Elt0, Elt1), 1244 ConstantInt::get(I32Ty, 0)); 1245 } else if (IsX86 && Name.startswith("avx512.mask.pcmp")) { 1246 // "avx512.mask.pcmpeq." or "avx512.mask.pcmpgt." 1247 bool CmpEq = Name[16] == 'e'; 1248 Rep = upgradeMaskedCompare(Builder, *CI, CmpEq ? 0 : 6, true); 1249 } else if (IsX86 && Name.startswith("avx512.mask.cmp")) { 1250 unsigned Imm = cast<ConstantInt>(CI->getArgOperand(2))->getZExtValue(); 1251 Rep = upgradeMaskedCompare(Builder, *CI, Imm, true); 1252 } else if (IsX86 && Name.startswith("avx512.mask.ucmp")) { 1253 unsigned Imm = cast<ConstantInt>(CI->getArgOperand(2))->getZExtValue(); 1254 Rep = upgradeMaskedCompare(Builder, *CI, Imm, false); 1255 } else if (IsX86 && (Name.startswith("avx512.cvtb2mask.") || 1256 Name.startswith("avx512.cvtw2mask.") || 1257 Name.startswith("avx512.cvtd2mask.") || 1258 Name.startswith("avx512.cvtq2mask."))) { 1259 Value *Op = CI->getArgOperand(0); 1260 Value *Zero = llvm::Constant::getNullValue(Op->getType()); 1261 Rep = Builder.CreateICmp(ICmpInst::ICMP_SLT, Op, Zero); 1262 Rep = ApplyX86MaskOn1BitsVec(Builder, Rep, nullptr, 1263 Op->getType()->getVectorNumElements()); 1264 } else if(IsX86 && (Name == "ssse3.pabs.b.128" || 1265 Name == "ssse3.pabs.w.128" || 1266 Name == "ssse3.pabs.d.128" || 1267 Name.startswith("avx2.pabs") || 1268 Name.startswith("avx512.mask.pabs"))) { 1269 Rep = upgradeAbs(Builder, *CI); 1270 } else if (IsX86 && (Name == "sse41.pmaxsb" || 1271 Name == "sse2.pmaxs.w" || 1272 Name == "sse41.pmaxsd" || 1273 Name.startswith("avx2.pmaxs") || 1274 Name.startswith("avx512.mask.pmaxs"))) { 1275 Rep = upgradeIntMinMax(Builder, *CI, ICmpInst::ICMP_SGT); 1276 } else if (IsX86 && (Name == "sse2.pmaxu.b" || 1277 Name == "sse41.pmaxuw" || 1278 Name == "sse41.pmaxud" || 1279 Name.startswith("avx2.pmaxu") || 1280 Name.startswith("avx512.mask.pmaxu"))) { 1281 Rep = upgradeIntMinMax(Builder, *CI, ICmpInst::ICMP_UGT); 1282 } else if (IsX86 && (Name == "sse41.pminsb" || 1283 Name == "sse2.pmins.w" || 1284 Name == "sse41.pminsd" || 1285 Name.startswith("avx2.pmins") || 1286 Name.startswith("avx512.mask.pmins"))) { 1287 Rep = upgradeIntMinMax(Builder, *CI, ICmpInst::ICMP_SLT); 1288 } else if (IsX86 && (Name == "sse2.pminu.b" || 1289 Name == "sse41.pminuw" || 1290 Name == "sse41.pminud" || 1291 Name.startswith("avx2.pminu") || 1292 Name.startswith("avx512.mask.pminu"))) { 1293 Rep = upgradeIntMinMax(Builder, *CI, ICmpInst::ICMP_ULT); 1294 } else if (IsX86 && (Name == "sse2.cvtdq2pd" || 1295 Name == "sse2.cvtps2pd" || 1296 Name == "avx.cvtdq2.pd.256" || 1297 Name == "avx.cvt.ps2.pd.256" || 1298 Name.startswith("avx512.mask.cvtdq2pd.") || 1299 Name.startswith("avx512.mask.cvtudq2pd."))) { 1300 // Lossless i32/float to double conversion. 1301 // Extract the bottom elements if necessary and convert to double vector. 1302 Value *Src = CI->getArgOperand(0); 1303 VectorType *SrcTy = cast<VectorType>(Src->getType()); 1304 VectorType *DstTy = cast<VectorType>(CI->getType()); 1305 Rep = CI->getArgOperand(0); 1306 1307 unsigned NumDstElts = DstTy->getNumElements(); 1308 if (NumDstElts < SrcTy->getNumElements()) { 1309 assert(NumDstElts == 2 && "Unexpected vector size"); 1310 uint32_t ShuffleMask[2] = { 0, 1 }; 1311 Rep = Builder.CreateShuffleVector(Rep, UndefValue::get(SrcTy), 1312 ShuffleMask); 1313 } 1314 1315 bool SInt2Double = (StringRef::npos != Name.find("cvtdq2")); 1316 bool UInt2Double = (StringRef::npos != Name.find("cvtudq2")); 1317 if (SInt2Double) 1318 Rep = Builder.CreateSIToFP(Rep, DstTy, "cvtdq2pd"); 1319 else if (UInt2Double) 1320 Rep = Builder.CreateUIToFP(Rep, DstTy, "cvtudq2pd"); 1321 else 1322 Rep = Builder.CreateFPExt(Rep, DstTy, "cvtps2pd"); 1323 1324 if (CI->getNumArgOperands() == 3) 1325 Rep = EmitX86Select(Builder, CI->getArgOperand(2), Rep, 1326 CI->getArgOperand(1)); 1327 } else if (IsX86 && (Name.startswith("avx512.mask.loadu."))) { 1328 Rep = UpgradeMaskedLoad(Builder, CI->getArgOperand(0), 1329 CI->getArgOperand(1), CI->getArgOperand(2), 1330 /*Aligned*/false); 1331 } else if (IsX86 && (Name.startswith("avx512.mask.load."))) { 1332 Rep = UpgradeMaskedLoad(Builder, CI->getArgOperand(0), 1333 CI->getArgOperand(1),CI->getArgOperand(2), 1334 /*Aligned*/true); 1335 } else if (IsX86 && Name.startswith("xop.vpcom")) { 1336 Intrinsic::ID intID; 1337 if (Name.endswith("ub")) 1338 intID = Intrinsic::x86_xop_vpcomub; 1339 else if (Name.endswith("uw")) 1340 intID = Intrinsic::x86_xop_vpcomuw; 1341 else if (Name.endswith("ud")) 1342 intID = Intrinsic::x86_xop_vpcomud; 1343 else if (Name.endswith("uq")) 1344 intID = Intrinsic::x86_xop_vpcomuq; 1345 else if (Name.endswith("b")) 1346 intID = Intrinsic::x86_xop_vpcomb; 1347 else if (Name.endswith("w")) 1348 intID = Intrinsic::x86_xop_vpcomw; 1349 else if (Name.endswith("d")) 1350 intID = Intrinsic::x86_xop_vpcomd; 1351 else if (Name.endswith("q")) 1352 intID = Intrinsic::x86_xop_vpcomq; 1353 else 1354 llvm_unreachable("Unknown suffix"); 1355 1356 Name = Name.substr(9); // strip off "xop.vpcom" 1357 unsigned Imm; 1358 if (Name.startswith("lt")) 1359 Imm = 0; 1360 else if (Name.startswith("le")) 1361 Imm = 1; 1362 else if (Name.startswith("gt")) 1363 Imm = 2; 1364 else if (Name.startswith("ge")) 1365 Imm = 3; 1366 else if (Name.startswith("eq")) 1367 Imm = 4; 1368 else if (Name.startswith("ne")) 1369 Imm = 5; 1370 else if (Name.startswith("false")) 1371 Imm = 6; 1372 else if (Name.startswith("true")) 1373 Imm = 7; 1374 else 1375 llvm_unreachable("Unknown condition"); 1376 1377 Function *VPCOM = Intrinsic::getDeclaration(F->getParent(), intID); 1378 Rep = 1379 Builder.CreateCall(VPCOM, {CI->getArgOperand(0), CI->getArgOperand(1), 1380 Builder.getInt8(Imm)}); 1381 } else if (IsX86 && Name.startswith("xop.vpcmov")) { 1382 Value *Sel = CI->getArgOperand(2); 1383 Value *NotSel = Builder.CreateNot(Sel); 1384 Value *Sel0 = Builder.CreateAnd(CI->getArgOperand(0), Sel); 1385 Value *Sel1 = Builder.CreateAnd(CI->getArgOperand(1), NotSel); 1386 Rep = Builder.CreateOr(Sel0, Sel1); 1387 } else if (IsX86 && Name == "sse42.crc32.64.8") { 1388 Function *CRC32 = Intrinsic::getDeclaration(F->getParent(), 1389 Intrinsic::x86_sse42_crc32_32_8); 1390 Value *Trunc0 = Builder.CreateTrunc(CI->getArgOperand(0), Type::getInt32Ty(C)); 1391 Rep = Builder.CreateCall(CRC32, {Trunc0, CI->getArgOperand(1)}); 1392 Rep = Builder.CreateZExt(Rep, CI->getType(), ""); 1393 } else if (IsX86 && Name.startswith("avx.vbroadcast.s")) { 1394 // Replace broadcasts with a series of insertelements. 1395 Type *VecTy = CI->getType(); 1396 Type *EltTy = VecTy->getVectorElementType(); 1397 unsigned EltNum = VecTy->getVectorNumElements(); 1398 Value *Cast = Builder.CreateBitCast(CI->getArgOperand(0), 1399 EltTy->getPointerTo()); 1400 Value *Load = Builder.CreateLoad(EltTy, Cast); 1401 Type *I32Ty = Type::getInt32Ty(C); 1402 Rep = UndefValue::get(VecTy); 1403 for (unsigned I = 0; I < EltNum; ++I) 1404 Rep = Builder.CreateInsertElement(Rep, Load, 1405 ConstantInt::get(I32Ty, I)); 1406 } else if (IsX86 && (Name.startswith("sse41.pmovsx") || 1407 Name.startswith("sse41.pmovzx") || 1408 Name.startswith("avx2.pmovsx") || 1409 Name.startswith("avx2.pmovzx") || 1410 Name.startswith("avx512.mask.pmovsx") || 1411 Name.startswith("avx512.mask.pmovzx"))) { 1412 VectorType *SrcTy = cast<VectorType>(CI->getArgOperand(0)->getType()); 1413 VectorType *DstTy = cast<VectorType>(CI->getType()); 1414 unsigned NumDstElts = DstTy->getNumElements(); 1415 1416 // Extract a subvector of the first NumDstElts lanes and sign/zero extend. 1417 SmallVector<uint32_t, 8> ShuffleMask(NumDstElts); 1418 for (unsigned i = 0; i != NumDstElts; ++i) 1419 ShuffleMask[i] = i; 1420 1421 Value *SV = Builder.CreateShuffleVector( 1422 CI->getArgOperand(0), UndefValue::get(SrcTy), ShuffleMask); 1423 1424 bool DoSext = (StringRef::npos != Name.find("pmovsx")); 1425 Rep = DoSext ? Builder.CreateSExt(SV, DstTy) 1426 : Builder.CreateZExt(SV, DstTy); 1427 // If there are 3 arguments, it's a masked intrinsic so we need a select. 1428 if (CI->getNumArgOperands() == 3) 1429 Rep = EmitX86Select(Builder, CI->getArgOperand(2), Rep, 1430 CI->getArgOperand(1)); 1431 } else if (IsX86 && (Name.startswith("avx.vbroadcastf128") || 1432 Name == "avx2.vbroadcasti128")) { 1433 // Replace vbroadcastf128/vbroadcasti128 with a vector load+shuffle. 1434 Type *EltTy = CI->getType()->getVectorElementType(); 1435 unsigned NumSrcElts = 128 / EltTy->getPrimitiveSizeInBits(); 1436 Type *VT = VectorType::get(EltTy, NumSrcElts); 1437 Value *Op = Builder.CreatePointerCast(CI->getArgOperand(0), 1438 PointerType::getUnqual(VT)); 1439 Value *Load = Builder.CreateAlignedLoad(Op, 1); 1440 if (NumSrcElts == 2) 1441 Rep = Builder.CreateShuffleVector(Load, UndefValue::get(Load->getType()), 1442 { 0, 1, 0, 1 }); 1443 else 1444 Rep = Builder.CreateShuffleVector(Load, UndefValue::get(Load->getType()), 1445 { 0, 1, 2, 3, 0, 1, 2, 3 }); 1446 } else if (IsX86 && (Name.startswith("avx512.mask.shuf.i") || 1447 Name.startswith("avx512.mask.shuf.f"))) { 1448 unsigned Imm = cast<ConstantInt>(CI->getArgOperand(2))->getZExtValue(); 1449 Type *VT = CI->getType(); 1450 unsigned NumLanes = VT->getPrimitiveSizeInBits() / 128; 1451 unsigned NumElementsInLane = 128 / VT->getScalarSizeInBits(); 1452 unsigned ControlBitsMask = NumLanes - 1; 1453 unsigned NumControlBits = NumLanes / 2; 1454 SmallVector<uint32_t, 8> ShuffleMask(0); 1455 1456 for (unsigned l = 0; l != NumLanes; ++l) { 1457 unsigned LaneMask = (Imm >> (l * NumControlBits)) & ControlBitsMask; 1458 // We actually need the other source. 1459 if (l >= NumLanes / 2) 1460 LaneMask += NumLanes; 1461 for (unsigned i = 0; i != NumElementsInLane; ++i) 1462 ShuffleMask.push_back(LaneMask * NumElementsInLane + i); 1463 } 1464 Rep = Builder.CreateShuffleVector(CI->getArgOperand(0), 1465 CI->getArgOperand(1), ShuffleMask); 1466 Rep = EmitX86Select(Builder, CI->getArgOperand(4), Rep, 1467 CI->getArgOperand(3)); 1468 }else if (IsX86 && (Name.startswith("avx512.mask.broadcastf") || 1469 Name.startswith("avx512.mask.broadcasti"))) { 1470 unsigned NumSrcElts = 1471 CI->getArgOperand(0)->getType()->getVectorNumElements(); 1472 unsigned NumDstElts = CI->getType()->getVectorNumElements(); 1473 1474 SmallVector<uint32_t, 8> ShuffleMask(NumDstElts); 1475 for (unsigned i = 0; i != NumDstElts; ++i) 1476 ShuffleMask[i] = i % NumSrcElts; 1477 1478 Rep = Builder.CreateShuffleVector(CI->getArgOperand(0), 1479 CI->getArgOperand(0), 1480 ShuffleMask); 1481 Rep = EmitX86Select(Builder, CI->getArgOperand(2), Rep, 1482 CI->getArgOperand(1)); 1483 } else if (IsX86 && (Name.startswith("avx2.pbroadcast") || 1484 Name.startswith("avx2.vbroadcast") || 1485 Name.startswith("avx512.pbroadcast") || 1486 Name.startswith("avx512.mask.broadcast.s"))) { 1487 // Replace vp?broadcasts with a vector shuffle. 1488 Value *Op = CI->getArgOperand(0); 1489 unsigned NumElts = CI->getType()->getVectorNumElements(); 1490 Type *MaskTy = VectorType::get(Type::getInt32Ty(C), NumElts); 1491 Rep = Builder.CreateShuffleVector(Op, UndefValue::get(Op->getType()), 1492 Constant::getNullValue(MaskTy)); 1493 1494 if (CI->getNumArgOperands() == 3) 1495 Rep = EmitX86Select(Builder, CI->getArgOperand(2), Rep, 1496 CI->getArgOperand(1)); 1497 } else if (IsX86 && Name.startswith("avx512.mask.palignr.")) { 1498 Rep = UpgradeX86ALIGNIntrinsics(Builder, CI->getArgOperand(0), 1499 CI->getArgOperand(1), 1500 CI->getArgOperand(2), 1501 CI->getArgOperand(3), 1502 CI->getArgOperand(4), 1503 false); 1504 } else if (IsX86 && Name.startswith("avx512.mask.valign.")) { 1505 Rep = UpgradeX86ALIGNIntrinsics(Builder, CI->getArgOperand(0), 1506 CI->getArgOperand(1), 1507 CI->getArgOperand(2), 1508 CI->getArgOperand(3), 1509 CI->getArgOperand(4), 1510 true); 1511 } else if (IsX86 && (Name == "sse2.psll.dq" || 1512 Name == "avx2.psll.dq")) { 1513 // 128/256-bit shift left specified in bits. 1514 unsigned Shift = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue(); 1515 Rep = UpgradeX86PSLLDQIntrinsics(Builder, CI->getArgOperand(0), 1516 Shift / 8); // Shift is in bits. 1517 } else if (IsX86 && (Name == "sse2.psrl.dq" || 1518 Name == "avx2.psrl.dq")) { 1519 // 128/256-bit shift right specified in bits. 1520 unsigned Shift = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue(); 1521 Rep = UpgradeX86PSRLDQIntrinsics(Builder, CI->getArgOperand(0), 1522 Shift / 8); // Shift is in bits. 1523 } else if (IsX86 && (Name == "sse2.psll.dq.bs" || 1524 Name == "avx2.psll.dq.bs" || 1525 Name == "avx512.psll.dq.512")) { 1526 // 128/256/512-bit shift left specified in bytes. 1527 unsigned Shift = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue(); 1528 Rep = UpgradeX86PSLLDQIntrinsics(Builder, CI->getArgOperand(0), Shift); 1529 } else if (IsX86 && (Name == "sse2.psrl.dq.bs" || 1530 Name == "avx2.psrl.dq.bs" || 1531 Name == "avx512.psrl.dq.512")) { 1532 // 128/256/512-bit shift right specified in bytes. 1533 unsigned Shift = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue(); 1534 Rep = UpgradeX86PSRLDQIntrinsics(Builder, CI->getArgOperand(0), Shift); 1535 } else if (IsX86 && (Name == "sse41.pblendw" || 1536 Name.startswith("sse41.blendp") || 1537 Name.startswith("avx.blend.p") || 1538 Name == "avx2.pblendw" || 1539 Name.startswith("avx2.pblendd."))) { 1540 Value *Op0 = CI->getArgOperand(0); 1541 Value *Op1 = CI->getArgOperand(1); 1542 unsigned Imm = cast <ConstantInt>(CI->getArgOperand(2))->getZExtValue(); 1543 VectorType *VecTy = cast<VectorType>(CI->getType()); 1544 unsigned NumElts = VecTy->getNumElements(); 1545 1546 SmallVector<uint32_t, 16> Idxs(NumElts); 1547 for (unsigned i = 0; i != NumElts; ++i) 1548 Idxs[i] = ((Imm >> (i%8)) & 1) ? i + NumElts : i; 1549 1550 Rep = Builder.CreateShuffleVector(Op0, Op1, Idxs); 1551 } else if (IsX86 && (Name.startswith("avx.vinsertf128.") || 1552 Name == "avx2.vinserti128" || 1553 Name.startswith("avx512.mask.insert"))) { 1554 Value *Op0 = CI->getArgOperand(0); 1555 Value *Op1 = CI->getArgOperand(1); 1556 unsigned Imm = cast<ConstantInt>(CI->getArgOperand(2))->getZExtValue(); 1557 unsigned DstNumElts = CI->getType()->getVectorNumElements(); 1558 unsigned SrcNumElts = Op1->getType()->getVectorNumElements(); 1559 unsigned Scale = DstNumElts / SrcNumElts; 1560 1561 // Mask off the high bits of the immediate value; hardware ignores those. 1562 Imm = Imm % Scale; 1563 1564 // Extend the second operand into a vector the size of the destination. 1565 Value *UndefV = UndefValue::get(Op1->getType()); 1566 SmallVector<uint32_t, 8> Idxs(DstNumElts); 1567 for (unsigned i = 0; i != SrcNumElts; ++i) 1568 Idxs[i] = i; 1569 for (unsigned i = SrcNumElts; i != DstNumElts; ++i) 1570 Idxs[i] = SrcNumElts; 1571 Rep = Builder.CreateShuffleVector(Op1, UndefV, Idxs); 1572 1573 // Insert the second operand into the first operand. 1574 1575 // Note that there is no guarantee that instruction lowering will actually 1576 // produce a vinsertf128 instruction for the created shuffles. In 1577 // particular, the 0 immediate case involves no lane changes, so it can 1578 // be handled as a blend. 1579 1580 // Example of shuffle mask for 32-bit elements: 1581 // Imm = 1 <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11> 1582 // Imm = 0 <i32 8, i32 9, i32 10, i32 11, i32 4, i32 5, i32 6, i32 7 > 1583 1584 // First fill with identify mask. 1585 for (unsigned i = 0; i != DstNumElts; ++i) 1586 Idxs[i] = i; 1587 // Then replace the elements where we need to insert. 1588 for (unsigned i = 0; i != SrcNumElts; ++i) 1589 Idxs[i + Imm * SrcNumElts] = i + DstNumElts; 1590 Rep = Builder.CreateShuffleVector(Op0, Rep, Idxs); 1591 1592 // If the intrinsic has a mask operand, handle that. 1593 if (CI->getNumArgOperands() == 5) 1594 Rep = EmitX86Select(Builder, CI->getArgOperand(4), Rep, 1595 CI->getArgOperand(3)); 1596 } else if (IsX86 && (Name.startswith("avx.vextractf128.") || 1597 Name == "avx2.vextracti128" || 1598 Name.startswith("avx512.mask.vextract"))) { 1599 Value *Op0 = CI->getArgOperand(0); 1600 unsigned Imm = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue(); 1601 unsigned DstNumElts = CI->getType()->getVectorNumElements(); 1602 unsigned SrcNumElts = Op0->getType()->getVectorNumElements(); 1603 unsigned Scale = SrcNumElts / DstNumElts; 1604 1605 // Mask off the high bits of the immediate value; hardware ignores those. 1606 Imm = Imm % Scale; 1607 1608 // Get indexes for the subvector of the input vector. 1609 SmallVector<uint32_t, 8> Idxs(DstNumElts); 1610 for (unsigned i = 0; i != DstNumElts; ++i) { 1611 Idxs[i] = i + (Imm * DstNumElts); 1612 } 1613 Rep = Builder.CreateShuffleVector(Op0, Op0, Idxs); 1614 1615 // If the intrinsic has a mask operand, handle that. 1616 if (CI->getNumArgOperands() == 4) 1617 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1618 CI->getArgOperand(2)); 1619 } else if (!IsX86 && Name == "stackprotectorcheck") { 1620 Rep = nullptr; 1621 } else if (IsX86 && (Name.startswith("avx512.mask.perm.df.") || 1622 Name.startswith("avx512.mask.perm.di."))) { 1623 Value *Op0 = CI->getArgOperand(0); 1624 unsigned Imm = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue(); 1625 VectorType *VecTy = cast<VectorType>(CI->getType()); 1626 unsigned NumElts = VecTy->getNumElements(); 1627 1628 SmallVector<uint32_t, 8> Idxs(NumElts); 1629 for (unsigned i = 0; i != NumElts; ++i) 1630 Idxs[i] = (i & ~0x3) + ((Imm >> (2 * (i & 0x3))) & 3); 1631 1632 Rep = Builder.CreateShuffleVector(Op0, Op0, Idxs); 1633 1634 if (CI->getNumArgOperands() == 4) 1635 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1636 CI->getArgOperand(2)); 1637 } else if (IsX86 && (Name.startswith("avx.vperm2f128.") || 1638 Name == "avx2.vperm2i128")) { 1639 // The immediate permute control byte looks like this: 1640 // [1:0] - select 128 bits from sources for low half of destination 1641 // [2] - ignore 1642 // [3] - zero low half of destination 1643 // [5:4] - select 128 bits from sources for high half of destination 1644 // [6] - ignore 1645 // [7] - zero high half of destination 1646 1647 uint8_t Imm = cast<ConstantInt>(CI->getArgOperand(2))->getZExtValue(); 1648 1649 unsigned NumElts = CI->getType()->getVectorNumElements(); 1650 unsigned HalfSize = NumElts / 2; 1651 SmallVector<uint32_t, 8> ShuffleMask(NumElts); 1652 1653 // Determine which operand(s) are actually in use for this instruction. 1654 Value *V0 = (Imm & 0x02) ? CI->getArgOperand(1) : CI->getArgOperand(0); 1655 Value *V1 = (Imm & 0x20) ? CI->getArgOperand(1) : CI->getArgOperand(0); 1656 1657 // If needed, replace operands based on zero mask. 1658 V0 = (Imm & 0x08) ? ConstantAggregateZero::get(CI->getType()) : V0; 1659 V1 = (Imm & 0x80) ? ConstantAggregateZero::get(CI->getType()) : V1; 1660 1661 // Permute low half of result. 1662 unsigned StartIndex = (Imm & 0x01) ? HalfSize : 0; 1663 for (unsigned i = 0; i < HalfSize; ++i) 1664 ShuffleMask[i] = StartIndex + i; 1665 1666 // Permute high half of result. 1667 StartIndex = (Imm & 0x10) ? HalfSize : 0; 1668 for (unsigned i = 0; i < HalfSize; ++i) 1669 ShuffleMask[i + HalfSize] = NumElts + StartIndex + i; 1670 1671 Rep = Builder.CreateShuffleVector(V0, V1, ShuffleMask); 1672 1673 } else if (IsX86 && (Name.startswith("avx.vpermil.") || 1674 Name == "sse2.pshuf.d" || 1675 Name.startswith("avx512.mask.vpermil.p") || 1676 Name.startswith("avx512.mask.pshuf.d."))) { 1677 Value *Op0 = CI->getArgOperand(0); 1678 unsigned Imm = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue(); 1679 VectorType *VecTy = cast<VectorType>(CI->getType()); 1680 unsigned NumElts = VecTy->getNumElements(); 1681 // Calculate the size of each index in the immediate. 1682 unsigned IdxSize = 64 / VecTy->getScalarSizeInBits(); 1683 unsigned IdxMask = ((1 << IdxSize) - 1); 1684 1685 SmallVector<uint32_t, 8> Idxs(NumElts); 1686 // Lookup the bits for this element, wrapping around the immediate every 1687 // 8-bits. Elements are grouped into sets of 2 or 4 elements so we need 1688 // to offset by the first index of each group. 1689 for (unsigned i = 0; i != NumElts; ++i) 1690 Idxs[i] = ((Imm >> ((i * IdxSize) % 8)) & IdxMask) | (i & ~IdxMask); 1691 1692 Rep = Builder.CreateShuffleVector(Op0, Op0, Idxs); 1693 1694 if (CI->getNumArgOperands() == 4) 1695 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1696 CI->getArgOperand(2)); 1697 } else if (IsX86 && (Name == "sse2.pshufl.w" || 1698 Name.startswith("avx512.mask.pshufl.w."))) { 1699 Value *Op0 = CI->getArgOperand(0); 1700 unsigned Imm = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue(); 1701 unsigned NumElts = CI->getType()->getVectorNumElements(); 1702 1703 SmallVector<uint32_t, 16> Idxs(NumElts); 1704 for (unsigned l = 0; l != NumElts; l += 8) { 1705 for (unsigned i = 0; i != 4; ++i) 1706 Idxs[i + l] = ((Imm >> (2 * i)) & 0x3) + l; 1707 for (unsigned i = 4; i != 8; ++i) 1708 Idxs[i + l] = i + l; 1709 } 1710 1711 Rep = Builder.CreateShuffleVector(Op0, Op0, Idxs); 1712 1713 if (CI->getNumArgOperands() == 4) 1714 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1715 CI->getArgOperand(2)); 1716 } else if (IsX86 && (Name == "sse2.pshufh.w" || 1717 Name.startswith("avx512.mask.pshufh.w."))) { 1718 Value *Op0 = CI->getArgOperand(0); 1719 unsigned Imm = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue(); 1720 unsigned NumElts = CI->getType()->getVectorNumElements(); 1721 1722 SmallVector<uint32_t, 16> Idxs(NumElts); 1723 for (unsigned l = 0; l != NumElts; l += 8) { 1724 for (unsigned i = 0; i != 4; ++i) 1725 Idxs[i + l] = i + l; 1726 for (unsigned i = 0; i != 4; ++i) 1727 Idxs[i + l + 4] = ((Imm >> (2 * i)) & 0x3) + 4 + l; 1728 } 1729 1730 Rep = Builder.CreateShuffleVector(Op0, Op0, Idxs); 1731 1732 if (CI->getNumArgOperands() == 4) 1733 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1734 CI->getArgOperand(2)); 1735 } else if (IsX86 && Name.startswith("avx512.mask.shuf.p")) { 1736 Value *Op0 = CI->getArgOperand(0); 1737 Value *Op1 = CI->getArgOperand(1); 1738 unsigned Imm = cast<ConstantInt>(CI->getArgOperand(2))->getZExtValue(); 1739 unsigned NumElts = CI->getType()->getVectorNumElements(); 1740 1741 unsigned NumLaneElts = 128/CI->getType()->getScalarSizeInBits(); 1742 unsigned HalfLaneElts = NumLaneElts / 2; 1743 1744 SmallVector<uint32_t, 16> Idxs(NumElts); 1745 for (unsigned i = 0; i != NumElts; ++i) { 1746 // Base index is the starting element of the lane. 1747 Idxs[i] = i - (i % NumLaneElts); 1748 // If we are half way through the lane switch to the other source. 1749 if ((i % NumLaneElts) >= HalfLaneElts) 1750 Idxs[i] += NumElts; 1751 // Now select the specific element. By adding HalfLaneElts bits from 1752 // the immediate. Wrapping around the immediate every 8-bits. 1753 Idxs[i] += (Imm >> ((i * HalfLaneElts) % 8)) & ((1 << HalfLaneElts) - 1); 1754 } 1755 1756 Rep = Builder.CreateShuffleVector(Op0, Op1, Idxs); 1757 1758 Rep = EmitX86Select(Builder, CI->getArgOperand(4), Rep, 1759 CI->getArgOperand(3)); 1760 } else if (IsX86 && (Name.startswith("avx512.mask.movddup") || 1761 Name.startswith("avx512.mask.movshdup") || 1762 Name.startswith("avx512.mask.movsldup"))) { 1763 Value *Op0 = CI->getArgOperand(0); 1764 unsigned NumElts = CI->getType()->getVectorNumElements(); 1765 unsigned NumLaneElts = 128/CI->getType()->getScalarSizeInBits(); 1766 1767 unsigned Offset = 0; 1768 if (Name.startswith("avx512.mask.movshdup.")) 1769 Offset = 1; 1770 1771 SmallVector<uint32_t, 16> Idxs(NumElts); 1772 for (unsigned l = 0; l != NumElts; l += NumLaneElts) 1773 for (unsigned i = 0; i != NumLaneElts; i += 2) { 1774 Idxs[i + l + 0] = i + l + Offset; 1775 Idxs[i + l + 1] = i + l + Offset; 1776 } 1777 1778 Rep = Builder.CreateShuffleVector(Op0, Op0, Idxs); 1779 1780 Rep = EmitX86Select(Builder, CI->getArgOperand(2), Rep, 1781 CI->getArgOperand(1)); 1782 } else if (IsX86 && (Name.startswith("avx512.mask.punpckl") || 1783 Name.startswith("avx512.mask.unpckl."))) { 1784 Value *Op0 = CI->getArgOperand(0); 1785 Value *Op1 = CI->getArgOperand(1); 1786 int NumElts = CI->getType()->getVectorNumElements(); 1787 int NumLaneElts = 128/CI->getType()->getScalarSizeInBits(); 1788 1789 SmallVector<uint32_t, 64> Idxs(NumElts); 1790 for (int l = 0; l != NumElts; l += NumLaneElts) 1791 for (int i = 0; i != NumLaneElts; ++i) 1792 Idxs[i + l] = l + (i / 2) + NumElts * (i % 2); 1793 1794 Rep = Builder.CreateShuffleVector(Op0, Op1, Idxs); 1795 1796 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1797 CI->getArgOperand(2)); 1798 } else if (IsX86 && (Name.startswith("avx512.mask.punpckh") || 1799 Name.startswith("avx512.mask.unpckh."))) { 1800 Value *Op0 = CI->getArgOperand(0); 1801 Value *Op1 = CI->getArgOperand(1); 1802 int NumElts = CI->getType()->getVectorNumElements(); 1803 int NumLaneElts = 128/CI->getType()->getScalarSizeInBits(); 1804 1805 SmallVector<uint32_t, 64> Idxs(NumElts); 1806 for (int l = 0; l != NumElts; l += NumLaneElts) 1807 for (int i = 0; i != NumLaneElts; ++i) 1808 Idxs[i + l] = (NumLaneElts / 2) + l + (i / 2) + NumElts * (i % 2); 1809 1810 Rep = Builder.CreateShuffleVector(Op0, Op1, Idxs); 1811 1812 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1813 CI->getArgOperand(2)); 1814 } else if (IsX86 && Name.startswith("avx512.mask.pand.")) { 1815 Rep = Builder.CreateAnd(CI->getArgOperand(0), CI->getArgOperand(1)); 1816 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1817 CI->getArgOperand(2)); 1818 } else if (IsX86 && Name.startswith("avx512.mask.pandn.")) { 1819 Rep = Builder.CreateAnd(Builder.CreateNot(CI->getArgOperand(0)), 1820 CI->getArgOperand(1)); 1821 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1822 CI->getArgOperand(2)); 1823 } else if (IsX86 && Name.startswith("avx512.mask.por.")) { 1824 Rep = Builder.CreateOr(CI->getArgOperand(0), CI->getArgOperand(1)); 1825 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1826 CI->getArgOperand(2)); 1827 } else if (IsX86 && Name.startswith("avx512.mask.pxor.")) { 1828 Rep = Builder.CreateXor(CI->getArgOperand(0), CI->getArgOperand(1)); 1829 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1830 CI->getArgOperand(2)); 1831 } else if (IsX86 && Name.startswith("avx512.mask.and.")) { 1832 VectorType *FTy = cast<VectorType>(CI->getType()); 1833 VectorType *ITy = VectorType::getInteger(FTy); 1834 Rep = Builder.CreateAnd(Builder.CreateBitCast(CI->getArgOperand(0), ITy), 1835 Builder.CreateBitCast(CI->getArgOperand(1), ITy)); 1836 Rep = Builder.CreateBitCast(Rep, FTy); 1837 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1838 CI->getArgOperand(2)); 1839 } else if (IsX86 && Name.startswith("avx512.mask.andn.")) { 1840 VectorType *FTy = cast<VectorType>(CI->getType()); 1841 VectorType *ITy = VectorType::getInteger(FTy); 1842 Rep = Builder.CreateNot(Builder.CreateBitCast(CI->getArgOperand(0), ITy)); 1843 Rep = Builder.CreateAnd(Rep, 1844 Builder.CreateBitCast(CI->getArgOperand(1), ITy)); 1845 Rep = Builder.CreateBitCast(Rep, FTy); 1846 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1847 CI->getArgOperand(2)); 1848 } else if (IsX86 && Name.startswith("avx512.mask.or.")) { 1849 VectorType *FTy = cast<VectorType>(CI->getType()); 1850 VectorType *ITy = VectorType::getInteger(FTy); 1851 Rep = Builder.CreateOr(Builder.CreateBitCast(CI->getArgOperand(0), ITy), 1852 Builder.CreateBitCast(CI->getArgOperand(1), ITy)); 1853 Rep = Builder.CreateBitCast(Rep, FTy); 1854 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1855 CI->getArgOperand(2)); 1856 } else if (IsX86 && Name.startswith("avx512.mask.xor.")) { 1857 VectorType *FTy = cast<VectorType>(CI->getType()); 1858 VectorType *ITy = VectorType::getInteger(FTy); 1859 Rep = Builder.CreateXor(Builder.CreateBitCast(CI->getArgOperand(0), ITy), 1860 Builder.CreateBitCast(CI->getArgOperand(1), ITy)); 1861 Rep = Builder.CreateBitCast(Rep, FTy); 1862 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1863 CI->getArgOperand(2)); 1864 } else if (IsX86 && Name.startswith("avx512.mask.padd.")) { 1865 Rep = Builder.CreateAdd(CI->getArgOperand(0), CI->getArgOperand(1)); 1866 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1867 CI->getArgOperand(2)); 1868 } else if (IsX86 && Name.startswith("avx512.mask.psub.")) { 1869 Rep = Builder.CreateSub(CI->getArgOperand(0), CI->getArgOperand(1)); 1870 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1871 CI->getArgOperand(2)); 1872 } else if (IsX86 && Name.startswith("avx512.mask.pmull.")) { 1873 Rep = Builder.CreateMul(CI->getArgOperand(0), CI->getArgOperand(1)); 1874 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1875 CI->getArgOperand(2)); 1876 } else if (IsX86 && (Name.startswith("avx512.mask.add.p"))) { 1877 Rep = Builder.CreateFAdd(CI->getArgOperand(0), CI->getArgOperand(1)); 1878 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1879 CI->getArgOperand(2)); 1880 } else if (IsX86 && Name.startswith("avx512.mask.div.p")) { 1881 Rep = Builder.CreateFDiv(CI->getArgOperand(0), CI->getArgOperand(1)); 1882 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1883 CI->getArgOperand(2)); 1884 } else if (IsX86 && Name.startswith("avx512.mask.mul.p")) { 1885 Rep = Builder.CreateFMul(CI->getArgOperand(0), CI->getArgOperand(1)); 1886 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1887 CI->getArgOperand(2)); 1888 } else if (IsX86 && Name.startswith("avx512.mask.sub.p")) { 1889 Rep = Builder.CreateFSub(CI->getArgOperand(0), CI->getArgOperand(1)); 1890 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1891 CI->getArgOperand(2)); 1892 } else if (IsX86 && Name.startswith("avx512.mask.lzcnt.")) { 1893 Rep = Builder.CreateCall(Intrinsic::getDeclaration(F->getParent(), 1894 Intrinsic::ctlz, 1895 CI->getType()), 1896 { CI->getArgOperand(0), Builder.getInt1(false) }); 1897 Rep = EmitX86Select(Builder, CI->getArgOperand(2), Rep, 1898 CI->getArgOperand(1)); 1899 } else if (IsX86 && (Name.startswith("avx512.mask.max.p") || 1900 Name.startswith("avx512.mask.min.p"))) { 1901 bool IsMin = Name[13] == 'i'; 1902 VectorType *VecTy = cast<VectorType>(CI->getType()); 1903 unsigned VecWidth = VecTy->getPrimitiveSizeInBits(); 1904 unsigned EltWidth = VecTy->getScalarSizeInBits(); 1905 Intrinsic::ID IID; 1906 if (!IsMin && VecWidth == 128 && EltWidth == 32) 1907 IID = Intrinsic::x86_sse_max_ps; 1908 else if (!IsMin && VecWidth == 128 && EltWidth == 64) 1909 IID = Intrinsic::x86_sse2_max_pd; 1910 else if (!IsMin && VecWidth == 256 && EltWidth == 32) 1911 IID = Intrinsic::x86_avx_max_ps_256; 1912 else if (!IsMin && VecWidth == 256 && EltWidth == 64) 1913 IID = Intrinsic::x86_avx_max_pd_256; 1914 else if (IsMin && VecWidth == 128 && EltWidth == 32) 1915 IID = Intrinsic::x86_sse_min_ps; 1916 else if (IsMin && VecWidth == 128 && EltWidth == 64) 1917 IID = Intrinsic::x86_sse2_min_pd; 1918 else if (IsMin && VecWidth == 256 && EltWidth == 32) 1919 IID = Intrinsic::x86_avx_min_ps_256; 1920 else if (IsMin && VecWidth == 256 && EltWidth == 64) 1921 IID = Intrinsic::x86_avx_min_pd_256; 1922 else 1923 llvm_unreachable("Unexpected intrinsic"); 1924 1925 Rep = Builder.CreateCall(Intrinsic::getDeclaration(F->getParent(), IID), 1926 { CI->getArgOperand(0), CI->getArgOperand(1) }); 1927 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1928 CI->getArgOperand(2)); 1929 } else if (IsX86 && Name.startswith("avx512.mask.pshuf.b.")) { 1930 VectorType *VecTy = cast<VectorType>(CI->getType()); 1931 Intrinsic::ID IID; 1932 if (VecTy->getPrimitiveSizeInBits() == 128) 1933 IID = Intrinsic::x86_ssse3_pshuf_b_128; 1934 else if (VecTy->getPrimitiveSizeInBits() == 256) 1935 IID = Intrinsic::x86_avx2_pshuf_b; 1936 else if (VecTy->getPrimitiveSizeInBits() == 512) 1937 IID = Intrinsic::x86_avx512_pshuf_b_512; 1938 else 1939 llvm_unreachable("Unexpected intrinsic"); 1940 1941 Rep = Builder.CreateCall(Intrinsic::getDeclaration(F->getParent(), IID), 1942 { CI->getArgOperand(0), CI->getArgOperand(1) }); 1943 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1944 CI->getArgOperand(2)); 1945 } else if (IsX86 && (Name.startswith("avx512.mask.pmul.dq.") || 1946 Name.startswith("avx512.mask.pmulu.dq."))) { 1947 bool IsUnsigned = Name[16] == 'u'; 1948 VectorType *VecTy = cast<VectorType>(CI->getType()); 1949 Intrinsic::ID IID; 1950 if (!IsUnsigned && VecTy->getPrimitiveSizeInBits() == 128) 1951 IID = Intrinsic::x86_sse41_pmuldq; 1952 else if (!IsUnsigned && VecTy->getPrimitiveSizeInBits() == 256) 1953 IID = Intrinsic::x86_avx2_pmul_dq; 1954 else if (!IsUnsigned && VecTy->getPrimitiveSizeInBits() == 512) 1955 IID = Intrinsic::x86_avx512_pmul_dq_512; 1956 else if (IsUnsigned && VecTy->getPrimitiveSizeInBits() == 128) 1957 IID = Intrinsic::x86_sse2_pmulu_dq; 1958 else if (IsUnsigned && VecTy->getPrimitiveSizeInBits() == 256) 1959 IID = Intrinsic::x86_avx2_pmulu_dq; 1960 else if (IsUnsigned && VecTy->getPrimitiveSizeInBits() == 512) 1961 IID = Intrinsic::x86_avx512_pmulu_dq_512; 1962 else 1963 llvm_unreachable("Unexpected intrinsic"); 1964 1965 Rep = Builder.CreateCall(Intrinsic::getDeclaration(F->getParent(), IID), 1966 { CI->getArgOperand(0), CI->getArgOperand(1) }); 1967 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1968 CI->getArgOperand(2)); 1969 } else if (IsX86 && Name.startswith("avx512.mask.pmul.hr.sw.")) { 1970 VectorType *VecTy = cast<VectorType>(CI->getType()); 1971 Intrinsic::ID IID; 1972 if (VecTy->getPrimitiveSizeInBits() == 128) 1973 IID = Intrinsic::x86_ssse3_pmul_hr_sw_128; 1974 else if (VecTy->getPrimitiveSizeInBits() == 256) 1975 IID = Intrinsic::x86_avx2_pmul_hr_sw; 1976 else if (VecTy->getPrimitiveSizeInBits() == 512) 1977 IID = Intrinsic::x86_avx512_pmul_hr_sw_512; 1978 else 1979 llvm_unreachable("Unexpected intrinsic"); 1980 1981 Rep = Builder.CreateCall(Intrinsic::getDeclaration(F->getParent(), IID), 1982 { CI->getArgOperand(0), CI->getArgOperand(1) }); 1983 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 1984 CI->getArgOperand(2)); 1985 } else if (IsX86 && (Name.startswith("avx512.mask.pmulh.w.") || 1986 Name.startswith("avx512.mask.pmulhu.w."))) { 1987 bool IsUnsigned = Name[17] == 'u'; 1988 VectorType *VecTy = cast<VectorType>(CI->getType()); 1989 Intrinsic::ID IID; 1990 if (!IsUnsigned && VecTy->getPrimitiveSizeInBits() == 128) 1991 IID = Intrinsic::x86_sse2_pmulh_w; 1992 else if (!IsUnsigned && VecTy->getPrimitiveSizeInBits() == 256) 1993 IID = Intrinsic::x86_avx2_pmulh_w; 1994 else if (!IsUnsigned && VecTy->getPrimitiveSizeInBits() == 512) 1995 IID = Intrinsic::x86_avx512_pmulh_w_512; 1996 else if (IsUnsigned && VecTy->getPrimitiveSizeInBits() == 128) 1997 IID = Intrinsic::x86_sse2_pmulhu_w; 1998 else if (IsUnsigned && VecTy->getPrimitiveSizeInBits() == 256) 1999 IID = Intrinsic::x86_avx2_pmulhu_w; 2000 else if (IsUnsigned && VecTy->getPrimitiveSizeInBits() == 512) 2001 IID = Intrinsic::x86_avx512_pmulhu_w_512; 2002 else 2003 llvm_unreachable("Unexpected intrinsic"); 2004 2005 Rep = Builder.CreateCall(Intrinsic::getDeclaration(F->getParent(), IID), 2006 { CI->getArgOperand(0), CI->getArgOperand(1) }); 2007 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 2008 CI->getArgOperand(2)); 2009 } else if (IsX86 && Name.startswith("avx512.mask.pack")) { 2010 bool IsUnsigned = Name[16] == 'u'; 2011 bool IsDW = Name[18] == 'd'; 2012 VectorType *VecTy = cast<VectorType>(CI->getType()); 2013 Intrinsic::ID IID; 2014 if (!IsUnsigned && !IsDW && VecTy->getPrimitiveSizeInBits() == 128) 2015 IID = Intrinsic::x86_sse2_packsswb_128; 2016 else if (!IsUnsigned && !IsDW && VecTy->getPrimitiveSizeInBits() == 256) 2017 IID = Intrinsic::x86_avx2_packsswb; 2018 else if (!IsUnsigned && !IsDW && VecTy->getPrimitiveSizeInBits() == 512) 2019 IID = Intrinsic::x86_avx512_packsswb_512; 2020 else if (!IsUnsigned && IsDW && VecTy->getPrimitiveSizeInBits() == 128) 2021 IID = Intrinsic::x86_sse2_packssdw_128; 2022 else if (!IsUnsigned && IsDW && VecTy->getPrimitiveSizeInBits() == 256) 2023 IID = Intrinsic::x86_avx2_packssdw; 2024 else if (!IsUnsigned && IsDW && VecTy->getPrimitiveSizeInBits() == 512) 2025 IID = Intrinsic::x86_avx512_packssdw_512; 2026 else if (IsUnsigned && !IsDW && VecTy->getPrimitiveSizeInBits() == 128) 2027 IID = Intrinsic::x86_sse2_packuswb_128; 2028 else if (IsUnsigned && !IsDW && VecTy->getPrimitiveSizeInBits() == 256) 2029 IID = Intrinsic::x86_avx2_packuswb; 2030 else if (IsUnsigned && !IsDW && VecTy->getPrimitiveSizeInBits() == 512) 2031 IID = Intrinsic::x86_avx512_packuswb_512; 2032 else if (IsUnsigned && IsDW && VecTy->getPrimitiveSizeInBits() == 128) 2033 IID = Intrinsic::x86_sse41_packusdw; 2034 else if (IsUnsigned && IsDW && VecTy->getPrimitiveSizeInBits() == 256) 2035 IID = Intrinsic::x86_avx2_packusdw; 2036 else if (IsUnsigned && IsDW && VecTy->getPrimitiveSizeInBits() == 512) 2037 IID = Intrinsic::x86_avx512_packusdw_512; 2038 else 2039 llvm_unreachable("Unexpected intrinsic"); 2040 2041 Rep = Builder.CreateCall(Intrinsic::getDeclaration(F->getParent(), IID), 2042 { CI->getArgOperand(0), CI->getArgOperand(1) }); 2043 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 2044 CI->getArgOperand(2)); 2045 } else if (IsX86 && Name.startswith("avx512.mask.psll")) { 2046 bool IsImmediate = Name[16] == 'i' || 2047 (Name.size() > 18 && Name[18] == 'i'); 2048 bool IsVariable = Name[16] == 'v'; 2049 char Size = Name[16] == '.' ? Name[17] : 2050 Name[17] == '.' ? Name[18] : 2051 Name[18] == '.' ? Name[19] : 2052 Name[20]; 2053 2054 Intrinsic::ID IID; 2055 if (IsVariable && Name[17] != '.') { 2056 if (Size == 'd' && Name[17] == '2') // avx512.mask.psllv2.di 2057 IID = Intrinsic::x86_avx2_psllv_q; 2058 else if (Size == 'd' && Name[17] == '4') // avx512.mask.psllv4.di 2059 IID = Intrinsic::x86_avx2_psllv_q_256; 2060 else if (Size == 's' && Name[17] == '4') // avx512.mask.psllv4.si 2061 IID = Intrinsic::x86_avx2_psllv_d; 2062 else if (Size == 's' && Name[17] == '8') // avx512.mask.psllv8.si 2063 IID = Intrinsic::x86_avx2_psllv_d_256; 2064 else if (Size == 'h' && Name[17] == '8') // avx512.mask.psllv8.hi 2065 IID = Intrinsic::x86_avx512_psllv_w_128; 2066 else if (Size == 'h' && Name[17] == '1') // avx512.mask.psllv16.hi 2067 IID = Intrinsic::x86_avx512_psllv_w_256; 2068 else if (Name[17] == '3' && Name[18] == '2') // avx512.mask.psllv32hi 2069 IID = Intrinsic::x86_avx512_psllv_w_512; 2070 else 2071 llvm_unreachable("Unexpected size"); 2072 } else if (Name.endswith(".128")) { 2073 if (Size == 'd') // avx512.mask.psll.d.128, avx512.mask.psll.di.128 2074 IID = IsImmediate ? Intrinsic::x86_sse2_pslli_d 2075 : Intrinsic::x86_sse2_psll_d; 2076 else if (Size == 'q') // avx512.mask.psll.q.128, avx512.mask.psll.qi.128 2077 IID = IsImmediate ? Intrinsic::x86_sse2_pslli_q 2078 : Intrinsic::x86_sse2_psll_q; 2079 else if (Size == 'w') // avx512.mask.psll.w.128, avx512.mask.psll.wi.128 2080 IID = IsImmediate ? Intrinsic::x86_sse2_pslli_w 2081 : Intrinsic::x86_sse2_psll_w; 2082 else 2083 llvm_unreachable("Unexpected size"); 2084 } else if (Name.endswith(".256")) { 2085 if (Size == 'd') // avx512.mask.psll.d.256, avx512.mask.psll.di.256 2086 IID = IsImmediate ? Intrinsic::x86_avx2_pslli_d 2087 : Intrinsic::x86_avx2_psll_d; 2088 else if (Size == 'q') // avx512.mask.psll.q.256, avx512.mask.psll.qi.256 2089 IID = IsImmediate ? Intrinsic::x86_avx2_pslli_q 2090 : Intrinsic::x86_avx2_psll_q; 2091 else if (Size == 'w') // avx512.mask.psll.w.256, avx512.mask.psll.wi.256 2092 IID = IsImmediate ? Intrinsic::x86_avx2_pslli_w 2093 : Intrinsic::x86_avx2_psll_w; 2094 else 2095 llvm_unreachable("Unexpected size"); 2096 } else { 2097 if (Size == 'd') // psll.di.512, pslli.d, psll.d, psllv.d.512 2098 IID = IsImmediate ? Intrinsic::x86_avx512_pslli_d_512 : 2099 IsVariable ? Intrinsic::x86_avx512_psllv_d_512 : 2100 Intrinsic::x86_avx512_psll_d_512; 2101 else if (Size == 'q') // psll.qi.512, pslli.q, psll.q, psllv.q.512 2102 IID = IsImmediate ? Intrinsic::x86_avx512_pslli_q_512 : 2103 IsVariable ? Intrinsic::x86_avx512_psllv_q_512 : 2104 Intrinsic::x86_avx512_psll_q_512; 2105 else if (Size == 'w') // psll.wi.512, pslli.w, psll.w 2106 IID = IsImmediate ? Intrinsic::x86_avx512_pslli_w_512 2107 : Intrinsic::x86_avx512_psll_w_512; 2108 else 2109 llvm_unreachable("Unexpected size"); 2110 } 2111 2112 Rep = UpgradeX86MaskedShift(Builder, *CI, IID); 2113 } else if (IsX86 && Name.startswith("avx512.mask.psrl")) { 2114 bool IsImmediate = Name[16] == 'i' || 2115 (Name.size() > 18 && Name[18] == 'i'); 2116 bool IsVariable = Name[16] == 'v'; 2117 char Size = Name[16] == '.' ? Name[17] : 2118 Name[17] == '.' ? Name[18] : 2119 Name[18] == '.' ? Name[19] : 2120 Name[20]; 2121 2122 Intrinsic::ID IID; 2123 if (IsVariable && Name[17] != '.') { 2124 if (Size == 'd' && Name[17] == '2') // avx512.mask.psrlv2.di 2125 IID = Intrinsic::x86_avx2_psrlv_q; 2126 else if (Size == 'd' && Name[17] == '4') // avx512.mask.psrlv4.di 2127 IID = Intrinsic::x86_avx2_psrlv_q_256; 2128 else if (Size == 's' && Name[17] == '4') // avx512.mask.psrlv4.si 2129 IID = Intrinsic::x86_avx2_psrlv_d; 2130 else if (Size == 's' && Name[17] == '8') // avx512.mask.psrlv8.si 2131 IID = Intrinsic::x86_avx2_psrlv_d_256; 2132 else if (Size == 'h' && Name[17] == '8') // avx512.mask.psrlv8.hi 2133 IID = Intrinsic::x86_avx512_psrlv_w_128; 2134 else if (Size == 'h' && Name[17] == '1') // avx512.mask.psrlv16.hi 2135 IID = Intrinsic::x86_avx512_psrlv_w_256; 2136 else if (Name[17] == '3' && Name[18] == '2') // avx512.mask.psrlv32hi 2137 IID = Intrinsic::x86_avx512_psrlv_w_512; 2138 else 2139 llvm_unreachable("Unexpected size"); 2140 } else if (Name.endswith(".128")) { 2141 if (Size == 'd') // avx512.mask.psrl.d.128, avx512.mask.psrl.di.128 2142 IID = IsImmediate ? Intrinsic::x86_sse2_psrli_d 2143 : Intrinsic::x86_sse2_psrl_d; 2144 else if (Size == 'q') // avx512.mask.psrl.q.128, avx512.mask.psrl.qi.128 2145 IID = IsImmediate ? Intrinsic::x86_sse2_psrli_q 2146 : Intrinsic::x86_sse2_psrl_q; 2147 else if (Size == 'w') // avx512.mask.psrl.w.128, avx512.mask.psrl.wi.128 2148 IID = IsImmediate ? Intrinsic::x86_sse2_psrli_w 2149 : Intrinsic::x86_sse2_psrl_w; 2150 else 2151 llvm_unreachable("Unexpected size"); 2152 } else if (Name.endswith(".256")) { 2153 if (Size == 'd') // avx512.mask.psrl.d.256, avx512.mask.psrl.di.256 2154 IID = IsImmediate ? Intrinsic::x86_avx2_psrli_d 2155 : Intrinsic::x86_avx2_psrl_d; 2156 else if (Size == 'q') // avx512.mask.psrl.q.256, avx512.mask.psrl.qi.256 2157 IID = IsImmediate ? Intrinsic::x86_avx2_psrli_q 2158 : Intrinsic::x86_avx2_psrl_q; 2159 else if (Size == 'w') // avx512.mask.psrl.w.256, avx512.mask.psrl.wi.256 2160 IID = IsImmediate ? Intrinsic::x86_avx2_psrli_w 2161 : Intrinsic::x86_avx2_psrl_w; 2162 else 2163 llvm_unreachable("Unexpected size"); 2164 } else { 2165 if (Size == 'd') // psrl.di.512, psrli.d, psrl.d, psrl.d.512 2166 IID = IsImmediate ? Intrinsic::x86_avx512_psrli_d_512 : 2167 IsVariable ? Intrinsic::x86_avx512_psrlv_d_512 : 2168 Intrinsic::x86_avx512_psrl_d_512; 2169 else if (Size == 'q') // psrl.qi.512, psrli.q, psrl.q, psrl.q.512 2170 IID = IsImmediate ? Intrinsic::x86_avx512_psrli_q_512 : 2171 IsVariable ? Intrinsic::x86_avx512_psrlv_q_512 : 2172 Intrinsic::x86_avx512_psrl_q_512; 2173 else if (Size == 'w') // psrl.wi.512, psrli.w, psrl.w) 2174 IID = IsImmediate ? Intrinsic::x86_avx512_psrli_w_512 2175 : Intrinsic::x86_avx512_psrl_w_512; 2176 else 2177 llvm_unreachable("Unexpected size"); 2178 } 2179 2180 Rep = UpgradeX86MaskedShift(Builder, *CI, IID); 2181 } else if (IsX86 && Name.startswith("avx512.mask.psra")) { 2182 bool IsImmediate = Name[16] == 'i' || 2183 (Name.size() > 18 && Name[18] == 'i'); 2184 bool IsVariable = Name[16] == 'v'; 2185 char Size = Name[16] == '.' ? Name[17] : 2186 Name[17] == '.' ? Name[18] : 2187 Name[18] == '.' ? Name[19] : 2188 Name[20]; 2189 2190 Intrinsic::ID IID; 2191 if (IsVariable && Name[17] != '.') { 2192 if (Size == 's' && Name[17] == '4') // avx512.mask.psrav4.si 2193 IID = Intrinsic::x86_avx2_psrav_d; 2194 else if (Size == 's' && Name[17] == '8') // avx512.mask.psrav8.si 2195 IID = Intrinsic::x86_avx2_psrav_d_256; 2196 else if (Size == 'h' && Name[17] == '8') // avx512.mask.psrav8.hi 2197 IID = Intrinsic::x86_avx512_psrav_w_128; 2198 else if (Size == 'h' && Name[17] == '1') // avx512.mask.psrav16.hi 2199 IID = Intrinsic::x86_avx512_psrav_w_256; 2200 else if (Name[17] == '3' && Name[18] == '2') // avx512.mask.psrav32hi 2201 IID = Intrinsic::x86_avx512_psrav_w_512; 2202 else 2203 llvm_unreachable("Unexpected size"); 2204 } else if (Name.endswith(".128")) { 2205 if (Size == 'd') // avx512.mask.psra.d.128, avx512.mask.psra.di.128 2206 IID = IsImmediate ? Intrinsic::x86_sse2_psrai_d 2207 : Intrinsic::x86_sse2_psra_d; 2208 else if (Size == 'q') // avx512.mask.psra.q.128, avx512.mask.psra.qi.128 2209 IID = IsImmediate ? Intrinsic::x86_avx512_psrai_q_128 : 2210 IsVariable ? Intrinsic::x86_avx512_psrav_q_128 : 2211 Intrinsic::x86_avx512_psra_q_128; 2212 else if (Size == 'w') // avx512.mask.psra.w.128, avx512.mask.psra.wi.128 2213 IID = IsImmediate ? Intrinsic::x86_sse2_psrai_w 2214 : Intrinsic::x86_sse2_psra_w; 2215 else 2216 llvm_unreachable("Unexpected size"); 2217 } else if (Name.endswith(".256")) { 2218 if (Size == 'd') // avx512.mask.psra.d.256, avx512.mask.psra.di.256 2219 IID = IsImmediate ? Intrinsic::x86_avx2_psrai_d 2220 : Intrinsic::x86_avx2_psra_d; 2221 else if (Size == 'q') // avx512.mask.psra.q.256, avx512.mask.psra.qi.256 2222 IID = IsImmediate ? Intrinsic::x86_avx512_psrai_q_256 : 2223 IsVariable ? Intrinsic::x86_avx512_psrav_q_256 : 2224 Intrinsic::x86_avx512_psra_q_256; 2225 else if (Size == 'w') // avx512.mask.psra.w.256, avx512.mask.psra.wi.256 2226 IID = IsImmediate ? Intrinsic::x86_avx2_psrai_w 2227 : Intrinsic::x86_avx2_psra_w; 2228 else 2229 llvm_unreachable("Unexpected size"); 2230 } else { 2231 if (Size == 'd') // psra.di.512, psrai.d, psra.d, psrav.d.512 2232 IID = IsImmediate ? Intrinsic::x86_avx512_psrai_d_512 : 2233 IsVariable ? Intrinsic::x86_avx512_psrav_d_512 : 2234 Intrinsic::x86_avx512_psra_d_512; 2235 else if (Size == 'q') // psra.qi.512, psrai.q, psra.q 2236 IID = IsImmediate ? Intrinsic::x86_avx512_psrai_q_512 : 2237 IsVariable ? Intrinsic::x86_avx512_psrav_q_512 : 2238 Intrinsic::x86_avx512_psra_q_512; 2239 else if (Size == 'w') // psra.wi.512, psrai.w, psra.w 2240 IID = IsImmediate ? Intrinsic::x86_avx512_psrai_w_512 2241 : Intrinsic::x86_avx512_psra_w_512; 2242 else 2243 llvm_unreachable("Unexpected size"); 2244 } 2245 2246 Rep = UpgradeX86MaskedShift(Builder, *CI, IID); 2247 } else if (IsX86 && Name.startswith("avx512.mask.move.s")) { 2248 Rep = upgradeMaskedMove(Builder, *CI); 2249 } else if (IsX86 && Name.startswith("avx512.cvtmask2")) { 2250 Rep = UpgradeMaskToInt(Builder, *CI); 2251 } else if (IsX86 && Name.startswith("avx512.mask.vpermilvar.")) { 2252 Intrinsic::ID IID; 2253 if (Name.endswith("ps.128")) 2254 IID = Intrinsic::x86_avx_vpermilvar_ps; 2255 else if (Name.endswith("pd.128")) 2256 IID = Intrinsic::x86_avx_vpermilvar_pd; 2257 else if (Name.endswith("ps.256")) 2258 IID = Intrinsic::x86_avx_vpermilvar_ps_256; 2259 else if (Name.endswith("pd.256")) 2260 IID = Intrinsic::x86_avx_vpermilvar_pd_256; 2261 else if (Name.endswith("ps.512")) 2262 IID = Intrinsic::x86_avx512_vpermilvar_ps_512; 2263 else if (Name.endswith("pd.512")) 2264 IID = Intrinsic::x86_avx512_vpermilvar_pd_512; 2265 else 2266 llvm_unreachable("Unexpected vpermilvar intrinsic"); 2267 2268 Function *Intrin = Intrinsic::getDeclaration(F->getParent(), IID); 2269 Rep = Builder.CreateCall(Intrin, 2270 { CI->getArgOperand(0), CI->getArgOperand(1) }); 2271 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 2272 CI->getArgOperand(2)); 2273 } else if (IsX86 && Name.endswith(".movntdqa")) { 2274 Module *M = F->getParent(); 2275 MDNode *Node = MDNode::get( 2276 C, ConstantAsMetadata::get(ConstantInt::get(Type::getInt32Ty(C), 1))); 2277 2278 Value *Ptr = CI->getArgOperand(0); 2279 VectorType *VTy = cast<VectorType>(CI->getType()); 2280 2281 // Convert the type of the pointer to a pointer to the stored type. 2282 Value *BC = 2283 Builder.CreateBitCast(Ptr, PointerType::getUnqual(VTy), "cast"); 2284 LoadInst *LI = Builder.CreateAlignedLoad(BC, VTy->getBitWidth() / 8); 2285 LI->setMetadata(M->getMDKindID("nontemporal"), Node); 2286 Rep = LI; 2287 } else if (IsX86 && 2288 (Name.startswith("sse2.pavg") || Name.startswith("avx2.pavg") || 2289 Name.startswith("avx512.mask.pavg"))) { 2290 // llvm.x86.sse2.pavg.b/w, llvm.x86.avx2.pavg.b/w, 2291 // llvm.x86.avx512.mask.pavg.b/w 2292 Value *A = CI->getArgOperand(0); 2293 Value *B = CI->getArgOperand(1); 2294 VectorType *ZextType = VectorType::getExtendedElementVectorType( 2295 cast<VectorType>(A->getType())); 2296 Value *ExtendedA = Builder.CreateZExt(A, ZextType); 2297 Value *ExtendedB = Builder.CreateZExt(B, ZextType); 2298 Value *Sum = Builder.CreateAdd(ExtendedA, ExtendedB); 2299 Value *AddOne = Builder.CreateAdd(Sum, ConstantInt::get(ZextType, 1)); 2300 Value *ShiftR = Builder.CreateLShr(AddOne, ConstantInt::get(ZextType, 1)); 2301 Rep = Builder.CreateTrunc(ShiftR, A->getType()); 2302 if (CI->getNumArgOperands() > 2) { 2303 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep, 2304 CI->getArgOperand(2)); 2305 } 2306 } else if (IsNVVM && (Name == "abs.i" || Name == "abs.ll")) { 2307 Value *Arg = CI->getArgOperand(0); 2308 Value *Neg = Builder.CreateNeg(Arg, "neg"); 2309 Value *Cmp = Builder.CreateICmpSGE( 2310 Arg, llvm::Constant::getNullValue(Arg->getType()), "abs.cond"); 2311 Rep = Builder.CreateSelect(Cmp, Arg, Neg, "abs"); 2312 } else if (IsNVVM && (Name == "max.i" || Name == "max.ll" || 2313 Name == "max.ui" || Name == "max.ull")) { 2314 Value *Arg0 = CI->getArgOperand(0); 2315 Value *Arg1 = CI->getArgOperand(1); 2316 Value *Cmp = Name.endswith(".ui") || Name.endswith(".ull") 2317 ? Builder.CreateICmpUGE(Arg0, Arg1, "max.cond") 2318 : Builder.CreateICmpSGE(Arg0, Arg1, "max.cond"); 2319 Rep = Builder.CreateSelect(Cmp, Arg0, Arg1, "max"); 2320 } else if (IsNVVM && (Name == "min.i" || Name == "min.ll" || 2321 Name == "min.ui" || Name == "min.ull")) { 2322 Value *Arg0 = CI->getArgOperand(0); 2323 Value *Arg1 = CI->getArgOperand(1); 2324 Value *Cmp = Name.endswith(".ui") || Name.endswith(".ull") 2325 ? Builder.CreateICmpULE(Arg0, Arg1, "min.cond") 2326 : Builder.CreateICmpSLE(Arg0, Arg1, "min.cond"); 2327 Rep = Builder.CreateSelect(Cmp, Arg0, Arg1, "min"); 2328 } else if (IsNVVM && Name == "clz.ll") { 2329 // llvm.nvvm.clz.ll returns an i32, but llvm.ctlz.i64 and returns an i64. 2330 Value *Arg = CI->getArgOperand(0); 2331 Value *Ctlz = Builder.CreateCall( 2332 Intrinsic::getDeclaration(F->getParent(), Intrinsic::ctlz, 2333 {Arg->getType()}), 2334 {Arg, Builder.getFalse()}, "ctlz"); 2335 Rep = Builder.CreateTrunc(Ctlz, Builder.getInt32Ty(), "ctlz.trunc"); 2336 } else if (IsNVVM && Name == "popc.ll") { 2337 // llvm.nvvm.popc.ll returns an i32, but llvm.ctpop.i64 and returns an 2338 // i64. 2339 Value *Arg = CI->getArgOperand(0); 2340 Value *Popc = Builder.CreateCall( 2341 Intrinsic::getDeclaration(F->getParent(), Intrinsic::ctpop, 2342 {Arg->getType()}), 2343 Arg, "ctpop"); 2344 Rep = Builder.CreateTrunc(Popc, Builder.getInt32Ty(), "ctpop.trunc"); 2345 } else if (IsNVVM && Name == "h2f") { 2346 Rep = Builder.CreateCall(Intrinsic::getDeclaration( 2347 F->getParent(), Intrinsic::convert_from_fp16, 2348 {Builder.getFloatTy()}), 2349 CI->getArgOperand(0), "h2f"); 2350 } else { 2351 llvm_unreachable("Unknown function for CallInst upgrade."); 2352 } 2353 2354 if (Rep) 2355 CI->replaceAllUsesWith(Rep); 2356 CI->eraseFromParent(); 2357 return; 2358 } 2359 2360 const auto &DefaultCase = [&NewFn, &CI]() -> void { 2361 // Handle generic mangling change, but nothing else 2362 assert( 2363 (CI->getCalledFunction()->getName() != NewFn->getName()) && 2364 "Unknown function for CallInst upgrade and isn't just a name change"); 2365 CI->setCalledFunction(NewFn); 2366 }; 2367 CallInst *NewCall = nullptr; 2368 switch (NewFn->getIntrinsicID()) { 2369 default: { 2370 DefaultCase(); 2371 return; 2372 } 2373 2374 case Intrinsic::arm_neon_vld1: 2375 case Intrinsic::arm_neon_vld2: 2376 case Intrinsic::arm_neon_vld3: 2377 case Intrinsic::arm_neon_vld4: 2378 case Intrinsic::arm_neon_vld2lane: 2379 case Intrinsic::arm_neon_vld3lane: 2380 case Intrinsic::arm_neon_vld4lane: 2381 case Intrinsic::arm_neon_vst1: 2382 case Intrinsic::arm_neon_vst2: 2383 case Intrinsic::arm_neon_vst3: 2384 case Intrinsic::arm_neon_vst4: 2385 case Intrinsic::arm_neon_vst2lane: 2386 case Intrinsic::arm_neon_vst3lane: 2387 case Intrinsic::arm_neon_vst4lane: { 2388 SmallVector<Value *, 4> Args(CI->arg_operands().begin(), 2389 CI->arg_operands().end()); 2390 NewCall = Builder.CreateCall(NewFn, Args); 2391 break; 2392 } 2393 2394 case Intrinsic::bitreverse: 2395 NewCall = Builder.CreateCall(NewFn, {CI->getArgOperand(0)}); 2396 break; 2397 2398 case Intrinsic::ctlz: 2399 case Intrinsic::cttz: 2400 assert(CI->getNumArgOperands() == 1 && 2401 "Mismatch between function args and call args"); 2402 NewCall = 2403 Builder.CreateCall(NewFn, {CI->getArgOperand(0), Builder.getFalse()}); 2404 break; 2405 2406 case Intrinsic::objectsize: { 2407 Value *NullIsUnknownSize = CI->getNumArgOperands() == 2 2408 ? Builder.getFalse() 2409 : CI->getArgOperand(2); 2410 NewCall = Builder.CreateCall( 2411 NewFn, {CI->getArgOperand(0), CI->getArgOperand(1), NullIsUnknownSize}); 2412 break; 2413 } 2414 2415 case Intrinsic::ctpop: 2416 NewCall = Builder.CreateCall(NewFn, {CI->getArgOperand(0)}); 2417 break; 2418 2419 case Intrinsic::convert_from_fp16: 2420 NewCall = Builder.CreateCall(NewFn, {CI->getArgOperand(0)}); 2421 break; 2422 2423 case Intrinsic::dbg_value: 2424 // Upgrade from the old version that had an extra offset argument. 2425 assert(CI->getNumArgOperands() == 4); 2426 // Drop nonzero offsets instead of attempting to upgrade them. 2427 if (auto *Offset = dyn_cast_or_null<Constant>(CI->getArgOperand(1))) 2428 if (Offset->isZeroValue()) { 2429 NewCall = Builder.CreateCall( 2430 NewFn, 2431 {CI->getArgOperand(0), CI->getArgOperand(2), CI->getArgOperand(3)}); 2432 break; 2433 } 2434 CI->eraseFromParent(); 2435 return; 2436 2437 case Intrinsic::x86_xop_vfrcz_ss: 2438 case Intrinsic::x86_xop_vfrcz_sd: 2439 NewCall = Builder.CreateCall(NewFn, {CI->getArgOperand(1)}); 2440 break; 2441 2442 case Intrinsic::x86_xop_vpermil2pd: 2443 case Intrinsic::x86_xop_vpermil2ps: 2444 case Intrinsic::x86_xop_vpermil2pd_256: 2445 case Intrinsic::x86_xop_vpermil2ps_256: { 2446 SmallVector<Value *, 4> Args(CI->arg_operands().begin(), 2447 CI->arg_operands().end()); 2448 VectorType *FltIdxTy = cast<VectorType>(Args[2]->getType()); 2449 VectorType *IntIdxTy = VectorType::getInteger(FltIdxTy); 2450 Args[2] = Builder.CreateBitCast(Args[2], IntIdxTy); 2451 NewCall = Builder.CreateCall(NewFn, Args); 2452 break; 2453 } 2454 2455 case Intrinsic::x86_sse41_ptestc: 2456 case Intrinsic::x86_sse41_ptestz: 2457 case Intrinsic::x86_sse41_ptestnzc: { 2458 // The arguments for these intrinsics used to be v4f32, and changed 2459 // to v2i64. This is purely a nop, since those are bitwise intrinsics. 2460 // So, the only thing required is a bitcast for both arguments. 2461 // First, check the arguments have the old type. 2462 Value *Arg0 = CI->getArgOperand(0); 2463 if (Arg0->getType() != VectorType::get(Type::getFloatTy(C), 4)) 2464 return; 2465 2466 // Old intrinsic, add bitcasts 2467 Value *Arg1 = CI->getArgOperand(1); 2468 2469 Type *NewVecTy = VectorType::get(Type::getInt64Ty(C), 2); 2470 2471 Value *BC0 = Builder.CreateBitCast(Arg0, NewVecTy, "cast"); 2472 Value *BC1 = Builder.CreateBitCast(Arg1, NewVecTy, "cast"); 2473 2474 NewCall = Builder.CreateCall(NewFn, {BC0, BC1}); 2475 break; 2476 } 2477 2478 case Intrinsic::x86_sse41_insertps: 2479 case Intrinsic::x86_sse41_dppd: 2480 case Intrinsic::x86_sse41_dpps: 2481 case Intrinsic::x86_sse41_mpsadbw: 2482 case Intrinsic::x86_avx_dp_ps_256: 2483 case Intrinsic::x86_avx2_mpsadbw: { 2484 // Need to truncate the last argument from i32 to i8 -- this argument models 2485 // an inherently 8-bit immediate operand to these x86 instructions. 2486 SmallVector<Value *, 4> Args(CI->arg_operands().begin(), 2487 CI->arg_operands().end()); 2488 2489 // Replace the last argument with a trunc. 2490 Args.back() = Builder.CreateTrunc(Args.back(), Type::getInt8Ty(C), "trunc"); 2491 NewCall = Builder.CreateCall(NewFn, Args); 2492 break; 2493 } 2494 2495 case Intrinsic::x86_avx512_mask_cmp_pd_128: 2496 case Intrinsic::x86_avx512_mask_cmp_pd_256: 2497 case Intrinsic::x86_avx512_mask_cmp_pd_512: 2498 case Intrinsic::x86_avx512_mask_cmp_ps_128: 2499 case Intrinsic::x86_avx512_mask_cmp_ps_256: 2500 case Intrinsic::x86_avx512_mask_cmp_ps_512: { 2501 SmallVector<Value *, 4> Args; 2502 Args.push_back(CI->getArgOperand(0)); 2503 Args.push_back(CI->getArgOperand(1)); 2504 Args.push_back(CI->getArgOperand(2)); 2505 if (CI->getNumArgOperands() == 5) 2506 Args.push_back(CI->getArgOperand(4)); 2507 2508 NewCall = Builder.CreateCall(NewFn, Args); 2509 unsigned NumElts = Args[0]->getType()->getVectorNumElements(); 2510 Value *Res = ApplyX86MaskOn1BitsVec(Builder, NewCall, CI->getArgOperand(3), 2511 NumElts); 2512 2513 std::string Name = CI->getName(); 2514 if (!Name.empty()) { 2515 CI->setName(Name + ".old"); 2516 NewCall->setName(Name); 2517 } 2518 CI->replaceAllUsesWith(Res); 2519 CI->eraseFromParent(); 2520 return; 2521 } 2522 2523 case Intrinsic::thread_pointer: { 2524 NewCall = Builder.CreateCall(NewFn, {}); 2525 break; 2526 } 2527 2528 case Intrinsic::invariant_start: 2529 case Intrinsic::invariant_end: 2530 case Intrinsic::masked_load: 2531 case Intrinsic::masked_store: 2532 case Intrinsic::masked_gather: 2533 case Intrinsic::masked_scatter: { 2534 SmallVector<Value *, 4> Args(CI->arg_operands().begin(), 2535 CI->arg_operands().end()); 2536 NewCall = Builder.CreateCall(NewFn, Args); 2537 break; 2538 } 2539 2540 case Intrinsic::memcpy: 2541 case Intrinsic::memmove: 2542 case Intrinsic::memset: { 2543 // We have to make sure that the call signature is what we're expecting. 2544 // We only want to change the old signatures by removing the alignment arg: 2545 // @llvm.mem[cpy|move]...(i8*, i8*, i[32|i64], i32, i1) 2546 // -> @llvm.mem[cpy|move]...(i8*, i8*, i[32|i64], i1) 2547 // @llvm.memset...(i8*, i8, i[32|64], i32, i1) 2548 // -> @llvm.memset...(i8*, i8, i[32|64], i1) 2549 // Note: i8*'s in the above can be any pointer type 2550 if (CI->getNumArgOperands() != 5) { 2551 DefaultCase(); 2552 return; 2553 } 2554 // Remove alignment argument (3), and add alignment attributes to the 2555 // dest/src pointers. 2556 Value *Args[4] = {CI->getArgOperand(0), CI->getArgOperand(1), 2557 CI->getArgOperand(2), CI->getArgOperand(4)}; 2558 NewCall = Builder.CreateCall(NewFn, Args); 2559 auto *MemCI = cast<MemIntrinsic>(NewCall); 2560 // All mem intrinsics support dest alignment. 2561 const ConstantInt *Align = cast<ConstantInt>(CI->getArgOperand(3)); 2562 MemCI->setDestAlignment(Align->getZExtValue()); 2563 // Memcpy/Memmove also support source alignment. 2564 if (auto *MTI = dyn_cast<MemTransferInst>(MemCI)) 2565 MTI->setSourceAlignment(Align->getZExtValue()); 2566 break; 2567 } 2568 } 2569 assert(NewCall && "Should have either set this variable or returned through " 2570 "the default case"); 2571 std::string Name = CI->getName(); 2572 if (!Name.empty()) { 2573 CI->setName(Name + ".old"); 2574 NewCall->setName(Name); 2575 } 2576 CI->replaceAllUsesWith(NewCall); 2577 CI->eraseFromParent(); 2578 } 2579 2580 void llvm::UpgradeCallsToIntrinsic(Function *F) { 2581 assert(F && "Illegal attempt to upgrade a non-existent intrinsic."); 2582 2583 // Check if this function should be upgraded and get the replacement function 2584 // if there is one. 2585 Function *NewFn; 2586 if (UpgradeIntrinsicFunction(F, NewFn)) { 2587 // Replace all users of the old function with the new function or new 2588 // instructions. This is not a range loop because the call is deleted. 2589 for (auto UI = F->user_begin(), UE = F->user_end(); UI != UE; ) 2590 if (CallInst *CI = dyn_cast<CallInst>(*UI++)) 2591 UpgradeIntrinsicCall(CI, NewFn); 2592 2593 // Remove old function, no longer used, from the module. 2594 F->eraseFromParent(); 2595 } 2596 } 2597 2598 MDNode *llvm::UpgradeTBAANode(MDNode &MD) { 2599 // Check if the tag uses struct-path aware TBAA format. 2600 if (isa<MDNode>(MD.getOperand(0)) && MD.getNumOperands() >= 3) 2601 return &MD; 2602 2603 auto &Context = MD.getContext(); 2604 if (MD.getNumOperands() == 3) { 2605 Metadata *Elts[] = {MD.getOperand(0), MD.getOperand(1)}; 2606 MDNode *ScalarType = MDNode::get(Context, Elts); 2607 // Create a MDNode <ScalarType, ScalarType, offset 0, const> 2608 Metadata *Elts2[] = {ScalarType, ScalarType, 2609 ConstantAsMetadata::get( 2610 Constant::getNullValue(Type::getInt64Ty(Context))), 2611 MD.getOperand(2)}; 2612 return MDNode::get(Context, Elts2); 2613 } 2614 // Create a MDNode <MD, MD, offset 0> 2615 Metadata *Elts[] = {&MD, &MD, ConstantAsMetadata::get(Constant::getNullValue( 2616 Type::getInt64Ty(Context)))}; 2617 return MDNode::get(Context, Elts); 2618 } 2619 2620 Instruction *llvm::UpgradeBitCastInst(unsigned Opc, Value *V, Type *DestTy, 2621 Instruction *&Temp) { 2622 if (Opc != Instruction::BitCast) 2623 return nullptr; 2624 2625 Temp = nullptr; 2626 Type *SrcTy = V->getType(); 2627 if (SrcTy->isPtrOrPtrVectorTy() && DestTy->isPtrOrPtrVectorTy() && 2628 SrcTy->getPointerAddressSpace() != DestTy->getPointerAddressSpace()) { 2629 LLVMContext &Context = V->getContext(); 2630 2631 // We have no information about target data layout, so we assume that 2632 // the maximum pointer size is 64bit. 2633 Type *MidTy = Type::getInt64Ty(Context); 2634 Temp = CastInst::Create(Instruction::PtrToInt, V, MidTy); 2635 2636 return CastInst::Create(Instruction::IntToPtr, Temp, DestTy); 2637 } 2638 2639 return nullptr; 2640 } 2641 2642 Value *llvm::UpgradeBitCastExpr(unsigned Opc, Constant *C, Type *DestTy) { 2643 if (Opc != Instruction::BitCast) 2644 return nullptr; 2645 2646 Type *SrcTy = C->getType(); 2647 if (SrcTy->isPtrOrPtrVectorTy() && DestTy->isPtrOrPtrVectorTy() && 2648 SrcTy->getPointerAddressSpace() != DestTy->getPointerAddressSpace()) { 2649 LLVMContext &Context = C->getContext(); 2650 2651 // We have no information about target data layout, so we assume that 2652 // the maximum pointer size is 64bit. 2653 Type *MidTy = Type::getInt64Ty(Context); 2654 2655 return ConstantExpr::getIntToPtr(ConstantExpr::getPtrToInt(C, MidTy), 2656 DestTy); 2657 } 2658 2659 return nullptr; 2660 } 2661 2662 /// Check the debug info version number, if it is out-dated, drop the debug 2663 /// info. Return true if module is modified. 2664 bool llvm::UpgradeDebugInfo(Module &M) { 2665 unsigned Version = getDebugMetadataVersionFromModule(M); 2666 if (Version == DEBUG_METADATA_VERSION) { 2667 bool BrokenDebugInfo = false; 2668 if (verifyModule(M, &llvm::errs(), &BrokenDebugInfo)) 2669 report_fatal_error("Broken module found, compilation aborted!"); 2670 if (!BrokenDebugInfo) 2671 // Everything is ok. 2672 return false; 2673 else { 2674 // Diagnose malformed debug info. 2675 DiagnosticInfoIgnoringInvalidDebugMetadata Diag(M); 2676 M.getContext().diagnose(Diag); 2677 } 2678 } 2679 bool Modified = StripDebugInfo(M); 2680 if (Modified && Version != DEBUG_METADATA_VERSION) { 2681 // Diagnose a version mismatch. 2682 DiagnosticInfoDebugMetadataVersion DiagVersion(M, Version); 2683 M.getContext().diagnose(DiagVersion); 2684 } 2685 return Modified; 2686 } 2687 2688 bool llvm::UpgradeModuleFlags(Module &M) { 2689 NamedMDNode *ModFlags = M.getModuleFlagsMetadata(); 2690 if (!ModFlags) 2691 return false; 2692 2693 bool HasObjCFlag = false, HasClassProperties = false, Changed = false; 2694 for (unsigned I = 0, E = ModFlags->getNumOperands(); I != E; ++I) { 2695 MDNode *Op = ModFlags->getOperand(I); 2696 if (Op->getNumOperands() != 3) 2697 continue; 2698 MDString *ID = dyn_cast_or_null<MDString>(Op->getOperand(1)); 2699 if (!ID) 2700 continue; 2701 if (ID->getString() == "Objective-C Image Info Version") 2702 HasObjCFlag = true; 2703 if (ID->getString() == "Objective-C Class Properties") 2704 HasClassProperties = true; 2705 // Upgrade PIC/PIE Module Flags. The module flag behavior for these two 2706 // field was Error and now they are Max. 2707 if (ID->getString() == "PIC Level" || ID->getString() == "PIE Level") { 2708 if (auto *Behavior = 2709 mdconst::dyn_extract_or_null<ConstantInt>(Op->getOperand(0))) { 2710 if (Behavior->getLimitedValue() == Module::Error) { 2711 Type *Int32Ty = Type::getInt32Ty(M.getContext()); 2712 Metadata *Ops[3] = { 2713 ConstantAsMetadata::get(ConstantInt::get(Int32Ty, Module::Max)), 2714 MDString::get(M.getContext(), ID->getString()), 2715 Op->getOperand(2)}; 2716 ModFlags->setOperand(I, MDNode::get(M.getContext(), Ops)); 2717 Changed = true; 2718 } 2719 } 2720 } 2721 // Upgrade Objective-C Image Info Section. Removed the whitespce in the 2722 // section name so that llvm-lto will not complain about mismatching 2723 // module flags that is functionally the same. 2724 if (ID->getString() == "Objective-C Image Info Section") { 2725 if (auto *Value = dyn_cast_or_null<MDString>(Op->getOperand(2))) { 2726 SmallVector<StringRef, 4> ValueComp; 2727 Value->getString().split(ValueComp, " "); 2728 if (ValueComp.size() != 1) { 2729 std::string NewValue; 2730 for (auto &S : ValueComp) 2731 NewValue += S.str(); 2732 Metadata *Ops[3] = {Op->getOperand(0), Op->getOperand(1), 2733 MDString::get(M.getContext(), NewValue)}; 2734 ModFlags->setOperand(I, MDNode::get(M.getContext(), Ops)); 2735 Changed = true; 2736 } 2737 } 2738 } 2739 } 2740 2741 // "Objective-C Class Properties" is recently added for Objective-C. We 2742 // upgrade ObjC bitcodes to contain a "Objective-C Class Properties" module 2743 // flag of value 0, so we can correclty downgrade this flag when trying to 2744 // link an ObjC bitcode without this module flag with an ObjC bitcode with 2745 // this module flag. 2746 if (HasObjCFlag && !HasClassProperties) { 2747 M.addModuleFlag(llvm::Module::Override, "Objective-C Class Properties", 2748 (uint32_t)0); 2749 Changed = true; 2750 } 2751 2752 return Changed; 2753 } 2754 2755 void llvm::UpgradeSectionAttributes(Module &M) { 2756 auto TrimSpaces = [](StringRef Section) -> std::string { 2757 SmallVector<StringRef, 5> Components; 2758 Section.split(Components, ','); 2759 2760 SmallString<32> Buffer; 2761 raw_svector_ostream OS(Buffer); 2762 2763 for (auto Component : Components) 2764 OS << ',' << Component.trim(); 2765 2766 return OS.str().substr(1); 2767 }; 2768 2769 for (auto &GV : M.globals()) { 2770 if (!GV.hasSection()) 2771 continue; 2772 2773 StringRef Section = GV.getSection(); 2774 2775 if (!Section.startswith("__DATA, __objc_catlist")) 2776 continue; 2777 2778 // __DATA, __objc_catlist, regular, no_dead_strip 2779 // __DATA,__objc_catlist,regular,no_dead_strip 2780 GV.setSection(TrimSpaces(Section)); 2781 } 2782 } 2783 2784 static bool isOldLoopArgument(Metadata *MD) { 2785 auto *T = dyn_cast_or_null<MDTuple>(MD); 2786 if (!T) 2787 return false; 2788 if (T->getNumOperands() < 1) 2789 return false; 2790 auto *S = dyn_cast_or_null<MDString>(T->getOperand(0)); 2791 if (!S) 2792 return false; 2793 return S->getString().startswith("llvm.vectorizer."); 2794 } 2795 2796 static MDString *upgradeLoopTag(LLVMContext &C, StringRef OldTag) { 2797 StringRef OldPrefix = "llvm.vectorizer."; 2798 assert(OldTag.startswith(OldPrefix) && "Expected old prefix"); 2799 2800 if (OldTag == "llvm.vectorizer.unroll") 2801 return MDString::get(C, "llvm.loop.interleave.count"); 2802 2803 return MDString::get( 2804 C, (Twine("llvm.loop.vectorize.") + OldTag.drop_front(OldPrefix.size())) 2805 .str()); 2806 } 2807 2808 static Metadata *upgradeLoopArgument(Metadata *MD) { 2809 auto *T = dyn_cast_or_null<MDTuple>(MD); 2810 if (!T) 2811 return MD; 2812 if (T->getNumOperands() < 1) 2813 return MD; 2814 auto *OldTag = dyn_cast_or_null<MDString>(T->getOperand(0)); 2815 if (!OldTag) 2816 return MD; 2817 if (!OldTag->getString().startswith("llvm.vectorizer.")) 2818 return MD; 2819 2820 // This has an old tag. Upgrade it. 2821 SmallVector<Metadata *, 8> Ops; 2822 Ops.reserve(T->getNumOperands()); 2823 Ops.push_back(upgradeLoopTag(T->getContext(), OldTag->getString())); 2824 for (unsigned I = 1, E = T->getNumOperands(); I != E; ++I) 2825 Ops.push_back(T->getOperand(I)); 2826 2827 return MDTuple::get(T->getContext(), Ops); 2828 } 2829 2830 MDNode *llvm::upgradeInstructionLoopAttachment(MDNode &N) { 2831 auto *T = dyn_cast<MDTuple>(&N); 2832 if (!T) 2833 return &N; 2834 2835 if (none_of(T->operands(), isOldLoopArgument)) 2836 return &N; 2837 2838 SmallVector<Metadata *, 8> Ops; 2839 Ops.reserve(T->getNumOperands()); 2840 for (Metadata *MD : T->operands()) 2841 Ops.push_back(upgradeLoopArgument(MD)); 2842 2843 return MDTuple::get(T->getContext(), Ops); 2844 } 2845