1 //===-- DWARFExpression.cpp -----------------------------------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #include "llvm/DebugInfo/DWARF/DWARFExpression.h" 11 #include "llvm/BinaryFormat/Dwarf.h" 12 #include "llvm/DebugInfo/DWARF/DWARFCompileUnit.h" 13 #include "llvm/DebugInfo/DWARF/DWARFContext.h" 14 #include "llvm/MC/MCRegisterInfo.h" 15 #include "llvm/Support/Format.h" 16 #include <cassert> 17 #include <cstdint> 18 #include <vector> 19 20 using namespace llvm; 21 using namespace dwarf; 22 23 namespace llvm { 24 25 typedef std::vector<DWARFExpression::Operation::Description> DescVector; 26 27 static DescVector getDescriptions() { 28 DescVector Descriptions; 29 typedef DWARFExpression::Operation Op; 30 typedef Op::Description Desc; 31 32 Descriptions.resize(0xff); 33 Descriptions[DW_OP_addr] = Desc(Op::Dwarf2, Op::SizeAddr); 34 Descriptions[DW_OP_deref] = Desc(Op::Dwarf2); 35 Descriptions[DW_OP_const1u] = Desc(Op::Dwarf2, Op::Size1); 36 Descriptions[DW_OP_const1s] = Desc(Op::Dwarf2, Op::SignedSize1); 37 Descriptions[DW_OP_const2u] = Desc(Op::Dwarf2, Op::Size2); 38 Descriptions[DW_OP_const2s] = Desc(Op::Dwarf2, Op::SignedSize2); 39 Descriptions[DW_OP_const4u] = Desc(Op::Dwarf2, Op::Size4); 40 Descriptions[DW_OP_const4s] = Desc(Op::Dwarf2, Op::SignedSize4); 41 Descriptions[DW_OP_const8u] = Desc(Op::Dwarf2, Op::Size8); 42 Descriptions[DW_OP_const8s] = Desc(Op::Dwarf2, Op::SignedSize8); 43 Descriptions[DW_OP_constu] = Desc(Op::Dwarf2, Op::SizeLEB); 44 Descriptions[DW_OP_consts] = Desc(Op::Dwarf2, Op::SignedSizeLEB); 45 Descriptions[DW_OP_dup] = Desc(Op::Dwarf2); 46 Descriptions[DW_OP_drop] = Desc(Op::Dwarf2); 47 Descriptions[DW_OP_over] = Desc(Op::Dwarf2); 48 Descriptions[DW_OP_pick] = Desc(Op::Dwarf2, Op::Size1); 49 Descriptions[DW_OP_swap] = Desc(Op::Dwarf2); 50 Descriptions[DW_OP_rot] = Desc(Op::Dwarf2); 51 Descriptions[DW_OP_xderef] = Desc(Op::Dwarf2); 52 Descriptions[DW_OP_abs] = Desc(Op::Dwarf2); 53 Descriptions[DW_OP_and] = Desc(Op::Dwarf2); 54 Descriptions[DW_OP_div] = Desc(Op::Dwarf2); 55 Descriptions[DW_OP_minus] = Desc(Op::Dwarf2); 56 Descriptions[DW_OP_mod] = Desc(Op::Dwarf2); 57 Descriptions[DW_OP_mul] = Desc(Op::Dwarf2); 58 Descriptions[DW_OP_neg] = Desc(Op::Dwarf2); 59 Descriptions[DW_OP_not] = Desc(Op::Dwarf2); 60 Descriptions[DW_OP_or] = Desc(Op::Dwarf2); 61 Descriptions[DW_OP_plus] = Desc(Op::Dwarf2); 62 Descriptions[DW_OP_plus_uconst] = Desc(Op::Dwarf2, Op::SizeLEB); 63 Descriptions[DW_OP_shl] = Desc(Op::Dwarf2); 64 Descriptions[DW_OP_shr] = Desc(Op::Dwarf2); 65 Descriptions[DW_OP_shra] = Desc(Op::Dwarf2); 66 Descriptions[DW_OP_xor] = Desc(Op::Dwarf2); 67 Descriptions[DW_OP_skip] = Desc(Op::Dwarf2, Op::SignedSize2); 68 Descriptions[DW_OP_bra] = Desc(Op::Dwarf2, Op::SignedSize2); 69 Descriptions[DW_OP_eq] = Desc(Op::Dwarf2); 70 Descriptions[DW_OP_ge] = Desc(Op::Dwarf2); 71 Descriptions[DW_OP_gt] = Desc(Op::Dwarf2); 72 Descriptions[DW_OP_le] = Desc(Op::Dwarf2); 73 Descriptions[DW_OP_lt] = Desc(Op::Dwarf2); 74 Descriptions[DW_OP_ne] = Desc(Op::Dwarf2); 75 for (uint16_t LA = DW_OP_lit0; LA <= DW_OP_lit31; ++LA) 76 Descriptions[LA] = Desc(Op::Dwarf2); 77 for (uint16_t LA = DW_OP_reg0; LA <= DW_OP_reg31; ++LA) 78 Descriptions[LA] = Desc(Op::Dwarf2); 79 for (uint16_t LA = DW_OP_breg0; LA <= DW_OP_breg31; ++LA) 80 Descriptions[LA] = Desc(Op::Dwarf2, Op::SignedSizeLEB); 81 Descriptions[DW_OP_regx] = Desc(Op::Dwarf2, Op::SizeLEB); 82 Descriptions[DW_OP_fbreg] = Desc(Op::Dwarf2, Op::SignedSizeLEB); 83 Descriptions[DW_OP_bregx] = Desc(Op::Dwarf2, Op::SizeLEB, Op::SignedSizeLEB); 84 Descriptions[DW_OP_piece] = Desc(Op::Dwarf2, Op::SizeLEB); 85 Descriptions[DW_OP_deref_size] = Desc(Op::Dwarf2, Op::Size1); 86 Descriptions[DW_OP_xderef_size] = Desc(Op::Dwarf2, Op::Size1); 87 Descriptions[DW_OP_nop] = Desc(Op::Dwarf2); 88 Descriptions[DW_OP_push_object_address] = Desc(Op::Dwarf3); 89 Descriptions[DW_OP_call2] = Desc(Op::Dwarf3, Op::Size2); 90 Descriptions[DW_OP_call4] = Desc(Op::Dwarf3, Op::Size4); 91 Descriptions[DW_OP_call_ref] = Desc(Op::Dwarf3, Op::SizeRefAddr); 92 Descriptions[DW_OP_form_tls_address] = Desc(Op::Dwarf3); 93 Descriptions[DW_OP_call_frame_cfa] = Desc(Op::Dwarf3); 94 Descriptions[DW_OP_bit_piece] = Desc(Op::Dwarf3, Op::SizeLEB, Op::SizeLEB); 95 Descriptions[DW_OP_implicit_value] = 96 Desc(Op::Dwarf3, Op::SizeLEB, Op::SizeBlock); 97 Descriptions[DW_OP_stack_value] = Desc(Op::Dwarf3); 98 Descriptions[DW_OP_GNU_push_tls_address] = Desc(Op::Dwarf3); 99 Descriptions[DW_OP_GNU_addr_index] = Desc(Op::Dwarf4, Op::SizeLEB); 100 Descriptions[DW_OP_GNU_const_index] = Desc(Op::Dwarf4, Op::SizeLEB); 101 return Descriptions; 102 } 103 104 static DWARFExpression::Operation::Description getOpDesc(unsigned OpCode) { 105 // FIXME: Make this constexpr once all compilers are smart enough to do it. 106 static DescVector Descriptions = getDescriptions(); 107 // Handle possible corrupted or unsupported operation. 108 if (OpCode >= Descriptions.size()) 109 return {}; 110 return Descriptions[OpCode]; 111 } 112 113 static uint8_t getRefAddrSize(uint8_t AddrSize, uint16_t Version) { 114 return (Version == 2) ? AddrSize : 4; 115 } 116 117 bool DWARFExpression::Operation::extract(DataExtractor Data, uint16_t Version, 118 uint8_t AddressSize, uint32_t Offset) { 119 Opcode = Data.getU8(&Offset); 120 121 Desc = getOpDesc(Opcode); 122 if (Desc.Version == Operation::DwarfNA) { 123 EndOffset = Offset; 124 return false; 125 } 126 127 for (unsigned Operand = 0; Operand < 2; ++Operand) { 128 unsigned Size = Desc.Op[Operand]; 129 unsigned Signed = Size & Operation::SignBit; 130 131 if (Size == Operation::SizeNA) 132 break; 133 134 switch (Size & ~Operation::SignBit) { 135 case Operation::Size1: 136 Operands[Operand] = Data.getU8(&Offset); 137 if (Signed) 138 Operands[Operand] = (int8_t)Operands[Operand]; 139 break; 140 case Operation::Size2: 141 Operands[Operand] = Data.getU16(&Offset); 142 if (Signed) 143 Operands[Operand] = (int16_t)Operands[Operand]; 144 break; 145 case Operation::Size4: 146 Operands[Operand] = Data.getU32(&Offset); 147 if (Signed) 148 Operands[Operand] = (int32_t)Operands[Operand]; 149 break; 150 case Operation::Size8: 151 Operands[Operand] = Data.getU64(&Offset); 152 break; 153 case Operation::SizeAddr: 154 if (AddressSize == 8) { 155 Operands[Operand] = Data.getU64(&Offset); 156 } else { 157 assert(AddressSize == 4); 158 Operands[Operand] = Data.getU32(&Offset); 159 } 160 break; 161 case Operation::SizeRefAddr: 162 if (getRefAddrSize(AddressSize, Version) == 8) { 163 Operands[Operand] = Data.getU64(&Offset); 164 } else { 165 assert(getRefAddrSize(AddressSize, Version) == 4); 166 Operands[Operand] = Data.getU32(&Offset); 167 } 168 break; 169 case Operation::SizeLEB: 170 if (Signed) 171 Operands[Operand] = Data.getSLEB128(&Offset); 172 else 173 Operands[Operand] = Data.getULEB128(&Offset); 174 break; 175 case Operation::SizeBlock: 176 // We need a size, so this cannot be the first operand 177 if (Operand == 0) 178 return false; 179 // Store the offset of the block as the value. 180 Operands[Operand] = Offset; 181 Offset += Operands[Operand - 1]; 182 break; 183 default: 184 llvm_unreachable("Unknown DWARFExpression Op size"); 185 } 186 } 187 188 EndOffset = Offset; 189 return true; 190 } 191 192 static bool prettyPrintRegisterOp(raw_ostream &OS, uint8_t Opcode, 193 uint64_t Operands[2], 194 const MCRegisterInfo *MRI, bool isEH) { 195 if (!MRI) 196 return false; 197 198 uint64_t DwarfRegNum; 199 unsigned OpNum = 0; 200 201 if (Opcode == DW_OP_bregx || Opcode == DW_OP_regx) 202 DwarfRegNum = Operands[OpNum++]; 203 else if (Opcode >= DW_OP_breg0 && Opcode < DW_OP_bregx) 204 DwarfRegNum = Opcode - DW_OP_breg0; 205 else 206 DwarfRegNum = Opcode - DW_OP_reg0; 207 208 int LLVMRegNum = MRI->getLLVMRegNum(DwarfRegNum, isEH); 209 if (LLVMRegNum >= 0) { 210 if (const char *RegName = MRI->getName(LLVMRegNum)) { 211 if ((Opcode >= DW_OP_breg0 && Opcode <= DW_OP_breg31) || 212 Opcode == DW_OP_bregx) 213 OS << format(" %s%+" PRId64, RegName, Operands[OpNum]); 214 else 215 OS << ' ' << RegName; 216 return true; 217 } 218 } 219 220 return false; 221 } 222 223 bool DWARFExpression::Operation::print(raw_ostream &OS, 224 const DWARFExpression *Expr, 225 const MCRegisterInfo *RegInfo, 226 bool isEH) { 227 if (Error) { 228 OS << "<decoding error>"; 229 return false; 230 } 231 232 StringRef Name = OperationEncodingString(Opcode); 233 assert(!Name.empty() && "DW_OP has no name!"); 234 OS << Name; 235 236 if ((Opcode >= DW_OP_breg0 && Opcode <= DW_OP_breg31) || 237 (Opcode >= DW_OP_reg0 && Opcode <= DW_OP_reg31) || 238 Opcode == DW_OP_bregx || Opcode == DW_OP_regx) 239 if (prettyPrintRegisterOp(OS, Opcode, Operands, RegInfo, isEH)) 240 return true; 241 242 for (unsigned Operand = 0; Operand < 2; ++Operand) { 243 unsigned Size = Desc.Op[Operand]; 244 unsigned Signed = Size & Operation::SignBit; 245 246 if (Size == Operation::SizeNA) 247 break; 248 249 if (Size == Operation::SizeBlock) { 250 uint32_t Offset = Operands[Operand]; 251 for (unsigned i = 0; i < Operands[Operand - 1]; ++i) 252 OS << format(" 0x%02x", Expr->Data.getU8(&Offset)); 253 } else { 254 if (Signed) 255 OS << format(" %+" PRId64, (int64_t)Operands[Operand]); 256 else 257 OS << format(" 0x%" PRIx64, Operands[Operand]); 258 } 259 } 260 return true; 261 } 262 263 void DWARFExpression::print(raw_ostream &OS, const MCRegisterInfo *RegInfo) { 264 for (auto &Op : *this) { 265 if (!Op.print(OS, this, RegInfo, /* isEH */ false)) { 266 uint32_t FailOffset = Op.getEndOffset(); 267 while (FailOffset < Data.getData().size()) 268 OS << format(" %02x", Data.getU8(&FailOffset)); 269 return; 270 } 271 if (Op.getEndOffset() < Data.getData().size()) 272 OS << ", "; 273 } 274 } 275 276 } // namespace llvm 277