1 //===-- llvm/CodeGen/VirtRegMap.cpp - Virtual Register Map ----------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the VirtRegMap class.
11 //
12 // It also contains implementations of the Spiller interface, which, given a
13 // virtual register map and a machine function, eliminates all virtual
14 // references by replacing them with physical register references - adding spill
15 // code as necessary.
16 //
17 //===----------------------------------------------------------------------===//
18 
19 #include "llvm/CodeGen/VirtRegMap.h"
20 #include "LiveDebugVariables.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/ADT/SparseSet.h"
23 #include "llvm/ADT/Statistic.h"
24 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
25 #include "llvm/CodeGen/LiveStackAnalysis.h"
26 #include "llvm/CodeGen/MachineFrameInfo.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineInstrBuilder.h"
29 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 #include "llvm/CodeGen/Passes.h"
31 #include "llvm/IR/Function.h"
32 #include "llvm/Support/CommandLine.h"
33 #include "llvm/Support/Compiler.h"
34 #include "llvm/Support/Debug.h"
35 #include "llvm/Support/raw_ostream.h"
36 #include "llvm/Target/TargetInstrInfo.h"
37 #include "llvm/Target/TargetMachine.h"
38 #include "llvm/Target/TargetRegisterInfo.h"
39 #include "llvm/Target/TargetSubtargetInfo.h"
40 #include <algorithm>
41 using namespace llvm;
42 
43 #define DEBUG_TYPE "regalloc"
44 
45 STATISTIC(NumSpillSlots, "Number of spill slots allocated");
46 STATISTIC(NumIdCopies,   "Number of identity moves eliminated after rewriting");
47 
48 //===----------------------------------------------------------------------===//
49 //  VirtRegMap implementation
50 //===----------------------------------------------------------------------===//
51 
52 char VirtRegMap::ID = 0;
53 
54 INITIALIZE_PASS(VirtRegMap, "virtregmap", "Virtual Register Map", false, false)
55 
56 bool VirtRegMap::runOnMachineFunction(MachineFunction &mf) {
57   MRI = &mf.getRegInfo();
58   TII = mf.getSubtarget().getInstrInfo();
59   TRI = mf.getSubtarget().getRegisterInfo();
60   MF = &mf;
61 
62   Virt2PhysMap.clear();
63   Virt2StackSlotMap.clear();
64   Virt2SplitMap.clear();
65 
66   grow();
67   return false;
68 }
69 
70 void VirtRegMap::grow() {
71   unsigned NumRegs = MF->getRegInfo().getNumVirtRegs();
72   Virt2PhysMap.resize(NumRegs);
73   Virt2StackSlotMap.resize(NumRegs);
74   Virt2SplitMap.resize(NumRegs);
75 }
76 
77 unsigned VirtRegMap::createSpillSlot(const TargetRegisterClass *RC) {
78   int SS = MF->getFrameInfo()->CreateSpillStackObject(RC->getSize(),
79                                                       RC->getAlignment());
80   ++NumSpillSlots;
81   return SS;
82 }
83 
84 bool VirtRegMap::hasPreferredPhys(unsigned VirtReg) {
85   unsigned Hint = MRI->getSimpleHint(VirtReg);
86   if (!Hint)
87     return 0;
88   if (TargetRegisterInfo::isVirtualRegister(Hint))
89     Hint = getPhys(Hint);
90   return getPhys(VirtReg) == Hint;
91 }
92 
93 bool VirtRegMap::hasKnownPreference(unsigned VirtReg) {
94   std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(VirtReg);
95   if (TargetRegisterInfo::isPhysicalRegister(Hint.second))
96     return true;
97   if (TargetRegisterInfo::isVirtualRegister(Hint.second))
98     return hasPhys(Hint.second);
99   return false;
100 }
101 
102 int VirtRegMap::assignVirt2StackSlot(unsigned virtReg) {
103   assert(TargetRegisterInfo::isVirtualRegister(virtReg));
104   assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
105          "attempt to assign stack slot to already spilled register");
106   const TargetRegisterClass* RC = MF->getRegInfo().getRegClass(virtReg);
107   return Virt2StackSlotMap[virtReg] = createSpillSlot(RC);
108 }
109 
110 void VirtRegMap::assignVirt2StackSlot(unsigned virtReg, int SS) {
111   assert(TargetRegisterInfo::isVirtualRegister(virtReg));
112   assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
113          "attempt to assign stack slot to already spilled register");
114   assert((SS >= 0 ||
115           (SS >= MF->getFrameInfo()->getObjectIndexBegin())) &&
116          "illegal fixed frame index");
117   Virt2StackSlotMap[virtReg] = SS;
118 }
119 
120 void VirtRegMap::print(raw_ostream &OS, const Module*) const {
121   OS << "********** REGISTER MAP **********\n";
122   for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
123     unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
124     if (Virt2PhysMap[Reg] != (unsigned)VirtRegMap::NO_PHYS_REG) {
125       OS << '[' << PrintReg(Reg, TRI) << " -> "
126          << PrintReg(Virt2PhysMap[Reg], TRI) << "] "
127          << MRI->getRegClass(Reg)->getName() << "\n";
128     }
129   }
130 
131   for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
132     unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
133     if (Virt2StackSlotMap[Reg] != VirtRegMap::NO_STACK_SLOT) {
134       OS << '[' << PrintReg(Reg, TRI) << " -> fi#" << Virt2StackSlotMap[Reg]
135          << "] " << MRI->getRegClass(Reg)->getName() << "\n";
136     }
137   }
138   OS << '\n';
139 }
140 
141 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
142 void VirtRegMap::dump() const {
143   print(dbgs());
144 }
145 #endif
146 
147 //===----------------------------------------------------------------------===//
148 //                              VirtRegRewriter
149 //===----------------------------------------------------------------------===//
150 //
151 // The VirtRegRewriter is the last of the register allocator passes.
152 // It rewrites virtual registers to physical registers as specified in the
153 // VirtRegMap analysis. It also updates live-in information on basic blocks
154 // according to LiveIntervals.
155 //
156 namespace {
157 class VirtRegRewriter : public MachineFunctionPass {
158   MachineFunction *MF;
159   const TargetMachine *TM;
160   const TargetRegisterInfo *TRI;
161   const TargetInstrInfo *TII;
162   MachineRegisterInfo *MRI;
163   SlotIndexes *Indexes;
164   LiveIntervals *LIS;
165   VirtRegMap *VRM;
166   SparseSet<unsigned> PhysRegs;
167 
168   void rewrite();
169   void addMBBLiveIns();
170 public:
171   static char ID;
172   VirtRegRewriter() : MachineFunctionPass(ID) {}
173 
174   void getAnalysisUsage(AnalysisUsage &AU) const override;
175 
176   bool runOnMachineFunction(MachineFunction&) override;
177 };
178 } // end anonymous namespace
179 
180 char &llvm::VirtRegRewriterID = VirtRegRewriter::ID;
181 
182 INITIALIZE_PASS_BEGIN(VirtRegRewriter, "virtregrewriter",
183                       "Virtual Register Rewriter", false, false)
184 INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
185 INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
186 INITIALIZE_PASS_DEPENDENCY(LiveDebugVariables)
187 INITIALIZE_PASS_DEPENDENCY(LiveStacks)
188 INITIALIZE_PASS_DEPENDENCY(VirtRegMap)
189 INITIALIZE_PASS_END(VirtRegRewriter, "virtregrewriter",
190                     "Virtual Register Rewriter", false, false)
191 
192 char VirtRegRewriter::ID = 0;
193 
194 void VirtRegRewriter::getAnalysisUsage(AnalysisUsage &AU) const {
195   AU.setPreservesCFG();
196   AU.addRequired<LiveIntervals>();
197   AU.addRequired<SlotIndexes>();
198   AU.addPreserved<SlotIndexes>();
199   AU.addRequired<LiveDebugVariables>();
200   AU.addRequired<LiveStacks>();
201   AU.addPreserved<LiveStacks>();
202   AU.addRequired<VirtRegMap>();
203   MachineFunctionPass::getAnalysisUsage(AU);
204 }
205 
206 bool VirtRegRewriter::runOnMachineFunction(MachineFunction &fn) {
207   MF = &fn;
208   TM = &MF->getTarget();
209   TRI = MF->getSubtarget().getRegisterInfo();
210   TII = MF->getSubtarget().getInstrInfo();
211   MRI = &MF->getRegInfo();
212   Indexes = &getAnalysis<SlotIndexes>();
213   LIS = &getAnalysis<LiveIntervals>();
214   VRM = &getAnalysis<VirtRegMap>();
215   DEBUG(dbgs() << "********** REWRITE VIRTUAL REGISTERS **********\n"
216                << "********** Function: "
217                << MF->getName() << '\n');
218   DEBUG(VRM->dump());
219 
220   // Add kill flags while we still have virtual registers.
221   LIS->addKillFlags(VRM);
222 
223   // Live-in lists on basic blocks are required for physregs.
224   addMBBLiveIns();
225 
226   // Rewrite virtual registers.
227   rewrite();
228 
229   // Write out new DBG_VALUE instructions.
230   getAnalysis<LiveDebugVariables>().emitDebugValues(VRM);
231 
232   // All machine operands and other references to virtual registers have been
233   // replaced. Remove the virtual registers and release all the transient data.
234   VRM->clearAllVirt();
235   MRI->clearVirtRegs();
236   return true;
237 }
238 
239 // Compute MBB live-in lists from virtual register live ranges and their
240 // assignments.
241 void VirtRegRewriter::addMBBLiveIns() {
242   SmallVector<MachineBasicBlock*, 16> LiveIn;
243   for (unsigned Idx = 0, IdxE = MRI->getNumVirtRegs(); Idx != IdxE; ++Idx) {
244     unsigned VirtReg = TargetRegisterInfo::index2VirtReg(Idx);
245     if (MRI->reg_nodbg_empty(VirtReg))
246       continue;
247     LiveInterval &LI = LIS->getInterval(VirtReg);
248     if (LI.empty() || LIS->intervalIsInOneMBB(LI))
249       continue;
250     // This is a virtual register that is live across basic blocks. Its
251     // assigned PhysReg must be marked as live-in to those blocks.
252     unsigned PhysReg = VRM->getPhys(VirtReg);
253     assert(PhysReg != VirtRegMap::NO_PHYS_REG && "Unmapped virtual register.");
254 
255     // Scan the segments of LI.
256     for (LiveInterval::const_iterator I = LI.begin(), E = LI.end(); I != E;
257          ++I) {
258       if (!Indexes->findLiveInMBBs(I->start, I->end, LiveIn))
259         continue;
260       for (unsigned i = 0, e = LiveIn.size(); i != e; ++i)
261         if (!LiveIn[i]->isLiveIn(PhysReg))
262           LiveIn[i]->addLiveIn(PhysReg);
263       LiveIn.clear();
264     }
265   }
266 }
267 
268 void VirtRegRewriter::rewrite() {
269   SmallVector<unsigned, 8> SuperDeads;
270   SmallVector<unsigned, 8> SuperDefs;
271   SmallVector<unsigned, 8> SuperKills;
272   SmallPtrSet<const MachineInstr *, 4> NoReturnInsts;
273 
274   // Here we have a SparseSet to hold which PhysRegs are actually encountered
275   // in the MF we are about to iterate over so that later when we call
276   // setPhysRegUsed, we are only doing it for physRegs that were actually found
277   // in the program and not for all of the possible physRegs for the given
278   // target architecture. If the target has a lot of physRegs, then for a small
279   // program there will be a significant compile time reduction here.
280   PhysRegs.clear();
281   PhysRegs.setUniverse(TRI->getNumRegs());
282 
283   // The function with uwtable should guarantee that the stack unwinder
284   // can unwind the stack to the previous frame.  Thus, we can't apply the
285   // noreturn optimization if the caller function has uwtable attribute.
286   bool HasUWTable = MF->getFunction()->hasFnAttribute(Attribute::UWTable);
287 
288   for (MachineFunction::iterator MBBI = MF->begin(), MBBE = MF->end();
289        MBBI != MBBE; ++MBBI) {
290     DEBUG(MBBI->print(dbgs(), Indexes));
291     bool IsExitBB = MBBI->succ_empty();
292     for (MachineBasicBlock::instr_iterator
293            MII = MBBI->instr_begin(), MIE = MBBI->instr_end(); MII != MIE;) {
294       MachineInstr *MI = MII;
295       ++MII;
296 
297       // Check if this instruction is a call to a noreturn function.  If this
298       // is a call to noreturn function and we don't need the stack unwinding
299       // functionality (i.e. this function does not have uwtable attribute and
300       // the callee function has the nounwind attribute), then we can ignore
301       // the definitions set by this instruction.
302       if (!HasUWTable && IsExitBB && MI->isCall()) {
303         for (MachineInstr::mop_iterator MOI = MI->operands_begin(),
304                MOE = MI->operands_end(); MOI != MOE; ++MOI) {
305           MachineOperand &MO = *MOI;
306           if (!MO.isGlobal())
307             continue;
308           const Function *Func = dyn_cast<Function>(MO.getGlobal());
309           if (!Func || !Func->hasFnAttribute(Attribute::NoReturn) ||
310               // We need to keep correct unwind information
311               // even if the function will not return, since the
312               // runtime may need it.
313               !Func->hasFnAttribute(Attribute::NoUnwind))
314             continue;
315           NoReturnInsts.insert(MI);
316           break;
317         }
318       }
319 
320       for (MachineInstr::mop_iterator MOI = MI->operands_begin(),
321            MOE = MI->operands_end(); MOI != MOE; ++MOI) {
322         MachineOperand &MO = *MOI;
323 
324         // Make sure MRI knows about registers clobbered by regmasks.
325         if (MO.isRegMask())
326           MRI->addPhysRegsUsedFromRegMask(MO.getRegMask());
327 
328         // If we encounter a VirtReg or PhysReg then get at the PhysReg and add
329         // it to the physreg bitset.  Later we use only the PhysRegs that were
330         // actually encountered in the MF to populate the MRI's used physregs.
331         if (MO.isReg() && MO.getReg())
332           PhysRegs.insert(
333               TargetRegisterInfo::isVirtualRegister(MO.getReg()) ?
334               VRM->getPhys(MO.getReg()) :
335               MO.getReg());
336 
337         if (!MO.isReg() || !TargetRegisterInfo::isVirtualRegister(MO.getReg()))
338           continue;
339         unsigned VirtReg = MO.getReg();
340         unsigned PhysReg = VRM->getPhys(VirtReg);
341         assert(PhysReg != VirtRegMap::NO_PHYS_REG &&
342                "Instruction uses unmapped VirtReg");
343         assert(!MRI->isReserved(PhysReg) && "Reserved register assignment");
344 
345         // Preserve semantics of sub-register operands.
346         if (MO.getSubReg()) {
347           // A virtual register kill refers to the whole register, so we may
348           // have to add <imp-use,kill> operands for the super-register.  A
349           // partial redef always kills and redefines the super-register.
350           if (MO.readsReg() && (MO.isDef() || MO.isKill()))
351             SuperKills.push_back(PhysReg);
352 
353           if (MO.isDef()) {
354             // The <def,undef> flag only makes sense for sub-register defs, and
355             // we are substituting a full physreg.  An <imp-use,kill> operand
356             // from the SuperKills list will represent the partial read of the
357             // super-register.
358             MO.setIsUndef(false);
359 
360             // Also add implicit defs for the super-register.
361             if (MO.isDead())
362               SuperDeads.push_back(PhysReg);
363             else
364               SuperDefs.push_back(PhysReg);
365           }
366 
367           // PhysReg operands cannot have subregister indexes.
368           PhysReg = TRI->getSubReg(PhysReg, MO.getSubReg());
369           assert(PhysReg && "Invalid SubReg for physical register");
370           MO.setSubReg(0);
371         }
372         // Rewrite. Note we could have used MachineOperand::substPhysReg(), but
373         // we need the inlining here.
374         MO.setReg(PhysReg);
375       }
376 
377       // Add any missing super-register kills after rewriting the whole
378       // instruction.
379       while (!SuperKills.empty())
380         MI->addRegisterKilled(SuperKills.pop_back_val(), TRI, true);
381 
382       while (!SuperDeads.empty())
383         MI->addRegisterDead(SuperDeads.pop_back_val(), TRI, true);
384 
385       while (!SuperDefs.empty())
386         MI->addRegisterDefined(SuperDefs.pop_back_val(), TRI);
387 
388       DEBUG(dbgs() << "> " << *MI);
389 
390       // Finally, remove any identity copies.
391       if (MI->isIdentityCopy()) {
392         ++NumIdCopies;
393         if (MI->getNumOperands() == 2) {
394           DEBUG(dbgs() << "Deleting identity copy.\n");
395           if (Indexes)
396             Indexes->removeMachineInstrFromMaps(MI);
397           // It's safe to erase MI because MII has already been incremented.
398           MI->eraseFromParent();
399         } else {
400           // Transform identity copy to a KILL to deal with subregisters.
401           MI->setDesc(TII->get(TargetOpcode::KILL));
402           DEBUG(dbgs() << "Identity copy: " << *MI);
403         }
404       }
405     }
406   }
407 
408   // Tell MRI about physical registers in use.
409   if (NoReturnInsts.empty()) {
410     for (SparseSet<unsigned>::iterator
411         RegI = PhysRegs.begin(), E = PhysRegs.end(); RegI != E; ++RegI)
412       if (!MRI->reg_nodbg_empty(*RegI))
413         MRI->setPhysRegUsed(*RegI);
414   } else {
415     for (SparseSet<unsigned>::iterator
416         I = PhysRegs.begin(), E = PhysRegs.end(); I != E; ++I) {
417       unsigned Reg = *I;
418       if (MRI->reg_nodbg_empty(Reg))
419         continue;
420       // Check if this register has a use that will impact the rest of the
421       // code. Uses in debug and noreturn instructions do not impact the
422       // generated code.
423       for (MachineInstr &It : MRI->reg_nodbg_instructions(Reg)) {
424         if (!NoReturnInsts.count(&It)) {
425           MRI->setPhysRegUsed(Reg);
426           break;
427         }
428       }
429     }
430   }
431 }
432 
433