1 //===-- llvm/CodeGen/VirtRegMap.cpp - Virtual Register Map ----------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the VirtRegMap class.
11 //
12 // It also contains implementations of the Spiller interface, which, given a
13 // virtual register map and a machine function, eliminates all virtual
14 // references by replacing them with physical register references - adding spill
15 // code as necessary.
16 //
17 //===----------------------------------------------------------------------===//
18 
19 #define DEBUG_TYPE "virtregmap"
20 #include "VirtRegMap.h"
21 #include "llvm/Function.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/SlotIndexes.h"
27 #include "llvm/Target/TargetMachine.h"
28 #include "llvm/Target/TargetInstrInfo.h"
29 #include "llvm/Target/TargetRegisterInfo.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Support/Compiler.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/raw_ostream.h"
34 #include "llvm/ADT/Statistic.h"
35 #include "llvm/ADT/STLExtras.h"
36 #include <algorithm>
37 using namespace llvm;
38 
39 STATISTIC(NumSpillSlots, "Number of spill slots allocated");
40 STATISTIC(NumIdCopies,   "Number of identity moves eliminated after rewriting");
41 
42 //===----------------------------------------------------------------------===//
43 //  VirtRegMap implementation
44 //===----------------------------------------------------------------------===//
45 
46 char VirtRegMap::ID = 0;
47 
48 INITIALIZE_PASS(VirtRegMap, "virtregmap", "Virtual Register Map", false, false)
49 
50 bool VirtRegMap::runOnMachineFunction(MachineFunction &mf) {
51   MRI = &mf.getRegInfo();
52   TII = mf.getTarget().getInstrInfo();
53   TRI = mf.getTarget().getRegisterInfo();
54   MF = &mf;
55 
56   Virt2PhysMap.clear();
57   Virt2StackSlotMap.clear();
58   Virt2SplitMap.clear();
59 
60   grow();
61   return false;
62 }
63 
64 void VirtRegMap::grow() {
65   unsigned NumRegs = MF->getRegInfo().getNumVirtRegs();
66   Virt2PhysMap.resize(NumRegs);
67   Virt2StackSlotMap.resize(NumRegs);
68   Virt2SplitMap.resize(NumRegs);
69 }
70 
71 unsigned VirtRegMap::createSpillSlot(const TargetRegisterClass *RC) {
72   int SS = MF->getFrameInfo()->CreateSpillStackObject(RC->getSize(),
73                                                       RC->getAlignment());
74   ++NumSpillSlots;
75   return SS;
76 }
77 
78 unsigned VirtRegMap::getRegAllocPref(unsigned virtReg) {
79   std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(virtReg);
80   unsigned physReg = Hint.second;
81   if (TargetRegisterInfo::isVirtualRegister(physReg) && hasPhys(physReg))
82     physReg = getPhys(physReg);
83   if (Hint.first == 0)
84     return (TargetRegisterInfo::isPhysicalRegister(physReg))
85       ? physReg : 0;
86   return TRI->ResolveRegAllocHint(Hint.first, physReg, *MF);
87 }
88 
89 int VirtRegMap::assignVirt2StackSlot(unsigned virtReg) {
90   assert(TargetRegisterInfo::isVirtualRegister(virtReg));
91   assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
92          "attempt to assign stack slot to already spilled register");
93   const TargetRegisterClass* RC = MF->getRegInfo().getRegClass(virtReg);
94   return Virt2StackSlotMap[virtReg] = createSpillSlot(RC);
95 }
96 
97 void VirtRegMap::assignVirt2StackSlot(unsigned virtReg, int SS) {
98   assert(TargetRegisterInfo::isVirtualRegister(virtReg));
99   assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
100          "attempt to assign stack slot to already spilled register");
101   assert((SS >= 0 ||
102           (SS >= MF->getFrameInfo()->getObjectIndexBegin())) &&
103          "illegal fixed frame index");
104   Virt2StackSlotMap[virtReg] = SS;
105 }
106 
107 void VirtRegMap::rewrite(SlotIndexes *Indexes) {
108   DEBUG(dbgs() << "********** REWRITE VIRTUAL REGISTERS **********\n"
109                << "********** Function: "
110                << MF->getFunction()->getName() << '\n');
111   DEBUG(dump());
112   SmallVector<unsigned, 8> SuperDeads;
113   SmallVector<unsigned, 8> SuperDefs;
114   SmallVector<unsigned, 8> SuperKills;
115 
116   for (MachineFunction::iterator MBBI = MF->begin(), MBBE = MF->end();
117        MBBI != MBBE; ++MBBI) {
118     DEBUG(MBBI->print(dbgs(), Indexes));
119     for (MachineBasicBlock::iterator MII = MBBI->begin(), MIE = MBBI->end();
120          MII != MIE;) {
121       MachineInstr *MI = MII;
122       ++MII;
123 
124       for (MachineInstr::mop_iterator MOI = MI->operands_begin(),
125            MOE = MI->operands_end(); MOI != MOE; ++MOI) {
126         MachineOperand &MO = *MOI;
127         if (!MO.isReg() || !TargetRegisterInfo::isVirtualRegister(MO.getReg()))
128           continue;
129         unsigned VirtReg = MO.getReg();
130         unsigned PhysReg = getPhys(VirtReg);
131         assert(PhysReg != NO_PHYS_REG && "Instruction uses unmapped VirtReg");
132 
133         // Preserve semantics of sub-register operands.
134         if (MO.getSubReg()) {
135           // A virtual register kill refers to the whole register, so we may
136           // have to add <imp-use,kill> operands for the super-register.  A
137           // partial redef always kills and redefines the super-register.
138           if (MO.readsReg() && (MO.isDef() || MO.isKill()))
139             SuperKills.push_back(PhysReg);
140 
141           if (MO.isDef()) {
142             // The <def,undef> flag only makes sense for sub-register defs, and
143             // we are substituting a full physreg.  An <imp-use,kill> operand
144             // from the SuperKills list will represent the partial read of the
145             // super-register.
146             MO.setIsUndef(false);
147 
148             // Also add implicit defs for the super-register.
149             if (MO.isDead())
150               SuperDeads.push_back(PhysReg);
151             else
152               SuperDefs.push_back(PhysReg);
153           }
154 
155           // PhysReg operands cannot have subregister indexes.
156           PhysReg = TRI->getSubReg(PhysReg, MO.getSubReg());
157           assert(PhysReg && "Invalid SubReg for physical register");
158           MO.setSubReg(0);
159         }
160         // Rewrite. Note we could have used MachineOperand::substPhysReg(), but
161         // we need the inlining here.
162         MO.setReg(PhysReg);
163       }
164 
165       // Add any missing super-register kills after rewriting the whole
166       // instruction.
167       while (!SuperKills.empty())
168         MI->addRegisterKilled(SuperKills.pop_back_val(), TRI, true);
169 
170       while (!SuperDeads.empty())
171         MI->addRegisterDead(SuperDeads.pop_back_val(), TRI, true);
172 
173       while (!SuperDefs.empty())
174         MI->addRegisterDefined(SuperDefs.pop_back_val(), TRI);
175 
176       DEBUG(dbgs() << "> " << *MI);
177 
178       // Finally, remove any identity copies.
179       if (MI->isIdentityCopy()) {
180         ++NumIdCopies;
181         if (MI->getNumOperands() == 2) {
182           DEBUG(dbgs() << "Deleting identity copy.\n");
183           if (Indexes)
184             Indexes->removeMachineInstrFromMaps(MI);
185           // It's safe to erase MI because MII has already been incremented.
186           MI->eraseFromParent();
187         } else {
188           // Transform identity copy to a KILL to deal with subregisters.
189           MI->setDesc(TII->get(TargetOpcode::KILL));
190           DEBUG(dbgs() << "Identity copy: " << *MI);
191         }
192       }
193     }
194   }
195 
196   // Tell MRI about physical registers in use.
197   for (unsigned Reg = 1, RegE = TRI->getNumRegs(); Reg != RegE; ++Reg)
198     if (!MRI->reg_nodbg_empty(Reg))
199       MRI->setPhysRegUsed(Reg);
200 }
201 
202 void VirtRegMap::print(raw_ostream &OS, const Module* M) const {
203   const TargetRegisterInfo* TRI = MF->getTarget().getRegisterInfo();
204   const MachineRegisterInfo &MRI = MF->getRegInfo();
205 
206   OS << "********** REGISTER MAP **********\n";
207   for (unsigned i = 0, e = MRI.getNumVirtRegs(); i != e; ++i) {
208     unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
209     if (Virt2PhysMap[Reg] != (unsigned)VirtRegMap::NO_PHYS_REG) {
210       OS << '[' << PrintReg(Reg, TRI) << " -> "
211          << PrintReg(Virt2PhysMap[Reg], TRI) << "] "
212          << MRI.getRegClass(Reg)->getName() << "\n";
213     }
214   }
215 
216   for (unsigned i = 0, e = MRI.getNumVirtRegs(); i != e; ++i) {
217     unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
218     if (Virt2StackSlotMap[Reg] != VirtRegMap::NO_STACK_SLOT) {
219       OS << '[' << PrintReg(Reg, TRI) << " -> fi#" << Virt2StackSlotMap[Reg]
220          << "] " << MRI.getRegClass(Reg)->getName() << "\n";
221     }
222   }
223   OS << '\n';
224 }
225 
226 void VirtRegMap::dump() const {
227   print(dbgs());
228 }
229