1 //===-- llvm/CodeGen/VirtRegMap.cpp - Virtual Register Map ----------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the VirtRegMap class.
11 //
12 // It also contains implementations of the Spiller interface, which, given a
13 // virtual register map and a machine function, eliminates all virtual
14 // references by replacing them with physical register references - adding spill
15 // code as necessary.
16 //
17 //===----------------------------------------------------------------------===//
18 
19 #define DEBUG_TYPE "virtregmap"
20 #include "VirtRegMap.h"
21 #include "llvm/Function.h"
22 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/CodeGen/MachineFunction.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/Target/TargetMachine.h"
28 #include "llvm/Target/TargetInstrInfo.h"
29 #include "llvm/Target/TargetRegisterInfo.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Support/Compiler.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/raw_ostream.h"
34 #include "llvm/ADT/BitVector.h"
35 #include "llvm/ADT/DenseMap.h"
36 #include "llvm/ADT/DepthFirstIterator.h"
37 #include "llvm/ADT/Statistic.h"
38 #include "llvm/ADT/STLExtras.h"
39 #include "llvm/ADT/SmallSet.h"
40 #include <algorithm>
41 using namespace llvm;
42 
43 STATISTIC(NumSpills  , "Number of register spills");
44 
45 //===----------------------------------------------------------------------===//
46 //  VirtRegMap implementation
47 //===----------------------------------------------------------------------===//
48 
49 char VirtRegMap::ID = 0;
50 
51 INITIALIZE_PASS(VirtRegMap, "virtregmap", "Virtual Register Map", false, false)
52 
53 bool VirtRegMap::runOnMachineFunction(MachineFunction &mf) {
54   MRI = &mf.getRegInfo();
55   TII = mf.getTarget().getInstrInfo();
56   TRI = mf.getTarget().getRegisterInfo();
57   MF = &mf;
58 
59   ReMatId = MAX_STACK_SLOT+1;
60   LowSpillSlot = HighSpillSlot = NO_STACK_SLOT;
61 
62   Virt2PhysMap.clear();
63   Virt2StackSlotMap.clear();
64   Virt2ReMatIdMap.clear();
65   Virt2SplitMap.clear();
66   Virt2SplitKillMap.clear();
67   ReMatMap.clear();
68   ImplicitDefed.clear();
69   SpillSlotToUsesMap.clear();
70   MI2VirtMap.clear();
71   SpillPt2VirtMap.clear();
72   RestorePt2VirtMap.clear();
73   EmergencySpillMap.clear();
74   EmergencySpillSlots.clear();
75 
76   SpillSlotToUsesMap.resize(8);
77   ImplicitDefed.resize(MF->getRegInfo().getNumVirtRegs());
78 
79   allocatableRCRegs.clear();
80   for (TargetRegisterInfo::regclass_iterator I = TRI->regclass_begin(),
81          E = TRI->regclass_end(); I != E; ++I)
82     allocatableRCRegs.insert(std::make_pair(*I,
83                                             TRI->getAllocatableSet(mf, *I)));
84 
85   grow();
86 
87   return false;
88 }
89 
90 void VirtRegMap::grow() {
91   unsigned NumRegs = MF->getRegInfo().getNumVirtRegs();
92   Virt2PhysMap.resize(NumRegs);
93   Virt2StackSlotMap.resize(NumRegs);
94   Virt2ReMatIdMap.resize(NumRegs);
95   Virt2SplitMap.resize(NumRegs);
96   Virt2SplitKillMap.resize(NumRegs);
97   ReMatMap.resize(NumRegs);
98   ImplicitDefed.resize(NumRegs);
99 }
100 
101 unsigned VirtRegMap::createSpillSlot(const TargetRegisterClass *RC) {
102   int SS = MF->getFrameInfo()->CreateSpillStackObject(RC->getSize(),
103                                                       RC->getAlignment());
104   if (LowSpillSlot == NO_STACK_SLOT)
105     LowSpillSlot = SS;
106   if (HighSpillSlot == NO_STACK_SLOT || SS > HighSpillSlot)
107     HighSpillSlot = SS;
108   assert(SS >= LowSpillSlot && "Unexpected low spill slot");
109   unsigned Idx = SS-LowSpillSlot;
110   while (Idx >= SpillSlotToUsesMap.size())
111     SpillSlotToUsesMap.resize(SpillSlotToUsesMap.size()*2);
112   return SS;
113 }
114 
115 unsigned VirtRegMap::getRegAllocPref(unsigned virtReg) {
116   std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(virtReg);
117   unsigned physReg = Hint.second;
118   if (TargetRegisterInfo::isVirtualRegister(physReg) && hasPhys(physReg))
119     physReg = getPhys(physReg);
120   if (Hint.first == 0)
121     return (TargetRegisterInfo::isPhysicalRegister(physReg))
122       ? physReg : 0;
123   return TRI->ResolveRegAllocHint(Hint.first, physReg, *MF);
124 }
125 
126 int VirtRegMap::assignVirt2StackSlot(unsigned virtReg) {
127   assert(TargetRegisterInfo::isVirtualRegister(virtReg));
128   assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
129          "attempt to assign stack slot to already spilled register");
130   const TargetRegisterClass* RC = MF->getRegInfo().getRegClass(virtReg);
131   ++NumSpills;
132   return Virt2StackSlotMap[virtReg] = createSpillSlot(RC);
133 }
134 
135 void VirtRegMap::assignVirt2StackSlot(unsigned virtReg, int SS) {
136   assert(TargetRegisterInfo::isVirtualRegister(virtReg));
137   assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
138          "attempt to assign stack slot to already spilled register");
139   assert((SS >= 0 ||
140           (SS >= MF->getFrameInfo()->getObjectIndexBegin())) &&
141          "illegal fixed frame index");
142   Virt2StackSlotMap[virtReg] = SS;
143 }
144 
145 int VirtRegMap::assignVirtReMatId(unsigned virtReg) {
146   assert(TargetRegisterInfo::isVirtualRegister(virtReg));
147   assert(Virt2ReMatIdMap[virtReg] == NO_STACK_SLOT &&
148          "attempt to assign re-mat id to already spilled register");
149   Virt2ReMatIdMap[virtReg] = ReMatId;
150   return ReMatId++;
151 }
152 
153 void VirtRegMap::assignVirtReMatId(unsigned virtReg, int id) {
154   assert(TargetRegisterInfo::isVirtualRegister(virtReg));
155   assert(Virt2ReMatIdMap[virtReg] == NO_STACK_SLOT &&
156          "attempt to assign re-mat id to already spilled register");
157   Virt2ReMatIdMap[virtReg] = id;
158 }
159 
160 int VirtRegMap::getEmergencySpillSlot(const TargetRegisterClass *RC) {
161   std::map<const TargetRegisterClass*, int>::iterator I =
162     EmergencySpillSlots.find(RC);
163   if (I != EmergencySpillSlots.end())
164     return I->second;
165   return EmergencySpillSlots[RC] = createSpillSlot(RC);
166 }
167 
168 void VirtRegMap::addSpillSlotUse(int FI, MachineInstr *MI) {
169   if (!MF->getFrameInfo()->isFixedObjectIndex(FI)) {
170     // If FI < LowSpillSlot, this stack reference was produced by
171     // instruction selection and is not a spill
172     if (FI >= LowSpillSlot) {
173       assert(FI >= 0 && "Spill slot index should not be negative!");
174       assert((unsigned)FI-LowSpillSlot < SpillSlotToUsesMap.size()
175              && "Invalid spill slot");
176       SpillSlotToUsesMap[FI-LowSpillSlot].insert(MI);
177     }
178   }
179 }
180 
181 void VirtRegMap::virtFolded(unsigned VirtReg, MachineInstr *OldMI,
182                             MachineInstr *NewMI, ModRef MRInfo) {
183   // Move previous memory references folded to new instruction.
184   MI2VirtMapTy::iterator IP = MI2VirtMap.lower_bound(NewMI);
185   for (MI2VirtMapTy::iterator I = MI2VirtMap.lower_bound(OldMI),
186          E = MI2VirtMap.end(); I != E && I->first == OldMI; ) {
187     MI2VirtMap.insert(IP, std::make_pair(NewMI, I->second));
188     MI2VirtMap.erase(I++);
189   }
190 
191   // add new memory reference
192   MI2VirtMap.insert(IP, std::make_pair(NewMI, std::make_pair(VirtReg, MRInfo)));
193 }
194 
195 void VirtRegMap::virtFolded(unsigned VirtReg, MachineInstr *MI, ModRef MRInfo) {
196   MI2VirtMapTy::iterator IP = MI2VirtMap.lower_bound(MI);
197   MI2VirtMap.insert(IP, std::make_pair(MI, std::make_pair(VirtReg, MRInfo)));
198 }
199 
200 void VirtRegMap::RemoveMachineInstrFromMaps(MachineInstr *MI) {
201   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
202     MachineOperand &MO = MI->getOperand(i);
203     if (!MO.isFI())
204       continue;
205     int FI = MO.getIndex();
206     if (MF->getFrameInfo()->isFixedObjectIndex(FI))
207       continue;
208     // This stack reference was produced by instruction selection and
209     // is not a spill
210     if (FI < LowSpillSlot)
211       continue;
212     assert((unsigned)FI-LowSpillSlot < SpillSlotToUsesMap.size()
213            && "Invalid spill slot");
214     SpillSlotToUsesMap[FI-LowSpillSlot].erase(MI);
215   }
216   MI2VirtMap.erase(MI);
217   SpillPt2VirtMap.erase(MI);
218   RestorePt2VirtMap.erase(MI);
219   EmergencySpillMap.erase(MI);
220 }
221 
222 /// FindUnusedRegisters - Gather a list of allocatable registers that
223 /// have not been allocated to any virtual register.
224 bool VirtRegMap::FindUnusedRegisters(LiveIntervals* LIs) {
225   unsigned NumRegs = TRI->getNumRegs();
226   UnusedRegs.reset();
227   UnusedRegs.resize(NumRegs);
228 
229   BitVector Used(NumRegs);
230   for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
231     unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
232     if (Virt2PhysMap[Reg] != (unsigned)VirtRegMap::NO_PHYS_REG)
233       Used.set(Virt2PhysMap[Reg]);
234   }
235 
236   BitVector Allocatable = TRI->getAllocatableSet(*MF);
237   bool AnyUnused = false;
238   for (unsigned Reg = 1; Reg < NumRegs; ++Reg) {
239     if (Allocatable[Reg] && !Used[Reg] && !LIs->hasInterval(Reg)) {
240       bool ReallyUnused = true;
241       for (const unsigned *AS = TRI->getAliasSet(Reg); *AS; ++AS) {
242         if (Used[*AS] || LIs->hasInterval(*AS)) {
243           ReallyUnused = false;
244           break;
245         }
246       }
247       if (ReallyUnused) {
248         AnyUnused = true;
249         UnusedRegs.set(Reg);
250       }
251     }
252   }
253 
254   return AnyUnused;
255 }
256 
257 void VirtRegMap::print(raw_ostream &OS, const Module* M) const {
258   const TargetRegisterInfo* TRI = MF->getTarget().getRegisterInfo();
259   const MachineRegisterInfo &MRI = MF->getRegInfo();
260 
261   OS << "********** REGISTER MAP **********\n";
262   for (unsigned i = 0, e = MRI.getNumVirtRegs(); i != e; ++i) {
263     unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
264     if (Virt2PhysMap[Reg] != (unsigned)VirtRegMap::NO_PHYS_REG) {
265       OS << '[' << PrintReg(Reg, TRI) << " -> "
266          << PrintReg(Virt2PhysMap[Reg], TRI) << "] "
267          << MRI.getRegClass(Reg)->getName() << "\n";
268     }
269   }
270 
271   for (unsigned i = 0, e = MRI.getNumVirtRegs(); i != e; ++i) {
272     unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
273     if (Virt2StackSlotMap[Reg] != VirtRegMap::NO_STACK_SLOT) {
274       OS << '[' << PrintReg(Reg, TRI) << " -> fi#" << Virt2StackSlotMap[Reg]
275          << "] " << MRI.getRegClass(Reg)->getName() << "\n";
276     }
277   }
278   OS << '\n';
279 }
280 
281 void VirtRegMap::dump() const {
282   print(dbgs());
283 }
284