1 //===-- llvm/CodeGen/VirtRegMap.cpp - Virtual Register Map ----------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the VirtRegMap class.
11 //
12 // It also contains implementations of the Spiller interface, which, given a
13 // virtual register map and a machine function, eliminates all virtual
14 // references by replacing them with physical register references - adding spill
15 // code as necessary.
16 //
17 //===----------------------------------------------------------------------===//
18 
19 #include "llvm/CodeGen/VirtRegMap.h"
20 #include "LiveDebugVariables.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/ADT/SparseSet.h"
23 #include "llvm/ADT/Statistic.h"
24 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
25 #include "llvm/CodeGen/LiveStackAnalysis.h"
26 #include "llvm/CodeGen/MachineFrameInfo.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineInstrBuilder.h"
29 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 #include "llvm/CodeGen/Passes.h"
31 #include "llvm/IR/Function.h"
32 #include "llvm/Support/CommandLine.h"
33 #include "llvm/Support/Compiler.h"
34 #include "llvm/Support/Debug.h"
35 #include "llvm/Support/raw_ostream.h"
36 #include "llvm/Target/TargetInstrInfo.h"
37 #include "llvm/Target/TargetMachine.h"
38 #include "llvm/Target/TargetRegisterInfo.h"
39 #include "llvm/Target/TargetSubtargetInfo.h"
40 #include <algorithm>
41 using namespace llvm;
42 
43 #define DEBUG_TYPE "regalloc"
44 
45 STATISTIC(NumSpillSlots, "Number of spill slots allocated");
46 STATISTIC(NumIdCopies,   "Number of identity moves eliminated after rewriting");
47 
48 //===----------------------------------------------------------------------===//
49 //  VirtRegMap implementation
50 //===----------------------------------------------------------------------===//
51 
52 char VirtRegMap::ID = 0;
53 
54 INITIALIZE_PASS(VirtRegMap, "virtregmap", "Virtual Register Map", false, false)
55 
56 bool VirtRegMap::runOnMachineFunction(MachineFunction &mf) {
57   MRI = &mf.getRegInfo();
58   TII = mf.getSubtarget().getInstrInfo();
59   TRI = mf.getSubtarget().getRegisterInfo();
60   MF = &mf;
61 
62   Virt2PhysMap.clear();
63   Virt2StackSlotMap.clear();
64   Virt2SplitMap.clear();
65 
66   grow();
67   return false;
68 }
69 
70 void VirtRegMap::grow() {
71   unsigned NumRegs = MF->getRegInfo().getNumVirtRegs();
72   Virt2PhysMap.resize(NumRegs);
73   Virt2StackSlotMap.resize(NumRegs);
74   Virt2SplitMap.resize(NumRegs);
75 }
76 
77 unsigned VirtRegMap::createSpillSlot(const TargetRegisterClass *RC) {
78   int SS = MF->getFrameInfo()->CreateSpillStackObject(RC->getSize(),
79                                                       RC->getAlignment());
80   ++NumSpillSlots;
81   return SS;
82 }
83 
84 bool VirtRegMap::hasPreferredPhys(unsigned VirtReg) {
85   unsigned Hint = MRI->getSimpleHint(VirtReg);
86   if (!Hint)
87     return 0;
88   if (TargetRegisterInfo::isVirtualRegister(Hint))
89     Hint = getPhys(Hint);
90   return getPhys(VirtReg) == Hint;
91 }
92 
93 bool VirtRegMap::hasKnownPreference(unsigned VirtReg) {
94   std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(VirtReg);
95   if (TargetRegisterInfo::isPhysicalRegister(Hint.second))
96     return true;
97   if (TargetRegisterInfo::isVirtualRegister(Hint.second))
98     return hasPhys(Hint.second);
99   return false;
100 }
101 
102 int VirtRegMap::assignVirt2StackSlot(unsigned virtReg) {
103   assert(TargetRegisterInfo::isVirtualRegister(virtReg));
104   assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
105          "attempt to assign stack slot to already spilled register");
106   const TargetRegisterClass* RC = MF->getRegInfo().getRegClass(virtReg);
107   return Virt2StackSlotMap[virtReg] = createSpillSlot(RC);
108 }
109 
110 void VirtRegMap::assignVirt2StackSlot(unsigned virtReg, int SS) {
111   assert(TargetRegisterInfo::isVirtualRegister(virtReg));
112   assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
113          "attempt to assign stack slot to already spilled register");
114   assert((SS >= 0 ||
115           (SS >= MF->getFrameInfo()->getObjectIndexBegin())) &&
116          "illegal fixed frame index");
117   Virt2StackSlotMap[virtReg] = SS;
118 }
119 
120 void VirtRegMap::print(raw_ostream &OS, const Module*) const {
121   OS << "********** REGISTER MAP **********\n";
122   for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
123     unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
124     if (Virt2PhysMap[Reg] != (unsigned)VirtRegMap::NO_PHYS_REG) {
125       OS << '[' << PrintReg(Reg, TRI) << " -> "
126          << PrintReg(Virt2PhysMap[Reg], TRI) << "] "
127          << TRI->getRegClassName(MRI->getRegClass(Reg)) << "\n";
128     }
129   }
130 
131   for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
132     unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
133     if (Virt2StackSlotMap[Reg] != VirtRegMap::NO_STACK_SLOT) {
134       OS << '[' << PrintReg(Reg, TRI) << " -> fi#" << Virt2StackSlotMap[Reg]
135          << "] " << TRI->getRegClassName(MRI->getRegClass(Reg)) << "\n";
136     }
137   }
138   OS << '\n';
139 }
140 
141 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
142 void VirtRegMap::dump() const {
143   print(dbgs());
144 }
145 #endif
146 
147 //===----------------------------------------------------------------------===//
148 //                              VirtRegRewriter
149 //===----------------------------------------------------------------------===//
150 //
151 // The VirtRegRewriter is the last of the register allocator passes.
152 // It rewrites virtual registers to physical registers as specified in the
153 // VirtRegMap analysis. It also updates live-in information on basic blocks
154 // according to LiveIntervals.
155 //
156 namespace {
157 class VirtRegRewriter : public MachineFunctionPass {
158   MachineFunction *MF;
159   const TargetMachine *TM;
160   const TargetRegisterInfo *TRI;
161   const TargetInstrInfo *TII;
162   MachineRegisterInfo *MRI;
163   SlotIndexes *Indexes;
164   LiveIntervals *LIS;
165   VirtRegMap *VRM;
166 
167   void rewrite();
168   void addMBBLiveIns();
169   bool readsUndefSubreg(const MachineOperand &MO) const;
170 public:
171   static char ID;
172   VirtRegRewriter() : MachineFunctionPass(ID) {}
173 
174   void getAnalysisUsage(AnalysisUsage &AU) const override;
175 
176   bool runOnMachineFunction(MachineFunction&) override;
177 };
178 } // end anonymous namespace
179 
180 char &llvm::VirtRegRewriterID = VirtRegRewriter::ID;
181 
182 INITIALIZE_PASS_BEGIN(VirtRegRewriter, "virtregrewriter",
183                       "Virtual Register Rewriter", false, false)
184 INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
185 INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
186 INITIALIZE_PASS_DEPENDENCY(LiveDebugVariables)
187 INITIALIZE_PASS_DEPENDENCY(LiveStacks)
188 INITIALIZE_PASS_DEPENDENCY(VirtRegMap)
189 INITIALIZE_PASS_END(VirtRegRewriter, "virtregrewriter",
190                     "Virtual Register Rewriter", false, false)
191 
192 char VirtRegRewriter::ID = 0;
193 
194 void VirtRegRewriter::getAnalysisUsage(AnalysisUsage &AU) const {
195   AU.setPreservesCFG();
196   AU.addRequired<LiveIntervals>();
197   AU.addRequired<SlotIndexes>();
198   AU.addPreserved<SlotIndexes>();
199   AU.addRequired<LiveDebugVariables>();
200   AU.addRequired<LiveStacks>();
201   AU.addPreserved<LiveStacks>();
202   AU.addRequired<VirtRegMap>();
203   MachineFunctionPass::getAnalysisUsage(AU);
204 }
205 
206 bool VirtRegRewriter::runOnMachineFunction(MachineFunction &fn) {
207   MF = &fn;
208   TM = &MF->getTarget();
209   TRI = MF->getSubtarget().getRegisterInfo();
210   TII = MF->getSubtarget().getInstrInfo();
211   MRI = &MF->getRegInfo();
212   Indexes = &getAnalysis<SlotIndexes>();
213   LIS = &getAnalysis<LiveIntervals>();
214   VRM = &getAnalysis<VirtRegMap>();
215   DEBUG(dbgs() << "********** REWRITE VIRTUAL REGISTERS **********\n"
216                << "********** Function: "
217                << MF->getName() << '\n');
218   DEBUG(VRM->dump());
219 
220   // Add kill flags while we still have virtual registers.
221   LIS->addKillFlags(VRM);
222 
223   // Live-in lists on basic blocks are required for physregs.
224   addMBBLiveIns();
225 
226   // Rewrite virtual registers.
227   rewrite();
228 
229   // Write out new DBG_VALUE instructions.
230   getAnalysis<LiveDebugVariables>().emitDebugValues(VRM);
231 
232   // All machine operands and other references to virtual registers have been
233   // replaced. Remove the virtual registers and release all the transient data.
234   VRM->clearAllVirt();
235   MRI->clearVirtRegs();
236   return true;
237 }
238 
239 // Compute MBB live-in lists from virtual register live ranges and their
240 // assignments.
241 void VirtRegRewriter::addMBBLiveIns() {
242   SmallVector<MachineBasicBlock*, 16> LiveIn;
243   for (unsigned Idx = 0, IdxE = MRI->getNumVirtRegs(); Idx != IdxE; ++Idx) {
244     unsigned VirtReg = TargetRegisterInfo::index2VirtReg(Idx);
245     if (MRI->reg_nodbg_empty(VirtReg))
246       continue;
247     LiveInterval &LI = LIS->getInterval(VirtReg);
248     if (LI.empty() || LIS->intervalIsInOneMBB(LI))
249       continue;
250     // This is a virtual register that is live across basic blocks. Its
251     // assigned PhysReg must be marked as live-in to those blocks.
252     unsigned PhysReg = VRM->getPhys(VirtReg);
253     assert(PhysReg != VirtRegMap::NO_PHYS_REG && "Unmapped virtual register.");
254 
255     if (LI.hasSubRanges()) {
256       for (LiveInterval::SubRange &S : LI.subranges()) {
257         for (const auto &Seg : S.segments) {
258           if (!Indexes->findLiveInMBBs(Seg.start, Seg.end, LiveIn))
259             continue;
260           for (MCSubRegIndexIterator SR(PhysReg, TRI); SR.isValid(); ++SR) {
261             unsigned SubReg = SR.getSubReg();
262             unsigned SubRegIndex = SR.getSubRegIndex();
263             unsigned SubRegLaneMask = TRI->getSubRegIndexLaneMask(SubRegIndex);
264             if ((SubRegLaneMask & S.LaneMask) == 0)
265               continue;
266             for (unsigned i = 0, e = LiveIn.size(); i != e; ++i) {
267               LiveIn[i]->addLiveIn(SubReg);
268             }
269           }
270           LiveIn.clear();
271         }
272       }
273     } else {
274       // Scan the segments of LI.
275       for (const auto &Seg : LI.segments) {
276         if (!Indexes->findLiveInMBBs(Seg.start, Seg.end, LiveIn))
277           continue;
278         for (unsigned i = 0, e = LiveIn.size(); i != e; ++i)
279           LiveIn[i]->addLiveIn(PhysReg);
280         LiveIn.clear();
281       }
282     }
283   }
284 
285   // Sort and unique MBB LiveIns as we've not checked if SubReg/PhysReg were in
286   // each MBB's LiveIns set before calling addLiveIn on them.
287   for (MachineBasicBlock &MBB : *MF)
288     MBB.sortUniqueLiveIns();
289 }
290 
291 /// Returns true if the given machine operand \p MO only reads undefined lanes.
292 /// The function only works for use operands with a subregister set.
293 bool VirtRegRewriter::readsUndefSubreg(const MachineOperand &MO) const {
294   // Shortcut if the operand is already marked undef.
295   if (MO.isUndef())
296     return true;
297 
298   unsigned Reg = MO.getReg();
299   const LiveInterval &LI = LIS->getInterval(Reg);
300   const MachineInstr &MI = *MO.getParent();
301   SlotIndex BaseIndex = LIS->getInstructionIndex(&MI);
302   // This code is only meant to handle reading undefined subregisters which
303   // we couldn't properly detect before.
304   assert(LI.liveAt(BaseIndex) &&
305          "Reads of completely dead register should be marked undef already");
306   unsigned SubRegIdx = MO.getSubReg();
307   unsigned UseMask = TRI->getSubRegIndexLaneMask(SubRegIdx);
308   // See if any of the relevant subregister liveranges is defined at this point.
309   for (const LiveInterval::SubRange &SR : LI.subranges()) {
310     if ((SR.LaneMask & UseMask) != 0 && SR.liveAt(BaseIndex))
311       return false;
312   }
313   return true;
314 }
315 
316 void VirtRegRewriter::rewrite() {
317   bool NoSubRegLiveness = !MRI->subRegLivenessEnabled();
318   SmallVector<unsigned, 8> SuperDeads;
319   SmallVector<unsigned, 8> SuperDefs;
320   SmallVector<unsigned, 8> SuperKills;
321 
322   for (MachineFunction::iterator MBBI = MF->begin(), MBBE = MF->end();
323        MBBI != MBBE; ++MBBI) {
324     DEBUG(MBBI->print(dbgs(), Indexes));
325     for (MachineBasicBlock::instr_iterator
326            MII = MBBI->instr_begin(), MIE = MBBI->instr_end(); MII != MIE;) {
327       MachineInstr *MI = MII;
328       ++MII;
329 
330       for (MachineInstr::mop_iterator MOI = MI->operands_begin(),
331            MOE = MI->operands_end(); MOI != MOE; ++MOI) {
332         MachineOperand &MO = *MOI;
333 
334         // Make sure MRI knows about registers clobbered by regmasks.
335         if (MO.isRegMask())
336           MRI->addPhysRegsUsedFromRegMask(MO.getRegMask());
337 
338         if (!MO.isReg() || !TargetRegisterInfo::isVirtualRegister(MO.getReg()))
339           continue;
340         unsigned VirtReg = MO.getReg();
341         unsigned PhysReg = VRM->getPhys(VirtReg);
342         assert(PhysReg != VirtRegMap::NO_PHYS_REG &&
343                "Instruction uses unmapped VirtReg");
344         assert(!MRI->isReserved(PhysReg) && "Reserved register assignment");
345 
346         // Preserve semantics of sub-register operands.
347         unsigned SubReg = MO.getSubReg();
348         if (SubReg != 0) {
349           if (NoSubRegLiveness) {
350             // A virtual register kill refers to the whole register, so we may
351             // have to add <imp-use,kill> operands for the super-register.  A
352             // partial redef always kills and redefines the super-register.
353             if (MO.readsReg() && (MO.isDef() || MO.isKill()))
354               SuperKills.push_back(PhysReg);
355 
356             if (MO.isDef()) {
357               // Also add implicit defs for the super-register.
358               if (MO.isDead())
359                 SuperDeads.push_back(PhysReg);
360               else
361                 SuperDefs.push_back(PhysReg);
362             }
363           } else {
364             if (MO.isUse()) {
365               if (readsUndefSubreg(MO))
366                 // We need to add an <undef> flag if the subregister is
367                 // completely undefined (and we are not adding super-register
368                 // defs).
369                 MO.setIsUndef(true);
370             } else if (!MO.isDead()) {
371               assert(MO.isDef());
372               // Things get tricky when we ran out of lane mask bits and
373               // merged multiple lanes into the overflow bit: In this case
374               // our subregister liveness tracking isn't precise and we can't
375               // know what subregister parts are undefined, fall back to the
376               // implicit super-register def then.
377               unsigned LaneMask = TRI->getSubRegIndexLaneMask(SubReg);
378               if (TargetRegisterInfo::isImpreciseLaneMask(LaneMask))
379                 SuperDefs.push_back(PhysReg);
380             }
381           }
382 
383           // The <def,undef> flag only makes sense for sub-register defs, and
384           // we are substituting a full physreg.  An <imp-use,kill> operand
385           // from the SuperKills list will represent the partial read of the
386           // super-register.
387           if (MO.isDef())
388             MO.setIsUndef(false);
389 
390           // PhysReg operands cannot have subregister indexes.
391           PhysReg = TRI->getSubReg(PhysReg, SubReg);
392           assert(PhysReg && "Invalid SubReg for physical register");
393           MO.setSubReg(0);
394         }
395         // Rewrite. Note we could have used MachineOperand::substPhysReg(), but
396         // we need the inlining here.
397         MO.setReg(PhysReg);
398       }
399 
400       // Add any missing super-register kills after rewriting the whole
401       // instruction.
402       while (!SuperKills.empty())
403         MI->addRegisterKilled(SuperKills.pop_back_val(), TRI, true);
404 
405       while (!SuperDeads.empty())
406         MI->addRegisterDead(SuperDeads.pop_back_val(), TRI, true);
407 
408       while (!SuperDefs.empty())
409         MI->addRegisterDefined(SuperDefs.pop_back_val(), TRI);
410 
411       DEBUG(dbgs() << "> " << *MI);
412 
413       // Finally, remove any identity copies.
414       if (MI->isIdentityCopy()) {
415         ++NumIdCopies;
416         DEBUG(dbgs() << "Deleting identity copy.\n");
417         if (Indexes)
418           Indexes->removeMachineInstrFromMaps(MI);
419         // It's safe to erase MI because MII has already been incremented.
420         MI->eraseFromParent();
421       }
422     }
423   }
424 }
425 
426