1 //===- TargetSubtargetInfo.cpp - General Target Information ----------------==//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file This file describes the general parts of a Subtarget.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "llvm/ADT/Optional.h"
15 #include "llvm/CodeGen/MachineInstr.h"
16 #include "llvm/CodeGen/TargetSchedule.h"
17 #include "llvm/MC/MCInst.h"
18 #include "llvm/Target/TargetSubtargetInfo.h"
19 #include "llvm/Support/Format.h"
20 #include "llvm/Support/raw_ostream.h"
21 #include <string>
22 
23 using namespace llvm;
24 
25 TargetSubtargetInfo::TargetSubtargetInfo(
26     const Triple &TT, StringRef CPU, StringRef FS,
27     ArrayRef<SubtargetFeatureKV> PF, ArrayRef<SubtargetFeatureKV> PD,
28     const SubtargetInfoKV *ProcSched, const MCWriteProcResEntry *WPR,
29     const MCWriteLatencyEntry *WL, const MCReadAdvanceEntry *RA,
30     const InstrStage *IS, const unsigned *OC, const unsigned *FP)
31     : MCSubtargetInfo(TT, CPU, FS, PF, PD, ProcSched, WPR, WL, RA, IS, OC, FP) {
32 }
33 
34 TargetSubtargetInfo::~TargetSubtargetInfo() = default;
35 
36 bool TargetSubtargetInfo::enableAtomicExpand() const {
37   return true;
38 }
39 
40 bool TargetSubtargetInfo::enableMachineScheduler() const {
41   return false;
42 }
43 
44 bool TargetSubtargetInfo::enableJoinGlobalCopies() const {
45   return enableMachineScheduler();
46 }
47 
48 bool TargetSubtargetInfo::enableRALocalReassignment(
49     CodeGenOpt::Level OptLevel) const {
50   return true;
51 }
52 
53 bool TargetSubtargetInfo::enablePostRAScheduler() const {
54   return getSchedModel().PostRAScheduler;
55 }
56 
57 bool TargetSubtargetInfo::useAA() const {
58   return false;
59 }
60 
61 static std::string createSchedInfoStr(unsigned Latency,
62                                      Optional<double> RThroughput) {
63   static const char *SchedPrefix = " sched: [";
64   std::string Comment;
65   raw_string_ostream CS(Comment);
66   if (Latency > 0 && RThroughput.hasValue())
67     CS << SchedPrefix << Latency << format(":%2.2f", RThroughput.getValue())
68        << "]";
69   else if (Latency > 0)
70     CS << SchedPrefix << Latency << ":?]";
71   else if (RThroughput.hasValue())
72     CS << SchedPrefix << "?:" << RThroughput.getValue() << "]";
73   CS.flush();
74   return Comment;
75 }
76 
77 /// Returns string representation of scheduler comment
78 std::string TargetSubtargetInfo::getSchedInfoStr(const MachineInstr &MI) const {
79   if (MI.isPseudo() || MI.isTerminator())
80     return std::string();
81   // We don't cache TSchedModel because it depends on TargetInstrInfo
82   // that could be changed during the compilation
83   TargetSchedModel TSchedModel;
84   TSchedModel.init(getSchedModel(), this, getInstrInfo());
85   unsigned Latency = TSchedModel.computeInstrLatency(&MI);
86   Optional<double> RThroughput = TSchedModel.computeInstrRThroughput(&MI);
87   return createSchedInfoStr(Latency, RThroughput);
88 }
89 
90 /// Returns string representation of scheduler comment
91 std::string TargetSubtargetInfo::getSchedInfoStr(MCInst const &MCI) const {
92   // We don't cache TSchedModel because it depends on TargetInstrInfo
93   // that could be changed during the compilation
94   TargetSchedModel TSchedModel;
95   TSchedModel.init(getSchedModel(), this, getInstrInfo());
96   if (!TSchedModel.hasInstrSchedModel())
97     return std::string();
98   unsigned Latency = TSchedModel.computeInstrLatency(MCI.getOpcode());
99   Optional<double> RThroughput =
100       TSchedModel.computeInstrRThroughput(MCI.getOpcode());
101   return createSchedInfoStr(Latency, RThroughput);
102 }
103