1 //===- llvm/Target/TargetSchedule.cpp - Sched Machine Model ---------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements a wrapper around MCSchedModel that allows the interface
11 // to benefit from information currently only available in TargetInstrInfo.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "llvm/CodeGen/TargetSchedule.h"
16 #include "llvm/CodeGen/MachineFunction.h"
17 #include "llvm/CodeGen/MachineInstr.h"
18 #include "llvm/CodeGen/MachineOperand.h"
19 #include "llvm/CodeGen/TargetInstrInfo.h"
20 #include "llvm/CodeGen/TargetRegisterInfo.h"
21 #include "llvm/CodeGen/TargetSubtargetInfo.h"
22 #include "llvm/MC/MCInstrDesc.h"
23 #include "llvm/MC/MCInstrItineraries.h"
24 #include "llvm/MC/MCSchedule.h"
25 #include "llvm/Support/CommandLine.h"
26 #include "llvm/Support/ErrorHandling.h"
27 #include "llvm/Support/raw_ostream.h"
28 #include <algorithm>
29 #include <cassert>
30 #include <cstdint>
31 
32 using namespace llvm;
33 
34 static cl::opt<bool> EnableSchedModel("schedmodel", cl::Hidden, cl::init(true),
35   cl::desc("Use TargetSchedModel for latency lookup"));
36 
37 static cl::opt<bool> EnableSchedItins("scheditins", cl::Hidden, cl::init(true),
38   cl::desc("Use InstrItineraryData for latency lookup"));
39 
40 bool TargetSchedModel::hasInstrSchedModel() const {
41   return EnableSchedModel && SchedModel.hasInstrSchedModel();
42 }
43 
44 bool TargetSchedModel::hasInstrItineraries() const {
45   return EnableSchedItins && !InstrItins.isEmpty();
46 }
47 
48 static unsigned gcd(unsigned Dividend, unsigned Divisor) {
49   // Dividend and Divisor will be naturally swapped as needed.
50   while (Divisor) {
51     unsigned Rem = Dividend % Divisor;
52     Dividend = Divisor;
53     Divisor = Rem;
54   };
55   return Dividend;
56 }
57 
58 static unsigned lcm(unsigned A, unsigned B) {
59   unsigned LCM = (uint64_t(A) * B) / gcd(A, B);
60   assert((LCM >= A && LCM >= B) && "LCM overflow");
61   return LCM;
62 }
63 
64 void TargetSchedModel::init(const TargetSubtargetInfo *TSInfo) {
65   STI = TSInfo;
66   SchedModel = TSInfo->getSchedModel();
67   TII = TSInfo->getInstrInfo();
68   STI->initInstrItins(InstrItins);
69 
70   unsigned NumRes = SchedModel.getNumProcResourceKinds();
71   ResourceFactors.resize(NumRes);
72   ResourceLCM = SchedModel.IssueWidth;
73   for (unsigned Idx = 0; Idx < NumRes; ++Idx) {
74     unsigned NumUnits = SchedModel.getProcResource(Idx)->NumUnits;
75     if (NumUnits > 0)
76       ResourceLCM = lcm(ResourceLCM, NumUnits);
77   }
78   MicroOpFactor = ResourceLCM / SchedModel.IssueWidth;
79   for (unsigned Idx = 0; Idx < NumRes; ++Idx) {
80     unsigned NumUnits = SchedModel.getProcResource(Idx)->NumUnits;
81     ResourceFactors[Idx] = NumUnits ? (ResourceLCM / NumUnits) : 0;
82   }
83 }
84 
85 /// Returns true only if instruction is specified as single issue.
86 bool TargetSchedModel::mustBeginGroup(const MachineInstr *MI,
87                                      const MCSchedClassDesc *SC) const {
88   if (hasInstrSchedModel()) {
89     if (!SC)
90       SC = resolveSchedClass(MI);
91     if (SC->isValid())
92       return SC->BeginGroup;
93   }
94   return false;
95 }
96 
97 bool TargetSchedModel::mustEndGroup(const MachineInstr *MI,
98                                      const MCSchedClassDesc *SC) const {
99   if (hasInstrSchedModel()) {
100     if (!SC)
101       SC = resolveSchedClass(MI);
102     if (SC->isValid())
103       return SC->EndGroup;
104   }
105   return false;
106 }
107 
108 unsigned TargetSchedModel::getNumMicroOps(const MachineInstr *MI,
109                                           const MCSchedClassDesc *SC) const {
110   if (hasInstrItineraries()) {
111     int UOps = InstrItins.getNumMicroOps(MI->getDesc().getSchedClass());
112     return (UOps >= 0) ? UOps : TII->getNumMicroOps(&InstrItins, *MI);
113   }
114   if (hasInstrSchedModel()) {
115     if (!SC)
116       SC = resolveSchedClass(MI);
117     if (SC->isValid())
118       return SC->NumMicroOps;
119   }
120   return MI->isTransient() ? 0 : 1;
121 }
122 
123 // The machine model may explicitly specify an invalid latency, which
124 // effectively means infinite latency. Since users of the TargetSchedule API
125 // don't know how to handle this, we convert it to a very large latency that is
126 // easy to distinguish when debugging the DAG but won't induce overflow.
127 static unsigned capLatency(int Cycles) {
128   return Cycles >= 0 ? Cycles : 1000;
129 }
130 
131 /// Return the MCSchedClassDesc for this instruction. Some SchedClasses require
132 /// evaluation of predicates that depend on instruction operands or flags.
133 const MCSchedClassDesc *TargetSchedModel::
134 resolveSchedClass(const MachineInstr *MI) const {
135   // Get the definition's scheduling class descriptor from this machine model.
136   unsigned SchedClass = MI->getDesc().getSchedClass();
137   const MCSchedClassDesc *SCDesc = SchedModel.getSchedClassDesc(SchedClass);
138   if (!SCDesc->isValid())
139     return SCDesc;
140 
141 #ifndef NDEBUG
142   unsigned NIter = 0;
143 #endif
144   while (SCDesc->isVariant()) {
145     assert(++NIter < 6 && "Variants are nested deeper than the magic number");
146 
147     SchedClass = STI->resolveSchedClass(SchedClass, MI, this);
148     SCDesc = SchedModel.getSchedClassDesc(SchedClass);
149   }
150   return SCDesc;
151 }
152 
153 /// Find the def index of this operand. This index maps to the machine model and
154 /// is independent of use operands. Def operands may be reordered with uses or
155 /// merged with uses without affecting the def index (e.g. before/after
156 /// regalloc). However, an instruction's def operands must never be reordered
157 /// with respect to each other.
158 static unsigned findDefIdx(const MachineInstr *MI, unsigned DefOperIdx) {
159   unsigned DefIdx = 0;
160   for (unsigned i = 0; i != DefOperIdx; ++i) {
161     const MachineOperand &MO = MI->getOperand(i);
162     if (MO.isReg() && MO.isDef())
163       ++DefIdx;
164   }
165   return DefIdx;
166 }
167 
168 /// Find the use index of this operand. This is independent of the instruction's
169 /// def operands.
170 ///
171 /// Note that uses are not determined by the operand's isUse property, which
172 /// is simply the inverse of isDef. Here we consider any readsReg operand to be
173 /// a "use". The machine model allows an operand to be both a Def and Use.
174 static unsigned findUseIdx(const MachineInstr *MI, unsigned UseOperIdx) {
175   unsigned UseIdx = 0;
176   for (unsigned i = 0; i != UseOperIdx; ++i) {
177     const MachineOperand &MO = MI->getOperand(i);
178     if (MO.isReg() && MO.readsReg() && !MO.isDef())
179       ++UseIdx;
180   }
181   return UseIdx;
182 }
183 
184 // Top-level API for clients that know the operand indices.
185 unsigned TargetSchedModel::computeOperandLatency(
186   const MachineInstr *DefMI, unsigned DefOperIdx,
187   const MachineInstr *UseMI, unsigned UseOperIdx) const {
188 
189   if (!hasInstrSchedModel() && !hasInstrItineraries())
190     return TII->defaultDefLatency(SchedModel, *DefMI);
191 
192   if (hasInstrItineraries()) {
193     int OperLatency = 0;
194     if (UseMI) {
195       OperLatency = TII->getOperandLatency(&InstrItins, *DefMI, DefOperIdx,
196                                            *UseMI, UseOperIdx);
197     }
198     else {
199       unsigned DefClass = DefMI->getDesc().getSchedClass();
200       OperLatency = InstrItins.getOperandCycle(DefClass, DefOperIdx);
201     }
202     if (OperLatency >= 0)
203       return OperLatency;
204 
205     // No operand latency was found.
206     unsigned InstrLatency = TII->getInstrLatency(&InstrItins, *DefMI);
207 
208     // Expected latency is the max of the stage latency and itinerary props.
209     // Rather than directly querying InstrItins stage latency, we call a TII
210     // hook to allow subtargets to specialize latency. This hook is only
211     // applicable to the InstrItins model. InstrSchedModel should model all
212     // special cases without TII hooks.
213     InstrLatency =
214         std::max(InstrLatency, TII->defaultDefLatency(SchedModel, *DefMI));
215     return InstrLatency;
216   }
217   // hasInstrSchedModel()
218   const MCSchedClassDesc *SCDesc = resolveSchedClass(DefMI);
219   unsigned DefIdx = findDefIdx(DefMI, DefOperIdx);
220   if (DefIdx < SCDesc->NumWriteLatencyEntries) {
221     // Lookup the definition's write latency in SubtargetInfo.
222     const MCWriteLatencyEntry *WLEntry =
223       STI->getWriteLatencyEntry(SCDesc, DefIdx);
224     unsigned WriteID = WLEntry->WriteResourceID;
225     unsigned Latency = capLatency(WLEntry->Cycles);
226     if (!UseMI)
227       return Latency;
228 
229     // Lookup the use's latency adjustment in SubtargetInfo.
230     const MCSchedClassDesc *UseDesc = resolveSchedClass(UseMI);
231     if (UseDesc->NumReadAdvanceEntries == 0)
232       return Latency;
233     unsigned UseIdx = findUseIdx(UseMI, UseOperIdx);
234     int Advance = STI->getReadAdvanceCycles(UseDesc, UseIdx, WriteID);
235     if (Advance > 0 && (unsigned)Advance > Latency) // unsigned wrap
236       return 0;
237     return Latency - Advance;
238   }
239   // If DefIdx does not exist in the model (e.g. implicit defs), then return
240   // unit latency (defaultDefLatency may be too conservative).
241 #ifndef NDEBUG
242   if (SCDesc->isValid() && !DefMI->getOperand(DefOperIdx).isImplicit()
243       && !DefMI->getDesc().OpInfo[DefOperIdx].isOptionalDef()
244       && SchedModel.isComplete()) {
245     errs() << "DefIdx " << DefIdx << " exceeds machine model writes for "
246            << *DefMI << " (Try with MCSchedModel.CompleteModel set to false)";
247     llvm_unreachable("incomplete machine model");
248   }
249 #endif
250   // FIXME: Automatically giving all implicit defs defaultDefLatency is
251   // undesirable. We should only do it for defs that are known to the MC
252   // desc like flags. Truly implicit defs should get 1 cycle latency.
253   return DefMI->isTransient() ? 0 : TII->defaultDefLatency(SchedModel, *DefMI);
254 }
255 
256 unsigned
257 TargetSchedModel::computeInstrLatency(const MCSchedClassDesc &SCDesc) const {
258   return capLatency(MCSchedModel::computeInstrLatency(*STI, SCDesc));
259 }
260 
261 unsigned TargetSchedModel::computeInstrLatency(unsigned Opcode) const {
262   assert(hasInstrSchedModel() && "Only call this function with a SchedModel");
263 
264   unsigned SCIdx = TII->get(Opcode).getSchedClass();
265   const MCSchedClassDesc *SCDesc = SchedModel.getSchedClassDesc(SCIdx);
266 
267   if (!SCDesc->isValid())
268     return 0;
269   if (!SCDesc->isVariant())
270     return computeInstrLatency(*SCDesc);
271 
272   llvm_unreachable("No MI sched latency");
273 }
274 
275 unsigned
276 TargetSchedModel::computeInstrLatency(const MachineInstr *MI,
277                                       bool UseDefaultDefLatency) const {
278   // For the itinerary model, fall back to the old subtarget hook.
279   // Allow subtargets to compute Bundle latencies outside the machine model.
280   if (hasInstrItineraries() || MI->isBundle() ||
281       (!hasInstrSchedModel() && !UseDefaultDefLatency))
282     return TII->getInstrLatency(&InstrItins, *MI);
283 
284   if (hasInstrSchedModel()) {
285     const MCSchedClassDesc *SCDesc = resolveSchedClass(MI);
286     if (SCDesc->isValid())
287       return computeInstrLatency(*SCDesc);
288   }
289   return TII->defaultDefLatency(SchedModel, *MI);
290 }
291 
292 unsigned TargetSchedModel::
293 computeOutputLatency(const MachineInstr *DefMI, unsigned DefOperIdx,
294                      const MachineInstr *DepMI) const {
295   if (!SchedModel.isOutOfOrder())
296     return 1;
297 
298   // Out-of-order processor can dispatch WAW dependencies in the same cycle.
299 
300   // Treat predication as a data dependency for out-of-order cpus. In-order
301   // cpus do not need to treat predicated writes specially.
302   //
303   // TODO: The following hack exists because predication passes do not
304   // correctly append imp-use operands, and readsReg() strangely returns false
305   // for predicated defs.
306   unsigned Reg = DefMI->getOperand(DefOperIdx).getReg();
307   const MachineFunction &MF = *DefMI->getMF();
308   const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
309   if (!DepMI->readsRegister(Reg, TRI) && TII->isPredicated(*DepMI))
310     return computeInstrLatency(DefMI);
311 
312   // If we have a per operand scheduling model, check if this def is writing
313   // an unbuffered resource. If so, it treated like an in-order cpu.
314   if (hasInstrSchedModel()) {
315     const MCSchedClassDesc *SCDesc = resolveSchedClass(DefMI);
316     if (SCDesc->isValid()) {
317       for (const MCWriteProcResEntry *PRI = STI->getWriteProcResBegin(SCDesc),
318              *PRE = STI->getWriteProcResEnd(SCDesc); PRI != PRE; ++PRI) {
319         if (!SchedModel.getProcResource(PRI->ProcResourceIdx)->BufferSize)
320           return 1;
321       }
322     }
323   }
324   return 0;
325 }
326 
327 static Optional<double>
328 getRThroughputFromItineraries(unsigned schedClass,
329                               const InstrItineraryData *IID){
330   Optional<double> Throughput;
331 
332   for (const InstrStage *IS = IID->beginStage(schedClass),
333                         *E = IID->endStage(schedClass);
334        IS != E; ++IS) {
335     if (IS->getCycles()) {
336       double Temp = countPopulation(IS->getUnits()) * 1.0 / IS->getCycles();
337       Throughput = Throughput.hasValue()
338                         ? std::min(Throughput.getValue(), Temp)
339                         : Temp;
340     }
341   }
342   if (Throughput.hasValue())
343     // We need reciprocal throughput that's why we return such value.
344     return 1 / Throughput.getValue();
345   return Throughput;
346 }
347 
348 Optional<double>
349 TargetSchedModel::computeInstrRThroughput(const MachineInstr *MI) const {
350   if (hasInstrItineraries())
351     return getRThroughputFromItineraries(MI->getDesc().getSchedClass(),
352                                          getInstrItineraries());
353   if (hasInstrSchedModel())
354     return MCSchedModel::getReciprocalThroughput(*STI, *resolveSchedClass(MI));
355   return Optional<double>();
356 }
357 
358 Optional<double>
359 TargetSchedModel::computeInstrRThroughput(unsigned Opcode) const {
360   unsigned SchedClass = TII->get(Opcode).getSchedClass();
361   if (hasInstrItineraries())
362     return getRThroughputFromItineraries(SchedClass, getInstrItineraries());
363   if (hasInstrSchedModel()) {
364     const MCSchedClassDesc &SCDesc = *SchedModel.getSchedClassDesc(SchedClass);
365     if (SCDesc.isValid() && !SCDesc.isVariant())
366       return MCSchedModel::getReciprocalThroughput(*STI, SCDesc);
367   }
368   return Optional<double>();
369 }
370