1 //==- TargetRegisterInfo.cpp - Target Register Information Implementation --==// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements the TargetRegisterInfo interface. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "llvm/ADT/ArrayRef.h" 15 #include "llvm/ADT/BitVector.h" 16 #include "llvm/ADT/STLExtras.h" 17 #include "llvm/CodeGen/MachineFrameInfo.h" 18 #include "llvm/CodeGen/MachineFunction.h" 19 #include "llvm/CodeGen/MachineRegisterInfo.h" 20 #include "llvm/CodeGen/MachineValueType.h" 21 #include "llvm/CodeGen/VirtRegMap.h" 22 #include "llvm/IR/Attributes.h" 23 #include "llvm/IR/Function.h" 24 #include "llvm/MC/MCRegisterInfo.h" 25 #include "llvm/Support/Compiler.h" 26 #include "llvm/Support/Debug.h" 27 #include "llvm/Support/MathExtras.h" 28 #include "llvm/Support/Printable.h" 29 #include "llvm/Support/raw_ostream.h" 30 #include "llvm/Target/TargetFrameLowering.h" 31 #include "llvm/Target/TargetRegisterInfo.h" 32 #include "llvm/Target/TargetSubtargetInfo.h" 33 #include <cassert> 34 #include <utility> 35 36 #define DEBUG_TYPE "target-reg-info" 37 38 using namespace llvm; 39 40 TargetRegisterInfo::TargetRegisterInfo(const TargetRegisterInfoDesc *ID, 41 regclass_iterator RCB, regclass_iterator RCE, 42 const char *const *SRINames, 43 const LaneBitmask *SRILaneMasks, 44 LaneBitmask SRICoveringLanes, 45 const RegClassInfo *const RCIs, 46 unsigned Mode) 47 : InfoDesc(ID), SubRegIndexNames(SRINames), 48 SubRegIndexLaneMasks(SRILaneMasks), 49 RegClassBegin(RCB), RegClassEnd(RCE), 50 CoveringLanes(SRICoveringLanes), 51 RCInfos(RCIs), HwMode(Mode) { 52 } 53 54 TargetRegisterInfo::~TargetRegisterInfo() = default; 55 56 void TargetRegisterInfo::markSuperRegs(BitVector &RegisterSet, unsigned Reg) 57 const { 58 for (MCSuperRegIterator AI(Reg, this, true); AI.isValid(); ++AI) 59 RegisterSet.set(*AI); 60 } 61 62 bool TargetRegisterInfo::checkAllSuperRegsMarked(const BitVector &RegisterSet, 63 ArrayRef<MCPhysReg> Exceptions) const { 64 // Check that all super registers of reserved regs are reserved as well. 65 BitVector Checked(getNumRegs()); 66 for (unsigned Reg : RegisterSet.set_bits()) { 67 if (Checked[Reg]) 68 continue; 69 for (MCSuperRegIterator SR(Reg, this); SR.isValid(); ++SR) { 70 if (!RegisterSet[*SR] && !is_contained(Exceptions, Reg)) { 71 dbgs() << "Error: Super register " << PrintReg(*SR, this) 72 << " of reserved register " << PrintReg(Reg, this) 73 << " is not reserved.\n"; 74 return false; 75 } 76 77 // We transitively check superregs. So we can remember this for later 78 // to avoid compiletime explosion in deep register hierarchies. 79 Checked.set(*SR); 80 } 81 } 82 return true; 83 } 84 85 namespace llvm { 86 87 Printable PrintReg(unsigned Reg, const TargetRegisterInfo *TRI, 88 unsigned SubIdx) { 89 return Printable([Reg, TRI, SubIdx](raw_ostream &OS) { 90 if (!Reg) 91 OS << "%noreg"; 92 else if (TargetRegisterInfo::isStackSlot(Reg)) 93 OS << "SS#" << TargetRegisterInfo::stackSlot2Index(Reg); 94 else if (TargetRegisterInfo::isVirtualRegister(Reg)) 95 OS << "%vreg" << TargetRegisterInfo::virtReg2Index(Reg); 96 else if (TRI && Reg < TRI->getNumRegs()) 97 OS << '%' << TRI->getName(Reg); 98 else 99 OS << "%physreg" << Reg; 100 if (SubIdx) { 101 if (TRI) 102 OS << ':' << TRI->getSubRegIndexName(SubIdx); 103 else 104 OS << ":sub(" << SubIdx << ')'; 105 } 106 }); 107 } 108 109 Printable PrintRegUnit(unsigned Unit, const TargetRegisterInfo *TRI) { 110 return Printable([Unit, TRI](raw_ostream &OS) { 111 // Generic printout when TRI is missing. 112 if (!TRI) { 113 OS << "Unit~" << Unit; 114 return; 115 } 116 117 // Check for invalid register units. 118 if (Unit >= TRI->getNumRegUnits()) { 119 OS << "BadUnit~" << Unit; 120 return; 121 } 122 123 // Normal units have at least one root. 124 MCRegUnitRootIterator Roots(Unit, TRI); 125 assert(Roots.isValid() && "Unit has no roots."); 126 OS << TRI->getName(*Roots); 127 for (++Roots; Roots.isValid(); ++Roots) 128 OS << '~' << TRI->getName(*Roots); 129 }); 130 } 131 132 Printable PrintVRegOrUnit(unsigned Unit, const TargetRegisterInfo *TRI) { 133 return Printable([Unit, TRI](raw_ostream &OS) { 134 if (TRI && TRI->isVirtualRegister(Unit)) { 135 OS << "%vreg" << TargetRegisterInfo::virtReg2Index(Unit); 136 } else { 137 OS << PrintRegUnit(Unit, TRI); 138 } 139 }); 140 } 141 142 } // end namespace llvm 143 144 /// getAllocatableClass - Return the maximal subclass of the given register 145 /// class that is alloctable, or NULL. 146 const TargetRegisterClass * 147 TargetRegisterInfo::getAllocatableClass(const TargetRegisterClass *RC) const { 148 if (!RC || RC->isAllocatable()) 149 return RC; 150 151 for (BitMaskClassIterator It(RC->getSubClassMask(), *this); It.isValid(); 152 ++It) { 153 const TargetRegisterClass *SubRC = getRegClass(It.getID()); 154 if (SubRC->isAllocatable()) 155 return SubRC; 156 } 157 return nullptr; 158 } 159 160 /// getMinimalPhysRegClass - Returns the Register Class of a physical 161 /// register of the given type, picking the most sub register class of 162 /// the right type that contains this physreg. 163 const TargetRegisterClass * 164 TargetRegisterInfo::getMinimalPhysRegClass(unsigned reg, MVT VT) const { 165 assert(isPhysicalRegister(reg) && "reg must be a physical register"); 166 167 // Pick the most sub register class of the right type that contains 168 // this physreg. 169 const TargetRegisterClass* BestRC = nullptr; 170 for (const TargetRegisterClass* RC : regclasses()) { 171 if ((VT == MVT::Other || isTypeLegalForClass(*RC, VT)) && 172 RC->contains(reg) && (!BestRC || BestRC->hasSubClass(RC))) 173 BestRC = RC; 174 } 175 176 assert(BestRC && "Couldn't find the register class"); 177 return BestRC; 178 } 179 180 /// getAllocatableSetForRC - Toggle the bits that represent allocatable 181 /// registers for the specific register class. 182 static void getAllocatableSetForRC(const MachineFunction &MF, 183 const TargetRegisterClass *RC, BitVector &R){ 184 assert(RC->isAllocatable() && "invalid for nonallocatable sets"); 185 ArrayRef<MCPhysReg> Order = RC->getRawAllocationOrder(MF); 186 for (unsigned i = 0; i != Order.size(); ++i) 187 R.set(Order[i]); 188 } 189 190 BitVector TargetRegisterInfo::getAllocatableSet(const MachineFunction &MF, 191 const TargetRegisterClass *RC) const { 192 BitVector Allocatable(getNumRegs()); 193 if (RC) { 194 // A register class with no allocatable subclass returns an empty set. 195 const TargetRegisterClass *SubClass = getAllocatableClass(RC); 196 if (SubClass) 197 getAllocatableSetForRC(MF, SubClass, Allocatable); 198 } else { 199 for (const TargetRegisterClass *C : regclasses()) 200 if (C->isAllocatable()) 201 getAllocatableSetForRC(MF, C, Allocatable); 202 } 203 204 // Mask out the reserved registers 205 BitVector Reserved = getReservedRegs(MF); 206 Allocatable &= Reserved.flip(); 207 208 return Allocatable; 209 } 210 211 static inline 212 const TargetRegisterClass *firstCommonClass(const uint32_t *A, 213 const uint32_t *B, 214 const TargetRegisterInfo *TRI, 215 const MVT::SimpleValueType SVT = 216 MVT::SimpleValueType::Any) { 217 const MVT VT(SVT); 218 for (unsigned I = 0, E = TRI->getNumRegClasses(); I < E; I += 32) 219 if (unsigned Common = *A++ & *B++) { 220 const TargetRegisterClass *RC = 221 TRI->getRegClass(I + countTrailingZeros(Common)); 222 if (SVT == MVT::SimpleValueType::Any || TRI->isTypeLegalForClass(*RC, VT)) 223 return RC; 224 } 225 return nullptr; 226 } 227 228 const TargetRegisterClass * 229 TargetRegisterInfo::getCommonSubClass(const TargetRegisterClass *A, 230 const TargetRegisterClass *B, 231 const MVT::SimpleValueType SVT) const { 232 // First take care of the trivial cases. 233 if (A == B) 234 return A; 235 if (!A || !B) 236 return nullptr; 237 238 // Register classes are ordered topologically, so the largest common 239 // sub-class it the common sub-class with the smallest ID. 240 return firstCommonClass(A->getSubClassMask(), B->getSubClassMask(), this, SVT); 241 } 242 243 const TargetRegisterClass * 244 TargetRegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A, 245 const TargetRegisterClass *B, 246 unsigned Idx) const { 247 assert(A && B && "Missing register class"); 248 assert(Idx && "Bad sub-register index"); 249 250 // Find Idx in the list of super-register indices. 251 for (SuperRegClassIterator RCI(B, this); RCI.isValid(); ++RCI) 252 if (RCI.getSubReg() == Idx) 253 // The bit mask contains all register classes that are projected into B 254 // by Idx. Find a class that is also a sub-class of A. 255 return firstCommonClass(RCI.getMask(), A->getSubClassMask(), this); 256 return nullptr; 257 } 258 259 const TargetRegisterClass *TargetRegisterInfo:: 260 getCommonSuperRegClass(const TargetRegisterClass *RCA, unsigned SubA, 261 const TargetRegisterClass *RCB, unsigned SubB, 262 unsigned &PreA, unsigned &PreB) const { 263 assert(RCA && SubA && RCB && SubB && "Invalid arguments"); 264 265 // Search all pairs of sub-register indices that project into RCA and RCB 266 // respectively. This is quadratic, but usually the sets are very small. On 267 // most targets like X86, there will only be a single sub-register index 268 // (e.g., sub_16bit projecting into GR16). 269 // 270 // The worst case is a register class like DPR on ARM. 271 // We have indices dsub_0..dsub_7 projecting into that class. 272 // 273 // It is very common that one register class is a sub-register of the other. 274 // Arrange for RCA to be the larger register so the answer will be found in 275 // the first iteration. This makes the search linear for the most common 276 // case. 277 const TargetRegisterClass *BestRC = nullptr; 278 unsigned *BestPreA = &PreA; 279 unsigned *BestPreB = &PreB; 280 if (getRegSizeInBits(*RCA) < getRegSizeInBits(*RCB)) { 281 std::swap(RCA, RCB); 282 std::swap(SubA, SubB); 283 std::swap(BestPreA, BestPreB); 284 } 285 286 // Also terminate the search one we have found a register class as small as 287 // RCA. 288 unsigned MinSize = getRegSizeInBits(*RCA); 289 290 for (SuperRegClassIterator IA(RCA, this, true); IA.isValid(); ++IA) { 291 unsigned FinalA = composeSubRegIndices(IA.getSubReg(), SubA); 292 for (SuperRegClassIterator IB(RCB, this, true); IB.isValid(); ++IB) { 293 // Check if a common super-register class exists for this index pair. 294 const TargetRegisterClass *RC = 295 firstCommonClass(IA.getMask(), IB.getMask(), this); 296 if (!RC || getRegSizeInBits(*RC) < MinSize) 297 continue; 298 299 // The indexes must compose identically: PreA+SubA == PreB+SubB. 300 unsigned FinalB = composeSubRegIndices(IB.getSubReg(), SubB); 301 if (FinalA != FinalB) 302 continue; 303 304 // Is RC a better candidate than BestRC? 305 if (BestRC && getRegSizeInBits(*RC) >= getRegSizeInBits(*BestRC)) 306 continue; 307 308 // Yes, RC is the smallest super-register seen so far. 309 BestRC = RC; 310 *BestPreA = IA.getSubReg(); 311 *BestPreB = IB.getSubReg(); 312 313 // Bail early if we reached MinSize. We won't find a better candidate. 314 if (getRegSizeInBits(*BestRC) == MinSize) 315 return BestRC; 316 } 317 } 318 return BestRC; 319 } 320 321 /// \brief Check if the registers defined by the pair (RegisterClass, SubReg) 322 /// share the same register file. 323 static bool shareSameRegisterFile(const TargetRegisterInfo &TRI, 324 const TargetRegisterClass *DefRC, 325 unsigned DefSubReg, 326 const TargetRegisterClass *SrcRC, 327 unsigned SrcSubReg) { 328 // Same register class. 329 if (DefRC == SrcRC) 330 return true; 331 332 // Both operands are sub registers. Check if they share a register class. 333 unsigned SrcIdx, DefIdx; 334 if (SrcSubReg && DefSubReg) { 335 return TRI.getCommonSuperRegClass(SrcRC, SrcSubReg, DefRC, DefSubReg, 336 SrcIdx, DefIdx) != nullptr; 337 } 338 339 // At most one of the register is a sub register, make it Src to avoid 340 // duplicating the test. 341 if (!SrcSubReg) { 342 std::swap(DefSubReg, SrcSubReg); 343 std::swap(DefRC, SrcRC); 344 } 345 346 // One of the register is a sub register, check if we can get a superclass. 347 if (SrcSubReg) 348 return TRI.getMatchingSuperRegClass(SrcRC, DefRC, SrcSubReg) != nullptr; 349 350 // Plain copy. 351 return TRI.getCommonSubClass(DefRC, SrcRC) != nullptr; 352 } 353 354 bool TargetRegisterInfo::shouldRewriteCopySrc(const TargetRegisterClass *DefRC, 355 unsigned DefSubReg, 356 const TargetRegisterClass *SrcRC, 357 unsigned SrcSubReg) const { 358 // If this source does not incur a cross register bank copy, use it. 359 return shareSameRegisterFile(*this, DefRC, DefSubReg, SrcRC, SrcSubReg); 360 } 361 362 // Compute target-independent register allocator hints to help eliminate copies. 363 void 364 TargetRegisterInfo::getRegAllocationHints(unsigned VirtReg, 365 ArrayRef<MCPhysReg> Order, 366 SmallVectorImpl<MCPhysReg> &Hints, 367 const MachineFunction &MF, 368 const VirtRegMap *VRM, 369 const LiveRegMatrix *Matrix) const { 370 const MachineRegisterInfo &MRI = MF.getRegInfo(); 371 std::pair<unsigned, unsigned> Hint = MRI.getRegAllocationHint(VirtReg); 372 373 // Hints with HintType != 0 were set by target-dependent code. 374 // Such targets must provide their own implementation of 375 // TRI::getRegAllocationHints to interpret those hint types. 376 assert(Hint.first == 0 && "Target must implement TRI::getRegAllocationHints"); 377 378 // Target-independent hints are either a physical or a virtual register. 379 unsigned Phys = Hint.second; 380 if (VRM && isVirtualRegister(Phys)) 381 Phys = VRM->getPhys(Phys); 382 383 // Check that Phys is a valid hint in VirtReg's register class. 384 if (!isPhysicalRegister(Phys)) 385 return; 386 if (MRI.isReserved(Phys)) 387 return; 388 // Check that Phys is in the allocation order. We shouldn't heed hints 389 // from VirtReg's register class if they aren't in the allocation order. The 390 // target probably has a reason for removing the register. 391 if (!is_contained(Order, Phys)) 392 return; 393 394 // All clear, tell the register allocator to prefer this register. 395 Hints.push_back(Phys); 396 } 397 398 bool TargetRegisterInfo::canRealignStack(const MachineFunction &MF) const { 399 return !MF.getFunction()->hasFnAttribute("no-realign-stack"); 400 } 401 402 bool TargetRegisterInfo::needsStackRealignment( 403 const MachineFunction &MF) const { 404 const MachineFrameInfo &MFI = MF.getFrameInfo(); 405 const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering(); 406 const Function *F = MF.getFunction(); 407 unsigned StackAlign = TFI->getStackAlignment(); 408 bool requiresRealignment = ((MFI.getMaxAlignment() > StackAlign) || 409 F->hasFnAttribute(Attribute::StackAlignment)); 410 if (MF.getFunction()->hasFnAttribute("stackrealign") || requiresRealignment) { 411 if (canRealignStack(MF)) 412 return true; 413 DEBUG(dbgs() << "Can't realign function's stack: " << F->getName() << "\n"); 414 } 415 return false; 416 } 417 418 bool TargetRegisterInfo::regmaskSubsetEqual(const uint32_t *mask0, 419 const uint32_t *mask1) const { 420 unsigned N = (getNumRegs()+31) / 32; 421 for (unsigned I = 0; I < N; ++I) 422 if ((mask0[I] & mask1[I]) != mask0[I]) 423 return false; 424 return true; 425 } 426 427 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) 428 LLVM_DUMP_METHOD 429 void TargetRegisterInfo::dumpReg(unsigned Reg, unsigned SubRegIndex, 430 const TargetRegisterInfo *TRI) { 431 dbgs() << PrintReg(Reg, TRI, SubRegIndex) << "\n"; 432 } 433 #endif 434