1 //===- TargetRegisterInfo.cpp - Target Register Information Implementation ===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the TargetRegisterInfo interface.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "llvm/ADT/BitVector.h"
15 #include "llvm/CodeGen/MachineFrameInfo.h"
16 #include "llvm/CodeGen/MachineFunction.h"
17 #include "llvm/CodeGen/MachineRegisterInfo.h"
18 #include "llvm/CodeGen/VirtRegMap.h"
19 #include "llvm/IR/Function.h"
20 #include "llvm/Support/Debug.h"
21 #include "llvm/Support/Format.h"
22 #include "llvm/Support/raw_ostream.h"
23 #include "llvm/Target/TargetFrameLowering.h"
24 #include "llvm/Target/TargetRegisterInfo.h"
25 
26 #define DEBUG_TYPE "target-reg-info"
27 
28 using namespace llvm;
29 
30 TargetRegisterInfo::TargetRegisterInfo(const TargetRegisterInfoDesc *ID,
31                              regclass_iterator RCB, regclass_iterator RCE,
32                              const char *const *SRINames,
33                              const unsigned *SRILaneMasks,
34                              unsigned SRICoveringLanes)
35   : InfoDesc(ID), SubRegIndexNames(SRINames),
36     SubRegIndexLaneMasks(SRILaneMasks),
37     RegClassBegin(RCB), RegClassEnd(RCE),
38     CoveringLanes(SRICoveringLanes) {
39 }
40 
41 TargetRegisterInfo::~TargetRegisterInfo() {}
42 
43 void PrintReg::print(raw_ostream &OS) const {
44   if (!Reg)
45     OS << "%noreg";
46   else if (TargetRegisterInfo::isStackSlot(Reg))
47     OS << "SS#" << TargetRegisterInfo::stackSlot2Index(Reg);
48   else if (TargetRegisterInfo::isVirtualRegister(Reg))
49     OS << "%vreg" << TargetRegisterInfo::virtReg2Index(Reg);
50   else if (TRI && Reg < TRI->getNumRegs())
51     OS << '%' << TRI->getName(Reg);
52   else
53     OS << "%physreg" << Reg;
54   if (SubIdx) {
55     if (TRI)
56       OS << ':' << TRI->getSubRegIndexName(SubIdx);
57     else
58       OS << ":sub(" << SubIdx << ')';
59   }
60 }
61 
62 void PrintRegUnit::print(raw_ostream &OS) const {
63   // Generic printout when TRI is missing.
64   if (!TRI) {
65     OS << "Unit~" << Unit;
66     return;
67   }
68 
69   // Check for invalid register units.
70   if (Unit >= TRI->getNumRegUnits()) {
71     OS << "BadUnit~" << Unit;
72     return;
73   }
74 
75   // Normal units have at least one root.
76   MCRegUnitRootIterator Roots(Unit, TRI);
77   assert(Roots.isValid() && "Unit has no roots.");
78   OS << TRI->getName(*Roots);
79   for (++Roots; Roots.isValid(); ++Roots)
80     OS << '~' << TRI->getName(*Roots);
81 }
82 
83 void PrintVRegOrUnit::print(raw_ostream &OS) const {
84   if (TRI && TRI->isVirtualRegister(Unit)) {
85     OS << "%vreg" << TargetRegisterInfo::virtReg2Index(Unit);
86     return;
87   }
88   PrintRegUnit::print(OS);
89 }
90 
91 void PrintLaneMask::print(raw_ostream &OS) const {
92   OS << format("%08X", LaneMask);
93 }
94 
95 /// getAllocatableClass - Return the maximal subclass of the given register
96 /// class that is alloctable, or NULL.
97 const TargetRegisterClass *
98 TargetRegisterInfo::getAllocatableClass(const TargetRegisterClass *RC) const {
99   if (!RC || RC->isAllocatable())
100     return RC;
101 
102   const unsigned *SubClass = RC->getSubClassMask();
103   for (unsigned Base = 0, BaseE = getNumRegClasses();
104        Base < BaseE; Base += 32) {
105     unsigned Idx = Base;
106     for (unsigned Mask = *SubClass++; Mask; Mask >>= 1) {
107       unsigned Offset = countTrailingZeros(Mask);
108       const TargetRegisterClass *SubRC = getRegClass(Idx + Offset);
109       if (SubRC->isAllocatable())
110         return SubRC;
111       Mask >>= Offset;
112       Idx += Offset + 1;
113     }
114   }
115   return nullptr;
116 }
117 
118 /// getMinimalPhysRegClass - Returns the Register Class of a physical
119 /// register of the given type, picking the most sub register class of
120 /// the right type that contains this physreg.
121 const TargetRegisterClass *
122 TargetRegisterInfo::getMinimalPhysRegClass(unsigned reg, MVT VT) const {
123   assert(isPhysicalRegister(reg) && "reg must be a physical register");
124 
125   // Pick the most sub register class of the right type that contains
126   // this physreg.
127   const TargetRegisterClass* BestRC = nullptr;
128   for (regclass_iterator I = regclass_begin(), E = regclass_end(); I != E; ++I){
129     const TargetRegisterClass* RC = *I;
130     if ((VT == MVT::Other || RC->hasType(VT)) && RC->contains(reg) &&
131         (!BestRC || BestRC->hasSubClass(RC)))
132       BestRC = RC;
133   }
134 
135   assert(BestRC && "Couldn't find the register class");
136   return BestRC;
137 }
138 
139 /// getAllocatableSetForRC - Toggle the bits that represent allocatable
140 /// registers for the specific register class.
141 static void getAllocatableSetForRC(const MachineFunction &MF,
142                                    const TargetRegisterClass *RC, BitVector &R){
143   assert(RC->isAllocatable() && "invalid for nonallocatable sets");
144   ArrayRef<MCPhysReg> Order = RC->getRawAllocationOrder(MF);
145   for (unsigned i = 0; i != Order.size(); ++i)
146     R.set(Order[i]);
147 }
148 
149 BitVector TargetRegisterInfo::getAllocatableSet(const MachineFunction &MF,
150                                           const TargetRegisterClass *RC) const {
151   BitVector Allocatable(getNumRegs());
152   if (RC) {
153     // A register class with no allocatable subclass returns an empty set.
154     const TargetRegisterClass *SubClass = getAllocatableClass(RC);
155     if (SubClass)
156       getAllocatableSetForRC(MF, SubClass, Allocatable);
157   } else {
158     for (TargetRegisterInfo::regclass_iterator I = regclass_begin(),
159          E = regclass_end(); I != E; ++I)
160       if ((*I)->isAllocatable())
161         getAllocatableSetForRC(MF, *I, Allocatable);
162   }
163 
164   // Mask out the reserved registers
165   BitVector Reserved = getReservedRegs(MF);
166   Allocatable &= Reserved.flip();
167 
168   return Allocatable;
169 }
170 
171 static inline
172 const TargetRegisterClass *firstCommonClass(const uint32_t *A,
173                                             const uint32_t *B,
174                                             const TargetRegisterInfo *TRI) {
175   for (unsigned I = 0, E = TRI->getNumRegClasses(); I < E; I += 32)
176     if (unsigned Common = *A++ & *B++)
177       return TRI->getRegClass(I + countTrailingZeros(Common));
178   return nullptr;
179 }
180 
181 const TargetRegisterClass *
182 TargetRegisterInfo::getCommonSubClass(const TargetRegisterClass *A,
183                                       const TargetRegisterClass *B) const {
184   // First take care of the trivial cases.
185   if (A == B)
186     return A;
187   if (!A || !B)
188     return nullptr;
189 
190   // Register classes are ordered topologically, so the largest common
191   // sub-class it the common sub-class with the smallest ID.
192   return firstCommonClass(A->getSubClassMask(), B->getSubClassMask(), this);
193 }
194 
195 const TargetRegisterClass *
196 TargetRegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
197                                              const TargetRegisterClass *B,
198                                              unsigned Idx) const {
199   assert(A && B && "Missing register class");
200   assert(Idx && "Bad sub-register index");
201 
202   // Find Idx in the list of super-register indices.
203   for (SuperRegClassIterator RCI(B, this); RCI.isValid(); ++RCI)
204     if (RCI.getSubReg() == Idx)
205       // The bit mask contains all register classes that are projected into B
206       // by Idx. Find a class that is also a sub-class of A.
207       return firstCommonClass(RCI.getMask(), A->getSubClassMask(), this);
208   return nullptr;
209 }
210 
211 const TargetRegisterClass *TargetRegisterInfo::
212 getCommonSuperRegClass(const TargetRegisterClass *RCA, unsigned SubA,
213                        const TargetRegisterClass *RCB, unsigned SubB,
214                        unsigned &PreA, unsigned &PreB) const {
215   assert(RCA && SubA && RCB && SubB && "Invalid arguments");
216 
217   // Search all pairs of sub-register indices that project into RCA and RCB
218   // respectively. This is quadratic, but usually the sets are very small. On
219   // most targets like X86, there will only be a single sub-register index
220   // (e.g., sub_16bit projecting into GR16).
221   //
222   // The worst case is a register class like DPR on ARM.
223   // We have indices dsub_0..dsub_7 projecting into that class.
224   //
225   // It is very common that one register class is a sub-register of the other.
226   // Arrange for RCA to be the larger register so the answer will be found in
227   // the first iteration. This makes the search linear for the most common
228   // case.
229   const TargetRegisterClass *BestRC = nullptr;
230   unsigned *BestPreA = &PreA;
231   unsigned *BestPreB = &PreB;
232   if (RCA->getSize() < RCB->getSize()) {
233     std::swap(RCA, RCB);
234     std::swap(SubA, SubB);
235     std::swap(BestPreA, BestPreB);
236   }
237 
238   // Also terminate the search one we have found a register class as small as
239   // RCA.
240   unsigned MinSize = RCA->getSize();
241 
242   for (SuperRegClassIterator IA(RCA, this, true); IA.isValid(); ++IA) {
243     unsigned FinalA = composeSubRegIndices(IA.getSubReg(), SubA);
244     for (SuperRegClassIterator IB(RCB, this, true); IB.isValid(); ++IB) {
245       // Check if a common super-register class exists for this index pair.
246       const TargetRegisterClass *RC =
247         firstCommonClass(IA.getMask(), IB.getMask(), this);
248       if (!RC || RC->getSize() < MinSize)
249         continue;
250 
251       // The indexes must compose identically: PreA+SubA == PreB+SubB.
252       unsigned FinalB = composeSubRegIndices(IB.getSubReg(), SubB);
253       if (FinalA != FinalB)
254         continue;
255 
256       // Is RC a better candidate than BestRC?
257       if (BestRC && RC->getSize() >= BestRC->getSize())
258         continue;
259 
260       // Yes, RC is the smallest super-register seen so far.
261       BestRC = RC;
262       *BestPreA = IA.getSubReg();
263       *BestPreB = IB.getSubReg();
264 
265       // Bail early if we reached MinSize. We won't find a better candidate.
266       if (BestRC->getSize() == MinSize)
267         return BestRC;
268     }
269   }
270   return BestRC;
271 }
272 
273 /// \brief Check if the registers defined by the pair (RegisterClass, SubReg)
274 /// share the same register file.
275 static bool shareSameRegisterFile(const TargetRegisterInfo &TRI,
276                                   const TargetRegisterClass *DefRC,
277                                   unsigned DefSubReg,
278                                   const TargetRegisterClass *SrcRC,
279                                   unsigned SrcSubReg) {
280   // Same register class.
281   if (DefRC == SrcRC)
282     return true;
283 
284   // Both operands are sub registers. Check if they share a register class.
285   unsigned SrcIdx, DefIdx;
286   if (SrcSubReg && DefSubReg) {
287     return TRI.getCommonSuperRegClass(SrcRC, SrcSubReg, DefRC, DefSubReg,
288                                       SrcIdx, DefIdx) != nullptr;
289   }
290 
291   // At most one of the register is a sub register, make it Src to avoid
292   // duplicating the test.
293   if (!SrcSubReg) {
294     std::swap(DefSubReg, SrcSubReg);
295     std::swap(DefRC, SrcRC);
296   }
297 
298   // One of the register is a sub register, check if we can get a superclass.
299   if (SrcSubReg)
300     return TRI.getMatchingSuperRegClass(SrcRC, DefRC, SrcSubReg) != nullptr;
301 
302   // Plain copy.
303   return TRI.getCommonSubClass(DefRC, SrcRC) != nullptr;
304 }
305 
306 bool TargetRegisterInfo::shouldRewriteCopySrc(const TargetRegisterClass *DefRC,
307                                               unsigned DefSubReg,
308                                               const TargetRegisterClass *SrcRC,
309                                               unsigned SrcSubReg) const {
310   // If this source does not incur a cross register bank copy, use it.
311   return shareSameRegisterFile(*this, DefRC, DefSubReg, SrcRC, SrcSubReg);
312 }
313 
314 // Compute target-independent register allocator hints to help eliminate copies.
315 void
316 TargetRegisterInfo::getRegAllocationHints(unsigned VirtReg,
317                                           ArrayRef<MCPhysReg> Order,
318                                           SmallVectorImpl<MCPhysReg> &Hints,
319                                           const MachineFunction &MF,
320                                           const VirtRegMap *VRM,
321                                           const LiveRegMatrix *Matrix) const {
322   const MachineRegisterInfo &MRI = MF.getRegInfo();
323   std::pair<unsigned, unsigned> Hint = MRI.getRegAllocationHint(VirtReg);
324 
325   // Hints with HintType != 0 were set by target-dependent code.
326   // Such targets must provide their own implementation of
327   // TRI::getRegAllocationHints to interpret those hint types.
328   assert(Hint.first == 0 && "Target must implement TRI::getRegAllocationHints");
329 
330   // Target-independent hints are either a physical or a virtual register.
331   unsigned Phys = Hint.second;
332   if (VRM && isVirtualRegister(Phys))
333     Phys = VRM->getPhys(Phys);
334 
335   // Check that Phys is a valid hint in VirtReg's register class.
336   if (!isPhysicalRegister(Phys))
337     return;
338   if (MRI.isReserved(Phys))
339     return;
340   // Check that Phys is in the allocation order. We shouldn't heed hints
341   // from VirtReg's register class if they aren't in the allocation order. The
342   // target probably has a reason for removing the register.
343   if (std::find(Order.begin(), Order.end(), Phys) == Order.end())
344     return;
345 
346   // All clear, tell the register allocator to prefer this register.
347   Hints.push_back(Phys);
348 }
349 
350 bool TargetRegisterInfo::canRealignStack(const MachineFunction &MF) const {
351   return !MF.getFunction()->hasFnAttribute("no-realign-stack");
352 }
353 
354 bool TargetRegisterInfo::needsStackRealignment(
355     const MachineFunction &MF) const {
356   const MachineFrameInfo *MFI = MF.getFrameInfo();
357   const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
358   const Function *F = MF.getFunction();
359   unsigned StackAlign = TFI->getStackAlignment();
360   bool requiresRealignment = ((MFI->getMaxAlignment() > StackAlign) ||
361                               F->hasFnAttribute(Attribute::StackAlignment));
362   if (MF.getFunction()->hasFnAttribute("stackrealign") || requiresRealignment) {
363     if (canRealignStack(MF))
364       return true;
365     DEBUG(dbgs() << "Can't realign function's stack: " << F->getName() << "\n");
366   }
367   return false;
368 }
369 
370 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
371 void
372 TargetRegisterInfo::dumpReg(unsigned Reg, unsigned SubRegIndex,
373                             const TargetRegisterInfo *TRI) {
374   dbgs() << PrintReg(Reg, TRI, SubRegIndex) << "\n";
375 }
376 #endif
377