1 //===-- TargetLoweringBase.cpp - Implement the TargetLoweringBase class ---===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This implements the TargetLoweringBase class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "llvm/Target/TargetLowering.h" 15 #include "llvm/ADT/BitVector.h" 16 #include "llvm/ADT/STLExtras.h" 17 #include "llvm/ADT/Triple.h" 18 #include "llvm/CodeGen/Analysis.h" 19 #include "llvm/CodeGen/MachineFrameInfo.h" 20 #include "llvm/CodeGen/MachineFunction.h" 21 #include "llvm/CodeGen/MachineInstrBuilder.h" 22 #include "llvm/CodeGen/MachineJumpTableInfo.h" 23 #include "llvm/CodeGen/StackMaps.h" 24 #include "llvm/IR/DataLayout.h" 25 #include "llvm/IR/DerivedTypes.h" 26 #include "llvm/IR/GlobalVariable.h" 27 #include "llvm/IR/Mangler.h" 28 #include "llvm/MC/MCAsmInfo.h" 29 #include "llvm/MC/MCContext.h" 30 #include "llvm/MC/MCExpr.h" 31 #include "llvm/Support/CommandLine.h" 32 #include "llvm/Support/ErrorHandling.h" 33 #include "llvm/Support/MathExtras.h" 34 #include "llvm/Target/TargetLoweringObjectFile.h" 35 #include "llvm/Target/TargetMachine.h" 36 #include "llvm/Target/TargetRegisterInfo.h" 37 #include "llvm/Target/TargetSubtargetInfo.h" 38 #include <cctype> 39 using namespace llvm; 40 41 static cl::opt<bool> JumpIsExpensiveOverride( 42 "jump-is-expensive", cl::init(false), 43 cl::desc("Do not create extra branches to split comparison logic."), 44 cl::Hidden); 45 46 /// InitLibcallNames - Set default libcall names. 47 /// 48 static void InitLibcallNames(const char **Names, const Triple &TT) { 49 Names[RTLIB::SHL_I16] = "__ashlhi3"; 50 Names[RTLIB::SHL_I32] = "__ashlsi3"; 51 Names[RTLIB::SHL_I64] = "__ashldi3"; 52 Names[RTLIB::SHL_I128] = "__ashlti3"; 53 Names[RTLIB::SRL_I16] = "__lshrhi3"; 54 Names[RTLIB::SRL_I32] = "__lshrsi3"; 55 Names[RTLIB::SRL_I64] = "__lshrdi3"; 56 Names[RTLIB::SRL_I128] = "__lshrti3"; 57 Names[RTLIB::SRA_I16] = "__ashrhi3"; 58 Names[RTLIB::SRA_I32] = "__ashrsi3"; 59 Names[RTLIB::SRA_I64] = "__ashrdi3"; 60 Names[RTLIB::SRA_I128] = "__ashrti3"; 61 Names[RTLIB::MUL_I8] = "__mulqi3"; 62 Names[RTLIB::MUL_I16] = "__mulhi3"; 63 Names[RTLIB::MUL_I32] = "__mulsi3"; 64 Names[RTLIB::MUL_I64] = "__muldi3"; 65 Names[RTLIB::MUL_I128] = "__multi3"; 66 Names[RTLIB::MULO_I32] = "__mulosi4"; 67 Names[RTLIB::MULO_I64] = "__mulodi4"; 68 Names[RTLIB::MULO_I128] = "__muloti4"; 69 Names[RTLIB::SDIV_I8] = "__divqi3"; 70 Names[RTLIB::SDIV_I16] = "__divhi3"; 71 Names[RTLIB::SDIV_I32] = "__divsi3"; 72 Names[RTLIB::SDIV_I64] = "__divdi3"; 73 Names[RTLIB::SDIV_I128] = "__divti3"; 74 Names[RTLIB::UDIV_I8] = "__udivqi3"; 75 Names[RTLIB::UDIV_I16] = "__udivhi3"; 76 Names[RTLIB::UDIV_I32] = "__udivsi3"; 77 Names[RTLIB::UDIV_I64] = "__udivdi3"; 78 Names[RTLIB::UDIV_I128] = "__udivti3"; 79 Names[RTLIB::SREM_I8] = "__modqi3"; 80 Names[RTLIB::SREM_I16] = "__modhi3"; 81 Names[RTLIB::SREM_I32] = "__modsi3"; 82 Names[RTLIB::SREM_I64] = "__moddi3"; 83 Names[RTLIB::SREM_I128] = "__modti3"; 84 Names[RTLIB::UREM_I8] = "__umodqi3"; 85 Names[RTLIB::UREM_I16] = "__umodhi3"; 86 Names[RTLIB::UREM_I32] = "__umodsi3"; 87 Names[RTLIB::UREM_I64] = "__umoddi3"; 88 Names[RTLIB::UREM_I128] = "__umodti3"; 89 90 // These are generally not available. 91 Names[RTLIB::SDIVREM_I8] = nullptr; 92 Names[RTLIB::SDIVREM_I16] = nullptr; 93 Names[RTLIB::SDIVREM_I32] = nullptr; 94 Names[RTLIB::SDIVREM_I64] = nullptr; 95 Names[RTLIB::SDIVREM_I128] = nullptr; 96 Names[RTLIB::UDIVREM_I8] = nullptr; 97 Names[RTLIB::UDIVREM_I16] = nullptr; 98 Names[RTLIB::UDIVREM_I32] = nullptr; 99 Names[RTLIB::UDIVREM_I64] = nullptr; 100 Names[RTLIB::UDIVREM_I128] = nullptr; 101 102 Names[RTLIB::NEG_I32] = "__negsi2"; 103 Names[RTLIB::NEG_I64] = "__negdi2"; 104 Names[RTLIB::ADD_F32] = "__addsf3"; 105 Names[RTLIB::ADD_F64] = "__adddf3"; 106 Names[RTLIB::ADD_F80] = "__addxf3"; 107 Names[RTLIB::ADD_F128] = "__addtf3"; 108 Names[RTLIB::ADD_PPCF128] = "__gcc_qadd"; 109 Names[RTLIB::SUB_F32] = "__subsf3"; 110 Names[RTLIB::SUB_F64] = "__subdf3"; 111 Names[RTLIB::SUB_F80] = "__subxf3"; 112 Names[RTLIB::SUB_F128] = "__subtf3"; 113 Names[RTLIB::SUB_PPCF128] = "__gcc_qsub"; 114 Names[RTLIB::MUL_F32] = "__mulsf3"; 115 Names[RTLIB::MUL_F64] = "__muldf3"; 116 Names[RTLIB::MUL_F80] = "__mulxf3"; 117 Names[RTLIB::MUL_F128] = "__multf3"; 118 Names[RTLIB::MUL_PPCF128] = "__gcc_qmul"; 119 Names[RTLIB::DIV_F32] = "__divsf3"; 120 Names[RTLIB::DIV_F64] = "__divdf3"; 121 Names[RTLIB::DIV_F80] = "__divxf3"; 122 Names[RTLIB::DIV_F128] = "__divtf3"; 123 Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv"; 124 Names[RTLIB::REM_F32] = "fmodf"; 125 Names[RTLIB::REM_F64] = "fmod"; 126 Names[RTLIB::REM_F80] = "fmodl"; 127 Names[RTLIB::REM_F128] = "fmodl"; 128 Names[RTLIB::REM_PPCF128] = "fmodl"; 129 Names[RTLIB::FMA_F32] = "fmaf"; 130 Names[RTLIB::FMA_F64] = "fma"; 131 Names[RTLIB::FMA_F80] = "fmal"; 132 Names[RTLIB::FMA_F128] = "fmal"; 133 Names[RTLIB::FMA_PPCF128] = "fmal"; 134 Names[RTLIB::POWI_F32] = "__powisf2"; 135 Names[RTLIB::POWI_F64] = "__powidf2"; 136 Names[RTLIB::POWI_F80] = "__powixf2"; 137 Names[RTLIB::POWI_F128] = "__powitf2"; 138 Names[RTLIB::POWI_PPCF128] = "__powitf2"; 139 Names[RTLIB::SQRT_F32] = "sqrtf"; 140 Names[RTLIB::SQRT_F64] = "sqrt"; 141 Names[RTLIB::SQRT_F80] = "sqrtl"; 142 Names[RTLIB::SQRT_F128] = "sqrtl"; 143 Names[RTLIB::SQRT_PPCF128] = "sqrtl"; 144 Names[RTLIB::LOG_F32] = "logf"; 145 Names[RTLIB::LOG_F64] = "log"; 146 Names[RTLIB::LOG_F80] = "logl"; 147 Names[RTLIB::LOG_F128] = "logl"; 148 Names[RTLIB::LOG_PPCF128] = "logl"; 149 Names[RTLIB::LOG2_F32] = "log2f"; 150 Names[RTLIB::LOG2_F64] = "log2"; 151 Names[RTLIB::LOG2_F80] = "log2l"; 152 Names[RTLIB::LOG2_F128] = "log2l"; 153 Names[RTLIB::LOG2_PPCF128] = "log2l"; 154 Names[RTLIB::LOG10_F32] = "log10f"; 155 Names[RTLIB::LOG10_F64] = "log10"; 156 Names[RTLIB::LOG10_F80] = "log10l"; 157 Names[RTLIB::LOG10_F128] = "log10l"; 158 Names[RTLIB::LOG10_PPCF128] = "log10l"; 159 Names[RTLIB::EXP_F32] = "expf"; 160 Names[RTLIB::EXP_F64] = "exp"; 161 Names[RTLIB::EXP_F80] = "expl"; 162 Names[RTLIB::EXP_F128] = "expl"; 163 Names[RTLIB::EXP_PPCF128] = "expl"; 164 Names[RTLIB::EXP2_F32] = "exp2f"; 165 Names[RTLIB::EXP2_F64] = "exp2"; 166 Names[RTLIB::EXP2_F80] = "exp2l"; 167 Names[RTLIB::EXP2_F128] = "exp2l"; 168 Names[RTLIB::EXP2_PPCF128] = "exp2l"; 169 Names[RTLIB::SIN_F32] = "sinf"; 170 Names[RTLIB::SIN_F64] = "sin"; 171 Names[RTLIB::SIN_F80] = "sinl"; 172 Names[RTLIB::SIN_F128] = "sinl"; 173 Names[RTLIB::SIN_PPCF128] = "sinl"; 174 Names[RTLIB::COS_F32] = "cosf"; 175 Names[RTLIB::COS_F64] = "cos"; 176 Names[RTLIB::COS_F80] = "cosl"; 177 Names[RTLIB::COS_F128] = "cosl"; 178 Names[RTLIB::COS_PPCF128] = "cosl"; 179 Names[RTLIB::POW_F32] = "powf"; 180 Names[RTLIB::POW_F64] = "pow"; 181 Names[RTLIB::POW_F80] = "powl"; 182 Names[RTLIB::POW_F128] = "powl"; 183 Names[RTLIB::POW_PPCF128] = "powl"; 184 Names[RTLIB::CEIL_F32] = "ceilf"; 185 Names[RTLIB::CEIL_F64] = "ceil"; 186 Names[RTLIB::CEIL_F80] = "ceill"; 187 Names[RTLIB::CEIL_F128] = "ceill"; 188 Names[RTLIB::CEIL_PPCF128] = "ceill"; 189 Names[RTLIB::TRUNC_F32] = "truncf"; 190 Names[RTLIB::TRUNC_F64] = "trunc"; 191 Names[RTLIB::TRUNC_F80] = "truncl"; 192 Names[RTLIB::TRUNC_F128] = "truncl"; 193 Names[RTLIB::TRUNC_PPCF128] = "truncl"; 194 Names[RTLIB::RINT_F32] = "rintf"; 195 Names[RTLIB::RINT_F64] = "rint"; 196 Names[RTLIB::RINT_F80] = "rintl"; 197 Names[RTLIB::RINT_F128] = "rintl"; 198 Names[RTLIB::RINT_PPCF128] = "rintl"; 199 Names[RTLIB::NEARBYINT_F32] = "nearbyintf"; 200 Names[RTLIB::NEARBYINT_F64] = "nearbyint"; 201 Names[RTLIB::NEARBYINT_F80] = "nearbyintl"; 202 Names[RTLIB::NEARBYINT_F128] = "nearbyintl"; 203 Names[RTLIB::NEARBYINT_PPCF128] = "nearbyintl"; 204 Names[RTLIB::ROUND_F32] = "roundf"; 205 Names[RTLIB::ROUND_F64] = "round"; 206 Names[RTLIB::ROUND_F80] = "roundl"; 207 Names[RTLIB::ROUND_F128] = "roundl"; 208 Names[RTLIB::ROUND_PPCF128] = "roundl"; 209 Names[RTLIB::FLOOR_F32] = "floorf"; 210 Names[RTLIB::FLOOR_F64] = "floor"; 211 Names[RTLIB::FLOOR_F80] = "floorl"; 212 Names[RTLIB::FLOOR_F128] = "floorl"; 213 Names[RTLIB::FLOOR_PPCF128] = "floorl"; 214 Names[RTLIB::FMIN_F32] = "fminf"; 215 Names[RTLIB::FMIN_F64] = "fmin"; 216 Names[RTLIB::FMIN_F80] = "fminl"; 217 Names[RTLIB::FMIN_F128] = "fminl"; 218 Names[RTLIB::FMIN_PPCF128] = "fminl"; 219 Names[RTLIB::FMAX_F32] = "fmaxf"; 220 Names[RTLIB::FMAX_F64] = "fmax"; 221 Names[RTLIB::FMAX_F80] = "fmaxl"; 222 Names[RTLIB::FMAX_F128] = "fmaxl"; 223 Names[RTLIB::FMAX_PPCF128] = "fmaxl"; 224 Names[RTLIB::ROUND_F32] = "roundf"; 225 Names[RTLIB::ROUND_F64] = "round"; 226 Names[RTLIB::ROUND_F80] = "roundl"; 227 Names[RTLIB::ROUND_F128] = "roundl"; 228 Names[RTLIB::ROUND_PPCF128] = "roundl"; 229 Names[RTLIB::COPYSIGN_F32] = "copysignf"; 230 Names[RTLIB::COPYSIGN_F64] = "copysign"; 231 Names[RTLIB::COPYSIGN_F80] = "copysignl"; 232 Names[RTLIB::COPYSIGN_F128] = "copysignl"; 233 Names[RTLIB::COPYSIGN_PPCF128] = "copysignl"; 234 Names[RTLIB::FPEXT_F32_PPCF128] = "__gcc_stoq"; 235 Names[RTLIB::FPEXT_F64_PPCF128] = "__gcc_dtoq"; 236 Names[RTLIB::FPEXT_F64_F128] = "__extenddftf2"; 237 Names[RTLIB::FPEXT_F32_F128] = "__extendsftf2"; 238 Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2"; 239 Names[RTLIB::FPEXT_F16_F32] = "__gnu_h2f_ieee"; 240 Names[RTLIB::FPROUND_F32_F16] = "__gnu_f2h_ieee"; 241 Names[RTLIB::FPROUND_F64_F16] = "__truncdfhf2"; 242 Names[RTLIB::FPROUND_F80_F16] = "__truncxfhf2"; 243 Names[RTLIB::FPROUND_F128_F16] = "__trunctfhf2"; 244 Names[RTLIB::FPROUND_PPCF128_F16] = "__trunctfhf2"; 245 Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2"; 246 Names[RTLIB::FPROUND_F80_F32] = "__truncxfsf2"; 247 Names[RTLIB::FPROUND_F128_F32] = "__trunctfsf2"; 248 Names[RTLIB::FPROUND_PPCF128_F32] = "__gcc_qtos"; 249 Names[RTLIB::FPROUND_F80_F64] = "__truncxfdf2"; 250 Names[RTLIB::FPROUND_F128_F64] = "__trunctfdf2"; 251 Names[RTLIB::FPROUND_PPCF128_F64] = "__gcc_qtod"; 252 Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi"; 253 Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi"; 254 Names[RTLIB::FPTOSINT_F32_I128] = "__fixsfti"; 255 Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi"; 256 Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi"; 257 Names[RTLIB::FPTOSINT_F64_I128] = "__fixdfti"; 258 Names[RTLIB::FPTOSINT_F80_I32] = "__fixxfsi"; 259 Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi"; 260 Names[RTLIB::FPTOSINT_F80_I128] = "__fixxfti"; 261 Names[RTLIB::FPTOSINT_F128_I32] = "__fixtfsi"; 262 Names[RTLIB::FPTOSINT_F128_I64] = "__fixtfdi"; 263 Names[RTLIB::FPTOSINT_F128_I128] = "__fixtfti"; 264 Names[RTLIB::FPTOSINT_PPCF128_I32] = "__gcc_qtou"; 265 Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi"; 266 Names[RTLIB::FPTOSINT_PPCF128_I128] = "__fixtfti"; 267 Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi"; 268 Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi"; 269 Names[RTLIB::FPTOUINT_F32_I128] = "__fixunssfti"; 270 Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi"; 271 Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi"; 272 Names[RTLIB::FPTOUINT_F64_I128] = "__fixunsdfti"; 273 Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi"; 274 Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi"; 275 Names[RTLIB::FPTOUINT_F80_I128] = "__fixunsxfti"; 276 Names[RTLIB::FPTOUINT_F128_I32] = "__fixunstfsi"; 277 Names[RTLIB::FPTOUINT_F128_I64] = "__fixunstfdi"; 278 Names[RTLIB::FPTOUINT_F128_I128] = "__fixunstfti"; 279 Names[RTLIB::FPTOUINT_PPCF128_I32] = "__fixunstfsi"; 280 Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi"; 281 Names[RTLIB::FPTOUINT_PPCF128_I128] = "__fixunstfti"; 282 Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf"; 283 Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf"; 284 Names[RTLIB::SINTTOFP_I32_F80] = "__floatsixf"; 285 Names[RTLIB::SINTTOFP_I32_F128] = "__floatsitf"; 286 Names[RTLIB::SINTTOFP_I32_PPCF128] = "__gcc_itoq"; 287 Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf"; 288 Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf"; 289 Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf"; 290 Names[RTLIB::SINTTOFP_I64_F128] = "__floatditf"; 291 Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf"; 292 Names[RTLIB::SINTTOFP_I128_F32] = "__floattisf"; 293 Names[RTLIB::SINTTOFP_I128_F64] = "__floattidf"; 294 Names[RTLIB::SINTTOFP_I128_F80] = "__floattixf"; 295 Names[RTLIB::SINTTOFP_I128_F128] = "__floattitf"; 296 Names[RTLIB::SINTTOFP_I128_PPCF128] = "__floattitf"; 297 Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf"; 298 Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf"; 299 Names[RTLIB::UINTTOFP_I32_F80] = "__floatunsixf"; 300 Names[RTLIB::UINTTOFP_I32_F128] = "__floatunsitf"; 301 Names[RTLIB::UINTTOFP_I32_PPCF128] = "__gcc_utoq"; 302 Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf"; 303 Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf"; 304 Names[RTLIB::UINTTOFP_I64_F80] = "__floatundixf"; 305 Names[RTLIB::UINTTOFP_I64_F128] = "__floatunditf"; 306 Names[RTLIB::UINTTOFP_I64_PPCF128] = "__floatunditf"; 307 Names[RTLIB::UINTTOFP_I128_F32] = "__floatuntisf"; 308 Names[RTLIB::UINTTOFP_I128_F64] = "__floatuntidf"; 309 Names[RTLIB::UINTTOFP_I128_F80] = "__floatuntixf"; 310 Names[RTLIB::UINTTOFP_I128_F128] = "__floatuntitf"; 311 Names[RTLIB::UINTTOFP_I128_PPCF128] = "__floatuntitf"; 312 Names[RTLIB::OEQ_F32] = "__eqsf2"; 313 Names[RTLIB::OEQ_F64] = "__eqdf2"; 314 Names[RTLIB::OEQ_F128] = "__eqtf2"; 315 Names[RTLIB::OEQ_PPCF128] = "__gcc_qeq"; 316 Names[RTLIB::UNE_F32] = "__nesf2"; 317 Names[RTLIB::UNE_F64] = "__nedf2"; 318 Names[RTLIB::UNE_F128] = "__netf2"; 319 Names[RTLIB::UNE_PPCF128] = "__gcc_qne"; 320 Names[RTLIB::OGE_F32] = "__gesf2"; 321 Names[RTLIB::OGE_F64] = "__gedf2"; 322 Names[RTLIB::OGE_F128] = "__getf2"; 323 Names[RTLIB::OGE_PPCF128] = "__gcc_qge"; 324 Names[RTLIB::OLT_F32] = "__ltsf2"; 325 Names[RTLIB::OLT_F64] = "__ltdf2"; 326 Names[RTLIB::OLT_F128] = "__lttf2"; 327 Names[RTLIB::OLT_PPCF128] = "__gcc_qlt"; 328 Names[RTLIB::OLE_F32] = "__lesf2"; 329 Names[RTLIB::OLE_F64] = "__ledf2"; 330 Names[RTLIB::OLE_F128] = "__letf2"; 331 Names[RTLIB::OLE_PPCF128] = "__gcc_qle"; 332 Names[RTLIB::OGT_F32] = "__gtsf2"; 333 Names[RTLIB::OGT_F64] = "__gtdf2"; 334 Names[RTLIB::OGT_F128] = "__gttf2"; 335 Names[RTLIB::OGT_PPCF128] = "__gcc_qgt"; 336 Names[RTLIB::UO_F32] = "__unordsf2"; 337 Names[RTLIB::UO_F64] = "__unorddf2"; 338 Names[RTLIB::UO_F128] = "__unordtf2"; 339 Names[RTLIB::UO_PPCF128] = "__gcc_qunord"; 340 Names[RTLIB::O_F32] = "__unordsf2"; 341 Names[RTLIB::O_F64] = "__unorddf2"; 342 Names[RTLIB::O_F128] = "__unordtf2"; 343 Names[RTLIB::O_PPCF128] = "__gcc_qunord"; 344 Names[RTLIB::MEMCPY] = "memcpy"; 345 Names[RTLIB::MEMMOVE] = "memmove"; 346 Names[RTLIB::MEMSET] = "memset"; 347 Names[RTLIB::UNWIND_RESUME] = "_Unwind_Resume"; 348 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1] = "__sync_val_compare_and_swap_1"; 349 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2] = "__sync_val_compare_and_swap_2"; 350 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4] = "__sync_val_compare_and_swap_4"; 351 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8] = "__sync_val_compare_and_swap_8"; 352 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_16] = "__sync_val_compare_and_swap_16"; 353 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_1] = "__sync_lock_test_and_set_1"; 354 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_2] = "__sync_lock_test_and_set_2"; 355 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_4] = "__sync_lock_test_and_set_4"; 356 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_8] = "__sync_lock_test_and_set_8"; 357 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_16] = "__sync_lock_test_and_set_16"; 358 Names[RTLIB::SYNC_FETCH_AND_ADD_1] = "__sync_fetch_and_add_1"; 359 Names[RTLIB::SYNC_FETCH_AND_ADD_2] = "__sync_fetch_and_add_2"; 360 Names[RTLIB::SYNC_FETCH_AND_ADD_4] = "__sync_fetch_and_add_4"; 361 Names[RTLIB::SYNC_FETCH_AND_ADD_8] = "__sync_fetch_and_add_8"; 362 Names[RTLIB::SYNC_FETCH_AND_ADD_16] = "__sync_fetch_and_add_16"; 363 Names[RTLIB::SYNC_FETCH_AND_SUB_1] = "__sync_fetch_and_sub_1"; 364 Names[RTLIB::SYNC_FETCH_AND_SUB_2] = "__sync_fetch_and_sub_2"; 365 Names[RTLIB::SYNC_FETCH_AND_SUB_4] = "__sync_fetch_and_sub_4"; 366 Names[RTLIB::SYNC_FETCH_AND_SUB_8] = "__sync_fetch_and_sub_8"; 367 Names[RTLIB::SYNC_FETCH_AND_SUB_16] = "__sync_fetch_and_sub_16"; 368 Names[RTLIB::SYNC_FETCH_AND_AND_1] = "__sync_fetch_and_and_1"; 369 Names[RTLIB::SYNC_FETCH_AND_AND_2] = "__sync_fetch_and_and_2"; 370 Names[RTLIB::SYNC_FETCH_AND_AND_4] = "__sync_fetch_and_and_4"; 371 Names[RTLIB::SYNC_FETCH_AND_AND_8] = "__sync_fetch_and_and_8"; 372 Names[RTLIB::SYNC_FETCH_AND_AND_16] = "__sync_fetch_and_and_16"; 373 Names[RTLIB::SYNC_FETCH_AND_OR_1] = "__sync_fetch_and_or_1"; 374 Names[RTLIB::SYNC_FETCH_AND_OR_2] = "__sync_fetch_and_or_2"; 375 Names[RTLIB::SYNC_FETCH_AND_OR_4] = "__sync_fetch_and_or_4"; 376 Names[RTLIB::SYNC_FETCH_AND_OR_8] = "__sync_fetch_and_or_8"; 377 Names[RTLIB::SYNC_FETCH_AND_OR_16] = "__sync_fetch_and_or_16"; 378 Names[RTLIB::SYNC_FETCH_AND_XOR_1] = "__sync_fetch_and_xor_1"; 379 Names[RTLIB::SYNC_FETCH_AND_XOR_2] = "__sync_fetch_and_xor_2"; 380 Names[RTLIB::SYNC_FETCH_AND_XOR_4] = "__sync_fetch_and_xor_4"; 381 Names[RTLIB::SYNC_FETCH_AND_XOR_8] = "__sync_fetch_and_xor_8"; 382 Names[RTLIB::SYNC_FETCH_AND_XOR_16] = "__sync_fetch_and_xor_16"; 383 Names[RTLIB::SYNC_FETCH_AND_NAND_1] = "__sync_fetch_and_nand_1"; 384 Names[RTLIB::SYNC_FETCH_AND_NAND_2] = "__sync_fetch_and_nand_2"; 385 Names[RTLIB::SYNC_FETCH_AND_NAND_4] = "__sync_fetch_and_nand_4"; 386 Names[RTLIB::SYNC_FETCH_AND_NAND_8] = "__sync_fetch_and_nand_8"; 387 Names[RTLIB::SYNC_FETCH_AND_NAND_16] = "__sync_fetch_and_nand_16"; 388 Names[RTLIB::SYNC_FETCH_AND_MAX_1] = "__sync_fetch_and_max_1"; 389 Names[RTLIB::SYNC_FETCH_AND_MAX_2] = "__sync_fetch_and_max_2"; 390 Names[RTLIB::SYNC_FETCH_AND_MAX_4] = "__sync_fetch_and_max_4"; 391 Names[RTLIB::SYNC_FETCH_AND_MAX_8] = "__sync_fetch_and_max_8"; 392 Names[RTLIB::SYNC_FETCH_AND_MAX_16] = "__sync_fetch_and_max_16"; 393 Names[RTLIB::SYNC_FETCH_AND_UMAX_1] = "__sync_fetch_and_umax_1"; 394 Names[RTLIB::SYNC_FETCH_AND_UMAX_2] = "__sync_fetch_and_umax_2"; 395 Names[RTLIB::SYNC_FETCH_AND_UMAX_4] = "__sync_fetch_and_umax_4"; 396 Names[RTLIB::SYNC_FETCH_AND_UMAX_8] = "__sync_fetch_and_umax_8"; 397 Names[RTLIB::SYNC_FETCH_AND_UMAX_16] = "__sync_fetch_and_umax_16"; 398 Names[RTLIB::SYNC_FETCH_AND_MIN_1] = "__sync_fetch_and_min_1"; 399 Names[RTLIB::SYNC_FETCH_AND_MIN_2] = "__sync_fetch_and_min_2"; 400 Names[RTLIB::SYNC_FETCH_AND_MIN_4] = "__sync_fetch_and_min_4"; 401 Names[RTLIB::SYNC_FETCH_AND_MIN_8] = "__sync_fetch_and_min_8"; 402 Names[RTLIB::SYNC_FETCH_AND_MIN_16] = "__sync_fetch_and_min_16"; 403 Names[RTLIB::SYNC_FETCH_AND_UMIN_1] = "__sync_fetch_and_umin_1"; 404 Names[RTLIB::SYNC_FETCH_AND_UMIN_2] = "__sync_fetch_and_umin_2"; 405 Names[RTLIB::SYNC_FETCH_AND_UMIN_4] = "__sync_fetch_and_umin_4"; 406 Names[RTLIB::SYNC_FETCH_AND_UMIN_8] = "__sync_fetch_and_umin_8"; 407 Names[RTLIB::SYNC_FETCH_AND_UMIN_16] = "__sync_fetch_and_umin_16"; 408 409 if (TT.getEnvironment() == Triple::GNU) { 410 Names[RTLIB::SINCOS_F32] = "sincosf"; 411 Names[RTLIB::SINCOS_F64] = "sincos"; 412 Names[RTLIB::SINCOS_F80] = "sincosl"; 413 Names[RTLIB::SINCOS_F128] = "sincosl"; 414 Names[RTLIB::SINCOS_PPCF128] = "sincosl"; 415 } else { 416 // These are generally not available. 417 Names[RTLIB::SINCOS_F32] = nullptr; 418 Names[RTLIB::SINCOS_F64] = nullptr; 419 Names[RTLIB::SINCOS_F80] = nullptr; 420 Names[RTLIB::SINCOS_F128] = nullptr; 421 Names[RTLIB::SINCOS_PPCF128] = nullptr; 422 } 423 424 if (!TT.isOSOpenBSD()) { 425 Names[RTLIB::STACKPROTECTOR_CHECK_FAIL] = "__stack_chk_fail"; 426 } else { 427 // These are generally not available. 428 Names[RTLIB::STACKPROTECTOR_CHECK_FAIL] = nullptr; 429 } 430 431 // For f16/f32 conversions, Darwin uses the standard naming scheme, instead 432 // of the gnueabi-style __gnu_*_ieee. 433 // FIXME: What about other targets? 434 if (TT.isOSDarwin()) { 435 Names[RTLIB::FPEXT_F16_F32] = "__extendhfsf2"; 436 Names[RTLIB::FPROUND_F32_F16] = "__truncsfhf2"; 437 } 438 439 Names[RTLIB::DEOPTIMIZE] = "__llvm_deoptimize"; 440 } 441 442 /// InitLibcallCallingConvs - Set default libcall CallingConvs. 443 /// 444 static void InitLibcallCallingConvs(CallingConv::ID *CCs) { 445 for (int i = 0; i < RTLIB::UNKNOWN_LIBCALL; ++i) { 446 CCs[i] = CallingConv::C; 447 } 448 } 449 450 /// getFPEXT - Return the FPEXT_*_* value for the given types, or 451 /// UNKNOWN_LIBCALL if there is none. 452 RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) { 453 if (OpVT == MVT::f16) { 454 if (RetVT == MVT::f32) 455 return FPEXT_F16_F32; 456 } else if (OpVT == MVT::f32) { 457 if (RetVT == MVT::f64) 458 return FPEXT_F32_F64; 459 if (RetVT == MVT::f128) 460 return FPEXT_F32_F128; 461 if (RetVT == MVT::ppcf128) 462 return FPEXT_F32_PPCF128; 463 } else if (OpVT == MVT::f64) { 464 if (RetVT == MVT::f128) 465 return FPEXT_F64_F128; 466 else if (RetVT == MVT::ppcf128) 467 return FPEXT_F64_PPCF128; 468 } 469 470 return UNKNOWN_LIBCALL; 471 } 472 473 /// getFPROUND - Return the FPROUND_*_* value for the given types, or 474 /// UNKNOWN_LIBCALL if there is none. 475 RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) { 476 if (RetVT == MVT::f16) { 477 if (OpVT == MVT::f32) 478 return FPROUND_F32_F16; 479 if (OpVT == MVT::f64) 480 return FPROUND_F64_F16; 481 if (OpVT == MVT::f80) 482 return FPROUND_F80_F16; 483 if (OpVT == MVT::f128) 484 return FPROUND_F128_F16; 485 if (OpVT == MVT::ppcf128) 486 return FPROUND_PPCF128_F16; 487 } else if (RetVT == MVT::f32) { 488 if (OpVT == MVT::f64) 489 return FPROUND_F64_F32; 490 if (OpVT == MVT::f80) 491 return FPROUND_F80_F32; 492 if (OpVT == MVT::f128) 493 return FPROUND_F128_F32; 494 if (OpVT == MVT::ppcf128) 495 return FPROUND_PPCF128_F32; 496 } else if (RetVT == MVT::f64) { 497 if (OpVT == MVT::f80) 498 return FPROUND_F80_F64; 499 if (OpVT == MVT::f128) 500 return FPROUND_F128_F64; 501 if (OpVT == MVT::ppcf128) 502 return FPROUND_PPCF128_F64; 503 } 504 505 return UNKNOWN_LIBCALL; 506 } 507 508 /// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or 509 /// UNKNOWN_LIBCALL if there is none. 510 RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT, EVT RetVT) { 511 if (OpVT == MVT::f32) { 512 if (RetVT == MVT::i32) 513 return FPTOSINT_F32_I32; 514 if (RetVT == MVT::i64) 515 return FPTOSINT_F32_I64; 516 if (RetVT == MVT::i128) 517 return FPTOSINT_F32_I128; 518 } else if (OpVT == MVT::f64) { 519 if (RetVT == MVT::i32) 520 return FPTOSINT_F64_I32; 521 if (RetVT == MVT::i64) 522 return FPTOSINT_F64_I64; 523 if (RetVT == MVT::i128) 524 return FPTOSINT_F64_I128; 525 } else if (OpVT == MVT::f80) { 526 if (RetVT == MVT::i32) 527 return FPTOSINT_F80_I32; 528 if (RetVT == MVT::i64) 529 return FPTOSINT_F80_I64; 530 if (RetVT == MVT::i128) 531 return FPTOSINT_F80_I128; 532 } else if (OpVT == MVT::f128) { 533 if (RetVT == MVT::i32) 534 return FPTOSINT_F128_I32; 535 if (RetVT == MVT::i64) 536 return FPTOSINT_F128_I64; 537 if (RetVT == MVT::i128) 538 return FPTOSINT_F128_I128; 539 } else if (OpVT == MVT::ppcf128) { 540 if (RetVT == MVT::i32) 541 return FPTOSINT_PPCF128_I32; 542 if (RetVT == MVT::i64) 543 return FPTOSINT_PPCF128_I64; 544 if (RetVT == MVT::i128) 545 return FPTOSINT_PPCF128_I128; 546 } 547 return UNKNOWN_LIBCALL; 548 } 549 550 /// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or 551 /// UNKNOWN_LIBCALL if there is none. 552 RTLIB::Libcall RTLIB::getFPTOUINT(EVT OpVT, EVT RetVT) { 553 if (OpVT == MVT::f32) { 554 if (RetVT == MVT::i32) 555 return FPTOUINT_F32_I32; 556 if (RetVT == MVT::i64) 557 return FPTOUINT_F32_I64; 558 if (RetVT == MVT::i128) 559 return FPTOUINT_F32_I128; 560 } else if (OpVT == MVT::f64) { 561 if (RetVT == MVT::i32) 562 return FPTOUINT_F64_I32; 563 if (RetVT == MVT::i64) 564 return FPTOUINT_F64_I64; 565 if (RetVT == MVT::i128) 566 return FPTOUINT_F64_I128; 567 } else if (OpVT == MVT::f80) { 568 if (RetVT == MVT::i32) 569 return FPTOUINT_F80_I32; 570 if (RetVT == MVT::i64) 571 return FPTOUINT_F80_I64; 572 if (RetVT == MVT::i128) 573 return FPTOUINT_F80_I128; 574 } else if (OpVT == MVT::f128) { 575 if (RetVT == MVT::i32) 576 return FPTOUINT_F128_I32; 577 if (RetVT == MVT::i64) 578 return FPTOUINT_F128_I64; 579 if (RetVT == MVT::i128) 580 return FPTOUINT_F128_I128; 581 } else if (OpVT == MVT::ppcf128) { 582 if (RetVT == MVT::i32) 583 return FPTOUINT_PPCF128_I32; 584 if (RetVT == MVT::i64) 585 return FPTOUINT_PPCF128_I64; 586 if (RetVT == MVT::i128) 587 return FPTOUINT_PPCF128_I128; 588 } 589 return UNKNOWN_LIBCALL; 590 } 591 592 /// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or 593 /// UNKNOWN_LIBCALL if there is none. 594 RTLIB::Libcall RTLIB::getSINTTOFP(EVT OpVT, EVT RetVT) { 595 if (OpVT == MVT::i32) { 596 if (RetVT == MVT::f32) 597 return SINTTOFP_I32_F32; 598 if (RetVT == MVT::f64) 599 return SINTTOFP_I32_F64; 600 if (RetVT == MVT::f80) 601 return SINTTOFP_I32_F80; 602 if (RetVT == MVT::f128) 603 return SINTTOFP_I32_F128; 604 if (RetVT == MVT::ppcf128) 605 return SINTTOFP_I32_PPCF128; 606 } else if (OpVT == MVT::i64) { 607 if (RetVT == MVT::f32) 608 return SINTTOFP_I64_F32; 609 if (RetVT == MVT::f64) 610 return SINTTOFP_I64_F64; 611 if (RetVT == MVT::f80) 612 return SINTTOFP_I64_F80; 613 if (RetVT == MVT::f128) 614 return SINTTOFP_I64_F128; 615 if (RetVT == MVT::ppcf128) 616 return SINTTOFP_I64_PPCF128; 617 } else if (OpVT == MVT::i128) { 618 if (RetVT == MVT::f32) 619 return SINTTOFP_I128_F32; 620 if (RetVT == MVT::f64) 621 return SINTTOFP_I128_F64; 622 if (RetVT == MVT::f80) 623 return SINTTOFP_I128_F80; 624 if (RetVT == MVT::f128) 625 return SINTTOFP_I128_F128; 626 if (RetVT == MVT::ppcf128) 627 return SINTTOFP_I128_PPCF128; 628 } 629 return UNKNOWN_LIBCALL; 630 } 631 632 /// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or 633 /// UNKNOWN_LIBCALL if there is none. 634 RTLIB::Libcall RTLIB::getUINTTOFP(EVT OpVT, EVT RetVT) { 635 if (OpVT == MVT::i32) { 636 if (RetVT == MVT::f32) 637 return UINTTOFP_I32_F32; 638 if (RetVT == MVT::f64) 639 return UINTTOFP_I32_F64; 640 if (RetVT == MVT::f80) 641 return UINTTOFP_I32_F80; 642 if (RetVT == MVT::f128) 643 return UINTTOFP_I32_F128; 644 if (RetVT == MVT::ppcf128) 645 return UINTTOFP_I32_PPCF128; 646 } else if (OpVT == MVT::i64) { 647 if (RetVT == MVT::f32) 648 return UINTTOFP_I64_F32; 649 if (RetVT == MVT::f64) 650 return UINTTOFP_I64_F64; 651 if (RetVT == MVT::f80) 652 return UINTTOFP_I64_F80; 653 if (RetVT == MVT::f128) 654 return UINTTOFP_I64_F128; 655 if (RetVT == MVT::ppcf128) 656 return UINTTOFP_I64_PPCF128; 657 } else if (OpVT == MVT::i128) { 658 if (RetVT == MVT::f32) 659 return UINTTOFP_I128_F32; 660 if (RetVT == MVT::f64) 661 return UINTTOFP_I128_F64; 662 if (RetVT == MVT::f80) 663 return UINTTOFP_I128_F80; 664 if (RetVT == MVT::f128) 665 return UINTTOFP_I128_F128; 666 if (RetVT == MVT::ppcf128) 667 return UINTTOFP_I128_PPCF128; 668 } 669 return UNKNOWN_LIBCALL; 670 } 671 672 RTLIB::Libcall RTLIB::getSYNC(unsigned Opc, MVT VT) { 673 #define OP_TO_LIBCALL(Name, Enum) \ 674 case Name: \ 675 switch (VT.SimpleTy) { \ 676 default: \ 677 return UNKNOWN_LIBCALL; \ 678 case MVT::i8: \ 679 return Enum##_1; \ 680 case MVT::i16: \ 681 return Enum##_2; \ 682 case MVT::i32: \ 683 return Enum##_4; \ 684 case MVT::i64: \ 685 return Enum##_8; \ 686 case MVT::i128: \ 687 return Enum##_16; \ 688 } 689 690 switch (Opc) { 691 OP_TO_LIBCALL(ISD::ATOMIC_SWAP, SYNC_LOCK_TEST_AND_SET) 692 OP_TO_LIBCALL(ISD::ATOMIC_CMP_SWAP, SYNC_VAL_COMPARE_AND_SWAP) 693 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_ADD, SYNC_FETCH_AND_ADD) 694 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_SUB, SYNC_FETCH_AND_SUB) 695 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_AND, SYNC_FETCH_AND_AND) 696 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_OR, SYNC_FETCH_AND_OR) 697 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_XOR, SYNC_FETCH_AND_XOR) 698 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_NAND, SYNC_FETCH_AND_NAND) 699 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_MAX, SYNC_FETCH_AND_MAX) 700 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_UMAX, SYNC_FETCH_AND_UMAX) 701 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_MIN, SYNC_FETCH_AND_MIN) 702 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_UMIN, SYNC_FETCH_AND_UMIN) 703 } 704 705 #undef OP_TO_LIBCALL 706 707 return UNKNOWN_LIBCALL; 708 } 709 710 /// InitCmpLibcallCCs - Set default comparison libcall CC. 711 /// 712 static void InitCmpLibcallCCs(ISD::CondCode *CCs) { 713 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL); 714 CCs[RTLIB::OEQ_F32] = ISD::SETEQ; 715 CCs[RTLIB::OEQ_F64] = ISD::SETEQ; 716 CCs[RTLIB::OEQ_F128] = ISD::SETEQ; 717 CCs[RTLIB::OEQ_PPCF128] = ISD::SETEQ; 718 CCs[RTLIB::UNE_F32] = ISD::SETNE; 719 CCs[RTLIB::UNE_F64] = ISD::SETNE; 720 CCs[RTLIB::UNE_F128] = ISD::SETNE; 721 CCs[RTLIB::UNE_PPCF128] = ISD::SETNE; 722 CCs[RTLIB::OGE_F32] = ISD::SETGE; 723 CCs[RTLIB::OGE_F64] = ISD::SETGE; 724 CCs[RTLIB::OGE_F128] = ISD::SETGE; 725 CCs[RTLIB::OGE_PPCF128] = ISD::SETGE; 726 CCs[RTLIB::OLT_F32] = ISD::SETLT; 727 CCs[RTLIB::OLT_F64] = ISD::SETLT; 728 CCs[RTLIB::OLT_F128] = ISD::SETLT; 729 CCs[RTLIB::OLT_PPCF128] = ISD::SETLT; 730 CCs[RTLIB::OLE_F32] = ISD::SETLE; 731 CCs[RTLIB::OLE_F64] = ISD::SETLE; 732 CCs[RTLIB::OLE_F128] = ISD::SETLE; 733 CCs[RTLIB::OLE_PPCF128] = ISD::SETLE; 734 CCs[RTLIB::OGT_F32] = ISD::SETGT; 735 CCs[RTLIB::OGT_F64] = ISD::SETGT; 736 CCs[RTLIB::OGT_F128] = ISD::SETGT; 737 CCs[RTLIB::OGT_PPCF128] = ISD::SETGT; 738 CCs[RTLIB::UO_F32] = ISD::SETNE; 739 CCs[RTLIB::UO_F64] = ISD::SETNE; 740 CCs[RTLIB::UO_F128] = ISD::SETNE; 741 CCs[RTLIB::UO_PPCF128] = ISD::SETNE; 742 CCs[RTLIB::O_F32] = ISD::SETEQ; 743 CCs[RTLIB::O_F64] = ISD::SETEQ; 744 CCs[RTLIB::O_F128] = ISD::SETEQ; 745 CCs[RTLIB::O_PPCF128] = ISD::SETEQ; 746 } 747 748 /// NOTE: The TargetMachine owns TLOF. 749 TargetLoweringBase::TargetLoweringBase(const TargetMachine &tm) : TM(tm) { 750 initActions(); 751 752 // Perform these initializations only once. 753 MaxStoresPerMemset = MaxStoresPerMemcpy = MaxStoresPerMemmove = 8; 754 MaxStoresPerMemsetOptSize = MaxStoresPerMemcpyOptSize 755 = MaxStoresPerMemmoveOptSize = 4; 756 UseUnderscoreSetJmp = false; 757 UseUnderscoreLongJmp = false; 758 SelectIsExpensive = false; 759 HasMultipleConditionRegisters = false; 760 HasExtractBitsInsn = false; 761 FsqrtIsCheap = false; 762 JumpIsExpensive = JumpIsExpensiveOverride; 763 PredictableSelectIsExpensive = false; 764 MaskAndBranchFoldingIsLegal = false; 765 EnableExtLdPromotion = false; 766 HasFloatingPointExceptions = true; 767 StackPointerRegisterToSaveRestore = 0; 768 BooleanContents = UndefinedBooleanContent; 769 BooleanFloatContents = UndefinedBooleanContent; 770 BooleanVectorContents = UndefinedBooleanContent; 771 SchedPreferenceInfo = Sched::ILP; 772 JumpBufSize = 0; 773 JumpBufAlignment = 0; 774 MinFunctionAlignment = 0; 775 PrefFunctionAlignment = 0; 776 PrefLoopAlignment = 0; 777 GatherAllAliasesMaxDepth = 6; 778 MinStackArgumentAlignment = 1; 779 MinimumJumpTableEntries = 4; 780 781 InitLibcallNames(LibcallRoutineNames, TM.getTargetTriple()); 782 InitCmpLibcallCCs(CmpLibcallCCs); 783 InitLibcallCallingConvs(LibcallCallingConvs); 784 } 785 786 void TargetLoweringBase::initActions() { 787 // All operations default to being supported. 788 memset(OpActions, 0, sizeof(OpActions)); 789 memset(LoadExtActions, 0, sizeof(LoadExtActions)); 790 memset(TruncStoreActions, 0, sizeof(TruncStoreActions)); 791 memset(IndexedModeActions, 0, sizeof(IndexedModeActions)); 792 memset(CondCodeActions, 0, sizeof(CondCodeActions)); 793 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*)); 794 memset(TargetDAGCombineArray, 0, array_lengthof(TargetDAGCombineArray)); 795 796 // Set default actions for various operations. 797 for (MVT VT : MVT::all_valuetypes()) { 798 // Default all indexed load / store to expand. 799 for (unsigned IM = (unsigned)ISD::PRE_INC; 800 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) { 801 setIndexedLoadAction(IM, VT, Expand); 802 setIndexedStoreAction(IM, VT, Expand); 803 } 804 805 // Most backends expect to see the node which just returns the value loaded. 806 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Expand); 807 808 // These operations default to expand. 809 setOperationAction(ISD::FGETSIGN, VT, Expand); 810 setOperationAction(ISD::CONCAT_VECTORS, VT, Expand); 811 setOperationAction(ISD::FMINNUM, VT, Expand); 812 setOperationAction(ISD::FMAXNUM, VT, Expand); 813 setOperationAction(ISD::FMINNAN, VT, Expand); 814 setOperationAction(ISD::FMAXNAN, VT, Expand); 815 setOperationAction(ISD::FMAD, VT, Expand); 816 setOperationAction(ISD::SMIN, VT, Expand); 817 setOperationAction(ISD::SMAX, VT, Expand); 818 setOperationAction(ISD::UMIN, VT, Expand); 819 setOperationAction(ISD::UMAX, VT, Expand); 820 821 // Overflow operations default to expand 822 setOperationAction(ISD::SADDO, VT, Expand); 823 setOperationAction(ISD::SSUBO, VT, Expand); 824 setOperationAction(ISD::UADDO, VT, Expand); 825 setOperationAction(ISD::USUBO, VT, Expand); 826 setOperationAction(ISD::SMULO, VT, Expand); 827 setOperationAction(ISD::UMULO, VT, Expand); 828 829 setOperationAction(ISD::BITREVERSE, VT, Expand); 830 831 // These library functions default to expand. 832 setOperationAction(ISD::FROUND, VT, Expand); 833 834 // These operations default to expand for vector types. 835 if (VT.isVector()) { 836 setOperationAction(ISD::FCOPYSIGN, VT, Expand); 837 setOperationAction(ISD::ANY_EXTEND_VECTOR_INREG, VT, Expand); 838 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, VT, Expand); 839 setOperationAction(ISD::ZERO_EXTEND_VECTOR_INREG, VT, Expand); 840 } 841 842 // For most targets @llvm.get.dynamic.area.offest just returns 0. 843 setOperationAction(ISD::GET_DYNAMIC_AREA_OFFSET, VT, Expand); 844 } 845 846 // Most targets ignore the @llvm.prefetch intrinsic. 847 setOperationAction(ISD::PREFETCH, MVT::Other, Expand); 848 849 // Most targets also ignore the @llvm.readcyclecounter intrinsic. 850 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Expand); 851 852 // ConstantFP nodes default to expand. Targets can either change this to 853 // Legal, in which case all fp constants are legal, or use isFPImmLegal() 854 // to optimize expansions for certain constants. 855 setOperationAction(ISD::ConstantFP, MVT::f16, Expand); 856 setOperationAction(ISD::ConstantFP, MVT::f32, Expand); 857 setOperationAction(ISD::ConstantFP, MVT::f64, Expand); 858 setOperationAction(ISD::ConstantFP, MVT::f80, Expand); 859 setOperationAction(ISD::ConstantFP, MVT::f128, Expand); 860 861 // These library functions default to expand. 862 for (MVT VT : {MVT::f32, MVT::f64, MVT::f128}) { 863 setOperationAction(ISD::FLOG , VT, Expand); 864 setOperationAction(ISD::FLOG2, VT, Expand); 865 setOperationAction(ISD::FLOG10, VT, Expand); 866 setOperationAction(ISD::FEXP , VT, Expand); 867 setOperationAction(ISD::FEXP2, VT, Expand); 868 setOperationAction(ISD::FFLOOR, VT, Expand); 869 setOperationAction(ISD::FMINNUM, VT, Expand); 870 setOperationAction(ISD::FMAXNUM, VT, Expand); 871 setOperationAction(ISD::FNEARBYINT, VT, Expand); 872 setOperationAction(ISD::FCEIL, VT, Expand); 873 setOperationAction(ISD::FRINT, VT, Expand); 874 setOperationAction(ISD::FTRUNC, VT, Expand); 875 setOperationAction(ISD::FROUND, VT, Expand); 876 } 877 878 // Default ISD::TRAP to expand (which turns it into abort). 879 setOperationAction(ISD::TRAP, MVT::Other, Expand); 880 881 // On most systems, DEBUGTRAP and TRAP have no difference. The "Expand" 882 // here is to inform DAG Legalizer to replace DEBUGTRAP with TRAP. 883 // 884 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Expand); 885 } 886 887 MVT TargetLoweringBase::getScalarShiftAmountTy(const DataLayout &DL, 888 EVT) const { 889 return MVT::getIntegerVT(8 * DL.getPointerSize(0)); 890 } 891 892 EVT TargetLoweringBase::getShiftAmountTy(EVT LHSTy, 893 const DataLayout &DL) const { 894 assert(LHSTy.isInteger() && "Shift amount is not an integer type!"); 895 if (LHSTy.isVector()) 896 return LHSTy; 897 return getScalarShiftAmountTy(DL, LHSTy); 898 } 899 900 /// canOpTrap - Returns true if the operation can trap for the value type. 901 /// VT must be a legal type. 902 bool TargetLoweringBase::canOpTrap(unsigned Op, EVT VT) const { 903 assert(isTypeLegal(VT)); 904 switch (Op) { 905 default: 906 return false; 907 case ISD::FDIV: 908 case ISD::FREM: 909 case ISD::SDIV: 910 case ISD::UDIV: 911 case ISD::SREM: 912 case ISD::UREM: 913 return true; 914 } 915 } 916 917 void TargetLoweringBase::setJumpIsExpensive(bool isExpensive) { 918 // If the command-line option was specified, ignore this request. 919 if (!JumpIsExpensiveOverride.getNumOccurrences()) 920 JumpIsExpensive = isExpensive; 921 } 922 923 TargetLoweringBase::LegalizeKind 924 TargetLoweringBase::getTypeConversion(LLVMContext &Context, EVT VT) const { 925 // If this is a simple type, use the ComputeRegisterProp mechanism. 926 if (VT.isSimple()) { 927 MVT SVT = VT.getSimpleVT(); 928 assert((unsigned)SVT.SimpleTy < array_lengthof(TransformToType)); 929 MVT NVT = TransformToType[SVT.SimpleTy]; 930 LegalizeTypeAction LA = ValueTypeActions.getTypeAction(SVT); 931 932 assert((LA == TypeLegal || LA == TypeSoftenFloat || 933 ValueTypeActions.getTypeAction(NVT) != TypePromoteInteger) && 934 "Promote may not follow Expand or Promote"); 935 936 if (LA == TypeSplitVector) 937 return LegalizeKind(LA, 938 EVT::getVectorVT(Context, SVT.getVectorElementType(), 939 SVT.getVectorNumElements() / 2)); 940 if (LA == TypeScalarizeVector) 941 return LegalizeKind(LA, SVT.getVectorElementType()); 942 return LegalizeKind(LA, NVT); 943 } 944 945 // Handle Extended Scalar Types. 946 if (!VT.isVector()) { 947 assert(VT.isInteger() && "Float types must be simple"); 948 unsigned BitSize = VT.getSizeInBits(); 949 // First promote to a power-of-two size, then expand if necessary. 950 if (BitSize < 8 || !isPowerOf2_32(BitSize)) { 951 EVT NVT = VT.getRoundIntegerType(Context); 952 assert(NVT != VT && "Unable to round integer VT"); 953 LegalizeKind NextStep = getTypeConversion(Context, NVT); 954 // Avoid multi-step promotion. 955 if (NextStep.first == TypePromoteInteger) 956 return NextStep; 957 // Return rounded integer type. 958 return LegalizeKind(TypePromoteInteger, NVT); 959 } 960 961 return LegalizeKind(TypeExpandInteger, 962 EVT::getIntegerVT(Context, VT.getSizeInBits() / 2)); 963 } 964 965 // Handle vector types. 966 unsigned NumElts = VT.getVectorNumElements(); 967 EVT EltVT = VT.getVectorElementType(); 968 969 // Vectors with only one element are always scalarized. 970 if (NumElts == 1) 971 return LegalizeKind(TypeScalarizeVector, EltVT); 972 973 // Try to widen vector elements until the element type is a power of two and 974 // promote it to a legal type later on, for example: 975 // <3 x i8> -> <4 x i8> -> <4 x i32> 976 if (EltVT.isInteger()) { 977 // Vectors with a number of elements that is not a power of two are always 978 // widened, for example <3 x i8> -> <4 x i8>. 979 if (!VT.isPow2VectorType()) { 980 NumElts = (unsigned)NextPowerOf2(NumElts); 981 EVT NVT = EVT::getVectorVT(Context, EltVT, NumElts); 982 return LegalizeKind(TypeWidenVector, NVT); 983 } 984 985 // Examine the element type. 986 LegalizeKind LK = getTypeConversion(Context, EltVT); 987 988 // If type is to be expanded, split the vector. 989 // <4 x i140> -> <2 x i140> 990 if (LK.first == TypeExpandInteger) 991 return LegalizeKind(TypeSplitVector, 992 EVT::getVectorVT(Context, EltVT, NumElts / 2)); 993 994 // Promote the integer element types until a legal vector type is found 995 // or until the element integer type is too big. If a legal type was not 996 // found, fallback to the usual mechanism of widening/splitting the 997 // vector. 998 EVT OldEltVT = EltVT; 999 while (1) { 1000 // Increase the bitwidth of the element to the next pow-of-two 1001 // (which is greater than 8 bits). 1002 EltVT = EVT::getIntegerVT(Context, 1 + EltVT.getSizeInBits()) 1003 .getRoundIntegerType(Context); 1004 1005 // Stop trying when getting a non-simple element type. 1006 // Note that vector elements may be greater than legal vector element 1007 // types. Example: X86 XMM registers hold 64bit element on 32bit 1008 // systems. 1009 if (!EltVT.isSimple()) 1010 break; 1011 1012 // Build a new vector type and check if it is legal. 1013 MVT NVT = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts); 1014 // Found a legal promoted vector type. 1015 if (NVT != MVT() && ValueTypeActions.getTypeAction(NVT) == TypeLegal) 1016 return LegalizeKind(TypePromoteInteger, 1017 EVT::getVectorVT(Context, EltVT, NumElts)); 1018 } 1019 1020 // Reset the type to the unexpanded type if we did not find a legal vector 1021 // type with a promoted vector element type. 1022 EltVT = OldEltVT; 1023 } 1024 1025 // Try to widen the vector until a legal type is found. 1026 // If there is no wider legal type, split the vector. 1027 while (1) { 1028 // Round up to the next power of 2. 1029 NumElts = (unsigned)NextPowerOf2(NumElts); 1030 1031 // If there is no simple vector type with this many elements then there 1032 // cannot be a larger legal vector type. Note that this assumes that 1033 // there are no skipped intermediate vector types in the simple types. 1034 if (!EltVT.isSimple()) 1035 break; 1036 MVT LargerVector = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts); 1037 if (LargerVector == MVT()) 1038 break; 1039 1040 // If this type is legal then widen the vector. 1041 if (ValueTypeActions.getTypeAction(LargerVector) == TypeLegal) 1042 return LegalizeKind(TypeWidenVector, LargerVector); 1043 } 1044 1045 // Widen odd vectors to next power of two. 1046 if (!VT.isPow2VectorType()) { 1047 EVT NVT = VT.getPow2VectorType(Context); 1048 return LegalizeKind(TypeWidenVector, NVT); 1049 } 1050 1051 // Vectors with illegal element types are expanded. 1052 EVT NVT = EVT::getVectorVT(Context, EltVT, VT.getVectorNumElements() / 2); 1053 return LegalizeKind(TypeSplitVector, NVT); 1054 } 1055 1056 static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT, 1057 unsigned &NumIntermediates, 1058 MVT &RegisterVT, 1059 TargetLoweringBase *TLI) { 1060 // Figure out the right, legal destination reg to copy into. 1061 unsigned NumElts = VT.getVectorNumElements(); 1062 MVT EltTy = VT.getVectorElementType(); 1063 1064 unsigned NumVectorRegs = 1; 1065 1066 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we 1067 // could break down into LHS/RHS like LegalizeDAG does. 1068 if (!isPowerOf2_32(NumElts)) { 1069 NumVectorRegs = NumElts; 1070 NumElts = 1; 1071 } 1072 1073 // Divide the input until we get to a supported size. This will always 1074 // end with a scalar if the target doesn't support vectors. 1075 while (NumElts > 1 && !TLI->isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) { 1076 NumElts >>= 1; 1077 NumVectorRegs <<= 1; 1078 } 1079 1080 NumIntermediates = NumVectorRegs; 1081 1082 MVT NewVT = MVT::getVectorVT(EltTy, NumElts); 1083 if (!TLI->isTypeLegal(NewVT)) 1084 NewVT = EltTy; 1085 IntermediateVT = NewVT; 1086 1087 unsigned NewVTSize = NewVT.getSizeInBits(); 1088 1089 // Convert sizes such as i33 to i64. 1090 if (!isPowerOf2_32(NewVTSize)) 1091 NewVTSize = NextPowerOf2(NewVTSize); 1092 1093 MVT DestVT = TLI->getRegisterType(NewVT); 1094 RegisterVT = DestVT; 1095 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16. 1096 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits()); 1097 1098 // Otherwise, promotion or legal types use the same number of registers as 1099 // the vector decimated to the appropriate level. 1100 return NumVectorRegs; 1101 } 1102 1103 /// isLegalRC - Return true if the value types that can be represented by the 1104 /// specified register class are all legal. 1105 bool TargetLoweringBase::isLegalRC(const TargetRegisterClass *RC) const { 1106 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end(); 1107 I != E; ++I) { 1108 if (isTypeLegal(*I)) 1109 return true; 1110 } 1111 return false; 1112 } 1113 1114 /// Replace/modify any TargetFrameIndex operands with a targte-dependent 1115 /// sequence of memory operands that is recognized by PrologEpilogInserter. 1116 MachineBasicBlock* 1117 TargetLoweringBase::emitPatchPoint(MachineInstr *MI, 1118 MachineBasicBlock *MBB) const { 1119 MachineFunction &MF = *MI->getParent()->getParent(); 1120 MachineFrameInfo &MFI = *MF.getFrameInfo(); 1121 1122 // We're handling multiple types of operands here: 1123 // PATCHPOINT MetaArgs - live-in, read only, direct 1124 // STATEPOINT Deopt Spill - live-through, read only, indirect 1125 // STATEPOINT Deopt Alloca - live-through, read only, direct 1126 // (We're currently conservative and mark the deopt slots read/write in 1127 // practice.) 1128 // STATEPOINT GC Spill - live-through, read/write, indirect 1129 // STATEPOINT GC Alloca - live-through, read/write, direct 1130 // The live-in vs live-through is handled already (the live through ones are 1131 // all stack slots), but we need to handle the different type of stackmap 1132 // operands and memory effects here. 1133 1134 // MI changes inside this loop as we grow operands. 1135 for(unsigned OperIdx = 0; OperIdx != MI->getNumOperands(); ++OperIdx) { 1136 MachineOperand &MO = MI->getOperand(OperIdx); 1137 if (!MO.isFI()) 1138 continue; 1139 1140 // foldMemoryOperand builds a new MI after replacing a single FI operand 1141 // with the canonical set of five x86 addressing-mode operands. 1142 int FI = MO.getIndex(); 1143 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), MI->getDesc()); 1144 1145 // Copy operands before the frame-index. 1146 for (unsigned i = 0; i < OperIdx; ++i) 1147 MIB.addOperand(MI->getOperand(i)); 1148 // Add frame index operands recognized by stackmaps.cpp 1149 if (MFI.isStatepointSpillSlotObjectIndex(FI)) { 1150 // indirect-mem-ref tag, size, #FI, offset. 1151 // Used for spills inserted by StatepointLowering. This codepath is not 1152 // used for patchpoints/stackmaps at all, for these spilling is done via 1153 // foldMemoryOperand callback only. 1154 assert(MI->getOpcode() == TargetOpcode::STATEPOINT && "sanity"); 1155 MIB.addImm(StackMaps::IndirectMemRefOp); 1156 MIB.addImm(MFI.getObjectSize(FI)); 1157 MIB.addOperand(MI->getOperand(OperIdx)); 1158 MIB.addImm(0); 1159 } else { 1160 // direct-mem-ref tag, #FI, offset. 1161 // Used by patchpoint, and direct alloca arguments to statepoints 1162 MIB.addImm(StackMaps::DirectMemRefOp); 1163 MIB.addOperand(MI->getOperand(OperIdx)); 1164 MIB.addImm(0); 1165 } 1166 // Copy the operands after the frame index. 1167 for (unsigned i = OperIdx + 1; i != MI->getNumOperands(); ++i) 1168 MIB.addOperand(MI->getOperand(i)); 1169 1170 // Inherit previous memory operands. 1171 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end()); 1172 assert(MIB->mayLoad() && "Folded a stackmap use to a non-load!"); 1173 1174 // Add a new memory operand for this FI. 1175 assert(MFI.getObjectOffset(FI) != -1); 1176 1177 unsigned Flags = MachineMemOperand::MOLoad; 1178 if (MI->getOpcode() == TargetOpcode::STATEPOINT) { 1179 Flags |= MachineMemOperand::MOStore; 1180 Flags |= MachineMemOperand::MOVolatile; 1181 } 1182 MachineMemOperand *MMO = MF.getMachineMemOperand( 1183 MachinePointerInfo::getFixedStack(MF, FI), Flags, 1184 MF.getDataLayout().getPointerSize(), MFI.getObjectAlignment(FI)); 1185 MIB->addMemOperand(MF, MMO); 1186 1187 // Replace the instruction and update the operand index. 1188 MBB->insert(MachineBasicBlock::iterator(MI), MIB); 1189 OperIdx += (MIB->getNumOperands() - MI->getNumOperands()) - 1; 1190 MI->eraseFromParent(); 1191 MI = MIB; 1192 } 1193 return MBB; 1194 } 1195 1196 /// findRepresentativeClass - Return the largest legal super-reg register class 1197 /// of the register class for the specified type and its associated "cost". 1198 // This function is in TargetLowering because it uses RegClassForVT which would 1199 // need to be moved to TargetRegisterInfo and would necessitate moving 1200 // isTypeLegal over as well - a massive change that would just require 1201 // TargetLowering having a TargetRegisterInfo class member that it would use. 1202 std::pair<const TargetRegisterClass *, uint8_t> 1203 TargetLoweringBase::findRepresentativeClass(const TargetRegisterInfo *TRI, 1204 MVT VT) const { 1205 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy]; 1206 if (!RC) 1207 return std::make_pair(RC, 0); 1208 1209 // Compute the set of all super-register classes. 1210 BitVector SuperRegRC(TRI->getNumRegClasses()); 1211 for (SuperRegClassIterator RCI(RC, TRI); RCI.isValid(); ++RCI) 1212 SuperRegRC.setBitsInMask(RCI.getMask()); 1213 1214 // Find the first legal register class with the largest spill size. 1215 const TargetRegisterClass *BestRC = RC; 1216 for (int i = SuperRegRC.find_first(); i >= 0; i = SuperRegRC.find_next(i)) { 1217 const TargetRegisterClass *SuperRC = TRI->getRegClass(i); 1218 // We want the largest possible spill size. 1219 if (SuperRC->getSize() <= BestRC->getSize()) 1220 continue; 1221 if (!isLegalRC(SuperRC)) 1222 continue; 1223 BestRC = SuperRC; 1224 } 1225 return std::make_pair(BestRC, 1); 1226 } 1227 1228 /// computeRegisterProperties - Once all of the register classes are added, 1229 /// this allows us to compute derived properties we expose. 1230 void TargetLoweringBase::computeRegisterProperties( 1231 const TargetRegisterInfo *TRI) { 1232 static_assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE, 1233 "Too many value types for ValueTypeActions to hold!"); 1234 1235 // Everything defaults to needing one register. 1236 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) { 1237 NumRegistersForVT[i] = 1; 1238 RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i; 1239 } 1240 // ...except isVoid, which doesn't need any registers. 1241 NumRegistersForVT[MVT::isVoid] = 0; 1242 1243 // Find the largest integer register class. 1244 unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE; 1245 for (; RegClassForVT[LargestIntReg] == nullptr; --LargestIntReg) 1246 assert(LargestIntReg != MVT::i1 && "No integer registers defined!"); 1247 1248 // Every integer value type larger than this largest register takes twice as 1249 // many registers to represent as the previous ValueType. 1250 for (unsigned ExpandedReg = LargestIntReg + 1; 1251 ExpandedReg <= MVT::LAST_INTEGER_VALUETYPE; ++ExpandedReg) { 1252 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1]; 1253 RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg; 1254 TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1); 1255 ValueTypeActions.setTypeAction((MVT::SimpleValueType)ExpandedReg, 1256 TypeExpandInteger); 1257 } 1258 1259 // Inspect all of the ValueType's smaller than the largest integer 1260 // register to see which ones need promotion. 1261 unsigned LegalIntReg = LargestIntReg; 1262 for (unsigned IntReg = LargestIntReg - 1; 1263 IntReg >= (unsigned)MVT::i1; --IntReg) { 1264 MVT IVT = (MVT::SimpleValueType)IntReg; 1265 if (isTypeLegal(IVT)) { 1266 LegalIntReg = IntReg; 1267 } else { 1268 RegisterTypeForVT[IntReg] = TransformToType[IntReg] = 1269 (const MVT::SimpleValueType)LegalIntReg; 1270 ValueTypeActions.setTypeAction(IVT, TypePromoteInteger); 1271 } 1272 } 1273 1274 // ppcf128 type is really two f64's. 1275 if (!isTypeLegal(MVT::ppcf128)) { 1276 if (isTypeLegal(MVT::f64)) { 1277 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64]; 1278 RegisterTypeForVT[MVT::ppcf128] = MVT::f64; 1279 TransformToType[MVT::ppcf128] = MVT::f64; 1280 ValueTypeActions.setTypeAction(MVT::ppcf128, TypeExpandFloat); 1281 } else { 1282 NumRegistersForVT[MVT::ppcf128] = NumRegistersForVT[MVT::i128]; 1283 RegisterTypeForVT[MVT::ppcf128] = RegisterTypeForVT[MVT::i128]; 1284 TransformToType[MVT::ppcf128] = MVT::i128; 1285 ValueTypeActions.setTypeAction(MVT::ppcf128, TypeSoftenFloat); 1286 } 1287 } 1288 1289 // Decide how to handle f128. If the target does not have native f128 support, 1290 // expand it to i128 and we will be generating soft float library calls. 1291 if (!isTypeLegal(MVT::f128)) { 1292 NumRegistersForVT[MVT::f128] = NumRegistersForVT[MVT::i128]; 1293 RegisterTypeForVT[MVT::f128] = RegisterTypeForVT[MVT::i128]; 1294 TransformToType[MVT::f128] = MVT::i128; 1295 ValueTypeActions.setTypeAction(MVT::f128, TypeSoftenFloat); 1296 } 1297 1298 // Decide how to handle f64. If the target does not have native f64 support, 1299 // expand it to i64 and we will be generating soft float library calls. 1300 if (!isTypeLegal(MVT::f64)) { 1301 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64]; 1302 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64]; 1303 TransformToType[MVT::f64] = MVT::i64; 1304 ValueTypeActions.setTypeAction(MVT::f64, TypeSoftenFloat); 1305 } 1306 1307 // Decide how to handle f32. If the target does not have native f32 support, 1308 // expand it to i32 and we will be generating soft float library calls. 1309 if (!isTypeLegal(MVT::f32)) { 1310 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32]; 1311 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32]; 1312 TransformToType[MVT::f32] = MVT::i32; 1313 ValueTypeActions.setTypeAction(MVT::f32, TypeSoftenFloat); 1314 } 1315 1316 // Decide how to handle f16. If the target does not have native f16 support, 1317 // promote it to f32, because there are no f16 library calls (except for 1318 // conversions). 1319 if (!isTypeLegal(MVT::f16)) { 1320 NumRegistersForVT[MVT::f16] = NumRegistersForVT[MVT::f32]; 1321 RegisterTypeForVT[MVT::f16] = RegisterTypeForVT[MVT::f32]; 1322 TransformToType[MVT::f16] = MVT::f32; 1323 ValueTypeActions.setTypeAction(MVT::f16, TypePromoteFloat); 1324 } 1325 1326 // Loop over all of the vector value types to see which need transformations. 1327 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE; 1328 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) { 1329 MVT VT = (MVT::SimpleValueType) i; 1330 if (isTypeLegal(VT)) 1331 continue; 1332 1333 MVT EltVT = VT.getVectorElementType(); 1334 unsigned NElts = VT.getVectorNumElements(); 1335 bool IsLegalWiderType = false; 1336 LegalizeTypeAction PreferredAction = getPreferredVectorAction(VT); 1337 switch (PreferredAction) { 1338 case TypePromoteInteger: { 1339 // Try to promote the elements of integer vectors. If no legal 1340 // promotion was found, fall through to the widen-vector method. 1341 for (unsigned nVT = i + 1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) { 1342 MVT SVT = (MVT::SimpleValueType) nVT; 1343 // Promote vectors of integers to vectors with the same number 1344 // of elements, with a wider element type. 1345 if (SVT.getVectorElementType().getSizeInBits() > EltVT.getSizeInBits() 1346 && SVT.getVectorNumElements() == NElts && isTypeLegal(SVT) 1347 && SVT.getScalarType().isInteger()) { 1348 TransformToType[i] = SVT; 1349 RegisterTypeForVT[i] = SVT; 1350 NumRegistersForVT[i] = 1; 1351 ValueTypeActions.setTypeAction(VT, TypePromoteInteger); 1352 IsLegalWiderType = true; 1353 break; 1354 } 1355 } 1356 if (IsLegalWiderType) 1357 break; 1358 } 1359 case TypeWidenVector: { 1360 // Try to widen the vector. 1361 for (unsigned nVT = i + 1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) { 1362 MVT SVT = (MVT::SimpleValueType) nVT; 1363 if (SVT.getVectorElementType() == EltVT 1364 && SVT.getVectorNumElements() > NElts && isTypeLegal(SVT)) { 1365 TransformToType[i] = SVT; 1366 RegisterTypeForVT[i] = SVT; 1367 NumRegistersForVT[i] = 1; 1368 ValueTypeActions.setTypeAction(VT, TypeWidenVector); 1369 IsLegalWiderType = true; 1370 break; 1371 } 1372 } 1373 if (IsLegalWiderType) 1374 break; 1375 } 1376 case TypeSplitVector: 1377 case TypeScalarizeVector: { 1378 MVT IntermediateVT; 1379 MVT RegisterVT; 1380 unsigned NumIntermediates; 1381 NumRegistersForVT[i] = getVectorTypeBreakdownMVT(VT, IntermediateVT, 1382 NumIntermediates, RegisterVT, this); 1383 RegisterTypeForVT[i] = RegisterVT; 1384 1385 MVT NVT = VT.getPow2VectorType(); 1386 if (NVT == VT) { 1387 // Type is already a power of 2. The default action is to split. 1388 TransformToType[i] = MVT::Other; 1389 if (PreferredAction == TypeScalarizeVector) 1390 ValueTypeActions.setTypeAction(VT, TypeScalarizeVector); 1391 else if (PreferredAction == TypeSplitVector) 1392 ValueTypeActions.setTypeAction(VT, TypeSplitVector); 1393 else 1394 // Set type action according to the number of elements. 1395 ValueTypeActions.setTypeAction(VT, NElts == 1 ? TypeScalarizeVector 1396 : TypeSplitVector); 1397 } else { 1398 TransformToType[i] = NVT; 1399 ValueTypeActions.setTypeAction(VT, TypeWidenVector); 1400 } 1401 break; 1402 } 1403 default: 1404 llvm_unreachable("Unknown vector legalization action!"); 1405 } 1406 } 1407 1408 // Determine the 'representative' register class for each value type. 1409 // An representative register class is the largest (meaning one which is 1410 // not a sub-register class / subreg register class) legal register class for 1411 // a group of value types. For example, on i386, i8, i16, and i32 1412 // representative would be GR32; while on x86_64 it's GR64. 1413 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) { 1414 const TargetRegisterClass* RRC; 1415 uint8_t Cost; 1416 std::tie(RRC, Cost) = findRepresentativeClass(TRI, (MVT::SimpleValueType)i); 1417 RepRegClassForVT[i] = RRC; 1418 RepRegClassCostForVT[i] = Cost; 1419 } 1420 } 1421 1422 EVT TargetLoweringBase::getSetCCResultType(const DataLayout &DL, LLVMContext &, 1423 EVT VT) const { 1424 assert(!VT.isVector() && "No default SetCC type for vectors!"); 1425 return getPointerTy(DL).SimpleTy; 1426 } 1427 1428 MVT::SimpleValueType TargetLoweringBase::getCmpLibcallReturnType() const { 1429 return MVT::i32; // return the default value 1430 } 1431 1432 /// getVectorTypeBreakdown - Vector types are broken down into some number of 1433 /// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32 1434 /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack. 1435 /// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86. 1436 /// 1437 /// This method returns the number of registers needed, and the VT for each 1438 /// register. It also returns the VT and quantity of the intermediate values 1439 /// before they are promoted/expanded. 1440 /// 1441 unsigned TargetLoweringBase::getVectorTypeBreakdown(LLVMContext &Context, EVT VT, 1442 EVT &IntermediateVT, 1443 unsigned &NumIntermediates, 1444 MVT &RegisterVT) const { 1445 unsigned NumElts = VT.getVectorNumElements(); 1446 1447 // If there is a wider vector type with the same element type as this one, 1448 // or a promoted vector type that has the same number of elements which 1449 // are wider, then we should convert to that legal vector type. 1450 // This handles things like <2 x float> -> <4 x float> and 1451 // <4 x i1> -> <4 x i32>. 1452 LegalizeTypeAction TA = getTypeAction(Context, VT); 1453 if (NumElts != 1 && (TA == TypeWidenVector || TA == TypePromoteInteger)) { 1454 EVT RegisterEVT = getTypeToTransformTo(Context, VT); 1455 if (isTypeLegal(RegisterEVT)) { 1456 IntermediateVT = RegisterEVT; 1457 RegisterVT = RegisterEVT.getSimpleVT(); 1458 NumIntermediates = 1; 1459 return 1; 1460 } 1461 } 1462 1463 // Figure out the right, legal destination reg to copy into. 1464 EVT EltTy = VT.getVectorElementType(); 1465 1466 unsigned NumVectorRegs = 1; 1467 1468 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we 1469 // could break down into LHS/RHS like LegalizeDAG does. 1470 if (!isPowerOf2_32(NumElts)) { 1471 NumVectorRegs = NumElts; 1472 NumElts = 1; 1473 } 1474 1475 // Divide the input until we get to a supported size. This will always 1476 // end with a scalar if the target doesn't support vectors. 1477 while (NumElts > 1 && !isTypeLegal( 1478 EVT::getVectorVT(Context, EltTy, NumElts))) { 1479 NumElts >>= 1; 1480 NumVectorRegs <<= 1; 1481 } 1482 1483 NumIntermediates = NumVectorRegs; 1484 1485 EVT NewVT = EVT::getVectorVT(Context, EltTy, NumElts); 1486 if (!isTypeLegal(NewVT)) 1487 NewVT = EltTy; 1488 IntermediateVT = NewVT; 1489 1490 MVT DestVT = getRegisterType(Context, NewVT); 1491 RegisterVT = DestVT; 1492 unsigned NewVTSize = NewVT.getSizeInBits(); 1493 1494 // Convert sizes such as i33 to i64. 1495 if (!isPowerOf2_32(NewVTSize)) 1496 NewVTSize = NextPowerOf2(NewVTSize); 1497 1498 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16. 1499 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits()); 1500 1501 // Otherwise, promotion or legal types use the same number of registers as 1502 // the vector decimated to the appropriate level. 1503 return NumVectorRegs; 1504 } 1505 1506 /// Get the EVTs and ArgFlags collections that represent the legalized return 1507 /// type of the given function. This does not require a DAG or a return value, 1508 /// and is suitable for use before any DAGs for the function are constructed. 1509 /// TODO: Move this out of TargetLowering.cpp. 1510 void llvm::GetReturnInfo(Type *ReturnType, AttributeSet attr, 1511 SmallVectorImpl<ISD::OutputArg> &Outs, 1512 const TargetLowering &TLI, const DataLayout &DL) { 1513 SmallVector<EVT, 4> ValueVTs; 1514 ComputeValueVTs(TLI, DL, ReturnType, ValueVTs); 1515 unsigned NumValues = ValueVTs.size(); 1516 if (NumValues == 0) return; 1517 1518 for (unsigned j = 0, f = NumValues; j != f; ++j) { 1519 EVT VT = ValueVTs[j]; 1520 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 1521 1522 if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::SExt)) 1523 ExtendKind = ISD::SIGN_EXTEND; 1524 else if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::ZExt)) 1525 ExtendKind = ISD::ZERO_EXTEND; 1526 1527 // FIXME: C calling convention requires the return type to be promoted to 1528 // at least 32-bit. But this is not necessary for non-C calling 1529 // conventions. The frontend should mark functions whose return values 1530 // require promoting with signext or zeroext attributes. 1531 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) { 1532 MVT MinVT = TLI.getRegisterType(ReturnType->getContext(), MVT::i32); 1533 if (VT.bitsLT(MinVT)) 1534 VT = MinVT; 1535 } 1536 1537 unsigned NumParts = TLI.getNumRegisters(ReturnType->getContext(), VT); 1538 MVT PartVT = TLI.getRegisterType(ReturnType->getContext(), VT); 1539 1540 // 'inreg' on function refers to return value 1541 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy(); 1542 if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::InReg)) 1543 Flags.setInReg(); 1544 1545 // Propagate extension type if any 1546 if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::SExt)) 1547 Flags.setSExt(); 1548 else if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::ZExt)) 1549 Flags.setZExt(); 1550 1551 for (unsigned i = 0; i < NumParts; ++i) 1552 Outs.push_back(ISD::OutputArg(Flags, PartVT, VT, /*isFixed=*/true, 0, 0)); 1553 } 1554 } 1555 1556 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 1557 /// function arguments in the caller parameter area. This is the actual 1558 /// alignment, not its logarithm. 1559 unsigned TargetLoweringBase::getByValTypeAlignment(Type *Ty, 1560 const DataLayout &DL) const { 1561 return DL.getABITypeAlignment(Ty); 1562 } 1563 1564 bool TargetLoweringBase::allowsMemoryAccess(LLVMContext &Context, 1565 const DataLayout &DL, EVT VT, 1566 unsigned AddrSpace, 1567 unsigned Alignment, 1568 bool *Fast) const { 1569 // Check if the specified alignment is sufficient based on the data layout. 1570 // TODO: While using the data layout works in practice, a better solution 1571 // would be to implement this check directly (make this a virtual function). 1572 // For example, the ABI alignment may change based on software platform while 1573 // this function should only be affected by hardware implementation. 1574 Type *Ty = VT.getTypeForEVT(Context); 1575 if (Alignment >= DL.getABITypeAlignment(Ty)) { 1576 // Assume that an access that meets the ABI-specified alignment is fast. 1577 if (Fast != nullptr) 1578 *Fast = true; 1579 return true; 1580 } 1581 1582 // This is a misaligned access. 1583 return allowsMisalignedMemoryAccesses(VT, AddrSpace, Alignment, Fast); 1584 } 1585 1586 1587 //===----------------------------------------------------------------------===// 1588 // TargetTransformInfo Helpers 1589 //===----------------------------------------------------------------------===// 1590 1591 int TargetLoweringBase::InstructionOpcodeToISD(unsigned Opcode) const { 1592 enum InstructionOpcodes { 1593 #define HANDLE_INST(NUM, OPCODE, CLASS) OPCODE = NUM, 1594 #define LAST_OTHER_INST(NUM) InstructionOpcodesCount = NUM 1595 #include "llvm/IR/Instruction.def" 1596 }; 1597 switch (static_cast<InstructionOpcodes>(Opcode)) { 1598 case Ret: return 0; 1599 case Br: return 0; 1600 case Switch: return 0; 1601 case IndirectBr: return 0; 1602 case Invoke: return 0; 1603 case Resume: return 0; 1604 case Unreachable: return 0; 1605 case CleanupRet: return 0; 1606 case CatchRet: return 0; 1607 case CatchPad: return 0; 1608 case CatchSwitch: return 0; 1609 case CleanupPad: return 0; 1610 case Add: return ISD::ADD; 1611 case FAdd: return ISD::FADD; 1612 case Sub: return ISD::SUB; 1613 case FSub: return ISD::FSUB; 1614 case Mul: return ISD::MUL; 1615 case FMul: return ISD::FMUL; 1616 case UDiv: return ISD::UDIV; 1617 case SDiv: return ISD::SDIV; 1618 case FDiv: return ISD::FDIV; 1619 case URem: return ISD::UREM; 1620 case SRem: return ISD::SREM; 1621 case FRem: return ISD::FREM; 1622 case Shl: return ISD::SHL; 1623 case LShr: return ISD::SRL; 1624 case AShr: return ISD::SRA; 1625 case And: return ISD::AND; 1626 case Or: return ISD::OR; 1627 case Xor: return ISD::XOR; 1628 case Alloca: return 0; 1629 case Load: return ISD::LOAD; 1630 case Store: return ISD::STORE; 1631 case GetElementPtr: return 0; 1632 case Fence: return 0; 1633 case AtomicCmpXchg: return 0; 1634 case AtomicRMW: return 0; 1635 case Trunc: return ISD::TRUNCATE; 1636 case ZExt: return ISD::ZERO_EXTEND; 1637 case SExt: return ISD::SIGN_EXTEND; 1638 case FPToUI: return ISD::FP_TO_UINT; 1639 case FPToSI: return ISD::FP_TO_SINT; 1640 case UIToFP: return ISD::UINT_TO_FP; 1641 case SIToFP: return ISD::SINT_TO_FP; 1642 case FPTrunc: return ISD::FP_ROUND; 1643 case FPExt: return ISD::FP_EXTEND; 1644 case PtrToInt: return ISD::BITCAST; 1645 case IntToPtr: return ISD::BITCAST; 1646 case BitCast: return ISD::BITCAST; 1647 case AddrSpaceCast: return ISD::ADDRSPACECAST; 1648 case ICmp: return ISD::SETCC; 1649 case FCmp: return ISD::SETCC; 1650 case PHI: return 0; 1651 case Call: return 0; 1652 case Select: return ISD::SELECT; 1653 case UserOp1: return 0; 1654 case UserOp2: return 0; 1655 case VAArg: return 0; 1656 case ExtractElement: return ISD::EXTRACT_VECTOR_ELT; 1657 case InsertElement: return ISD::INSERT_VECTOR_ELT; 1658 case ShuffleVector: return ISD::VECTOR_SHUFFLE; 1659 case ExtractValue: return ISD::MERGE_VALUES; 1660 case InsertValue: return ISD::MERGE_VALUES; 1661 case LandingPad: return 0; 1662 } 1663 1664 llvm_unreachable("Unknown instruction type encountered!"); 1665 } 1666 1667 std::pair<int, MVT> 1668 TargetLoweringBase::getTypeLegalizationCost(const DataLayout &DL, 1669 Type *Ty) const { 1670 LLVMContext &C = Ty->getContext(); 1671 EVT MTy = getValueType(DL, Ty); 1672 1673 int Cost = 1; 1674 // We keep legalizing the type until we find a legal kind. We assume that 1675 // the only operation that costs anything is the split. After splitting 1676 // we need to handle two types. 1677 while (true) { 1678 LegalizeKind LK = getTypeConversion(C, MTy); 1679 1680 if (LK.first == TypeLegal) 1681 return std::make_pair(Cost, MTy.getSimpleVT()); 1682 1683 if (LK.first == TypeSplitVector || LK.first == TypeExpandInteger) 1684 Cost *= 2; 1685 1686 // Do not loop with f128 type. 1687 if (MTy == LK.second) 1688 return std::make_pair(Cost, MTy.getSimpleVT()); 1689 1690 // Keep legalizing the type. 1691 MTy = LK.second; 1692 } 1693 } 1694 1695 Value *TargetLoweringBase::getSafeStackPointerLocation(IRBuilder<> &IRB) const { 1696 if (!TM.getTargetTriple().isAndroid()) 1697 return nullptr; 1698 1699 // Android provides a libc function to retrieve the address of the current 1700 // thread's unsafe stack pointer. 1701 Module *M = IRB.GetInsertBlock()->getParent()->getParent(); 1702 Type *StackPtrTy = Type::getInt8PtrTy(M->getContext()); 1703 Value *Fn = M->getOrInsertFunction("__safestack_pointer_address", 1704 StackPtrTy->getPointerTo(0), nullptr); 1705 return IRB.CreateCall(Fn); 1706 } 1707 1708 //===----------------------------------------------------------------------===// 1709 // Loop Strength Reduction hooks 1710 //===----------------------------------------------------------------------===// 1711 1712 /// isLegalAddressingMode - Return true if the addressing mode represented 1713 /// by AM is legal for this target, for a load/store of the specified type. 1714 bool TargetLoweringBase::isLegalAddressingMode(const DataLayout &DL, 1715 const AddrMode &AM, Type *Ty, 1716 unsigned AS) const { 1717 // The default implementation of this implements a conservative RISCy, r+r and 1718 // r+i addr mode. 1719 1720 // Allows a sign-extended 16-bit immediate field. 1721 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1) 1722 return false; 1723 1724 // No global is ever allowed as a base. 1725 if (AM.BaseGV) 1726 return false; 1727 1728 // Only support r+r, 1729 switch (AM.Scale) { 1730 case 0: // "r+i" or just "i", depending on HasBaseReg. 1731 break; 1732 case 1: 1733 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. 1734 return false; 1735 // Otherwise we have r+r or r+i. 1736 break; 1737 case 2: 1738 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. 1739 return false; 1740 // Allow 2*r as r+r. 1741 break; 1742 default: // Don't allow n * r 1743 return false; 1744 } 1745 1746 return true; 1747 } 1748