1 //===-- TargetLoweringBase.cpp - Implement the TargetLoweringBase class ---===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This implements the TargetLoweringBase class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "llvm/Target/TargetLowering.h" 15 #include "llvm/ADT/BitVector.h" 16 #include "llvm/ADT/STLExtras.h" 17 #include "llvm/ADT/Triple.h" 18 #include "llvm/CodeGen/Analysis.h" 19 #include "llvm/CodeGen/MachineFrameInfo.h" 20 #include "llvm/CodeGen/MachineFunction.h" 21 #include "llvm/CodeGen/MachineInstrBuilder.h" 22 #include "llvm/CodeGen/MachineJumpTableInfo.h" 23 #include "llvm/CodeGen/StackMaps.h" 24 #include "llvm/IR/DataLayout.h" 25 #include "llvm/IR/DerivedTypes.h" 26 #include "llvm/IR/GlobalVariable.h" 27 #include "llvm/IR/Mangler.h" 28 #include "llvm/MC/MCAsmInfo.h" 29 #include "llvm/MC/MCContext.h" 30 #include "llvm/MC/MCExpr.h" 31 #include "llvm/Support/CommandLine.h" 32 #include "llvm/Support/ErrorHandling.h" 33 #include "llvm/Support/MathExtras.h" 34 #include "llvm/Target/TargetLoweringObjectFile.h" 35 #include "llvm/Target/TargetMachine.h" 36 #include "llvm/Target/TargetRegisterInfo.h" 37 #include "llvm/Target/TargetSubtargetInfo.h" 38 #include <cctype> 39 using namespace llvm; 40 41 /// InitLibcallNames - Set default libcall names. 42 /// 43 static void InitLibcallNames(const char **Names, const Triple &TT) { 44 Names[RTLIB::SHL_I16] = "__ashlhi3"; 45 Names[RTLIB::SHL_I32] = "__ashlsi3"; 46 Names[RTLIB::SHL_I64] = "__ashldi3"; 47 Names[RTLIB::SHL_I128] = "__ashlti3"; 48 Names[RTLIB::SRL_I16] = "__lshrhi3"; 49 Names[RTLIB::SRL_I32] = "__lshrsi3"; 50 Names[RTLIB::SRL_I64] = "__lshrdi3"; 51 Names[RTLIB::SRL_I128] = "__lshrti3"; 52 Names[RTLIB::SRA_I16] = "__ashrhi3"; 53 Names[RTLIB::SRA_I32] = "__ashrsi3"; 54 Names[RTLIB::SRA_I64] = "__ashrdi3"; 55 Names[RTLIB::SRA_I128] = "__ashrti3"; 56 Names[RTLIB::MUL_I8] = "__mulqi3"; 57 Names[RTLIB::MUL_I16] = "__mulhi3"; 58 Names[RTLIB::MUL_I32] = "__mulsi3"; 59 Names[RTLIB::MUL_I64] = "__muldi3"; 60 Names[RTLIB::MUL_I128] = "__multi3"; 61 Names[RTLIB::MULO_I32] = "__mulosi4"; 62 Names[RTLIB::MULO_I64] = "__mulodi4"; 63 Names[RTLIB::MULO_I128] = "__muloti4"; 64 Names[RTLIB::SDIV_I8] = "__divqi3"; 65 Names[RTLIB::SDIV_I16] = "__divhi3"; 66 Names[RTLIB::SDIV_I32] = "__divsi3"; 67 Names[RTLIB::SDIV_I64] = "__divdi3"; 68 Names[RTLIB::SDIV_I128] = "__divti3"; 69 Names[RTLIB::UDIV_I8] = "__udivqi3"; 70 Names[RTLIB::UDIV_I16] = "__udivhi3"; 71 Names[RTLIB::UDIV_I32] = "__udivsi3"; 72 Names[RTLIB::UDIV_I64] = "__udivdi3"; 73 Names[RTLIB::UDIV_I128] = "__udivti3"; 74 Names[RTLIB::SREM_I8] = "__modqi3"; 75 Names[RTLIB::SREM_I16] = "__modhi3"; 76 Names[RTLIB::SREM_I32] = "__modsi3"; 77 Names[RTLIB::SREM_I64] = "__moddi3"; 78 Names[RTLIB::SREM_I128] = "__modti3"; 79 Names[RTLIB::UREM_I8] = "__umodqi3"; 80 Names[RTLIB::UREM_I16] = "__umodhi3"; 81 Names[RTLIB::UREM_I32] = "__umodsi3"; 82 Names[RTLIB::UREM_I64] = "__umoddi3"; 83 Names[RTLIB::UREM_I128] = "__umodti3"; 84 85 // These are generally not available. 86 Names[RTLIB::SDIVREM_I8] = nullptr; 87 Names[RTLIB::SDIVREM_I16] = nullptr; 88 Names[RTLIB::SDIVREM_I32] = nullptr; 89 Names[RTLIB::SDIVREM_I64] = nullptr; 90 Names[RTLIB::SDIVREM_I128] = nullptr; 91 Names[RTLIB::UDIVREM_I8] = nullptr; 92 Names[RTLIB::UDIVREM_I16] = nullptr; 93 Names[RTLIB::UDIVREM_I32] = nullptr; 94 Names[RTLIB::UDIVREM_I64] = nullptr; 95 Names[RTLIB::UDIVREM_I128] = nullptr; 96 97 Names[RTLIB::NEG_I32] = "__negsi2"; 98 Names[RTLIB::NEG_I64] = "__negdi2"; 99 Names[RTLIB::ADD_F32] = "__addsf3"; 100 Names[RTLIB::ADD_F64] = "__adddf3"; 101 Names[RTLIB::ADD_F80] = "__addxf3"; 102 Names[RTLIB::ADD_F128] = "__addtf3"; 103 Names[RTLIB::ADD_PPCF128] = "__gcc_qadd"; 104 Names[RTLIB::SUB_F32] = "__subsf3"; 105 Names[RTLIB::SUB_F64] = "__subdf3"; 106 Names[RTLIB::SUB_F80] = "__subxf3"; 107 Names[RTLIB::SUB_F128] = "__subtf3"; 108 Names[RTLIB::SUB_PPCF128] = "__gcc_qsub"; 109 Names[RTLIB::MUL_F32] = "__mulsf3"; 110 Names[RTLIB::MUL_F64] = "__muldf3"; 111 Names[RTLIB::MUL_F80] = "__mulxf3"; 112 Names[RTLIB::MUL_F128] = "__multf3"; 113 Names[RTLIB::MUL_PPCF128] = "__gcc_qmul"; 114 Names[RTLIB::DIV_F32] = "__divsf3"; 115 Names[RTLIB::DIV_F64] = "__divdf3"; 116 Names[RTLIB::DIV_F80] = "__divxf3"; 117 Names[RTLIB::DIV_F128] = "__divtf3"; 118 Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv"; 119 Names[RTLIB::REM_F32] = "fmodf"; 120 Names[RTLIB::REM_F64] = "fmod"; 121 Names[RTLIB::REM_F80] = "fmodl"; 122 Names[RTLIB::REM_F128] = "fmodl"; 123 Names[RTLIB::REM_PPCF128] = "fmodl"; 124 Names[RTLIB::FMA_F32] = "fmaf"; 125 Names[RTLIB::FMA_F64] = "fma"; 126 Names[RTLIB::FMA_F80] = "fmal"; 127 Names[RTLIB::FMA_F128] = "fmal"; 128 Names[RTLIB::FMA_PPCF128] = "fmal"; 129 Names[RTLIB::POWI_F32] = "__powisf2"; 130 Names[RTLIB::POWI_F64] = "__powidf2"; 131 Names[RTLIB::POWI_F80] = "__powixf2"; 132 Names[RTLIB::POWI_F128] = "__powitf2"; 133 Names[RTLIB::POWI_PPCF128] = "__powitf2"; 134 Names[RTLIB::SQRT_F32] = "sqrtf"; 135 Names[RTLIB::SQRT_F64] = "sqrt"; 136 Names[RTLIB::SQRT_F80] = "sqrtl"; 137 Names[RTLIB::SQRT_F128] = "sqrtl"; 138 Names[RTLIB::SQRT_PPCF128] = "sqrtl"; 139 Names[RTLIB::LOG_F32] = "logf"; 140 Names[RTLIB::LOG_F64] = "log"; 141 Names[RTLIB::LOG_F80] = "logl"; 142 Names[RTLIB::LOG_F128] = "logl"; 143 Names[RTLIB::LOG_PPCF128] = "logl"; 144 Names[RTLIB::LOG2_F32] = "log2f"; 145 Names[RTLIB::LOG2_F64] = "log2"; 146 Names[RTLIB::LOG2_F80] = "log2l"; 147 Names[RTLIB::LOG2_F128] = "log2l"; 148 Names[RTLIB::LOG2_PPCF128] = "log2l"; 149 Names[RTLIB::LOG10_F32] = "log10f"; 150 Names[RTLIB::LOG10_F64] = "log10"; 151 Names[RTLIB::LOG10_F80] = "log10l"; 152 Names[RTLIB::LOG10_F128] = "log10l"; 153 Names[RTLIB::LOG10_PPCF128] = "log10l"; 154 Names[RTLIB::EXP_F32] = "expf"; 155 Names[RTLIB::EXP_F64] = "exp"; 156 Names[RTLIB::EXP_F80] = "expl"; 157 Names[RTLIB::EXP_F128] = "expl"; 158 Names[RTLIB::EXP_PPCF128] = "expl"; 159 Names[RTLIB::EXP2_F32] = "exp2f"; 160 Names[RTLIB::EXP2_F64] = "exp2"; 161 Names[RTLIB::EXP2_F80] = "exp2l"; 162 Names[RTLIB::EXP2_F128] = "exp2l"; 163 Names[RTLIB::EXP2_PPCF128] = "exp2l"; 164 Names[RTLIB::SIN_F32] = "sinf"; 165 Names[RTLIB::SIN_F64] = "sin"; 166 Names[RTLIB::SIN_F80] = "sinl"; 167 Names[RTLIB::SIN_F128] = "sinl"; 168 Names[RTLIB::SIN_PPCF128] = "sinl"; 169 Names[RTLIB::COS_F32] = "cosf"; 170 Names[RTLIB::COS_F64] = "cos"; 171 Names[RTLIB::COS_F80] = "cosl"; 172 Names[RTLIB::COS_F128] = "cosl"; 173 Names[RTLIB::COS_PPCF128] = "cosl"; 174 Names[RTLIB::POW_F32] = "powf"; 175 Names[RTLIB::POW_F64] = "pow"; 176 Names[RTLIB::POW_F80] = "powl"; 177 Names[RTLIB::POW_F128] = "powl"; 178 Names[RTLIB::POW_PPCF128] = "powl"; 179 Names[RTLIB::CEIL_F32] = "ceilf"; 180 Names[RTLIB::CEIL_F64] = "ceil"; 181 Names[RTLIB::CEIL_F80] = "ceill"; 182 Names[RTLIB::CEIL_F128] = "ceill"; 183 Names[RTLIB::CEIL_PPCF128] = "ceill"; 184 Names[RTLIB::TRUNC_F32] = "truncf"; 185 Names[RTLIB::TRUNC_F64] = "trunc"; 186 Names[RTLIB::TRUNC_F80] = "truncl"; 187 Names[RTLIB::TRUNC_F128] = "truncl"; 188 Names[RTLIB::TRUNC_PPCF128] = "truncl"; 189 Names[RTLIB::RINT_F32] = "rintf"; 190 Names[RTLIB::RINT_F64] = "rint"; 191 Names[RTLIB::RINT_F80] = "rintl"; 192 Names[RTLIB::RINT_F128] = "rintl"; 193 Names[RTLIB::RINT_PPCF128] = "rintl"; 194 Names[RTLIB::NEARBYINT_F32] = "nearbyintf"; 195 Names[RTLIB::NEARBYINT_F64] = "nearbyint"; 196 Names[RTLIB::NEARBYINT_F80] = "nearbyintl"; 197 Names[RTLIB::NEARBYINT_F128] = "nearbyintl"; 198 Names[RTLIB::NEARBYINT_PPCF128] = "nearbyintl"; 199 Names[RTLIB::ROUND_F32] = "roundf"; 200 Names[RTLIB::ROUND_F64] = "round"; 201 Names[RTLIB::ROUND_F80] = "roundl"; 202 Names[RTLIB::ROUND_F128] = "roundl"; 203 Names[RTLIB::ROUND_PPCF128] = "roundl"; 204 Names[RTLIB::FLOOR_F32] = "floorf"; 205 Names[RTLIB::FLOOR_F64] = "floor"; 206 Names[RTLIB::FLOOR_F80] = "floorl"; 207 Names[RTLIB::FLOOR_F128] = "floorl"; 208 Names[RTLIB::FLOOR_PPCF128] = "floorl"; 209 Names[RTLIB::ROUND_F32] = "roundf"; 210 Names[RTLIB::ROUND_F64] = "round"; 211 Names[RTLIB::ROUND_F80] = "roundl"; 212 Names[RTLIB::ROUND_F128] = "roundl"; 213 Names[RTLIB::ROUND_PPCF128] = "roundl"; 214 Names[RTLIB::COPYSIGN_F32] = "copysignf"; 215 Names[RTLIB::COPYSIGN_F64] = "copysign"; 216 Names[RTLIB::COPYSIGN_F80] = "copysignl"; 217 Names[RTLIB::COPYSIGN_F128] = "copysignl"; 218 Names[RTLIB::COPYSIGN_PPCF128] = "copysignl"; 219 Names[RTLIB::FPEXT_F64_F128] = "__extenddftf2"; 220 Names[RTLIB::FPEXT_F32_F128] = "__extendsftf2"; 221 Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2"; 222 Names[RTLIB::FPEXT_F16_F32] = "__gnu_h2f_ieee"; 223 Names[RTLIB::FPROUND_F32_F16] = "__gnu_f2h_ieee"; 224 Names[RTLIB::FPROUND_F64_F16] = "__truncdfhf2"; 225 Names[RTLIB::FPROUND_F80_F16] = "__truncxfhf2"; 226 Names[RTLIB::FPROUND_F128_F16] = "__trunctfhf2"; 227 Names[RTLIB::FPROUND_PPCF128_F16] = "__trunctfhf2"; 228 Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2"; 229 Names[RTLIB::FPROUND_F80_F32] = "__truncxfsf2"; 230 Names[RTLIB::FPROUND_F128_F32] = "__trunctfsf2"; 231 Names[RTLIB::FPROUND_PPCF128_F32] = "__trunctfsf2"; 232 Names[RTLIB::FPROUND_F80_F64] = "__truncxfdf2"; 233 Names[RTLIB::FPROUND_F128_F64] = "__trunctfdf2"; 234 Names[RTLIB::FPROUND_PPCF128_F64] = "__trunctfdf2"; 235 Names[RTLIB::FPTOSINT_F32_I8] = "__fixsfqi"; 236 Names[RTLIB::FPTOSINT_F32_I16] = "__fixsfhi"; 237 Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi"; 238 Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi"; 239 Names[RTLIB::FPTOSINT_F32_I128] = "__fixsfti"; 240 Names[RTLIB::FPTOSINT_F64_I8] = "__fixdfqi"; 241 Names[RTLIB::FPTOSINT_F64_I16] = "__fixdfhi"; 242 Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi"; 243 Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi"; 244 Names[RTLIB::FPTOSINT_F64_I128] = "__fixdfti"; 245 Names[RTLIB::FPTOSINT_F80_I32] = "__fixxfsi"; 246 Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi"; 247 Names[RTLIB::FPTOSINT_F80_I128] = "__fixxfti"; 248 Names[RTLIB::FPTOSINT_F128_I32] = "__fixtfsi"; 249 Names[RTLIB::FPTOSINT_F128_I64] = "__fixtfdi"; 250 Names[RTLIB::FPTOSINT_F128_I128] = "__fixtfti"; 251 Names[RTLIB::FPTOSINT_PPCF128_I32] = "__fixtfsi"; 252 Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi"; 253 Names[RTLIB::FPTOSINT_PPCF128_I128] = "__fixtfti"; 254 Names[RTLIB::FPTOUINT_F32_I8] = "__fixunssfqi"; 255 Names[RTLIB::FPTOUINT_F32_I16] = "__fixunssfhi"; 256 Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi"; 257 Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi"; 258 Names[RTLIB::FPTOUINT_F32_I128] = "__fixunssfti"; 259 Names[RTLIB::FPTOUINT_F64_I8] = "__fixunsdfqi"; 260 Names[RTLIB::FPTOUINT_F64_I16] = "__fixunsdfhi"; 261 Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi"; 262 Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi"; 263 Names[RTLIB::FPTOUINT_F64_I128] = "__fixunsdfti"; 264 Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi"; 265 Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi"; 266 Names[RTLIB::FPTOUINT_F80_I128] = "__fixunsxfti"; 267 Names[RTLIB::FPTOUINT_F128_I32] = "__fixunstfsi"; 268 Names[RTLIB::FPTOUINT_F128_I64] = "__fixunstfdi"; 269 Names[RTLIB::FPTOUINT_F128_I128] = "__fixunstfti"; 270 Names[RTLIB::FPTOUINT_PPCF128_I32] = "__fixunstfsi"; 271 Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi"; 272 Names[RTLIB::FPTOUINT_PPCF128_I128] = "__fixunstfti"; 273 Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf"; 274 Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf"; 275 Names[RTLIB::SINTTOFP_I32_F80] = "__floatsixf"; 276 Names[RTLIB::SINTTOFP_I32_F128] = "__floatsitf"; 277 Names[RTLIB::SINTTOFP_I32_PPCF128] = "__floatsitf"; 278 Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf"; 279 Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf"; 280 Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf"; 281 Names[RTLIB::SINTTOFP_I64_F128] = "__floatditf"; 282 Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf"; 283 Names[RTLIB::SINTTOFP_I128_F32] = "__floattisf"; 284 Names[RTLIB::SINTTOFP_I128_F64] = "__floattidf"; 285 Names[RTLIB::SINTTOFP_I128_F80] = "__floattixf"; 286 Names[RTLIB::SINTTOFP_I128_F128] = "__floattitf"; 287 Names[RTLIB::SINTTOFP_I128_PPCF128] = "__floattitf"; 288 Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf"; 289 Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf"; 290 Names[RTLIB::UINTTOFP_I32_F80] = "__floatunsixf"; 291 Names[RTLIB::UINTTOFP_I32_F128] = "__floatunsitf"; 292 Names[RTLIB::UINTTOFP_I32_PPCF128] = "__floatunsitf"; 293 Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf"; 294 Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf"; 295 Names[RTLIB::UINTTOFP_I64_F80] = "__floatundixf"; 296 Names[RTLIB::UINTTOFP_I64_F128] = "__floatunditf"; 297 Names[RTLIB::UINTTOFP_I64_PPCF128] = "__floatunditf"; 298 Names[RTLIB::UINTTOFP_I128_F32] = "__floatuntisf"; 299 Names[RTLIB::UINTTOFP_I128_F64] = "__floatuntidf"; 300 Names[RTLIB::UINTTOFP_I128_F80] = "__floatuntixf"; 301 Names[RTLIB::UINTTOFP_I128_F128] = "__floatuntitf"; 302 Names[RTLIB::UINTTOFP_I128_PPCF128] = "__floatuntitf"; 303 Names[RTLIB::OEQ_F32] = "__eqsf2"; 304 Names[RTLIB::OEQ_F64] = "__eqdf2"; 305 Names[RTLIB::OEQ_F128] = "__eqtf2"; 306 Names[RTLIB::UNE_F32] = "__nesf2"; 307 Names[RTLIB::UNE_F64] = "__nedf2"; 308 Names[RTLIB::UNE_F128] = "__netf2"; 309 Names[RTLIB::OGE_F32] = "__gesf2"; 310 Names[RTLIB::OGE_F64] = "__gedf2"; 311 Names[RTLIB::OGE_F128] = "__getf2"; 312 Names[RTLIB::OLT_F32] = "__ltsf2"; 313 Names[RTLIB::OLT_F64] = "__ltdf2"; 314 Names[RTLIB::OLT_F128] = "__lttf2"; 315 Names[RTLIB::OLE_F32] = "__lesf2"; 316 Names[RTLIB::OLE_F64] = "__ledf2"; 317 Names[RTLIB::OLE_F128] = "__letf2"; 318 Names[RTLIB::OGT_F32] = "__gtsf2"; 319 Names[RTLIB::OGT_F64] = "__gtdf2"; 320 Names[RTLIB::OGT_F128] = "__gttf2"; 321 Names[RTLIB::UO_F32] = "__unordsf2"; 322 Names[RTLIB::UO_F64] = "__unorddf2"; 323 Names[RTLIB::UO_F128] = "__unordtf2"; 324 Names[RTLIB::O_F32] = "__unordsf2"; 325 Names[RTLIB::O_F64] = "__unorddf2"; 326 Names[RTLIB::O_F128] = "__unordtf2"; 327 Names[RTLIB::MEMCPY] = "memcpy"; 328 Names[RTLIB::MEMMOVE] = "memmove"; 329 Names[RTLIB::MEMSET] = "memset"; 330 Names[RTLIB::UNWIND_RESUME] = "_Unwind_Resume"; 331 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1] = "__sync_val_compare_and_swap_1"; 332 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2] = "__sync_val_compare_and_swap_2"; 333 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4] = "__sync_val_compare_and_swap_4"; 334 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8] = "__sync_val_compare_and_swap_8"; 335 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_16] = "__sync_val_compare_and_swap_16"; 336 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_1] = "__sync_lock_test_and_set_1"; 337 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_2] = "__sync_lock_test_and_set_2"; 338 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_4] = "__sync_lock_test_and_set_4"; 339 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_8] = "__sync_lock_test_and_set_8"; 340 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_16] = "__sync_lock_test_and_set_16"; 341 Names[RTLIB::SYNC_FETCH_AND_ADD_1] = "__sync_fetch_and_add_1"; 342 Names[RTLIB::SYNC_FETCH_AND_ADD_2] = "__sync_fetch_and_add_2"; 343 Names[RTLIB::SYNC_FETCH_AND_ADD_4] = "__sync_fetch_and_add_4"; 344 Names[RTLIB::SYNC_FETCH_AND_ADD_8] = "__sync_fetch_and_add_8"; 345 Names[RTLIB::SYNC_FETCH_AND_ADD_16] = "__sync_fetch_and_add_16"; 346 Names[RTLIB::SYNC_FETCH_AND_SUB_1] = "__sync_fetch_and_sub_1"; 347 Names[RTLIB::SYNC_FETCH_AND_SUB_2] = "__sync_fetch_and_sub_2"; 348 Names[RTLIB::SYNC_FETCH_AND_SUB_4] = "__sync_fetch_and_sub_4"; 349 Names[RTLIB::SYNC_FETCH_AND_SUB_8] = "__sync_fetch_and_sub_8"; 350 Names[RTLIB::SYNC_FETCH_AND_SUB_16] = "__sync_fetch_and_sub_16"; 351 Names[RTLIB::SYNC_FETCH_AND_AND_1] = "__sync_fetch_and_and_1"; 352 Names[RTLIB::SYNC_FETCH_AND_AND_2] = "__sync_fetch_and_and_2"; 353 Names[RTLIB::SYNC_FETCH_AND_AND_4] = "__sync_fetch_and_and_4"; 354 Names[RTLIB::SYNC_FETCH_AND_AND_8] = "__sync_fetch_and_and_8"; 355 Names[RTLIB::SYNC_FETCH_AND_AND_16] = "__sync_fetch_and_and_16"; 356 Names[RTLIB::SYNC_FETCH_AND_OR_1] = "__sync_fetch_and_or_1"; 357 Names[RTLIB::SYNC_FETCH_AND_OR_2] = "__sync_fetch_and_or_2"; 358 Names[RTLIB::SYNC_FETCH_AND_OR_4] = "__sync_fetch_and_or_4"; 359 Names[RTLIB::SYNC_FETCH_AND_OR_8] = "__sync_fetch_and_or_8"; 360 Names[RTLIB::SYNC_FETCH_AND_OR_16] = "__sync_fetch_and_or_16"; 361 Names[RTLIB::SYNC_FETCH_AND_XOR_1] = "__sync_fetch_and_xor_1"; 362 Names[RTLIB::SYNC_FETCH_AND_XOR_2] = "__sync_fetch_and_xor_2"; 363 Names[RTLIB::SYNC_FETCH_AND_XOR_4] = "__sync_fetch_and_xor_4"; 364 Names[RTLIB::SYNC_FETCH_AND_XOR_8] = "__sync_fetch_and_xor_8"; 365 Names[RTLIB::SYNC_FETCH_AND_XOR_16] = "__sync_fetch_and_xor_16"; 366 Names[RTLIB::SYNC_FETCH_AND_NAND_1] = "__sync_fetch_and_nand_1"; 367 Names[RTLIB::SYNC_FETCH_AND_NAND_2] = "__sync_fetch_and_nand_2"; 368 Names[RTLIB::SYNC_FETCH_AND_NAND_4] = "__sync_fetch_and_nand_4"; 369 Names[RTLIB::SYNC_FETCH_AND_NAND_8] = "__sync_fetch_and_nand_8"; 370 Names[RTLIB::SYNC_FETCH_AND_NAND_16] = "__sync_fetch_and_nand_16"; 371 Names[RTLIB::SYNC_FETCH_AND_MAX_1] = "__sync_fetch_and_max_1"; 372 Names[RTLIB::SYNC_FETCH_AND_MAX_2] = "__sync_fetch_and_max_2"; 373 Names[RTLIB::SYNC_FETCH_AND_MAX_4] = "__sync_fetch_and_max_4"; 374 Names[RTLIB::SYNC_FETCH_AND_MAX_8] = "__sync_fetch_and_max_8"; 375 Names[RTLIB::SYNC_FETCH_AND_MAX_16] = "__sync_fetch_and_max_16"; 376 Names[RTLIB::SYNC_FETCH_AND_UMAX_1] = "__sync_fetch_and_umax_1"; 377 Names[RTLIB::SYNC_FETCH_AND_UMAX_2] = "__sync_fetch_and_umax_2"; 378 Names[RTLIB::SYNC_FETCH_AND_UMAX_4] = "__sync_fetch_and_umax_4"; 379 Names[RTLIB::SYNC_FETCH_AND_UMAX_8] = "__sync_fetch_and_umax_8"; 380 Names[RTLIB::SYNC_FETCH_AND_UMAX_16] = "__sync_fetch_and_umax_16"; 381 Names[RTLIB::SYNC_FETCH_AND_MIN_1] = "__sync_fetch_and_min_1"; 382 Names[RTLIB::SYNC_FETCH_AND_MIN_2] = "__sync_fetch_and_min_2"; 383 Names[RTLIB::SYNC_FETCH_AND_MIN_4] = "__sync_fetch_and_min_4"; 384 Names[RTLIB::SYNC_FETCH_AND_MIN_8] = "__sync_fetch_and_min_8"; 385 Names[RTLIB::SYNC_FETCH_AND_MIN_16] = "__sync_fetch_and_min_16"; 386 Names[RTLIB::SYNC_FETCH_AND_UMIN_1] = "__sync_fetch_and_umin_1"; 387 Names[RTLIB::SYNC_FETCH_AND_UMIN_2] = "__sync_fetch_and_umin_2"; 388 Names[RTLIB::SYNC_FETCH_AND_UMIN_4] = "__sync_fetch_and_umin_4"; 389 Names[RTLIB::SYNC_FETCH_AND_UMIN_8] = "__sync_fetch_and_umin_8"; 390 Names[RTLIB::SYNC_FETCH_AND_UMIN_16] = "__sync_fetch_and_umin_16"; 391 392 if (TT.getEnvironment() == Triple::GNU) { 393 Names[RTLIB::SINCOS_F32] = "sincosf"; 394 Names[RTLIB::SINCOS_F64] = "sincos"; 395 Names[RTLIB::SINCOS_F80] = "sincosl"; 396 Names[RTLIB::SINCOS_F128] = "sincosl"; 397 Names[RTLIB::SINCOS_PPCF128] = "sincosl"; 398 } else { 399 // These are generally not available. 400 Names[RTLIB::SINCOS_F32] = nullptr; 401 Names[RTLIB::SINCOS_F64] = nullptr; 402 Names[RTLIB::SINCOS_F80] = nullptr; 403 Names[RTLIB::SINCOS_F128] = nullptr; 404 Names[RTLIB::SINCOS_PPCF128] = nullptr; 405 } 406 407 if (TT.getOS() != Triple::OpenBSD) { 408 Names[RTLIB::STACKPROTECTOR_CHECK_FAIL] = "__stack_chk_fail"; 409 } else { 410 // These are generally not available. 411 Names[RTLIB::STACKPROTECTOR_CHECK_FAIL] = nullptr; 412 } 413 } 414 415 /// InitLibcallCallingConvs - Set default libcall CallingConvs. 416 /// 417 static void InitLibcallCallingConvs(CallingConv::ID *CCs) { 418 for (int i = 0; i < RTLIB::UNKNOWN_LIBCALL; ++i) { 419 CCs[i] = CallingConv::C; 420 } 421 } 422 423 /// getFPEXT - Return the FPEXT_*_* value for the given types, or 424 /// UNKNOWN_LIBCALL if there is none. 425 RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) { 426 if (OpVT == MVT::f16) { 427 if (RetVT == MVT::f32) 428 return FPEXT_F16_F32; 429 } else if (OpVT == MVT::f32) { 430 if (RetVT == MVT::f64) 431 return FPEXT_F32_F64; 432 if (RetVT == MVT::f128) 433 return FPEXT_F32_F128; 434 } else if (OpVT == MVT::f64) { 435 if (RetVT == MVT::f128) 436 return FPEXT_F64_F128; 437 } 438 439 return UNKNOWN_LIBCALL; 440 } 441 442 /// getFPROUND - Return the FPROUND_*_* value for the given types, or 443 /// UNKNOWN_LIBCALL if there is none. 444 RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) { 445 if (RetVT == MVT::f16) { 446 if (OpVT == MVT::f32) 447 return FPROUND_F32_F16; 448 if (OpVT == MVT::f64) 449 return FPROUND_F64_F16; 450 if (OpVT == MVT::f80) 451 return FPROUND_F80_F16; 452 if (OpVT == MVT::f128) 453 return FPROUND_F128_F16; 454 if (OpVT == MVT::ppcf128) 455 return FPROUND_PPCF128_F16; 456 } else if (RetVT == MVT::f32) { 457 if (OpVT == MVT::f64) 458 return FPROUND_F64_F32; 459 if (OpVT == MVT::f80) 460 return FPROUND_F80_F32; 461 if (OpVT == MVT::f128) 462 return FPROUND_F128_F32; 463 if (OpVT == MVT::ppcf128) 464 return FPROUND_PPCF128_F32; 465 } else if (RetVT == MVT::f64) { 466 if (OpVT == MVT::f80) 467 return FPROUND_F80_F64; 468 if (OpVT == MVT::f128) 469 return FPROUND_F128_F64; 470 if (OpVT == MVT::ppcf128) 471 return FPROUND_PPCF128_F64; 472 } 473 474 return UNKNOWN_LIBCALL; 475 } 476 477 /// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or 478 /// UNKNOWN_LIBCALL if there is none. 479 RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT, EVT RetVT) { 480 if (OpVT == MVT::f32) { 481 if (RetVT == MVT::i8) 482 return FPTOSINT_F32_I8; 483 if (RetVT == MVT::i16) 484 return FPTOSINT_F32_I16; 485 if (RetVT == MVT::i32) 486 return FPTOSINT_F32_I32; 487 if (RetVT == MVT::i64) 488 return FPTOSINT_F32_I64; 489 if (RetVT == MVT::i128) 490 return FPTOSINT_F32_I128; 491 } else if (OpVT == MVT::f64) { 492 if (RetVT == MVT::i8) 493 return FPTOSINT_F64_I8; 494 if (RetVT == MVT::i16) 495 return FPTOSINT_F64_I16; 496 if (RetVT == MVT::i32) 497 return FPTOSINT_F64_I32; 498 if (RetVT == MVT::i64) 499 return FPTOSINT_F64_I64; 500 if (RetVT == MVT::i128) 501 return FPTOSINT_F64_I128; 502 } else if (OpVT == MVT::f80) { 503 if (RetVT == MVT::i32) 504 return FPTOSINT_F80_I32; 505 if (RetVT == MVT::i64) 506 return FPTOSINT_F80_I64; 507 if (RetVT == MVT::i128) 508 return FPTOSINT_F80_I128; 509 } else if (OpVT == MVT::f128) { 510 if (RetVT == MVT::i32) 511 return FPTOSINT_F128_I32; 512 if (RetVT == MVT::i64) 513 return FPTOSINT_F128_I64; 514 if (RetVT == MVT::i128) 515 return FPTOSINT_F128_I128; 516 } else if (OpVT == MVT::ppcf128) { 517 if (RetVT == MVT::i32) 518 return FPTOSINT_PPCF128_I32; 519 if (RetVT == MVT::i64) 520 return FPTOSINT_PPCF128_I64; 521 if (RetVT == MVT::i128) 522 return FPTOSINT_PPCF128_I128; 523 } 524 return UNKNOWN_LIBCALL; 525 } 526 527 /// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or 528 /// UNKNOWN_LIBCALL if there is none. 529 RTLIB::Libcall RTLIB::getFPTOUINT(EVT OpVT, EVT RetVT) { 530 if (OpVT == MVT::f32) { 531 if (RetVT == MVT::i8) 532 return FPTOUINT_F32_I8; 533 if (RetVT == MVT::i16) 534 return FPTOUINT_F32_I16; 535 if (RetVT == MVT::i32) 536 return FPTOUINT_F32_I32; 537 if (RetVT == MVT::i64) 538 return FPTOUINT_F32_I64; 539 if (RetVT == MVT::i128) 540 return FPTOUINT_F32_I128; 541 } else if (OpVT == MVT::f64) { 542 if (RetVT == MVT::i8) 543 return FPTOUINT_F64_I8; 544 if (RetVT == MVT::i16) 545 return FPTOUINT_F64_I16; 546 if (RetVT == MVT::i32) 547 return FPTOUINT_F64_I32; 548 if (RetVT == MVT::i64) 549 return FPTOUINT_F64_I64; 550 if (RetVT == MVT::i128) 551 return FPTOUINT_F64_I128; 552 } else if (OpVT == MVT::f80) { 553 if (RetVT == MVT::i32) 554 return FPTOUINT_F80_I32; 555 if (RetVT == MVT::i64) 556 return FPTOUINT_F80_I64; 557 if (RetVT == MVT::i128) 558 return FPTOUINT_F80_I128; 559 } else if (OpVT == MVT::f128) { 560 if (RetVT == MVT::i32) 561 return FPTOUINT_F128_I32; 562 if (RetVT == MVT::i64) 563 return FPTOUINT_F128_I64; 564 if (RetVT == MVT::i128) 565 return FPTOUINT_F128_I128; 566 } else if (OpVT == MVT::ppcf128) { 567 if (RetVT == MVT::i32) 568 return FPTOUINT_PPCF128_I32; 569 if (RetVT == MVT::i64) 570 return FPTOUINT_PPCF128_I64; 571 if (RetVT == MVT::i128) 572 return FPTOUINT_PPCF128_I128; 573 } 574 return UNKNOWN_LIBCALL; 575 } 576 577 /// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or 578 /// UNKNOWN_LIBCALL if there is none. 579 RTLIB::Libcall RTLIB::getSINTTOFP(EVT OpVT, EVT RetVT) { 580 if (OpVT == MVT::i32) { 581 if (RetVT == MVT::f32) 582 return SINTTOFP_I32_F32; 583 if (RetVT == MVT::f64) 584 return SINTTOFP_I32_F64; 585 if (RetVT == MVT::f80) 586 return SINTTOFP_I32_F80; 587 if (RetVT == MVT::f128) 588 return SINTTOFP_I32_F128; 589 if (RetVT == MVT::ppcf128) 590 return SINTTOFP_I32_PPCF128; 591 } else if (OpVT == MVT::i64) { 592 if (RetVT == MVT::f32) 593 return SINTTOFP_I64_F32; 594 if (RetVT == MVT::f64) 595 return SINTTOFP_I64_F64; 596 if (RetVT == MVT::f80) 597 return SINTTOFP_I64_F80; 598 if (RetVT == MVT::f128) 599 return SINTTOFP_I64_F128; 600 if (RetVT == MVT::ppcf128) 601 return SINTTOFP_I64_PPCF128; 602 } else if (OpVT == MVT::i128) { 603 if (RetVT == MVT::f32) 604 return SINTTOFP_I128_F32; 605 if (RetVT == MVT::f64) 606 return SINTTOFP_I128_F64; 607 if (RetVT == MVT::f80) 608 return SINTTOFP_I128_F80; 609 if (RetVT == MVT::f128) 610 return SINTTOFP_I128_F128; 611 if (RetVT == MVT::ppcf128) 612 return SINTTOFP_I128_PPCF128; 613 } 614 return UNKNOWN_LIBCALL; 615 } 616 617 /// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or 618 /// UNKNOWN_LIBCALL if there is none. 619 RTLIB::Libcall RTLIB::getUINTTOFP(EVT OpVT, EVT RetVT) { 620 if (OpVT == MVT::i32) { 621 if (RetVT == MVT::f32) 622 return UINTTOFP_I32_F32; 623 if (RetVT == MVT::f64) 624 return UINTTOFP_I32_F64; 625 if (RetVT == MVT::f80) 626 return UINTTOFP_I32_F80; 627 if (RetVT == MVT::f128) 628 return UINTTOFP_I32_F128; 629 if (RetVT == MVT::ppcf128) 630 return UINTTOFP_I32_PPCF128; 631 } else if (OpVT == MVT::i64) { 632 if (RetVT == MVT::f32) 633 return UINTTOFP_I64_F32; 634 if (RetVT == MVT::f64) 635 return UINTTOFP_I64_F64; 636 if (RetVT == MVT::f80) 637 return UINTTOFP_I64_F80; 638 if (RetVT == MVT::f128) 639 return UINTTOFP_I64_F128; 640 if (RetVT == MVT::ppcf128) 641 return UINTTOFP_I64_PPCF128; 642 } else if (OpVT == MVT::i128) { 643 if (RetVT == MVT::f32) 644 return UINTTOFP_I128_F32; 645 if (RetVT == MVT::f64) 646 return UINTTOFP_I128_F64; 647 if (RetVT == MVT::f80) 648 return UINTTOFP_I128_F80; 649 if (RetVT == MVT::f128) 650 return UINTTOFP_I128_F128; 651 if (RetVT == MVT::ppcf128) 652 return UINTTOFP_I128_PPCF128; 653 } 654 return UNKNOWN_LIBCALL; 655 } 656 657 /// InitCmpLibcallCCs - Set default comparison libcall CC. 658 /// 659 static void InitCmpLibcallCCs(ISD::CondCode *CCs) { 660 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL); 661 CCs[RTLIB::OEQ_F32] = ISD::SETEQ; 662 CCs[RTLIB::OEQ_F64] = ISD::SETEQ; 663 CCs[RTLIB::OEQ_F128] = ISD::SETEQ; 664 CCs[RTLIB::UNE_F32] = ISD::SETNE; 665 CCs[RTLIB::UNE_F64] = ISD::SETNE; 666 CCs[RTLIB::UNE_F128] = ISD::SETNE; 667 CCs[RTLIB::OGE_F32] = ISD::SETGE; 668 CCs[RTLIB::OGE_F64] = ISD::SETGE; 669 CCs[RTLIB::OGE_F128] = ISD::SETGE; 670 CCs[RTLIB::OLT_F32] = ISD::SETLT; 671 CCs[RTLIB::OLT_F64] = ISD::SETLT; 672 CCs[RTLIB::OLT_F128] = ISD::SETLT; 673 CCs[RTLIB::OLE_F32] = ISD::SETLE; 674 CCs[RTLIB::OLE_F64] = ISD::SETLE; 675 CCs[RTLIB::OLE_F128] = ISD::SETLE; 676 CCs[RTLIB::OGT_F32] = ISD::SETGT; 677 CCs[RTLIB::OGT_F64] = ISD::SETGT; 678 CCs[RTLIB::OGT_F128] = ISD::SETGT; 679 CCs[RTLIB::UO_F32] = ISD::SETNE; 680 CCs[RTLIB::UO_F64] = ISD::SETNE; 681 CCs[RTLIB::UO_F128] = ISD::SETNE; 682 CCs[RTLIB::O_F32] = ISD::SETEQ; 683 CCs[RTLIB::O_F64] = ISD::SETEQ; 684 CCs[RTLIB::O_F128] = ISD::SETEQ; 685 } 686 687 /// NOTE: The constructor takes ownership of TLOF. 688 TargetLoweringBase::TargetLoweringBase(const TargetMachine &tm, 689 const TargetLoweringObjectFile *tlof) 690 : TM(tm), DL(TM.getSubtargetImpl()->getDataLayout()), TLOF(*tlof) { 691 initActions(); 692 693 // Perform these initializations only once. 694 IsLittleEndian = DL->isLittleEndian(); 695 MaxStoresPerMemset = MaxStoresPerMemcpy = MaxStoresPerMemmove = 8; 696 MaxStoresPerMemsetOptSize = MaxStoresPerMemcpyOptSize 697 = MaxStoresPerMemmoveOptSize = 4; 698 UseUnderscoreSetJmp = false; 699 UseUnderscoreLongJmp = false; 700 SelectIsExpensive = false; 701 HasMultipleConditionRegisters = false; 702 HasExtractBitsInsn = false; 703 IntDivIsCheap = false; 704 Pow2SDivIsCheap = false; 705 JumpIsExpensive = false; 706 PredictableSelectIsExpensive = false; 707 MaskAndBranchFoldingIsLegal = false; 708 HasFloatingPointExceptions = true; 709 StackPointerRegisterToSaveRestore = 0; 710 ExceptionPointerRegister = 0; 711 ExceptionSelectorRegister = 0; 712 BooleanContents = UndefinedBooleanContent; 713 BooleanFloatContents = UndefinedBooleanContent; 714 BooleanVectorContents = UndefinedBooleanContent; 715 SchedPreferenceInfo = Sched::ILP; 716 JumpBufSize = 0; 717 JumpBufAlignment = 0; 718 MinFunctionAlignment = 0; 719 PrefFunctionAlignment = 0; 720 PrefLoopAlignment = 0; 721 MinStackArgumentAlignment = 1; 722 InsertFencesForAtomic = false; 723 MinimumJumpTableEntries = 4; 724 725 InitLibcallNames(LibcallRoutineNames, Triple(TM.getTargetTriple())); 726 InitCmpLibcallCCs(CmpLibcallCCs); 727 InitLibcallCallingConvs(LibcallCallingConvs); 728 } 729 730 TargetLoweringBase::~TargetLoweringBase() { 731 delete &TLOF; 732 } 733 734 void TargetLoweringBase::initActions() { 735 // All operations default to being supported. 736 memset(OpActions, 0, sizeof(OpActions)); 737 memset(LoadExtActions, 0, sizeof(LoadExtActions)); 738 memset(TruncStoreActions, 0, sizeof(TruncStoreActions)); 739 memset(IndexedModeActions, 0, sizeof(IndexedModeActions)); 740 memset(CondCodeActions, 0, sizeof(CondCodeActions)); 741 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*)); 742 memset(TargetDAGCombineArray, 0, array_lengthof(TargetDAGCombineArray)); 743 744 // Set default actions for various operations. 745 for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) { 746 // Default all indexed load / store to expand. 747 for (unsigned IM = (unsigned)ISD::PRE_INC; 748 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) { 749 setIndexedLoadAction(IM, (MVT::SimpleValueType)VT, Expand); 750 setIndexedStoreAction(IM, (MVT::SimpleValueType)VT, Expand); 751 } 752 753 // Most backends expect to see the node which just returns the value loaded. 754 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, 755 (MVT::SimpleValueType)VT, Expand); 756 757 // These operations default to expand. 758 setOperationAction(ISD::FGETSIGN, (MVT::SimpleValueType)VT, Expand); 759 setOperationAction(ISD::CONCAT_VECTORS, (MVT::SimpleValueType)VT, Expand); 760 761 // These library functions default to expand. 762 setOperationAction(ISD::FROUND, (MVT::SimpleValueType)VT, Expand); 763 764 // These operations default to expand for vector types. 765 if (VT >= MVT::FIRST_VECTOR_VALUETYPE && 766 VT <= MVT::LAST_VECTOR_VALUETYPE) { 767 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand); 768 setOperationAction(ISD::ANY_EXTEND_VECTOR_INREG, 769 (MVT::SimpleValueType)VT, Expand); 770 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, 771 (MVT::SimpleValueType)VT, Expand); 772 setOperationAction(ISD::ZERO_EXTEND_VECTOR_INREG, 773 (MVT::SimpleValueType)VT, Expand); 774 } 775 } 776 777 // Most targets ignore the @llvm.prefetch intrinsic. 778 setOperationAction(ISD::PREFETCH, MVT::Other, Expand); 779 780 // ConstantFP nodes default to expand. Targets can either change this to 781 // Legal, in which case all fp constants are legal, or use isFPImmLegal() 782 // to optimize expansions for certain constants. 783 setOperationAction(ISD::ConstantFP, MVT::f16, Expand); 784 setOperationAction(ISD::ConstantFP, MVT::f32, Expand); 785 setOperationAction(ISD::ConstantFP, MVT::f64, Expand); 786 setOperationAction(ISD::ConstantFP, MVT::f80, Expand); 787 setOperationAction(ISD::ConstantFP, MVT::f128, Expand); 788 789 // These library functions default to expand. 790 setOperationAction(ISD::FLOG , MVT::f16, Expand); 791 setOperationAction(ISD::FLOG2, MVT::f16, Expand); 792 setOperationAction(ISD::FLOG10, MVT::f16, Expand); 793 setOperationAction(ISD::FEXP , MVT::f16, Expand); 794 setOperationAction(ISD::FEXP2, MVT::f16, Expand); 795 setOperationAction(ISD::FFLOOR, MVT::f16, Expand); 796 setOperationAction(ISD::FNEARBYINT, MVT::f16, Expand); 797 setOperationAction(ISD::FCEIL, MVT::f16, Expand); 798 setOperationAction(ISD::FRINT, MVT::f16, Expand); 799 setOperationAction(ISD::FTRUNC, MVT::f16, Expand); 800 setOperationAction(ISD::FROUND, MVT::f16, Expand); 801 setOperationAction(ISD::FLOG , MVT::f32, Expand); 802 setOperationAction(ISD::FLOG2, MVT::f32, Expand); 803 setOperationAction(ISD::FLOG10, MVT::f32, Expand); 804 setOperationAction(ISD::FEXP , MVT::f32, Expand); 805 setOperationAction(ISD::FEXP2, MVT::f32, Expand); 806 setOperationAction(ISD::FFLOOR, MVT::f32, Expand); 807 setOperationAction(ISD::FNEARBYINT, MVT::f32, Expand); 808 setOperationAction(ISD::FCEIL, MVT::f32, Expand); 809 setOperationAction(ISD::FRINT, MVT::f32, Expand); 810 setOperationAction(ISD::FTRUNC, MVT::f32, Expand); 811 setOperationAction(ISD::FROUND, MVT::f32, Expand); 812 setOperationAction(ISD::FLOG , MVT::f64, Expand); 813 setOperationAction(ISD::FLOG2, MVT::f64, Expand); 814 setOperationAction(ISD::FLOG10, MVT::f64, Expand); 815 setOperationAction(ISD::FEXP , MVT::f64, Expand); 816 setOperationAction(ISD::FEXP2, MVT::f64, Expand); 817 setOperationAction(ISD::FFLOOR, MVT::f64, Expand); 818 setOperationAction(ISD::FNEARBYINT, MVT::f64, Expand); 819 setOperationAction(ISD::FCEIL, MVT::f64, Expand); 820 setOperationAction(ISD::FRINT, MVT::f64, Expand); 821 setOperationAction(ISD::FTRUNC, MVT::f64, Expand); 822 setOperationAction(ISD::FROUND, MVT::f64, Expand); 823 setOperationAction(ISD::FLOG , MVT::f128, Expand); 824 setOperationAction(ISD::FLOG2, MVT::f128, Expand); 825 setOperationAction(ISD::FLOG10, MVT::f128, Expand); 826 setOperationAction(ISD::FEXP , MVT::f128, Expand); 827 setOperationAction(ISD::FEXP2, MVT::f128, Expand); 828 setOperationAction(ISD::FFLOOR, MVT::f128, Expand); 829 setOperationAction(ISD::FNEARBYINT, MVT::f128, Expand); 830 setOperationAction(ISD::FCEIL, MVT::f128, Expand); 831 setOperationAction(ISD::FRINT, MVT::f128, Expand); 832 setOperationAction(ISD::FTRUNC, MVT::f128, Expand); 833 setOperationAction(ISD::FROUND, MVT::f128, Expand); 834 835 // Default ISD::TRAP to expand (which turns it into abort). 836 setOperationAction(ISD::TRAP, MVT::Other, Expand); 837 838 // On most systems, DEBUGTRAP and TRAP have no difference. The "Expand" 839 // here is to inform DAG Legalizer to replace DEBUGTRAP with TRAP. 840 // 841 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Expand); 842 } 843 844 MVT TargetLoweringBase::getPointerTy(uint32_t AS) const { 845 return MVT::getIntegerVT(getPointerSizeInBits(AS)); 846 } 847 848 unsigned TargetLoweringBase::getPointerSizeInBits(uint32_t AS) const { 849 return DL->getPointerSizeInBits(AS); 850 } 851 852 unsigned TargetLoweringBase::getPointerTypeSizeInBits(Type *Ty) const { 853 assert(Ty->isPointerTy()); 854 return getPointerSizeInBits(Ty->getPointerAddressSpace()); 855 } 856 857 MVT TargetLoweringBase::getScalarShiftAmountTy(EVT LHSTy) const { 858 return MVT::getIntegerVT(8*DL->getPointerSize(0)); 859 } 860 861 EVT TargetLoweringBase::getShiftAmountTy(EVT LHSTy) const { 862 assert(LHSTy.isInteger() && "Shift amount is not an integer type!"); 863 if (LHSTy.isVector()) 864 return LHSTy; 865 return getScalarShiftAmountTy(LHSTy); 866 } 867 868 /// canOpTrap - Returns true if the operation can trap for the value type. 869 /// VT must be a legal type. 870 bool TargetLoweringBase::canOpTrap(unsigned Op, EVT VT) const { 871 assert(isTypeLegal(VT)); 872 switch (Op) { 873 default: 874 return false; 875 case ISD::FDIV: 876 case ISD::FREM: 877 case ISD::SDIV: 878 case ISD::UDIV: 879 case ISD::SREM: 880 case ISD::UREM: 881 return true; 882 } 883 } 884 885 886 static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT, 887 unsigned &NumIntermediates, 888 MVT &RegisterVT, 889 TargetLoweringBase *TLI) { 890 // Figure out the right, legal destination reg to copy into. 891 unsigned NumElts = VT.getVectorNumElements(); 892 MVT EltTy = VT.getVectorElementType(); 893 894 unsigned NumVectorRegs = 1; 895 896 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we 897 // could break down into LHS/RHS like LegalizeDAG does. 898 if (!isPowerOf2_32(NumElts)) { 899 NumVectorRegs = NumElts; 900 NumElts = 1; 901 } 902 903 // Divide the input until we get to a supported size. This will always 904 // end with a scalar if the target doesn't support vectors. 905 while (NumElts > 1 && !TLI->isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) { 906 NumElts >>= 1; 907 NumVectorRegs <<= 1; 908 } 909 910 NumIntermediates = NumVectorRegs; 911 912 MVT NewVT = MVT::getVectorVT(EltTy, NumElts); 913 if (!TLI->isTypeLegal(NewVT)) 914 NewVT = EltTy; 915 IntermediateVT = NewVT; 916 917 unsigned NewVTSize = NewVT.getSizeInBits(); 918 919 // Convert sizes such as i33 to i64. 920 if (!isPowerOf2_32(NewVTSize)) 921 NewVTSize = NextPowerOf2(NewVTSize); 922 923 MVT DestVT = TLI->getRegisterType(NewVT); 924 RegisterVT = DestVT; 925 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16. 926 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits()); 927 928 // Otherwise, promotion or legal types use the same number of registers as 929 // the vector decimated to the appropriate level. 930 return NumVectorRegs; 931 } 932 933 /// isLegalRC - Return true if the value types that can be represented by the 934 /// specified register class are all legal. 935 bool TargetLoweringBase::isLegalRC(const TargetRegisterClass *RC) const { 936 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end(); 937 I != E; ++I) { 938 if (isTypeLegal(*I)) 939 return true; 940 } 941 return false; 942 } 943 944 /// Replace/modify any TargetFrameIndex operands with a targte-dependent 945 /// sequence of memory operands that is recognized by PrologEpilogInserter. 946 MachineBasicBlock* 947 TargetLoweringBase::emitPatchPoint(MachineInstr *MI, 948 MachineBasicBlock *MBB) const { 949 MachineFunction &MF = *MI->getParent()->getParent(); 950 951 // MI changes inside this loop as we grow operands. 952 for(unsigned OperIdx = 0; OperIdx != MI->getNumOperands(); ++OperIdx) { 953 MachineOperand &MO = MI->getOperand(OperIdx); 954 if (!MO.isFI()) 955 continue; 956 957 // foldMemoryOperand builds a new MI after replacing a single FI operand 958 // with the canonical set of five x86 addressing-mode operands. 959 int FI = MO.getIndex(); 960 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), MI->getDesc()); 961 962 // Copy operands before the frame-index. 963 for (unsigned i = 0; i < OperIdx; ++i) 964 MIB.addOperand(MI->getOperand(i)); 965 // Add frame index operands: direct-mem-ref tag, #FI, offset. 966 MIB.addImm(StackMaps::DirectMemRefOp); 967 MIB.addOperand(MI->getOperand(OperIdx)); 968 MIB.addImm(0); 969 // Copy the operands after the frame index. 970 for (unsigned i = OperIdx + 1; i != MI->getNumOperands(); ++i) 971 MIB.addOperand(MI->getOperand(i)); 972 973 // Inherit previous memory operands. 974 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end()); 975 assert(MIB->mayLoad() && "Folded a stackmap use to a non-load!"); 976 977 // Add a new memory operand for this FI. 978 const MachineFrameInfo &MFI = *MF.getFrameInfo(); 979 assert(MFI.getObjectOffset(FI) != -1); 980 MachineMemOperand *MMO = MF.getMachineMemOperand( 981 MachinePointerInfo::getFixedStack(FI), MachineMemOperand::MOLoad, 982 TM.getSubtargetImpl()->getDataLayout()->getPointerSize(), 983 MFI.getObjectAlignment(FI)); 984 MIB->addMemOperand(MF, MMO); 985 986 // Replace the instruction and update the operand index. 987 MBB->insert(MachineBasicBlock::iterator(MI), MIB); 988 OperIdx += (MIB->getNumOperands() - MI->getNumOperands()) - 1; 989 MI->eraseFromParent(); 990 MI = MIB; 991 } 992 return MBB; 993 } 994 995 /// findRepresentativeClass - Return the largest legal super-reg register class 996 /// of the register class for the specified type and its associated "cost". 997 std::pair<const TargetRegisterClass*, uint8_t> 998 TargetLoweringBase::findRepresentativeClass(MVT VT) const { 999 const TargetRegisterInfo *TRI = 1000 getTargetMachine().getSubtargetImpl()->getRegisterInfo(); 1001 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy]; 1002 if (!RC) 1003 return std::make_pair(RC, 0); 1004 1005 // Compute the set of all super-register classes. 1006 BitVector SuperRegRC(TRI->getNumRegClasses()); 1007 for (SuperRegClassIterator RCI(RC, TRI); RCI.isValid(); ++RCI) 1008 SuperRegRC.setBitsInMask(RCI.getMask()); 1009 1010 // Find the first legal register class with the largest spill size. 1011 const TargetRegisterClass *BestRC = RC; 1012 for (int i = SuperRegRC.find_first(); i >= 0; i = SuperRegRC.find_next(i)) { 1013 const TargetRegisterClass *SuperRC = TRI->getRegClass(i); 1014 // We want the largest possible spill size. 1015 if (SuperRC->getSize() <= BestRC->getSize()) 1016 continue; 1017 if (!isLegalRC(SuperRC)) 1018 continue; 1019 BestRC = SuperRC; 1020 } 1021 return std::make_pair(BestRC, 1); 1022 } 1023 1024 /// computeRegisterProperties - Once all of the register classes are added, 1025 /// this allows us to compute derived properties we expose. 1026 void TargetLoweringBase::computeRegisterProperties() { 1027 assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE && 1028 "Too many value types for ValueTypeActions to hold!"); 1029 1030 // Everything defaults to needing one register. 1031 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) { 1032 NumRegistersForVT[i] = 1; 1033 RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i; 1034 } 1035 // ...except isVoid, which doesn't need any registers. 1036 NumRegistersForVT[MVT::isVoid] = 0; 1037 1038 // Find the largest integer register class. 1039 unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE; 1040 for (; RegClassForVT[LargestIntReg] == nullptr; --LargestIntReg) 1041 assert(LargestIntReg != MVT::i1 && "No integer registers defined!"); 1042 1043 // Every integer value type larger than this largest register takes twice as 1044 // many registers to represent as the previous ValueType. 1045 for (unsigned ExpandedReg = LargestIntReg + 1; 1046 ExpandedReg <= MVT::LAST_INTEGER_VALUETYPE; ++ExpandedReg) { 1047 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1]; 1048 RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg; 1049 TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1); 1050 ValueTypeActions.setTypeAction((MVT::SimpleValueType)ExpandedReg, 1051 TypeExpandInteger); 1052 } 1053 1054 // Inspect all of the ValueType's smaller than the largest integer 1055 // register to see which ones need promotion. 1056 unsigned LegalIntReg = LargestIntReg; 1057 for (unsigned IntReg = LargestIntReg - 1; 1058 IntReg >= (unsigned)MVT::i1; --IntReg) { 1059 MVT IVT = (MVT::SimpleValueType)IntReg; 1060 if (isTypeLegal(IVT)) { 1061 LegalIntReg = IntReg; 1062 } else { 1063 RegisterTypeForVT[IntReg] = TransformToType[IntReg] = 1064 (const MVT::SimpleValueType)LegalIntReg; 1065 ValueTypeActions.setTypeAction(IVT, TypePromoteInteger); 1066 } 1067 } 1068 1069 // ppcf128 type is really two f64's. 1070 if (!isTypeLegal(MVT::ppcf128)) { 1071 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64]; 1072 RegisterTypeForVT[MVT::ppcf128] = MVT::f64; 1073 TransformToType[MVT::ppcf128] = MVT::f64; 1074 ValueTypeActions.setTypeAction(MVT::ppcf128, TypeExpandFloat); 1075 } 1076 1077 // Decide how to handle f128. If the target does not have native f128 support, 1078 // expand it to i128 and we will be generating soft float library calls. 1079 if (!isTypeLegal(MVT::f128)) { 1080 NumRegistersForVT[MVT::f128] = NumRegistersForVT[MVT::i128]; 1081 RegisterTypeForVT[MVT::f128] = RegisterTypeForVT[MVT::i128]; 1082 TransformToType[MVT::f128] = MVT::i128; 1083 ValueTypeActions.setTypeAction(MVT::f128, TypeSoftenFloat); 1084 } 1085 1086 // Decide how to handle f64. If the target does not have native f64 support, 1087 // expand it to i64 and we will be generating soft float library calls. 1088 if (!isTypeLegal(MVT::f64)) { 1089 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64]; 1090 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64]; 1091 TransformToType[MVT::f64] = MVT::i64; 1092 ValueTypeActions.setTypeAction(MVT::f64, TypeSoftenFloat); 1093 } 1094 1095 // Decide how to handle f32. If the target does not have native support for 1096 // f32, promote it to f64 if it is legal. Otherwise, expand it to i32. 1097 if (!isTypeLegal(MVT::f32)) { 1098 if (isTypeLegal(MVT::f64)) { 1099 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::f64]; 1100 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::f64]; 1101 TransformToType[MVT::f32] = MVT::f64; 1102 ValueTypeActions.setTypeAction(MVT::f32, TypePromoteInteger); 1103 } else { 1104 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32]; 1105 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32]; 1106 TransformToType[MVT::f32] = MVT::i32; 1107 ValueTypeActions.setTypeAction(MVT::f32, TypeSoftenFloat); 1108 } 1109 } 1110 1111 if (!isTypeLegal(MVT::f16)) { 1112 NumRegistersForVT[MVT::f16] = NumRegistersForVT[MVT::i16]; 1113 RegisterTypeForVT[MVT::f16] = RegisterTypeForVT[MVT::i16]; 1114 TransformToType[MVT::f16] = MVT::i16; 1115 ValueTypeActions.setTypeAction(MVT::f16, TypeSoftenFloat); 1116 } 1117 1118 // Loop over all of the vector value types to see which need transformations. 1119 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE; 1120 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) { 1121 MVT VT = (MVT::SimpleValueType) i; 1122 if (isTypeLegal(VT)) 1123 continue; 1124 1125 MVT EltVT = VT.getVectorElementType(); 1126 unsigned NElts = VT.getVectorNumElements(); 1127 bool IsLegalWiderType = false; 1128 LegalizeTypeAction PreferredAction = getPreferredVectorAction(VT); 1129 switch (PreferredAction) { 1130 case TypePromoteInteger: { 1131 // Try to promote the elements of integer vectors. If no legal 1132 // promotion was found, fall through to the widen-vector method. 1133 for (unsigned nVT = i + 1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) { 1134 MVT SVT = (MVT::SimpleValueType) nVT; 1135 // Promote vectors of integers to vectors with the same number 1136 // of elements, with a wider element type. 1137 if (SVT.getVectorElementType().getSizeInBits() > EltVT.getSizeInBits() 1138 && SVT.getVectorNumElements() == NElts && isTypeLegal(SVT) 1139 && SVT.getScalarType().isInteger()) { 1140 TransformToType[i] = SVT; 1141 RegisterTypeForVT[i] = SVT; 1142 NumRegistersForVT[i] = 1; 1143 ValueTypeActions.setTypeAction(VT, TypePromoteInteger); 1144 IsLegalWiderType = true; 1145 break; 1146 } 1147 } 1148 if (IsLegalWiderType) 1149 break; 1150 } 1151 case TypeWidenVector: { 1152 // Try to widen the vector. 1153 for (unsigned nVT = i + 1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) { 1154 MVT SVT = (MVT::SimpleValueType) nVT; 1155 if (SVT.getVectorElementType() == EltVT 1156 && SVT.getVectorNumElements() > NElts && isTypeLegal(SVT)) { 1157 TransformToType[i] = SVT; 1158 RegisterTypeForVT[i] = SVT; 1159 NumRegistersForVT[i] = 1; 1160 ValueTypeActions.setTypeAction(VT, TypeWidenVector); 1161 IsLegalWiderType = true; 1162 break; 1163 } 1164 } 1165 if (IsLegalWiderType) 1166 break; 1167 } 1168 case TypeSplitVector: 1169 case TypeScalarizeVector: { 1170 MVT IntermediateVT; 1171 MVT RegisterVT; 1172 unsigned NumIntermediates; 1173 NumRegistersForVT[i] = getVectorTypeBreakdownMVT(VT, IntermediateVT, 1174 NumIntermediates, RegisterVT, this); 1175 RegisterTypeForVT[i] = RegisterVT; 1176 1177 MVT NVT = VT.getPow2VectorType(); 1178 if (NVT == VT) { 1179 // Type is already a power of 2. The default action is to split. 1180 TransformToType[i] = MVT::Other; 1181 if (PreferredAction == TypeScalarizeVector) 1182 ValueTypeActions.setTypeAction(VT, TypeScalarizeVector); 1183 else 1184 ValueTypeActions.setTypeAction(VT, TypeSplitVector); 1185 } else { 1186 TransformToType[i] = NVT; 1187 ValueTypeActions.setTypeAction(VT, TypeWidenVector); 1188 } 1189 break; 1190 } 1191 default: 1192 llvm_unreachable("Unknown vector legalization action!"); 1193 } 1194 } 1195 1196 // Determine the 'representative' register class for each value type. 1197 // An representative register class is the largest (meaning one which is 1198 // not a sub-register class / subreg register class) legal register class for 1199 // a group of value types. For example, on i386, i8, i16, and i32 1200 // representative would be GR32; while on x86_64 it's GR64. 1201 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) { 1202 const TargetRegisterClass* RRC; 1203 uint8_t Cost; 1204 std::tie(RRC, Cost) = findRepresentativeClass((MVT::SimpleValueType)i); 1205 RepRegClassForVT[i] = RRC; 1206 RepRegClassCostForVT[i] = Cost; 1207 } 1208 } 1209 1210 EVT TargetLoweringBase::getSetCCResultType(LLVMContext &, EVT VT) const { 1211 assert(!VT.isVector() && "No default SetCC type for vectors!"); 1212 return getPointerTy(0).SimpleTy; 1213 } 1214 1215 MVT::SimpleValueType TargetLoweringBase::getCmpLibcallReturnType() const { 1216 return MVT::i32; // return the default value 1217 } 1218 1219 /// getVectorTypeBreakdown - Vector types are broken down into some number of 1220 /// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32 1221 /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack. 1222 /// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86. 1223 /// 1224 /// This method returns the number of registers needed, and the VT for each 1225 /// register. It also returns the VT and quantity of the intermediate values 1226 /// before they are promoted/expanded. 1227 /// 1228 unsigned TargetLoweringBase::getVectorTypeBreakdown(LLVMContext &Context, EVT VT, 1229 EVT &IntermediateVT, 1230 unsigned &NumIntermediates, 1231 MVT &RegisterVT) const { 1232 unsigned NumElts = VT.getVectorNumElements(); 1233 1234 // If there is a wider vector type with the same element type as this one, 1235 // or a promoted vector type that has the same number of elements which 1236 // are wider, then we should convert to that legal vector type. 1237 // This handles things like <2 x float> -> <4 x float> and 1238 // <4 x i1> -> <4 x i32>. 1239 LegalizeTypeAction TA = getTypeAction(Context, VT); 1240 if (NumElts != 1 && (TA == TypeWidenVector || TA == TypePromoteInteger)) { 1241 EVT RegisterEVT = getTypeToTransformTo(Context, VT); 1242 if (isTypeLegal(RegisterEVT)) { 1243 IntermediateVT = RegisterEVT; 1244 RegisterVT = RegisterEVT.getSimpleVT(); 1245 NumIntermediates = 1; 1246 return 1; 1247 } 1248 } 1249 1250 // Figure out the right, legal destination reg to copy into. 1251 EVT EltTy = VT.getVectorElementType(); 1252 1253 unsigned NumVectorRegs = 1; 1254 1255 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we 1256 // could break down into LHS/RHS like LegalizeDAG does. 1257 if (!isPowerOf2_32(NumElts)) { 1258 NumVectorRegs = NumElts; 1259 NumElts = 1; 1260 } 1261 1262 // Divide the input until we get to a supported size. This will always 1263 // end with a scalar if the target doesn't support vectors. 1264 while (NumElts > 1 && !isTypeLegal( 1265 EVT::getVectorVT(Context, EltTy, NumElts))) { 1266 NumElts >>= 1; 1267 NumVectorRegs <<= 1; 1268 } 1269 1270 NumIntermediates = NumVectorRegs; 1271 1272 EVT NewVT = EVT::getVectorVT(Context, EltTy, NumElts); 1273 if (!isTypeLegal(NewVT)) 1274 NewVT = EltTy; 1275 IntermediateVT = NewVT; 1276 1277 MVT DestVT = getRegisterType(Context, NewVT); 1278 RegisterVT = DestVT; 1279 unsigned NewVTSize = NewVT.getSizeInBits(); 1280 1281 // Convert sizes such as i33 to i64. 1282 if (!isPowerOf2_32(NewVTSize)) 1283 NewVTSize = NextPowerOf2(NewVTSize); 1284 1285 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16. 1286 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits()); 1287 1288 // Otherwise, promotion or legal types use the same number of registers as 1289 // the vector decimated to the appropriate level. 1290 return NumVectorRegs; 1291 } 1292 1293 /// Get the EVTs and ArgFlags collections that represent the legalized return 1294 /// type of the given function. This does not require a DAG or a return value, 1295 /// and is suitable for use before any DAGs for the function are constructed. 1296 /// TODO: Move this out of TargetLowering.cpp. 1297 void llvm::GetReturnInfo(Type* ReturnType, AttributeSet attr, 1298 SmallVectorImpl<ISD::OutputArg> &Outs, 1299 const TargetLowering &TLI) { 1300 SmallVector<EVT, 4> ValueVTs; 1301 ComputeValueVTs(TLI, ReturnType, ValueVTs); 1302 unsigned NumValues = ValueVTs.size(); 1303 if (NumValues == 0) return; 1304 1305 for (unsigned j = 0, f = NumValues; j != f; ++j) { 1306 EVT VT = ValueVTs[j]; 1307 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 1308 1309 if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::SExt)) 1310 ExtendKind = ISD::SIGN_EXTEND; 1311 else if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::ZExt)) 1312 ExtendKind = ISD::ZERO_EXTEND; 1313 1314 // FIXME: C calling convention requires the return type to be promoted to 1315 // at least 32-bit. But this is not necessary for non-C calling 1316 // conventions. The frontend should mark functions whose return values 1317 // require promoting with signext or zeroext attributes. 1318 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) { 1319 MVT MinVT = TLI.getRegisterType(ReturnType->getContext(), MVT::i32); 1320 if (VT.bitsLT(MinVT)) 1321 VT = MinVT; 1322 } 1323 1324 unsigned NumParts = TLI.getNumRegisters(ReturnType->getContext(), VT); 1325 MVT PartVT = TLI.getRegisterType(ReturnType->getContext(), VT); 1326 1327 // 'inreg' on function refers to return value 1328 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy(); 1329 if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::InReg)) 1330 Flags.setInReg(); 1331 1332 // Propagate extension type if any 1333 if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::SExt)) 1334 Flags.setSExt(); 1335 else if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::ZExt)) 1336 Flags.setZExt(); 1337 1338 for (unsigned i = 0; i < NumParts; ++i) 1339 Outs.push_back(ISD::OutputArg(Flags, PartVT, VT, /*isFixed=*/true, 0, 0)); 1340 } 1341 } 1342 1343 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 1344 /// function arguments in the caller parameter area. This is the actual 1345 /// alignment, not its logarithm. 1346 unsigned TargetLoweringBase::getByValTypeAlignment(Type *Ty) const { 1347 return DL->getABITypeAlignment(Ty); 1348 } 1349 1350 //===----------------------------------------------------------------------===// 1351 // TargetTransformInfo Helpers 1352 //===----------------------------------------------------------------------===// 1353 1354 int TargetLoweringBase::InstructionOpcodeToISD(unsigned Opcode) const { 1355 enum InstructionOpcodes { 1356 #define HANDLE_INST(NUM, OPCODE, CLASS) OPCODE = NUM, 1357 #define LAST_OTHER_INST(NUM) InstructionOpcodesCount = NUM 1358 #include "llvm/IR/Instruction.def" 1359 }; 1360 switch (static_cast<InstructionOpcodes>(Opcode)) { 1361 case Ret: return 0; 1362 case Br: return 0; 1363 case Switch: return 0; 1364 case IndirectBr: return 0; 1365 case Invoke: return 0; 1366 case Resume: return 0; 1367 case Unreachable: return 0; 1368 case Add: return ISD::ADD; 1369 case FAdd: return ISD::FADD; 1370 case Sub: return ISD::SUB; 1371 case FSub: return ISD::FSUB; 1372 case Mul: return ISD::MUL; 1373 case FMul: return ISD::FMUL; 1374 case UDiv: return ISD::UDIV; 1375 case SDiv: return ISD::SDIV; 1376 case FDiv: return ISD::FDIV; 1377 case URem: return ISD::UREM; 1378 case SRem: return ISD::SREM; 1379 case FRem: return ISD::FREM; 1380 case Shl: return ISD::SHL; 1381 case LShr: return ISD::SRL; 1382 case AShr: return ISD::SRA; 1383 case And: return ISD::AND; 1384 case Or: return ISD::OR; 1385 case Xor: return ISD::XOR; 1386 case Alloca: return 0; 1387 case Load: return ISD::LOAD; 1388 case Store: return ISD::STORE; 1389 case GetElementPtr: return 0; 1390 case Fence: return 0; 1391 case AtomicCmpXchg: return 0; 1392 case AtomicRMW: return 0; 1393 case Trunc: return ISD::TRUNCATE; 1394 case ZExt: return ISD::ZERO_EXTEND; 1395 case SExt: return ISD::SIGN_EXTEND; 1396 case FPToUI: return ISD::FP_TO_UINT; 1397 case FPToSI: return ISD::FP_TO_SINT; 1398 case UIToFP: return ISD::UINT_TO_FP; 1399 case SIToFP: return ISD::SINT_TO_FP; 1400 case FPTrunc: return ISD::FP_ROUND; 1401 case FPExt: return ISD::FP_EXTEND; 1402 case PtrToInt: return ISD::BITCAST; 1403 case IntToPtr: return ISD::BITCAST; 1404 case BitCast: return ISD::BITCAST; 1405 case AddrSpaceCast: return ISD::ADDRSPACECAST; 1406 case ICmp: return ISD::SETCC; 1407 case FCmp: return ISD::SETCC; 1408 case PHI: return 0; 1409 case Call: return 0; 1410 case Select: return ISD::SELECT; 1411 case UserOp1: return 0; 1412 case UserOp2: return 0; 1413 case VAArg: return 0; 1414 case ExtractElement: return ISD::EXTRACT_VECTOR_ELT; 1415 case InsertElement: return ISD::INSERT_VECTOR_ELT; 1416 case ShuffleVector: return ISD::VECTOR_SHUFFLE; 1417 case ExtractValue: return ISD::MERGE_VALUES; 1418 case InsertValue: return ISD::MERGE_VALUES; 1419 case LandingPad: return 0; 1420 } 1421 1422 llvm_unreachable("Unknown instruction type encountered!"); 1423 } 1424 1425 std::pair<unsigned, MVT> 1426 TargetLoweringBase::getTypeLegalizationCost(Type *Ty) const { 1427 LLVMContext &C = Ty->getContext(); 1428 EVT MTy = getValueType(Ty); 1429 1430 unsigned Cost = 1; 1431 // We keep legalizing the type until we find a legal kind. We assume that 1432 // the only operation that costs anything is the split. After splitting 1433 // we need to handle two types. 1434 while (true) { 1435 LegalizeKind LK = getTypeConversion(C, MTy); 1436 1437 if (LK.first == TypeLegal) 1438 return std::make_pair(Cost, MTy.getSimpleVT()); 1439 1440 if (LK.first == TypeSplitVector || LK.first == TypeExpandInteger) 1441 Cost *= 2; 1442 1443 // Keep legalizing the type. 1444 MTy = LK.second; 1445 } 1446 } 1447 1448 //===----------------------------------------------------------------------===// 1449 // Loop Strength Reduction hooks 1450 //===----------------------------------------------------------------------===// 1451 1452 /// isLegalAddressingMode - Return true if the addressing mode represented 1453 /// by AM is legal for this target, for a load/store of the specified type. 1454 bool TargetLoweringBase::isLegalAddressingMode(const AddrMode &AM, 1455 Type *Ty) const { 1456 // The default implementation of this implements a conservative RISCy, r+r and 1457 // r+i addr mode. 1458 1459 // Allows a sign-extended 16-bit immediate field. 1460 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1) 1461 return false; 1462 1463 // No global is ever allowed as a base. 1464 if (AM.BaseGV) 1465 return false; 1466 1467 // Only support r+r, 1468 switch (AM.Scale) { 1469 case 0: // "r+i" or just "i", depending on HasBaseReg. 1470 break; 1471 case 1: 1472 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. 1473 return false; 1474 // Otherwise we have r+r or r+i. 1475 break; 1476 case 2: 1477 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. 1478 return false; 1479 // Allow 2*r as r+r. 1480 break; 1481 default: // Don't allow n * r 1482 return false; 1483 } 1484 1485 return true; 1486 } 1487