1 //===-- TargetLoweringBase.cpp - Implement the TargetLoweringBase class ---===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This implements the TargetLoweringBase class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "llvm/Target/TargetLowering.h" 15 #include "llvm/ADT/BitVector.h" 16 #include "llvm/ADT/STLExtras.h" 17 #include "llvm/ADT/Triple.h" 18 #include "llvm/CodeGen/Analysis.h" 19 #include "llvm/CodeGen/MachineFrameInfo.h" 20 #include "llvm/CodeGen/MachineFunction.h" 21 #include "llvm/CodeGen/MachineInstrBuilder.h" 22 #include "llvm/CodeGen/MachineJumpTableInfo.h" 23 #include "llvm/CodeGen/StackMaps.h" 24 #include "llvm/IR/DataLayout.h" 25 #include "llvm/IR/DerivedTypes.h" 26 #include "llvm/IR/GlobalVariable.h" 27 #include "llvm/IR/Mangler.h" 28 #include "llvm/MC/MCAsmInfo.h" 29 #include "llvm/MC/MCContext.h" 30 #include "llvm/MC/MCExpr.h" 31 #include "llvm/Support/BranchProbability.h" 32 #include "llvm/Support/CommandLine.h" 33 #include "llvm/Support/ErrorHandling.h" 34 #include "llvm/Support/MathExtras.h" 35 #include "llvm/Target/TargetLoweringObjectFile.h" 36 #include "llvm/Target/TargetMachine.h" 37 #include "llvm/Target/TargetRegisterInfo.h" 38 #include "llvm/Target/TargetSubtargetInfo.h" 39 #include <cctype> 40 using namespace llvm; 41 42 static cl::opt<bool> JumpIsExpensiveOverride( 43 "jump-is-expensive", cl::init(false), 44 cl::desc("Do not create extra branches to split comparison logic."), 45 cl::Hidden); 46 47 static cl::opt<unsigned> MaximumJumpTableSize 48 ("max-jump-table", cl::init(0), cl::Hidden, 49 cl::desc("Set maximum number of jump table entries; zero for no limit.")); 50 51 // Although this default value is arbitrary, it is not random. It is assumed 52 // that a condition that evaluates the same way by a higher percentage than this 53 // is best represented as control flow. Therefore, the default value N should be 54 // set such that the win from N% correct executions is greater than the loss 55 // from (100 - N)% mispredicted executions for the majority of intended targets. 56 static cl::opt<int> MinPercentageForPredictableBranch( 57 "min-predictable-branch", cl::init(99), 58 cl::desc("Minimum percentage (0-100) that a condition must be either true " 59 "or false to assume that the condition is predictable"), 60 cl::Hidden); 61 62 /// InitLibcallNames - Set default libcall names. 63 /// 64 static void InitLibcallNames(const char **Names, const Triple &TT) { 65 Names[RTLIB::SHL_I16] = "__ashlhi3"; 66 Names[RTLIB::SHL_I32] = "__ashlsi3"; 67 Names[RTLIB::SHL_I64] = "__ashldi3"; 68 Names[RTLIB::SHL_I128] = "__ashlti3"; 69 Names[RTLIB::SRL_I16] = "__lshrhi3"; 70 Names[RTLIB::SRL_I32] = "__lshrsi3"; 71 Names[RTLIB::SRL_I64] = "__lshrdi3"; 72 Names[RTLIB::SRL_I128] = "__lshrti3"; 73 Names[RTLIB::SRA_I16] = "__ashrhi3"; 74 Names[RTLIB::SRA_I32] = "__ashrsi3"; 75 Names[RTLIB::SRA_I64] = "__ashrdi3"; 76 Names[RTLIB::SRA_I128] = "__ashrti3"; 77 Names[RTLIB::MUL_I8] = "__mulqi3"; 78 Names[RTLIB::MUL_I16] = "__mulhi3"; 79 Names[RTLIB::MUL_I32] = "__mulsi3"; 80 Names[RTLIB::MUL_I64] = "__muldi3"; 81 Names[RTLIB::MUL_I128] = "__multi3"; 82 Names[RTLIB::MULO_I32] = "__mulosi4"; 83 Names[RTLIB::MULO_I64] = "__mulodi4"; 84 Names[RTLIB::MULO_I128] = "__muloti4"; 85 Names[RTLIB::SDIV_I8] = "__divqi3"; 86 Names[RTLIB::SDIV_I16] = "__divhi3"; 87 Names[RTLIB::SDIV_I32] = "__divsi3"; 88 Names[RTLIB::SDIV_I64] = "__divdi3"; 89 Names[RTLIB::SDIV_I128] = "__divti3"; 90 Names[RTLIB::UDIV_I8] = "__udivqi3"; 91 Names[RTLIB::UDIV_I16] = "__udivhi3"; 92 Names[RTLIB::UDIV_I32] = "__udivsi3"; 93 Names[RTLIB::UDIV_I64] = "__udivdi3"; 94 Names[RTLIB::UDIV_I128] = "__udivti3"; 95 Names[RTLIB::SREM_I8] = "__modqi3"; 96 Names[RTLIB::SREM_I16] = "__modhi3"; 97 Names[RTLIB::SREM_I32] = "__modsi3"; 98 Names[RTLIB::SREM_I64] = "__moddi3"; 99 Names[RTLIB::SREM_I128] = "__modti3"; 100 Names[RTLIB::UREM_I8] = "__umodqi3"; 101 Names[RTLIB::UREM_I16] = "__umodhi3"; 102 Names[RTLIB::UREM_I32] = "__umodsi3"; 103 Names[RTLIB::UREM_I64] = "__umoddi3"; 104 Names[RTLIB::UREM_I128] = "__umodti3"; 105 106 Names[RTLIB::NEG_I32] = "__negsi2"; 107 Names[RTLIB::NEG_I64] = "__negdi2"; 108 Names[RTLIB::ADD_F32] = "__addsf3"; 109 Names[RTLIB::ADD_F64] = "__adddf3"; 110 Names[RTLIB::ADD_F80] = "__addxf3"; 111 Names[RTLIB::ADD_F128] = "__addtf3"; 112 Names[RTLIB::ADD_PPCF128] = "__gcc_qadd"; 113 Names[RTLIB::SUB_F32] = "__subsf3"; 114 Names[RTLIB::SUB_F64] = "__subdf3"; 115 Names[RTLIB::SUB_F80] = "__subxf3"; 116 Names[RTLIB::SUB_F128] = "__subtf3"; 117 Names[RTLIB::SUB_PPCF128] = "__gcc_qsub"; 118 Names[RTLIB::MUL_F32] = "__mulsf3"; 119 Names[RTLIB::MUL_F64] = "__muldf3"; 120 Names[RTLIB::MUL_F80] = "__mulxf3"; 121 Names[RTLIB::MUL_F128] = "__multf3"; 122 Names[RTLIB::MUL_PPCF128] = "__gcc_qmul"; 123 Names[RTLIB::DIV_F32] = "__divsf3"; 124 Names[RTLIB::DIV_F64] = "__divdf3"; 125 Names[RTLIB::DIV_F80] = "__divxf3"; 126 Names[RTLIB::DIV_F128] = "__divtf3"; 127 Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv"; 128 Names[RTLIB::REM_F32] = "fmodf"; 129 Names[RTLIB::REM_F64] = "fmod"; 130 Names[RTLIB::REM_F80] = "fmodl"; 131 Names[RTLIB::REM_F128] = "fmodl"; 132 Names[RTLIB::REM_PPCF128] = "fmodl"; 133 Names[RTLIB::FMA_F32] = "fmaf"; 134 Names[RTLIB::FMA_F64] = "fma"; 135 Names[RTLIB::FMA_F80] = "fmal"; 136 Names[RTLIB::FMA_F128] = "fmal"; 137 Names[RTLIB::FMA_PPCF128] = "fmal"; 138 Names[RTLIB::POWI_F32] = "__powisf2"; 139 Names[RTLIB::POWI_F64] = "__powidf2"; 140 Names[RTLIB::POWI_F80] = "__powixf2"; 141 Names[RTLIB::POWI_F128] = "__powitf2"; 142 Names[RTLIB::POWI_PPCF128] = "__powitf2"; 143 Names[RTLIB::SQRT_F32] = "sqrtf"; 144 Names[RTLIB::SQRT_F64] = "sqrt"; 145 Names[RTLIB::SQRT_F80] = "sqrtl"; 146 Names[RTLIB::SQRT_F128] = "sqrtl"; 147 Names[RTLIB::SQRT_PPCF128] = "sqrtl"; 148 Names[RTLIB::LOG_F32] = "logf"; 149 Names[RTLIB::LOG_F64] = "log"; 150 Names[RTLIB::LOG_F80] = "logl"; 151 Names[RTLIB::LOG_F128] = "logl"; 152 Names[RTLIB::LOG_PPCF128] = "logl"; 153 Names[RTLIB::LOG2_F32] = "log2f"; 154 Names[RTLIB::LOG2_F64] = "log2"; 155 Names[RTLIB::LOG2_F80] = "log2l"; 156 Names[RTLIB::LOG2_F128] = "log2l"; 157 Names[RTLIB::LOG2_PPCF128] = "log2l"; 158 Names[RTLIB::LOG10_F32] = "log10f"; 159 Names[RTLIB::LOG10_F64] = "log10"; 160 Names[RTLIB::LOG10_F80] = "log10l"; 161 Names[RTLIB::LOG10_F128] = "log10l"; 162 Names[RTLIB::LOG10_PPCF128] = "log10l"; 163 Names[RTLIB::EXP_F32] = "expf"; 164 Names[RTLIB::EXP_F64] = "exp"; 165 Names[RTLIB::EXP_F80] = "expl"; 166 Names[RTLIB::EXP_F128] = "expl"; 167 Names[RTLIB::EXP_PPCF128] = "expl"; 168 Names[RTLIB::EXP2_F32] = "exp2f"; 169 Names[RTLIB::EXP2_F64] = "exp2"; 170 Names[RTLIB::EXP2_F80] = "exp2l"; 171 Names[RTLIB::EXP2_F128] = "exp2l"; 172 Names[RTLIB::EXP2_PPCF128] = "exp2l"; 173 Names[RTLIB::SIN_F32] = "sinf"; 174 Names[RTLIB::SIN_F64] = "sin"; 175 Names[RTLIB::SIN_F80] = "sinl"; 176 Names[RTLIB::SIN_F128] = "sinl"; 177 Names[RTLIB::SIN_PPCF128] = "sinl"; 178 Names[RTLIB::COS_F32] = "cosf"; 179 Names[RTLIB::COS_F64] = "cos"; 180 Names[RTLIB::COS_F80] = "cosl"; 181 Names[RTLIB::COS_F128] = "cosl"; 182 Names[RTLIB::COS_PPCF128] = "cosl"; 183 Names[RTLIB::POW_F32] = "powf"; 184 Names[RTLIB::POW_F64] = "pow"; 185 Names[RTLIB::POW_F80] = "powl"; 186 Names[RTLIB::POW_F128] = "powl"; 187 Names[RTLIB::POW_PPCF128] = "powl"; 188 Names[RTLIB::CEIL_F32] = "ceilf"; 189 Names[RTLIB::CEIL_F64] = "ceil"; 190 Names[RTLIB::CEIL_F80] = "ceill"; 191 Names[RTLIB::CEIL_F128] = "ceill"; 192 Names[RTLIB::CEIL_PPCF128] = "ceill"; 193 Names[RTLIB::TRUNC_F32] = "truncf"; 194 Names[RTLIB::TRUNC_F64] = "trunc"; 195 Names[RTLIB::TRUNC_F80] = "truncl"; 196 Names[RTLIB::TRUNC_F128] = "truncl"; 197 Names[RTLIB::TRUNC_PPCF128] = "truncl"; 198 Names[RTLIB::RINT_F32] = "rintf"; 199 Names[RTLIB::RINT_F64] = "rint"; 200 Names[RTLIB::RINT_F80] = "rintl"; 201 Names[RTLIB::RINT_F128] = "rintl"; 202 Names[RTLIB::RINT_PPCF128] = "rintl"; 203 Names[RTLIB::NEARBYINT_F32] = "nearbyintf"; 204 Names[RTLIB::NEARBYINT_F64] = "nearbyint"; 205 Names[RTLIB::NEARBYINT_F80] = "nearbyintl"; 206 Names[RTLIB::NEARBYINT_F128] = "nearbyintl"; 207 Names[RTLIB::NEARBYINT_PPCF128] = "nearbyintl"; 208 Names[RTLIB::ROUND_F32] = "roundf"; 209 Names[RTLIB::ROUND_F64] = "round"; 210 Names[RTLIB::ROUND_F80] = "roundl"; 211 Names[RTLIB::ROUND_F128] = "roundl"; 212 Names[RTLIB::ROUND_PPCF128] = "roundl"; 213 Names[RTLIB::FLOOR_F32] = "floorf"; 214 Names[RTLIB::FLOOR_F64] = "floor"; 215 Names[RTLIB::FLOOR_F80] = "floorl"; 216 Names[RTLIB::FLOOR_F128] = "floorl"; 217 Names[RTLIB::FLOOR_PPCF128] = "floorl"; 218 Names[RTLIB::FMIN_F32] = "fminf"; 219 Names[RTLIB::FMIN_F64] = "fmin"; 220 Names[RTLIB::FMIN_F80] = "fminl"; 221 Names[RTLIB::FMIN_F128] = "fminl"; 222 Names[RTLIB::FMIN_PPCF128] = "fminl"; 223 Names[RTLIB::FMAX_F32] = "fmaxf"; 224 Names[RTLIB::FMAX_F64] = "fmax"; 225 Names[RTLIB::FMAX_F80] = "fmaxl"; 226 Names[RTLIB::FMAX_F128] = "fmaxl"; 227 Names[RTLIB::FMAX_PPCF128] = "fmaxl"; 228 Names[RTLIB::ROUND_F32] = "roundf"; 229 Names[RTLIB::ROUND_F64] = "round"; 230 Names[RTLIB::ROUND_F80] = "roundl"; 231 Names[RTLIB::ROUND_F128] = "roundl"; 232 Names[RTLIB::ROUND_PPCF128] = "roundl"; 233 Names[RTLIB::COPYSIGN_F32] = "copysignf"; 234 Names[RTLIB::COPYSIGN_F64] = "copysign"; 235 Names[RTLIB::COPYSIGN_F80] = "copysignl"; 236 Names[RTLIB::COPYSIGN_F128] = "copysignl"; 237 Names[RTLIB::COPYSIGN_PPCF128] = "copysignl"; 238 Names[RTLIB::FPEXT_F32_PPCF128] = "__gcc_stoq"; 239 Names[RTLIB::FPEXT_F64_PPCF128] = "__gcc_dtoq"; 240 Names[RTLIB::FPEXT_F64_F128] = "__extenddftf2"; 241 Names[RTLIB::FPEXT_F32_F128] = "__extendsftf2"; 242 Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2"; 243 if (TT.isOSDarwin()) { 244 // For f16/f32 conversions, Darwin uses the standard naming scheme, instead 245 // of the gnueabi-style __gnu_*_ieee. 246 // FIXME: What about other targets? 247 Names[RTLIB::FPEXT_F16_F32] = "__extendhfsf2"; 248 Names[RTLIB::FPROUND_F32_F16] = "__truncsfhf2"; 249 } else { 250 Names[RTLIB::FPEXT_F16_F32] = "__gnu_h2f_ieee"; 251 Names[RTLIB::FPROUND_F32_F16] = "__gnu_f2h_ieee"; 252 } 253 Names[RTLIB::FPROUND_F64_F16] = "__truncdfhf2"; 254 Names[RTLIB::FPROUND_F80_F16] = "__truncxfhf2"; 255 Names[RTLIB::FPROUND_F128_F16] = "__trunctfhf2"; 256 Names[RTLIB::FPROUND_PPCF128_F16] = "__trunctfhf2"; 257 Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2"; 258 Names[RTLIB::FPROUND_F80_F32] = "__truncxfsf2"; 259 Names[RTLIB::FPROUND_F128_F32] = "__trunctfsf2"; 260 Names[RTLIB::FPROUND_PPCF128_F32] = "__gcc_qtos"; 261 Names[RTLIB::FPROUND_F80_F64] = "__truncxfdf2"; 262 Names[RTLIB::FPROUND_F128_F64] = "__trunctfdf2"; 263 Names[RTLIB::FPROUND_PPCF128_F64] = "__gcc_qtod"; 264 Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi"; 265 Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi"; 266 Names[RTLIB::FPTOSINT_F32_I128] = "__fixsfti"; 267 Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi"; 268 Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi"; 269 Names[RTLIB::FPTOSINT_F64_I128] = "__fixdfti"; 270 Names[RTLIB::FPTOSINT_F80_I32] = "__fixxfsi"; 271 Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi"; 272 Names[RTLIB::FPTOSINT_F80_I128] = "__fixxfti"; 273 Names[RTLIB::FPTOSINT_F128_I32] = "__fixtfsi"; 274 Names[RTLIB::FPTOSINT_F128_I64] = "__fixtfdi"; 275 Names[RTLIB::FPTOSINT_F128_I128] = "__fixtfti"; 276 Names[RTLIB::FPTOSINT_PPCF128_I32] = "__gcc_qtou"; 277 Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi"; 278 Names[RTLIB::FPTOSINT_PPCF128_I128] = "__fixtfti"; 279 Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi"; 280 Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi"; 281 Names[RTLIB::FPTOUINT_F32_I128] = "__fixunssfti"; 282 Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi"; 283 Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi"; 284 Names[RTLIB::FPTOUINT_F64_I128] = "__fixunsdfti"; 285 Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi"; 286 Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi"; 287 Names[RTLIB::FPTOUINT_F80_I128] = "__fixunsxfti"; 288 Names[RTLIB::FPTOUINT_F128_I32] = "__fixunstfsi"; 289 Names[RTLIB::FPTOUINT_F128_I64] = "__fixunstfdi"; 290 Names[RTLIB::FPTOUINT_F128_I128] = "__fixunstfti"; 291 Names[RTLIB::FPTOUINT_PPCF128_I32] = "__fixunstfsi"; 292 Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi"; 293 Names[RTLIB::FPTOUINT_PPCF128_I128] = "__fixunstfti"; 294 Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf"; 295 Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf"; 296 Names[RTLIB::SINTTOFP_I32_F80] = "__floatsixf"; 297 Names[RTLIB::SINTTOFP_I32_F128] = "__floatsitf"; 298 Names[RTLIB::SINTTOFP_I32_PPCF128] = "__gcc_itoq"; 299 Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf"; 300 Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf"; 301 Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf"; 302 Names[RTLIB::SINTTOFP_I64_F128] = "__floatditf"; 303 Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf"; 304 Names[RTLIB::SINTTOFP_I128_F32] = "__floattisf"; 305 Names[RTLIB::SINTTOFP_I128_F64] = "__floattidf"; 306 Names[RTLIB::SINTTOFP_I128_F80] = "__floattixf"; 307 Names[RTLIB::SINTTOFP_I128_F128] = "__floattitf"; 308 Names[RTLIB::SINTTOFP_I128_PPCF128] = "__floattitf"; 309 Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf"; 310 Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf"; 311 Names[RTLIB::UINTTOFP_I32_F80] = "__floatunsixf"; 312 Names[RTLIB::UINTTOFP_I32_F128] = "__floatunsitf"; 313 Names[RTLIB::UINTTOFP_I32_PPCF128] = "__gcc_utoq"; 314 Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf"; 315 Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf"; 316 Names[RTLIB::UINTTOFP_I64_F80] = "__floatundixf"; 317 Names[RTLIB::UINTTOFP_I64_F128] = "__floatunditf"; 318 Names[RTLIB::UINTTOFP_I64_PPCF128] = "__floatunditf"; 319 Names[RTLIB::UINTTOFP_I128_F32] = "__floatuntisf"; 320 Names[RTLIB::UINTTOFP_I128_F64] = "__floatuntidf"; 321 Names[RTLIB::UINTTOFP_I128_F80] = "__floatuntixf"; 322 Names[RTLIB::UINTTOFP_I128_F128] = "__floatuntitf"; 323 Names[RTLIB::UINTTOFP_I128_PPCF128] = "__floatuntitf"; 324 Names[RTLIB::OEQ_F32] = "__eqsf2"; 325 Names[RTLIB::OEQ_F64] = "__eqdf2"; 326 Names[RTLIB::OEQ_F128] = "__eqtf2"; 327 Names[RTLIB::OEQ_PPCF128] = "__gcc_qeq"; 328 Names[RTLIB::UNE_F32] = "__nesf2"; 329 Names[RTLIB::UNE_F64] = "__nedf2"; 330 Names[RTLIB::UNE_F128] = "__netf2"; 331 Names[RTLIB::UNE_PPCF128] = "__gcc_qne"; 332 Names[RTLIB::OGE_F32] = "__gesf2"; 333 Names[RTLIB::OGE_F64] = "__gedf2"; 334 Names[RTLIB::OGE_F128] = "__getf2"; 335 Names[RTLIB::OGE_PPCF128] = "__gcc_qge"; 336 Names[RTLIB::OLT_F32] = "__ltsf2"; 337 Names[RTLIB::OLT_F64] = "__ltdf2"; 338 Names[RTLIB::OLT_F128] = "__lttf2"; 339 Names[RTLIB::OLT_PPCF128] = "__gcc_qlt"; 340 Names[RTLIB::OLE_F32] = "__lesf2"; 341 Names[RTLIB::OLE_F64] = "__ledf2"; 342 Names[RTLIB::OLE_F128] = "__letf2"; 343 Names[RTLIB::OLE_PPCF128] = "__gcc_qle"; 344 Names[RTLIB::OGT_F32] = "__gtsf2"; 345 Names[RTLIB::OGT_F64] = "__gtdf2"; 346 Names[RTLIB::OGT_F128] = "__gttf2"; 347 Names[RTLIB::OGT_PPCF128] = "__gcc_qgt"; 348 Names[RTLIB::UO_F32] = "__unordsf2"; 349 Names[RTLIB::UO_F64] = "__unorddf2"; 350 Names[RTLIB::UO_F128] = "__unordtf2"; 351 Names[RTLIB::UO_PPCF128] = "__gcc_qunord"; 352 Names[RTLIB::O_F32] = "__unordsf2"; 353 Names[RTLIB::O_F64] = "__unorddf2"; 354 Names[RTLIB::O_F128] = "__unordtf2"; 355 Names[RTLIB::O_PPCF128] = "__gcc_qunord"; 356 Names[RTLIB::MEMCPY] = "memcpy"; 357 Names[RTLIB::MEMMOVE] = "memmove"; 358 Names[RTLIB::MEMSET] = "memset"; 359 Names[RTLIB::UNWIND_RESUME] = "_Unwind_Resume"; 360 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1] = "__sync_val_compare_and_swap_1"; 361 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2] = "__sync_val_compare_and_swap_2"; 362 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4] = "__sync_val_compare_and_swap_4"; 363 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8] = "__sync_val_compare_and_swap_8"; 364 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_16] = "__sync_val_compare_and_swap_16"; 365 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_1] = "__sync_lock_test_and_set_1"; 366 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_2] = "__sync_lock_test_and_set_2"; 367 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_4] = "__sync_lock_test_and_set_4"; 368 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_8] = "__sync_lock_test_and_set_8"; 369 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_16] = "__sync_lock_test_and_set_16"; 370 Names[RTLIB::SYNC_FETCH_AND_ADD_1] = "__sync_fetch_and_add_1"; 371 Names[RTLIB::SYNC_FETCH_AND_ADD_2] = "__sync_fetch_and_add_2"; 372 Names[RTLIB::SYNC_FETCH_AND_ADD_4] = "__sync_fetch_and_add_4"; 373 Names[RTLIB::SYNC_FETCH_AND_ADD_8] = "__sync_fetch_and_add_8"; 374 Names[RTLIB::SYNC_FETCH_AND_ADD_16] = "__sync_fetch_and_add_16"; 375 Names[RTLIB::SYNC_FETCH_AND_SUB_1] = "__sync_fetch_and_sub_1"; 376 Names[RTLIB::SYNC_FETCH_AND_SUB_2] = "__sync_fetch_and_sub_2"; 377 Names[RTLIB::SYNC_FETCH_AND_SUB_4] = "__sync_fetch_and_sub_4"; 378 Names[RTLIB::SYNC_FETCH_AND_SUB_8] = "__sync_fetch_and_sub_8"; 379 Names[RTLIB::SYNC_FETCH_AND_SUB_16] = "__sync_fetch_and_sub_16"; 380 Names[RTLIB::SYNC_FETCH_AND_AND_1] = "__sync_fetch_and_and_1"; 381 Names[RTLIB::SYNC_FETCH_AND_AND_2] = "__sync_fetch_and_and_2"; 382 Names[RTLIB::SYNC_FETCH_AND_AND_4] = "__sync_fetch_and_and_4"; 383 Names[RTLIB::SYNC_FETCH_AND_AND_8] = "__sync_fetch_and_and_8"; 384 Names[RTLIB::SYNC_FETCH_AND_AND_16] = "__sync_fetch_and_and_16"; 385 Names[RTLIB::SYNC_FETCH_AND_OR_1] = "__sync_fetch_and_or_1"; 386 Names[RTLIB::SYNC_FETCH_AND_OR_2] = "__sync_fetch_and_or_2"; 387 Names[RTLIB::SYNC_FETCH_AND_OR_4] = "__sync_fetch_and_or_4"; 388 Names[RTLIB::SYNC_FETCH_AND_OR_8] = "__sync_fetch_and_or_8"; 389 Names[RTLIB::SYNC_FETCH_AND_OR_16] = "__sync_fetch_and_or_16"; 390 Names[RTLIB::SYNC_FETCH_AND_XOR_1] = "__sync_fetch_and_xor_1"; 391 Names[RTLIB::SYNC_FETCH_AND_XOR_2] = "__sync_fetch_and_xor_2"; 392 Names[RTLIB::SYNC_FETCH_AND_XOR_4] = "__sync_fetch_and_xor_4"; 393 Names[RTLIB::SYNC_FETCH_AND_XOR_8] = "__sync_fetch_and_xor_8"; 394 Names[RTLIB::SYNC_FETCH_AND_XOR_16] = "__sync_fetch_and_xor_16"; 395 Names[RTLIB::SYNC_FETCH_AND_NAND_1] = "__sync_fetch_and_nand_1"; 396 Names[RTLIB::SYNC_FETCH_AND_NAND_2] = "__sync_fetch_and_nand_2"; 397 Names[RTLIB::SYNC_FETCH_AND_NAND_4] = "__sync_fetch_and_nand_4"; 398 Names[RTLIB::SYNC_FETCH_AND_NAND_8] = "__sync_fetch_and_nand_8"; 399 Names[RTLIB::SYNC_FETCH_AND_NAND_16] = "__sync_fetch_and_nand_16"; 400 Names[RTLIB::SYNC_FETCH_AND_MAX_1] = "__sync_fetch_and_max_1"; 401 Names[RTLIB::SYNC_FETCH_AND_MAX_2] = "__sync_fetch_and_max_2"; 402 Names[RTLIB::SYNC_FETCH_AND_MAX_4] = "__sync_fetch_and_max_4"; 403 Names[RTLIB::SYNC_FETCH_AND_MAX_8] = "__sync_fetch_and_max_8"; 404 Names[RTLIB::SYNC_FETCH_AND_MAX_16] = "__sync_fetch_and_max_16"; 405 Names[RTLIB::SYNC_FETCH_AND_UMAX_1] = "__sync_fetch_and_umax_1"; 406 Names[RTLIB::SYNC_FETCH_AND_UMAX_2] = "__sync_fetch_and_umax_2"; 407 Names[RTLIB::SYNC_FETCH_AND_UMAX_4] = "__sync_fetch_and_umax_4"; 408 Names[RTLIB::SYNC_FETCH_AND_UMAX_8] = "__sync_fetch_and_umax_8"; 409 Names[RTLIB::SYNC_FETCH_AND_UMAX_16] = "__sync_fetch_and_umax_16"; 410 Names[RTLIB::SYNC_FETCH_AND_MIN_1] = "__sync_fetch_and_min_1"; 411 Names[RTLIB::SYNC_FETCH_AND_MIN_2] = "__sync_fetch_and_min_2"; 412 Names[RTLIB::SYNC_FETCH_AND_MIN_4] = "__sync_fetch_and_min_4"; 413 Names[RTLIB::SYNC_FETCH_AND_MIN_8] = "__sync_fetch_and_min_8"; 414 Names[RTLIB::SYNC_FETCH_AND_MIN_16] = "__sync_fetch_and_min_16"; 415 Names[RTLIB::SYNC_FETCH_AND_UMIN_1] = "__sync_fetch_and_umin_1"; 416 Names[RTLIB::SYNC_FETCH_AND_UMIN_2] = "__sync_fetch_and_umin_2"; 417 Names[RTLIB::SYNC_FETCH_AND_UMIN_4] = "__sync_fetch_and_umin_4"; 418 Names[RTLIB::SYNC_FETCH_AND_UMIN_8] = "__sync_fetch_and_umin_8"; 419 Names[RTLIB::SYNC_FETCH_AND_UMIN_16] = "__sync_fetch_and_umin_16"; 420 421 Names[RTLIB::ATOMIC_LOAD] = "__atomic_load"; 422 Names[RTLIB::ATOMIC_LOAD_1] = "__atomic_load_1"; 423 Names[RTLIB::ATOMIC_LOAD_2] = "__atomic_load_2"; 424 Names[RTLIB::ATOMIC_LOAD_4] = "__atomic_load_4"; 425 Names[RTLIB::ATOMIC_LOAD_8] = "__atomic_load_8"; 426 Names[RTLIB::ATOMIC_LOAD_16] = "__atomic_load_16"; 427 428 Names[RTLIB::ATOMIC_STORE] = "__atomic_store"; 429 Names[RTLIB::ATOMIC_STORE_1] = "__atomic_store_1"; 430 Names[RTLIB::ATOMIC_STORE_2] = "__atomic_store_2"; 431 Names[RTLIB::ATOMIC_STORE_4] = "__atomic_store_4"; 432 Names[RTLIB::ATOMIC_STORE_8] = "__atomic_store_8"; 433 Names[RTLIB::ATOMIC_STORE_16] = "__atomic_store_16"; 434 435 Names[RTLIB::ATOMIC_EXCHANGE] = "__atomic_exchange"; 436 Names[RTLIB::ATOMIC_EXCHANGE_1] = "__atomic_exchange_1"; 437 Names[RTLIB::ATOMIC_EXCHANGE_2] = "__atomic_exchange_2"; 438 Names[RTLIB::ATOMIC_EXCHANGE_4] = "__atomic_exchange_4"; 439 Names[RTLIB::ATOMIC_EXCHANGE_8] = "__atomic_exchange_8"; 440 Names[RTLIB::ATOMIC_EXCHANGE_16] = "__atomic_exchange_16"; 441 442 Names[RTLIB::ATOMIC_COMPARE_EXCHANGE] = "__atomic_compare_exchange"; 443 Names[RTLIB::ATOMIC_COMPARE_EXCHANGE_1] = "__atomic_compare_exchange_1"; 444 Names[RTLIB::ATOMIC_COMPARE_EXCHANGE_2] = "__atomic_compare_exchange_2"; 445 Names[RTLIB::ATOMIC_COMPARE_EXCHANGE_4] = "__atomic_compare_exchange_4"; 446 Names[RTLIB::ATOMIC_COMPARE_EXCHANGE_8] = "__atomic_compare_exchange_8"; 447 Names[RTLIB::ATOMIC_COMPARE_EXCHANGE_16] = "__atomic_compare_exchange_16"; 448 449 Names[RTLIB::ATOMIC_FETCH_ADD_1] = "__atomic_fetch_add_1"; 450 Names[RTLIB::ATOMIC_FETCH_ADD_2] = "__atomic_fetch_add_2"; 451 Names[RTLIB::ATOMIC_FETCH_ADD_4] = "__atomic_fetch_add_4"; 452 Names[RTLIB::ATOMIC_FETCH_ADD_8] = "__atomic_fetch_add_8"; 453 Names[RTLIB::ATOMIC_FETCH_ADD_16] = "__atomic_fetch_add_16"; 454 Names[RTLIB::ATOMIC_FETCH_SUB_1] = "__atomic_fetch_sub_1"; 455 Names[RTLIB::ATOMIC_FETCH_SUB_2] = "__atomic_fetch_sub_2"; 456 Names[RTLIB::ATOMIC_FETCH_SUB_4] = "__atomic_fetch_sub_4"; 457 Names[RTLIB::ATOMIC_FETCH_SUB_8] = "__atomic_fetch_sub_8"; 458 Names[RTLIB::ATOMIC_FETCH_SUB_16] = "__atomic_fetch_sub_16"; 459 Names[RTLIB::ATOMIC_FETCH_AND_1] = "__atomic_fetch_and_1"; 460 Names[RTLIB::ATOMIC_FETCH_AND_2] = "__atomic_fetch_and_2"; 461 Names[RTLIB::ATOMIC_FETCH_AND_4] = "__atomic_fetch_and_4"; 462 Names[RTLIB::ATOMIC_FETCH_AND_8] = "__atomic_fetch_and_8"; 463 Names[RTLIB::ATOMIC_FETCH_AND_16] = "__atomic_fetch_and_16"; 464 Names[RTLIB::ATOMIC_FETCH_OR_1] = "__atomic_fetch_or_1"; 465 Names[RTLIB::ATOMIC_FETCH_OR_2] = "__atomic_fetch_or_2"; 466 Names[RTLIB::ATOMIC_FETCH_OR_4] = "__atomic_fetch_or_4"; 467 Names[RTLIB::ATOMIC_FETCH_OR_8] = "__atomic_fetch_or_8"; 468 Names[RTLIB::ATOMIC_FETCH_OR_16] = "__atomic_fetch_or_16"; 469 Names[RTLIB::ATOMIC_FETCH_XOR_1] = "__atomic_fetch_xor_1"; 470 Names[RTLIB::ATOMIC_FETCH_XOR_2] = "__atomic_fetch_xor_2"; 471 Names[RTLIB::ATOMIC_FETCH_XOR_4] = "__atomic_fetch_xor_4"; 472 Names[RTLIB::ATOMIC_FETCH_XOR_8] = "__atomic_fetch_xor_8"; 473 Names[RTLIB::ATOMIC_FETCH_XOR_16] = "__atomic_fetch_xor_16"; 474 Names[RTLIB::ATOMIC_FETCH_NAND_1] = "__atomic_fetch_nand_1"; 475 Names[RTLIB::ATOMIC_FETCH_NAND_2] = "__atomic_fetch_nand_2"; 476 Names[RTLIB::ATOMIC_FETCH_NAND_4] = "__atomic_fetch_nand_4"; 477 Names[RTLIB::ATOMIC_FETCH_NAND_8] = "__atomic_fetch_nand_8"; 478 Names[RTLIB::ATOMIC_FETCH_NAND_16] = "__atomic_fetch_nand_16"; 479 480 if (TT.isGNUEnvironment()) { 481 Names[RTLIB::SINCOS_F32] = "sincosf"; 482 Names[RTLIB::SINCOS_F64] = "sincos"; 483 Names[RTLIB::SINCOS_F80] = "sincosl"; 484 Names[RTLIB::SINCOS_F128] = "sincosl"; 485 Names[RTLIB::SINCOS_PPCF128] = "sincosl"; 486 } 487 488 if (!TT.isOSOpenBSD()) { 489 Names[RTLIB::STACKPROTECTOR_CHECK_FAIL] = "__stack_chk_fail"; 490 } 491 492 Names[RTLIB::DEOPTIMIZE] = "__llvm_deoptimize"; 493 } 494 495 /// Set default libcall CallingConvs. 496 static void InitLibcallCallingConvs(CallingConv::ID *CCs) { 497 for (int LC = 0; LC < RTLIB::UNKNOWN_LIBCALL; ++LC) 498 CCs[LC] = CallingConv::C; 499 } 500 501 /// getFPEXT - Return the FPEXT_*_* value for the given types, or 502 /// UNKNOWN_LIBCALL if there is none. 503 RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) { 504 if (OpVT == MVT::f16) { 505 if (RetVT == MVT::f32) 506 return FPEXT_F16_F32; 507 } else if (OpVT == MVT::f32) { 508 if (RetVT == MVT::f64) 509 return FPEXT_F32_F64; 510 if (RetVT == MVT::f128) 511 return FPEXT_F32_F128; 512 if (RetVT == MVT::ppcf128) 513 return FPEXT_F32_PPCF128; 514 } else if (OpVT == MVT::f64) { 515 if (RetVT == MVT::f128) 516 return FPEXT_F64_F128; 517 else if (RetVT == MVT::ppcf128) 518 return FPEXT_F64_PPCF128; 519 } 520 521 return UNKNOWN_LIBCALL; 522 } 523 524 /// getFPROUND - Return the FPROUND_*_* value for the given types, or 525 /// UNKNOWN_LIBCALL if there is none. 526 RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) { 527 if (RetVT == MVT::f16) { 528 if (OpVT == MVT::f32) 529 return FPROUND_F32_F16; 530 if (OpVT == MVT::f64) 531 return FPROUND_F64_F16; 532 if (OpVT == MVT::f80) 533 return FPROUND_F80_F16; 534 if (OpVT == MVT::f128) 535 return FPROUND_F128_F16; 536 if (OpVT == MVT::ppcf128) 537 return FPROUND_PPCF128_F16; 538 } else if (RetVT == MVT::f32) { 539 if (OpVT == MVT::f64) 540 return FPROUND_F64_F32; 541 if (OpVT == MVT::f80) 542 return FPROUND_F80_F32; 543 if (OpVT == MVT::f128) 544 return FPROUND_F128_F32; 545 if (OpVT == MVT::ppcf128) 546 return FPROUND_PPCF128_F32; 547 } else if (RetVT == MVT::f64) { 548 if (OpVT == MVT::f80) 549 return FPROUND_F80_F64; 550 if (OpVT == MVT::f128) 551 return FPROUND_F128_F64; 552 if (OpVT == MVT::ppcf128) 553 return FPROUND_PPCF128_F64; 554 } 555 556 return UNKNOWN_LIBCALL; 557 } 558 559 /// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or 560 /// UNKNOWN_LIBCALL if there is none. 561 RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT, EVT RetVT) { 562 if (OpVT == MVT::f32) { 563 if (RetVT == MVT::i32) 564 return FPTOSINT_F32_I32; 565 if (RetVT == MVT::i64) 566 return FPTOSINT_F32_I64; 567 if (RetVT == MVT::i128) 568 return FPTOSINT_F32_I128; 569 } else if (OpVT == MVT::f64) { 570 if (RetVT == MVT::i32) 571 return FPTOSINT_F64_I32; 572 if (RetVT == MVT::i64) 573 return FPTOSINT_F64_I64; 574 if (RetVT == MVT::i128) 575 return FPTOSINT_F64_I128; 576 } else if (OpVT == MVT::f80) { 577 if (RetVT == MVT::i32) 578 return FPTOSINT_F80_I32; 579 if (RetVT == MVT::i64) 580 return FPTOSINT_F80_I64; 581 if (RetVT == MVT::i128) 582 return FPTOSINT_F80_I128; 583 } else if (OpVT == MVT::f128) { 584 if (RetVT == MVT::i32) 585 return FPTOSINT_F128_I32; 586 if (RetVT == MVT::i64) 587 return FPTOSINT_F128_I64; 588 if (RetVT == MVT::i128) 589 return FPTOSINT_F128_I128; 590 } else if (OpVT == MVT::ppcf128) { 591 if (RetVT == MVT::i32) 592 return FPTOSINT_PPCF128_I32; 593 if (RetVT == MVT::i64) 594 return FPTOSINT_PPCF128_I64; 595 if (RetVT == MVT::i128) 596 return FPTOSINT_PPCF128_I128; 597 } 598 return UNKNOWN_LIBCALL; 599 } 600 601 /// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or 602 /// UNKNOWN_LIBCALL if there is none. 603 RTLIB::Libcall RTLIB::getFPTOUINT(EVT OpVT, EVT RetVT) { 604 if (OpVT == MVT::f32) { 605 if (RetVT == MVT::i32) 606 return FPTOUINT_F32_I32; 607 if (RetVT == MVT::i64) 608 return FPTOUINT_F32_I64; 609 if (RetVT == MVT::i128) 610 return FPTOUINT_F32_I128; 611 } else if (OpVT == MVT::f64) { 612 if (RetVT == MVT::i32) 613 return FPTOUINT_F64_I32; 614 if (RetVT == MVT::i64) 615 return FPTOUINT_F64_I64; 616 if (RetVT == MVT::i128) 617 return FPTOUINT_F64_I128; 618 } else if (OpVT == MVT::f80) { 619 if (RetVT == MVT::i32) 620 return FPTOUINT_F80_I32; 621 if (RetVT == MVT::i64) 622 return FPTOUINT_F80_I64; 623 if (RetVT == MVT::i128) 624 return FPTOUINT_F80_I128; 625 } else if (OpVT == MVT::f128) { 626 if (RetVT == MVT::i32) 627 return FPTOUINT_F128_I32; 628 if (RetVT == MVT::i64) 629 return FPTOUINT_F128_I64; 630 if (RetVT == MVT::i128) 631 return FPTOUINT_F128_I128; 632 } else if (OpVT == MVT::ppcf128) { 633 if (RetVT == MVT::i32) 634 return FPTOUINT_PPCF128_I32; 635 if (RetVT == MVT::i64) 636 return FPTOUINT_PPCF128_I64; 637 if (RetVT == MVT::i128) 638 return FPTOUINT_PPCF128_I128; 639 } 640 return UNKNOWN_LIBCALL; 641 } 642 643 /// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or 644 /// UNKNOWN_LIBCALL if there is none. 645 RTLIB::Libcall RTLIB::getSINTTOFP(EVT OpVT, EVT RetVT) { 646 if (OpVT == MVT::i32) { 647 if (RetVT == MVT::f32) 648 return SINTTOFP_I32_F32; 649 if (RetVT == MVT::f64) 650 return SINTTOFP_I32_F64; 651 if (RetVT == MVT::f80) 652 return SINTTOFP_I32_F80; 653 if (RetVT == MVT::f128) 654 return SINTTOFP_I32_F128; 655 if (RetVT == MVT::ppcf128) 656 return SINTTOFP_I32_PPCF128; 657 } else if (OpVT == MVT::i64) { 658 if (RetVT == MVT::f32) 659 return SINTTOFP_I64_F32; 660 if (RetVT == MVT::f64) 661 return SINTTOFP_I64_F64; 662 if (RetVT == MVT::f80) 663 return SINTTOFP_I64_F80; 664 if (RetVT == MVT::f128) 665 return SINTTOFP_I64_F128; 666 if (RetVT == MVT::ppcf128) 667 return SINTTOFP_I64_PPCF128; 668 } else if (OpVT == MVT::i128) { 669 if (RetVT == MVT::f32) 670 return SINTTOFP_I128_F32; 671 if (RetVT == MVT::f64) 672 return SINTTOFP_I128_F64; 673 if (RetVT == MVT::f80) 674 return SINTTOFP_I128_F80; 675 if (RetVT == MVT::f128) 676 return SINTTOFP_I128_F128; 677 if (RetVT == MVT::ppcf128) 678 return SINTTOFP_I128_PPCF128; 679 } 680 return UNKNOWN_LIBCALL; 681 } 682 683 /// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or 684 /// UNKNOWN_LIBCALL if there is none. 685 RTLIB::Libcall RTLIB::getUINTTOFP(EVT OpVT, EVT RetVT) { 686 if (OpVT == MVT::i32) { 687 if (RetVT == MVT::f32) 688 return UINTTOFP_I32_F32; 689 if (RetVT == MVT::f64) 690 return UINTTOFP_I32_F64; 691 if (RetVT == MVT::f80) 692 return UINTTOFP_I32_F80; 693 if (RetVT == MVT::f128) 694 return UINTTOFP_I32_F128; 695 if (RetVT == MVT::ppcf128) 696 return UINTTOFP_I32_PPCF128; 697 } else if (OpVT == MVT::i64) { 698 if (RetVT == MVT::f32) 699 return UINTTOFP_I64_F32; 700 if (RetVT == MVT::f64) 701 return UINTTOFP_I64_F64; 702 if (RetVT == MVT::f80) 703 return UINTTOFP_I64_F80; 704 if (RetVT == MVT::f128) 705 return UINTTOFP_I64_F128; 706 if (RetVT == MVT::ppcf128) 707 return UINTTOFP_I64_PPCF128; 708 } else if (OpVT == MVT::i128) { 709 if (RetVT == MVT::f32) 710 return UINTTOFP_I128_F32; 711 if (RetVT == MVT::f64) 712 return UINTTOFP_I128_F64; 713 if (RetVT == MVT::f80) 714 return UINTTOFP_I128_F80; 715 if (RetVT == MVT::f128) 716 return UINTTOFP_I128_F128; 717 if (RetVT == MVT::ppcf128) 718 return UINTTOFP_I128_PPCF128; 719 } 720 return UNKNOWN_LIBCALL; 721 } 722 723 RTLIB::Libcall RTLIB::getSYNC(unsigned Opc, MVT VT) { 724 #define OP_TO_LIBCALL(Name, Enum) \ 725 case Name: \ 726 switch (VT.SimpleTy) { \ 727 default: \ 728 return UNKNOWN_LIBCALL; \ 729 case MVT::i8: \ 730 return Enum##_1; \ 731 case MVT::i16: \ 732 return Enum##_2; \ 733 case MVT::i32: \ 734 return Enum##_4; \ 735 case MVT::i64: \ 736 return Enum##_8; \ 737 case MVT::i128: \ 738 return Enum##_16; \ 739 } 740 741 switch (Opc) { 742 OP_TO_LIBCALL(ISD::ATOMIC_SWAP, SYNC_LOCK_TEST_AND_SET) 743 OP_TO_LIBCALL(ISD::ATOMIC_CMP_SWAP, SYNC_VAL_COMPARE_AND_SWAP) 744 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_ADD, SYNC_FETCH_AND_ADD) 745 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_SUB, SYNC_FETCH_AND_SUB) 746 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_AND, SYNC_FETCH_AND_AND) 747 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_OR, SYNC_FETCH_AND_OR) 748 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_XOR, SYNC_FETCH_AND_XOR) 749 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_NAND, SYNC_FETCH_AND_NAND) 750 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_MAX, SYNC_FETCH_AND_MAX) 751 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_UMAX, SYNC_FETCH_AND_UMAX) 752 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_MIN, SYNC_FETCH_AND_MIN) 753 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_UMIN, SYNC_FETCH_AND_UMIN) 754 } 755 756 #undef OP_TO_LIBCALL 757 758 return UNKNOWN_LIBCALL; 759 } 760 761 /// InitCmpLibcallCCs - Set default comparison libcall CC. 762 /// 763 static void InitCmpLibcallCCs(ISD::CondCode *CCs) { 764 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL); 765 CCs[RTLIB::OEQ_F32] = ISD::SETEQ; 766 CCs[RTLIB::OEQ_F64] = ISD::SETEQ; 767 CCs[RTLIB::OEQ_F128] = ISD::SETEQ; 768 CCs[RTLIB::OEQ_PPCF128] = ISD::SETEQ; 769 CCs[RTLIB::UNE_F32] = ISD::SETNE; 770 CCs[RTLIB::UNE_F64] = ISD::SETNE; 771 CCs[RTLIB::UNE_F128] = ISD::SETNE; 772 CCs[RTLIB::UNE_PPCF128] = ISD::SETNE; 773 CCs[RTLIB::OGE_F32] = ISD::SETGE; 774 CCs[RTLIB::OGE_F64] = ISD::SETGE; 775 CCs[RTLIB::OGE_F128] = ISD::SETGE; 776 CCs[RTLIB::OGE_PPCF128] = ISD::SETGE; 777 CCs[RTLIB::OLT_F32] = ISD::SETLT; 778 CCs[RTLIB::OLT_F64] = ISD::SETLT; 779 CCs[RTLIB::OLT_F128] = ISD::SETLT; 780 CCs[RTLIB::OLT_PPCF128] = ISD::SETLT; 781 CCs[RTLIB::OLE_F32] = ISD::SETLE; 782 CCs[RTLIB::OLE_F64] = ISD::SETLE; 783 CCs[RTLIB::OLE_F128] = ISD::SETLE; 784 CCs[RTLIB::OLE_PPCF128] = ISD::SETLE; 785 CCs[RTLIB::OGT_F32] = ISD::SETGT; 786 CCs[RTLIB::OGT_F64] = ISD::SETGT; 787 CCs[RTLIB::OGT_F128] = ISD::SETGT; 788 CCs[RTLIB::OGT_PPCF128] = ISD::SETGT; 789 CCs[RTLIB::UO_F32] = ISD::SETNE; 790 CCs[RTLIB::UO_F64] = ISD::SETNE; 791 CCs[RTLIB::UO_F128] = ISD::SETNE; 792 CCs[RTLIB::UO_PPCF128] = ISD::SETNE; 793 CCs[RTLIB::O_F32] = ISD::SETEQ; 794 CCs[RTLIB::O_F64] = ISD::SETEQ; 795 CCs[RTLIB::O_F128] = ISD::SETEQ; 796 CCs[RTLIB::O_PPCF128] = ISD::SETEQ; 797 } 798 799 /// NOTE: The TargetMachine owns TLOF. 800 TargetLoweringBase::TargetLoweringBase(const TargetMachine &tm) : TM(tm) { 801 initActions(); 802 803 // Perform these initializations only once. 804 MaxStoresPerMemset = MaxStoresPerMemcpy = MaxStoresPerMemmove = 8; 805 MaxStoresPerMemsetOptSize = MaxStoresPerMemcpyOptSize 806 = MaxStoresPerMemmoveOptSize = 4; 807 UseUnderscoreSetJmp = false; 808 UseUnderscoreLongJmp = false; 809 SelectIsExpensive = false; 810 HasMultipleConditionRegisters = false; 811 HasExtractBitsInsn = false; 812 JumpIsExpensive = JumpIsExpensiveOverride; 813 PredictableSelectIsExpensive = false; 814 MaskAndBranchFoldingIsLegal = false; 815 EnableExtLdPromotion = false; 816 HasFloatingPointExceptions = true; 817 StackPointerRegisterToSaveRestore = 0; 818 BooleanContents = UndefinedBooleanContent; 819 BooleanFloatContents = UndefinedBooleanContent; 820 BooleanVectorContents = UndefinedBooleanContent; 821 SchedPreferenceInfo = Sched::ILP; 822 JumpBufSize = 0; 823 JumpBufAlignment = 0; 824 MinFunctionAlignment = 0; 825 PrefFunctionAlignment = 0; 826 PrefLoopAlignment = 0; 827 GatherAllAliasesMaxDepth = 6; 828 MinStackArgumentAlignment = 1; 829 MinimumJumpTableEntries = 4; 830 // TODO: the default will be switched to 0 in the next commit, along 831 // with the Target-specific changes necessary. 832 MaxAtomicSizeInBitsSupported = 1024; 833 834 MinCmpXchgSizeInBits = 0; 835 836 std::fill(std::begin(LibcallRoutineNames), std::end(LibcallRoutineNames), nullptr); 837 838 InitLibcallNames(LibcallRoutineNames, TM.getTargetTriple()); 839 InitCmpLibcallCCs(CmpLibcallCCs); 840 InitLibcallCallingConvs(LibcallCallingConvs); 841 ReciprocalEstimates.set("all", false, 0); 842 } 843 844 void TargetLoweringBase::initActions() { 845 // All operations default to being supported. 846 memset(OpActions, 0, sizeof(OpActions)); 847 memset(LoadExtActions, 0, sizeof(LoadExtActions)); 848 memset(TruncStoreActions, 0, sizeof(TruncStoreActions)); 849 memset(IndexedModeActions, 0, sizeof(IndexedModeActions)); 850 memset(CondCodeActions, 0, sizeof(CondCodeActions)); 851 std::fill(std::begin(RegClassForVT), std::end(RegClassForVT), nullptr); 852 std::fill(std::begin(TargetDAGCombineArray), 853 std::end(TargetDAGCombineArray), 0); 854 855 // Set default actions for various operations. 856 for (MVT VT : MVT::all_valuetypes()) { 857 // Default all indexed load / store to expand. 858 for (unsigned IM = (unsigned)ISD::PRE_INC; 859 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) { 860 setIndexedLoadAction(IM, VT, Expand); 861 setIndexedStoreAction(IM, VT, Expand); 862 } 863 864 // Most backends expect to see the node which just returns the value loaded. 865 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Expand); 866 867 // These operations default to expand. 868 setOperationAction(ISD::FGETSIGN, VT, Expand); 869 setOperationAction(ISD::CONCAT_VECTORS, VT, Expand); 870 setOperationAction(ISD::FMINNUM, VT, Expand); 871 setOperationAction(ISD::FMAXNUM, VT, Expand); 872 setOperationAction(ISD::FMINNAN, VT, Expand); 873 setOperationAction(ISD::FMAXNAN, VT, Expand); 874 setOperationAction(ISD::FMAD, VT, Expand); 875 setOperationAction(ISD::SMIN, VT, Expand); 876 setOperationAction(ISD::SMAX, VT, Expand); 877 setOperationAction(ISD::UMIN, VT, Expand); 878 setOperationAction(ISD::UMAX, VT, Expand); 879 880 // Overflow operations default to expand 881 setOperationAction(ISD::SADDO, VT, Expand); 882 setOperationAction(ISD::SSUBO, VT, Expand); 883 setOperationAction(ISD::UADDO, VT, Expand); 884 setOperationAction(ISD::USUBO, VT, Expand); 885 setOperationAction(ISD::SMULO, VT, Expand); 886 setOperationAction(ISD::UMULO, VT, Expand); 887 888 // These default to Expand so they will be expanded to CTLZ/CTTZ by default. 889 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand); 890 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand); 891 892 setOperationAction(ISD::BITREVERSE, VT, Expand); 893 894 // These library functions default to expand. 895 setOperationAction(ISD::FROUND, VT, Expand); 896 897 // These operations default to expand for vector types. 898 if (VT.isVector()) { 899 setOperationAction(ISD::FCOPYSIGN, VT, Expand); 900 setOperationAction(ISD::ANY_EXTEND_VECTOR_INREG, VT, Expand); 901 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, VT, Expand); 902 setOperationAction(ISD::ZERO_EXTEND_VECTOR_INREG, VT, Expand); 903 } 904 905 // For most targets @llvm.get.dynamic.area.offset just returns 0. 906 setOperationAction(ISD::GET_DYNAMIC_AREA_OFFSET, VT, Expand); 907 } 908 909 // Most targets ignore the @llvm.prefetch intrinsic. 910 setOperationAction(ISD::PREFETCH, MVT::Other, Expand); 911 912 // Most targets also ignore the @llvm.readcyclecounter intrinsic. 913 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Expand); 914 915 // ConstantFP nodes default to expand. Targets can either change this to 916 // Legal, in which case all fp constants are legal, or use isFPImmLegal() 917 // to optimize expansions for certain constants. 918 setOperationAction(ISD::ConstantFP, MVT::f16, Expand); 919 setOperationAction(ISD::ConstantFP, MVT::f32, Expand); 920 setOperationAction(ISD::ConstantFP, MVT::f64, Expand); 921 setOperationAction(ISD::ConstantFP, MVT::f80, Expand); 922 setOperationAction(ISD::ConstantFP, MVT::f128, Expand); 923 924 // These library functions default to expand. 925 for (MVT VT : {MVT::f32, MVT::f64, MVT::f128}) { 926 setOperationAction(ISD::FLOG , VT, Expand); 927 setOperationAction(ISD::FLOG2, VT, Expand); 928 setOperationAction(ISD::FLOG10, VT, Expand); 929 setOperationAction(ISD::FEXP , VT, Expand); 930 setOperationAction(ISD::FEXP2, VT, Expand); 931 setOperationAction(ISD::FFLOOR, VT, Expand); 932 setOperationAction(ISD::FNEARBYINT, VT, Expand); 933 setOperationAction(ISD::FCEIL, VT, Expand); 934 setOperationAction(ISD::FRINT, VT, Expand); 935 setOperationAction(ISD::FTRUNC, VT, Expand); 936 setOperationAction(ISD::FROUND, VT, Expand); 937 } 938 939 // Default ISD::TRAP to expand (which turns it into abort). 940 setOperationAction(ISD::TRAP, MVT::Other, Expand); 941 942 // On most systems, DEBUGTRAP and TRAP have no difference. The "Expand" 943 // here is to inform DAG Legalizer to replace DEBUGTRAP with TRAP. 944 // 945 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Expand); 946 } 947 948 MVT TargetLoweringBase::getScalarShiftAmountTy(const DataLayout &DL, 949 EVT) const { 950 return MVT::getIntegerVT(8 * DL.getPointerSize(0)); 951 } 952 953 EVT TargetLoweringBase::getShiftAmountTy(EVT LHSTy, 954 const DataLayout &DL) const { 955 assert(LHSTy.isInteger() && "Shift amount is not an integer type!"); 956 if (LHSTy.isVector()) 957 return LHSTy; 958 return getScalarShiftAmountTy(DL, LHSTy); 959 } 960 961 bool TargetLoweringBase::canOpTrap(unsigned Op, EVT VT) const { 962 assert(isTypeLegal(VT)); 963 switch (Op) { 964 default: 965 return false; 966 case ISD::SDIV: 967 case ISD::UDIV: 968 case ISD::SREM: 969 case ISD::UREM: 970 return true; 971 } 972 } 973 974 void TargetLoweringBase::setJumpIsExpensive(bool isExpensive) { 975 // If the command-line option was specified, ignore this request. 976 if (!JumpIsExpensiveOverride.getNumOccurrences()) 977 JumpIsExpensive = isExpensive; 978 } 979 980 TargetLoweringBase::LegalizeKind 981 TargetLoweringBase::getTypeConversion(LLVMContext &Context, EVT VT) const { 982 // If this is a simple type, use the ComputeRegisterProp mechanism. 983 if (VT.isSimple()) { 984 MVT SVT = VT.getSimpleVT(); 985 assert((unsigned)SVT.SimpleTy < array_lengthof(TransformToType)); 986 MVT NVT = TransformToType[SVT.SimpleTy]; 987 LegalizeTypeAction LA = ValueTypeActions.getTypeAction(SVT); 988 989 assert((LA == TypeLegal || LA == TypeSoftenFloat || 990 ValueTypeActions.getTypeAction(NVT) != TypePromoteInteger) && 991 "Promote may not follow Expand or Promote"); 992 993 if (LA == TypeSplitVector) 994 return LegalizeKind(LA, 995 EVT::getVectorVT(Context, SVT.getVectorElementType(), 996 SVT.getVectorNumElements() / 2)); 997 if (LA == TypeScalarizeVector) 998 return LegalizeKind(LA, SVT.getVectorElementType()); 999 return LegalizeKind(LA, NVT); 1000 } 1001 1002 // Handle Extended Scalar Types. 1003 if (!VT.isVector()) { 1004 assert(VT.isInteger() && "Float types must be simple"); 1005 unsigned BitSize = VT.getSizeInBits(); 1006 // First promote to a power-of-two size, then expand if necessary. 1007 if (BitSize < 8 || !isPowerOf2_32(BitSize)) { 1008 EVT NVT = VT.getRoundIntegerType(Context); 1009 assert(NVT != VT && "Unable to round integer VT"); 1010 LegalizeKind NextStep = getTypeConversion(Context, NVT); 1011 // Avoid multi-step promotion. 1012 if (NextStep.first == TypePromoteInteger) 1013 return NextStep; 1014 // Return rounded integer type. 1015 return LegalizeKind(TypePromoteInteger, NVT); 1016 } 1017 1018 return LegalizeKind(TypeExpandInteger, 1019 EVT::getIntegerVT(Context, VT.getSizeInBits() / 2)); 1020 } 1021 1022 // Handle vector types. 1023 unsigned NumElts = VT.getVectorNumElements(); 1024 EVT EltVT = VT.getVectorElementType(); 1025 1026 // Vectors with only one element are always scalarized. 1027 if (NumElts == 1) 1028 return LegalizeKind(TypeScalarizeVector, EltVT); 1029 1030 // Try to widen vector elements until the element type is a power of two and 1031 // promote it to a legal type later on, for example: 1032 // <3 x i8> -> <4 x i8> -> <4 x i32> 1033 if (EltVT.isInteger()) { 1034 // Vectors with a number of elements that is not a power of two are always 1035 // widened, for example <3 x i8> -> <4 x i8>. 1036 if (!VT.isPow2VectorType()) { 1037 NumElts = (unsigned)NextPowerOf2(NumElts); 1038 EVT NVT = EVT::getVectorVT(Context, EltVT, NumElts); 1039 return LegalizeKind(TypeWidenVector, NVT); 1040 } 1041 1042 // Examine the element type. 1043 LegalizeKind LK = getTypeConversion(Context, EltVT); 1044 1045 // If type is to be expanded, split the vector. 1046 // <4 x i140> -> <2 x i140> 1047 if (LK.first == TypeExpandInteger) 1048 return LegalizeKind(TypeSplitVector, 1049 EVT::getVectorVT(Context, EltVT, NumElts / 2)); 1050 1051 // Promote the integer element types until a legal vector type is found 1052 // or until the element integer type is too big. If a legal type was not 1053 // found, fallback to the usual mechanism of widening/splitting the 1054 // vector. 1055 EVT OldEltVT = EltVT; 1056 while (1) { 1057 // Increase the bitwidth of the element to the next pow-of-two 1058 // (which is greater than 8 bits). 1059 EltVT = EVT::getIntegerVT(Context, 1 + EltVT.getSizeInBits()) 1060 .getRoundIntegerType(Context); 1061 1062 // Stop trying when getting a non-simple element type. 1063 // Note that vector elements may be greater than legal vector element 1064 // types. Example: X86 XMM registers hold 64bit element on 32bit 1065 // systems. 1066 if (!EltVT.isSimple()) 1067 break; 1068 1069 // Build a new vector type and check if it is legal. 1070 MVT NVT = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts); 1071 // Found a legal promoted vector type. 1072 if (NVT != MVT() && ValueTypeActions.getTypeAction(NVT) == TypeLegal) 1073 return LegalizeKind(TypePromoteInteger, 1074 EVT::getVectorVT(Context, EltVT, NumElts)); 1075 } 1076 1077 // Reset the type to the unexpanded type if we did not find a legal vector 1078 // type with a promoted vector element type. 1079 EltVT = OldEltVT; 1080 } 1081 1082 // Try to widen the vector until a legal type is found. 1083 // If there is no wider legal type, split the vector. 1084 while (1) { 1085 // Round up to the next power of 2. 1086 NumElts = (unsigned)NextPowerOf2(NumElts); 1087 1088 // If there is no simple vector type with this many elements then there 1089 // cannot be a larger legal vector type. Note that this assumes that 1090 // there are no skipped intermediate vector types in the simple types. 1091 if (!EltVT.isSimple()) 1092 break; 1093 MVT LargerVector = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts); 1094 if (LargerVector == MVT()) 1095 break; 1096 1097 // If this type is legal then widen the vector. 1098 if (ValueTypeActions.getTypeAction(LargerVector) == TypeLegal) 1099 return LegalizeKind(TypeWidenVector, LargerVector); 1100 } 1101 1102 // Widen odd vectors to next power of two. 1103 if (!VT.isPow2VectorType()) { 1104 EVT NVT = VT.getPow2VectorType(Context); 1105 return LegalizeKind(TypeWidenVector, NVT); 1106 } 1107 1108 // Vectors with illegal element types are expanded. 1109 EVT NVT = EVT::getVectorVT(Context, EltVT, VT.getVectorNumElements() / 2); 1110 return LegalizeKind(TypeSplitVector, NVT); 1111 } 1112 1113 static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT, 1114 unsigned &NumIntermediates, 1115 MVT &RegisterVT, 1116 TargetLoweringBase *TLI) { 1117 // Figure out the right, legal destination reg to copy into. 1118 unsigned NumElts = VT.getVectorNumElements(); 1119 MVT EltTy = VT.getVectorElementType(); 1120 1121 unsigned NumVectorRegs = 1; 1122 1123 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we 1124 // could break down into LHS/RHS like LegalizeDAG does. 1125 if (!isPowerOf2_32(NumElts)) { 1126 NumVectorRegs = NumElts; 1127 NumElts = 1; 1128 } 1129 1130 // Divide the input until we get to a supported size. This will always 1131 // end with a scalar if the target doesn't support vectors. 1132 while (NumElts > 1 && !TLI->isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) { 1133 NumElts >>= 1; 1134 NumVectorRegs <<= 1; 1135 } 1136 1137 NumIntermediates = NumVectorRegs; 1138 1139 MVT NewVT = MVT::getVectorVT(EltTy, NumElts); 1140 if (!TLI->isTypeLegal(NewVT)) 1141 NewVT = EltTy; 1142 IntermediateVT = NewVT; 1143 1144 unsigned NewVTSize = NewVT.getSizeInBits(); 1145 1146 // Convert sizes such as i33 to i64. 1147 if (!isPowerOf2_32(NewVTSize)) 1148 NewVTSize = NextPowerOf2(NewVTSize); 1149 1150 MVT DestVT = TLI->getRegisterType(NewVT); 1151 RegisterVT = DestVT; 1152 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16. 1153 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits()); 1154 1155 // Otherwise, promotion or legal types use the same number of registers as 1156 // the vector decimated to the appropriate level. 1157 return NumVectorRegs; 1158 } 1159 1160 /// isLegalRC - Return true if the value types that can be represented by the 1161 /// specified register class are all legal. 1162 bool TargetLoweringBase::isLegalRC(const TargetRegisterClass *RC) const { 1163 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end(); 1164 I != E; ++I) { 1165 if (isTypeLegal(*I)) 1166 return true; 1167 } 1168 return false; 1169 } 1170 1171 /// Replace/modify any TargetFrameIndex operands with a targte-dependent 1172 /// sequence of memory operands that is recognized by PrologEpilogInserter. 1173 MachineBasicBlock * 1174 TargetLoweringBase::emitPatchPoint(MachineInstr &InitialMI, 1175 MachineBasicBlock *MBB) const { 1176 MachineInstr *MI = &InitialMI; 1177 MachineFunction &MF = *MI->getParent()->getParent(); 1178 MachineFrameInfo &MFI = MF.getFrameInfo(); 1179 1180 // We're handling multiple types of operands here: 1181 // PATCHPOINT MetaArgs - live-in, read only, direct 1182 // STATEPOINT Deopt Spill - live-through, read only, indirect 1183 // STATEPOINT Deopt Alloca - live-through, read only, direct 1184 // (We're currently conservative and mark the deopt slots read/write in 1185 // practice.) 1186 // STATEPOINT GC Spill - live-through, read/write, indirect 1187 // STATEPOINT GC Alloca - live-through, read/write, direct 1188 // The live-in vs live-through is handled already (the live through ones are 1189 // all stack slots), but we need to handle the different type of stackmap 1190 // operands and memory effects here. 1191 1192 // MI changes inside this loop as we grow operands. 1193 for(unsigned OperIdx = 0; OperIdx != MI->getNumOperands(); ++OperIdx) { 1194 MachineOperand &MO = MI->getOperand(OperIdx); 1195 if (!MO.isFI()) 1196 continue; 1197 1198 // foldMemoryOperand builds a new MI after replacing a single FI operand 1199 // with the canonical set of five x86 addressing-mode operands. 1200 int FI = MO.getIndex(); 1201 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), MI->getDesc()); 1202 1203 // Copy operands before the frame-index. 1204 for (unsigned i = 0; i < OperIdx; ++i) 1205 MIB.addOperand(MI->getOperand(i)); 1206 // Add frame index operands recognized by stackmaps.cpp 1207 if (MFI.isStatepointSpillSlotObjectIndex(FI)) { 1208 // indirect-mem-ref tag, size, #FI, offset. 1209 // Used for spills inserted by StatepointLowering. This codepath is not 1210 // used for patchpoints/stackmaps at all, for these spilling is done via 1211 // foldMemoryOperand callback only. 1212 assert(MI->getOpcode() == TargetOpcode::STATEPOINT && "sanity"); 1213 MIB.addImm(StackMaps::IndirectMemRefOp); 1214 MIB.addImm(MFI.getObjectSize(FI)); 1215 MIB.addOperand(MI->getOperand(OperIdx)); 1216 MIB.addImm(0); 1217 } else { 1218 // direct-mem-ref tag, #FI, offset. 1219 // Used by patchpoint, and direct alloca arguments to statepoints 1220 MIB.addImm(StackMaps::DirectMemRefOp); 1221 MIB.addOperand(MI->getOperand(OperIdx)); 1222 MIB.addImm(0); 1223 } 1224 // Copy the operands after the frame index. 1225 for (unsigned i = OperIdx + 1; i != MI->getNumOperands(); ++i) 1226 MIB.addOperand(MI->getOperand(i)); 1227 1228 // Inherit previous memory operands. 1229 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end()); 1230 assert(MIB->mayLoad() && "Folded a stackmap use to a non-load!"); 1231 1232 // Add a new memory operand for this FI. 1233 assert(MFI.getObjectOffset(FI) != -1); 1234 1235 auto Flags = MachineMemOperand::MOLoad; 1236 if (MI->getOpcode() == TargetOpcode::STATEPOINT) { 1237 Flags |= MachineMemOperand::MOStore; 1238 Flags |= MachineMemOperand::MOVolatile; 1239 } 1240 MachineMemOperand *MMO = MF.getMachineMemOperand( 1241 MachinePointerInfo::getFixedStack(MF, FI), Flags, 1242 MF.getDataLayout().getPointerSize(), MFI.getObjectAlignment(FI)); 1243 MIB->addMemOperand(MF, MMO); 1244 1245 // Replace the instruction and update the operand index. 1246 MBB->insert(MachineBasicBlock::iterator(MI), MIB); 1247 OperIdx += (MIB->getNumOperands() - MI->getNumOperands()) - 1; 1248 MI->eraseFromParent(); 1249 MI = MIB; 1250 } 1251 return MBB; 1252 } 1253 1254 /// findRepresentativeClass - Return the largest legal super-reg register class 1255 /// of the register class for the specified type and its associated "cost". 1256 // This function is in TargetLowering because it uses RegClassForVT which would 1257 // need to be moved to TargetRegisterInfo and would necessitate moving 1258 // isTypeLegal over as well - a massive change that would just require 1259 // TargetLowering having a TargetRegisterInfo class member that it would use. 1260 std::pair<const TargetRegisterClass *, uint8_t> 1261 TargetLoweringBase::findRepresentativeClass(const TargetRegisterInfo *TRI, 1262 MVT VT) const { 1263 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy]; 1264 if (!RC) 1265 return std::make_pair(RC, 0); 1266 1267 // Compute the set of all super-register classes. 1268 BitVector SuperRegRC(TRI->getNumRegClasses()); 1269 for (SuperRegClassIterator RCI(RC, TRI); RCI.isValid(); ++RCI) 1270 SuperRegRC.setBitsInMask(RCI.getMask()); 1271 1272 // Find the first legal register class with the largest spill size. 1273 const TargetRegisterClass *BestRC = RC; 1274 for (int i = SuperRegRC.find_first(); i >= 0; i = SuperRegRC.find_next(i)) { 1275 const TargetRegisterClass *SuperRC = TRI->getRegClass(i); 1276 // We want the largest possible spill size. 1277 if (SuperRC->getSize() <= BestRC->getSize()) 1278 continue; 1279 if (!isLegalRC(SuperRC)) 1280 continue; 1281 BestRC = SuperRC; 1282 } 1283 return std::make_pair(BestRC, 1); 1284 } 1285 1286 /// computeRegisterProperties - Once all of the register classes are added, 1287 /// this allows us to compute derived properties we expose. 1288 void TargetLoweringBase::computeRegisterProperties( 1289 const TargetRegisterInfo *TRI) { 1290 static_assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE, 1291 "Too many value types for ValueTypeActions to hold!"); 1292 1293 // Everything defaults to needing one register. 1294 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) { 1295 NumRegistersForVT[i] = 1; 1296 RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i; 1297 } 1298 // ...except isVoid, which doesn't need any registers. 1299 NumRegistersForVT[MVT::isVoid] = 0; 1300 1301 // Find the largest integer register class. 1302 unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE; 1303 for (; RegClassForVT[LargestIntReg] == nullptr; --LargestIntReg) 1304 assert(LargestIntReg != MVT::i1 && "No integer registers defined!"); 1305 1306 // Every integer value type larger than this largest register takes twice as 1307 // many registers to represent as the previous ValueType. 1308 for (unsigned ExpandedReg = LargestIntReg + 1; 1309 ExpandedReg <= MVT::LAST_INTEGER_VALUETYPE; ++ExpandedReg) { 1310 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1]; 1311 RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg; 1312 TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1); 1313 ValueTypeActions.setTypeAction((MVT::SimpleValueType)ExpandedReg, 1314 TypeExpandInteger); 1315 } 1316 1317 // Inspect all of the ValueType's smaller than the largest integer 1318 // register to see which ones need promotion. 1319 unsigned LegalIntReg = LargestIntReg; 1320 for (unsigned IntReg = LargestIntReg - 1; 1321 IntReg >= (unsigned)MVT::i1; --IntReg) { 1322 MVT IVT = (MVT::SimpleValueType)IntReg; 1323 if (isTypeLegal(IVT)) { 1324 LegalIntReg = IntReg; 1325 } else { 1326 RegisterTypeForVT[IntReg] = TransformToType[IntReg] = 1327 (const MVT::SimpleValueType)LegalIntReg; 1328 ValueTypeActions.setTypeAction(IVT, TypePromoteInteger); 1329 } 1330 } 1331 1332 // ppcf128 type is really two f64's. 1333 if (!isTypeLegal(MVT::ppcf128)) { 1334 if (isTypeLegal(MVT::f64)) { 1335 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64]; 1336 RegisterTypeForVT[MVT::ppcf128] = MVT::f64; 1337 TransformToType[MVT::ppcf128] = MVT::f64; 1338 ValueTypeActions.setTypeAction(MVT::ppcf128, TypeExpandFloat); 1339 } else { 1340 NumRegistersForVT[MVT::ppcf128] = NumRegistersForVT[MVT::i128]; 1341 RegisterTypeForVT[MVT::ppcf128] = RegisterTypeForVT[MVT::i128]; 1342 TransformToType[MVT::ppcf128] = MVT::i128; 1343 ValueTypeActions.setTypeAction(MVT::ppcf128, TypeSoftenFloat); 1344 } 1345 } 1346 1347 // Decide how to handle f128. If the target does not have native f128 support, 1348 // expand it to i128 and we will be generating soft float library calls. 1349 if (!isTypeLegal(MVT::f128)) { 1350 NumRegistersForVT[MVT::f128] = NumRegistersForVT[MVT::i128]; 1351 RegisterTypeForVT[MVT::f128] = RegisterTypeForVT[MVT::i128]; 1352 TransformToType[MVT::f128] = MVT::i128; 1353 ValueTypeActions.setTypeAction(MVT::f128, TypeSoftenFloat); 1354 } 1355 1356 // Decide how to handle f64. If the target does not have native f64 support, 1357 // expand it to i64 and we will be generating soft float library calls. 1358 if (!isTypeLegal(MVT::f64)) { 1359 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64]; 1360 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64]; 1361 TransformToType[MVT::f64] = MVT::i64; 1362 ValueTypeActions.setTypeAction(MVT::f64, TypeSoftenFloat); 1363 } 1364 1365 // Decide how to handle f32. If the target does not have native f32 support, 1366 // expand it to i32 and we will be generating soft float library calls. 1367 if (!isTypeLegal(MVT::f32)) { 1368 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32]; 1369 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32]; 1370 TransformToType[MVT::f32] = MVT::i32; 1371 ValueTypeActions.setTypeAction(MVT::f32, TypeSoftenFloat); 1372 } 1373 1374 // Decide how to handle f16. If the target does not have native f16 support, 1375 // promote it to f32, because there are no f16 library calls (except for 1376 // conversions). 1377 if (!isTypeLegal(MVT::f16)) { 1378 NumRegistersForVT[MVT::f16] = NumRegistersForVT[MVT::f32]; 1379 RegisterTypeForVT[MVT::f16] = RegisterTypeForVT[MVT::f32]; 1380 TransformToType[MVT::f16] = MVT::f32; 1381 ValueTypeActions.setTypeAction(MVT::f16, TypePromoteFloat); 1382 } 1383 1384 // Loop over all of the vector value types to see which need transformations. 1385 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE; 1386 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) { 1387 MVT VT = (MVT::SimpleValueType) i; 1388 if (isTypeLegal(VT)) 1389 continue; 1390 1391 MVT EltVT = VT.getVectorElementType(); 1392 unsigned NElts = VT.getVectorNumElements(); 1393 bool IsLegalWiderType = false; 1394 LegalizeTypeAction PreferredAction = getPreferredVectorAction(VT); 1395 switch (PreferredAction) { 1396 case TypePromoteInteger: { 1397 // Try to promote the elements of integer vectors. If no legal 1398 // promotion was found, fall through to the widen-vector method. 1399 for (unsigned nVT = i + 1; nVT <= MVT::LAST_INTEGER_VECTOR_VALUETYPE; ++nVT) { 1400 MVT SVT = (MVT::SimpleValueType) nVT; 1401 // Promote vectors of integers to vectors with the same number 1402 // of elements, with a wider element type. 1403 if (SVT.getScalarSizeInBits() > EltVT.getSizeInBits() && 1404 SVT.getVectorNumElements() == NElts && isTypeLegal(SVT)) { 1405 TransformToType[i] = SVT; 1406 RegisterTypeForVT[i] = SVT; 1407 NumRegistersForVT[i] = 1; 1408 ValueTypeActions.setTypeAction(VT, TypePromoteInteger); 1409 IsLegalWiderType = true; 1410 break; 1411 } 1412 } 1413 if (IsLegalWiderType) 1414 break; 1415 } 1416 case TypeWidenVector: { 1417 // Try to widen the vector. 1418 for (unsigned nVT = i + 1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) { 1419 MVT SVT = (MVT::SimpleValueType) nVT; 1420 if (SVT.getVectorElementType() == EltVT 1421 && SVT.getVectorNumElements() > NElts && isTypeLegal(SVT)) { 1422 TransformToType[i] = SVT; 1423 RegisterTypeForVT[i] = SVT; 1424 NumRegistersForVT[i] = 1; 1425 ValueTypeActions.setTypeAction(VT, TypeWidenVector); 1426 IsLegalWiderType = true; 1427 break; 1428 } 1429 } 1430 if (IsLegalWiderType) 1431 break; 1432 } 1433 case TypeSplitVector: 1434 case TypeScalarizeVector: { 1435 MVT IntermediateVT; 1436 MVT RegisterVT; 1437 unsigned NumIntermediates; 1438 NumRegistersForVT[i] = getVectorTypeBreakdownMVT(VT, IntermediateVT, 1439 NumIntermediates, RegisterVT, this); 1440 RegisterTypeForVT[i] = RegisterVT; 1441 1442 MVT NVT = VT.getPow2VectorType(); 1443 if (NVT == VT) { 1444 // Type is already a power of 2. The default action is to split. 1445 TransformToType[i] = MVT::Other; 1446 if (PreferredAction == TypeScalarizeVector) 1447 ValueTypeActions.setTypeAction(VT, TypeScalarizeVector); 1448 else if (PreferredAction == TypeSplitVector) 1449 ValueTypeActions.setTypeAction(VT, TypeSplitVector); 1450 else 1451 // Set type action according to the number of elements. 1452 ValueTypeActions.setTypeAction(VT, NElts == 1 ? TypeScalarizeVector 1453 : TypeSplitVector); 1454 } else { 1455 TransformToType[i] = NVT; 1456 ValueTypeActions.setTypeAction(VT, TypeWidenVector); 1457 } 1458 break; 1459 } 1460 default: 1461 llvm_unreachable("Unknown vector legalization action!"); 1462 } 1463 } 1464 1465 // Determine the 'representative' register class for each value type. 1466 // An representative register class is the largest (meaning one which is 1467 // not a sub-register class / subreg register class) legal register class for 1468 // a group of value types. For example, on i386, i8, i16, and i32 1469 // representative would be GR32; while on x86_64 it's GR64. 1470 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) { 1471 const TargetRegisterClass* RRC; 1472 uint8_t Cost; 1473 std::tie(RRC, Cost) = findRepresentativeClass(TRI, (MVT::SimpleValueType)i); 1474 RepRegClassForVT[i] = RRC; 1475 RepRegClassCostForVT[i] = Cost; 1476 } 1477 } 1478 1479 EVT TargetLoweringBase::getSetCCResultType(const DataLayout &DL, LLVMContext &, 1480 EVT VT) const { 1481 assert(!VT.isVector() && "No default SetCC type for vectors!"); 1482 return getPointerTy(DL).SimpleTy; 1483 } 1484 1485 MVT::SimpleValueType TargetLoweringBase::getCmpLibcallReturnType() const { 1486 return MVT::i32; // return the default value 1487 } 1488 1489 TargetRecip 1490 TargetLoweringBase::getTargetRecipForFunc(MachineFunction &MF) const { 1491 const Function *F = MF.getFunction(); 1492 StringRef RecipAttrName = "reciprocal-estimates"; 1493 if (!F->hasFnAttribute(RecipAttrName)) 1494 return ReciprocalEstimates; 1495 1496 // Make a copy of the target's default reciprocal codegen settings. 1497 TargetRecip Recips = ReciprocalEstimates; 1498 1499 // Override any settings that are customized for this function. 1500 StringRef RecipString = F->getFnAttribute(RecipAttrName).getValueAsString(); 1501 Recips.set(RecipString); 1502 return Recips; 1503 } 1504 1505 /// getVectorTypeBreakdown - Vector types are broken down into some number of 1506 /// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32 1507 /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack. 1508 /// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86. 1509 /// 1510 /// This method returns the number of registers needed, and the VT for each 1511 /// register. It also returns the VT and quantity of the intermediate values 1512 /// before they are promoted/expanded. 1513 /// 1514 unsigned TargetLoweringBase::getVectorTypeBreakdown(LLVMContext &Context, EVT VT, 1515 EVT &IntermediateVT, 1516 unsigned &NumIntermediates, 1517 MVT &RegisterVT) const { 1518 unsigned NumElts = VT.getVectorNumElements(); 1519 1520 // If there is a wider vector type with the same element type as this one, 1521 // or a promoted vector type that has the same number of elements which 1522 // are wider, then we should convert to that legal vector type. 1523 // This handles things like <2 x float> -> <4 x float> and 1524 // <4 x i1> -> <4 x i32>. 1525 LegalizeTypeAction TA = getTypeAction(Context, VT); 1526 if (NumElts != 1 && (TA == TypeWidenVector || TA == TypePromoteInteger)) { 1527 EVT RegisterEVT = getTypeToTransformTo(Context, VT); 1528 if (isTypeLegal(RegisterEVT)) { 1529 IntermediateVT = RegisterEVT; 1530 RegisterVT = RegisterEVT.getSimpleVT(); 1531 NumIntermediates = 1; 1532 return 1; 1533 } 1534 } 1535 1536 // Figure out the right, legal destination reg to copy into. 1537 EVT EltTy = VT.getVectorElementType(); 1538 1539 unsigned NumVectorRegs = 1; 1540 1541 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we 1542 // could break down into LHS/RHS like LegalizeDAG does. 1543 if (!isPowerOf2_32(NumElts)) { 1544 NumVectorRegs = NumElts; 1545 NumElts = 1; 1546 } 1547 1548 // Divide the input until we get to a supported size. This will always 1549 // end with a scalar if the target doesn't support vectors. 1550 while (NumElts > 1 && !isTypeLegal( 1551 EVT::getVectorVT(Context, EltTy, NumElts))) { 1552 NumElts >>= 1; 1553 NumVectorRegs <<= 1; 1554 } 1555 1556 NumIntermediates = NumVectorRegs; 1557 1558 EVT NewVT = EVT::getVectorVT(Context, EltTy, NumElts); 1559 if (!isTypeLegal(NewVT)) 1560 NewVT = EltTy; 1561 IntermediateVT = NewVT; 1562 1563 MVT DestVT = getRegisterType(Context, NewVT); 1564 RegisterVT = DestVT; 1565 unsigned NewVTSize = NewVT.getSizeInBits(); 1566 1567 // Convert sizes such as i33 to i64. 1568 if (!isPowerOf2_32(NewVTSize)) 1569 NewVTSize = NextPowerOf2(NewVTSize); 1570 1571 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16. 1572 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits()); 1573 1574 // Otherwise, promotion or legal types use the same number of registers as 1575 // the vector decimated to the appropriate level. 1576 return NumVectorRegs; 1577 } 1578 1579 /// Get the EVTs and ArgFlags collections that represent the legalized return 1580 /// type of the given function. This does not require a DAG or a return value, 1581 /// and is suitable for use before any DAGs for the function are constructed. 1582 /// TODO: Move this out of TargetLowering.cpp. 1583 void llvm::GetReturnInfo(Type *ReturnType, AttributeSet attr, 1584 SmallVectorImpl<ISD::OutputArg> &Outs, 1585 const TargetLowering &TLI, const DataLayout &DL) { 1586 SmallVector<EVT, 4> ValueVTs; 1587 ComputeValueVTs(TLI, DL, ReturnType, ValueVTs); 1588 unsigned NumValues = ValueVTs.size(); 1589 if (NumValues == 0) return; 1590 1591 for (unsigned j = 0, f = NumValues; j != f; ++j) { 1592 EVT VT = ValueVTs[j]; 1593 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 1594 1595 if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::SExt)) 1596 ExtendKind = ISD::SIGN_EXTEND; 1597 else if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::ZExt)) 1598 ExtendKind = ISD::ZERO_EXTEND; 1599 1600 // FIXME: C calling convention requires the return type to be promoted to 1601 // at least 32-bit. But this is not necessary for non-C calling 1602 // conventions. The frontend should mark functions whose return values 1603 // require promoting with signext or zeroext attributes. 1604 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) { 1605 MVT MinVT = TLI.getRegisterType(ReturnType->getContext(), MVT::i32); 1606 if (VT.bitsLT(MinVT)) 1607 VT = MinVT; 1608 } 1609 1610 unsigned NumParts = TLI.getNumRegisters(ReturnType->getContext(), VT); 1611 MVT PartVT = TLI.getRegisterType(ReturnType->getContext(), VT); 1612 1613 // 'inreg' on function refers to return value 1614 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy(); 1615 if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::InReg)) 1616 Flags.setInReg(); 1617 1618 // Propagate extension type if any 1619 if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::SExt)) 1620 Flags.setSExt(); 1621 else if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::ZExt)) 1622 Flags.setZExt(); 1623 1624 for (unsigned i = 0; i < NumParts; ++i) 1625 Outs.push_back(ISD::OutputArg(Flags, PartVT, VT, /*isFixed=*/true, 0, 0)); 1626 } 1627 } 1628 1629 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 1630 /// function arguments in the caller parameter area. This is the actual 1631 /// alignment, not its logarithm. 1632 unsigned TargetLoweringBase::getByValTypeAlignment(Type *Ty, 1633 const DataLayout &DL) const { 1634 return DL.getABITypeAlignment(Ty); 1635 } 1636 1637 bool TargetLoweringBase::allowsMemoryAccess(LLVMContext &Context, 1638 const DataLayout &DL, EVT VT, 1639 unsigned AddrSpace, 1640 unsigned Alignment, 1641 bool *Fast) const { 1642 // Check if the specified alignment is sufficient based on the data layout. 1643 // TODO: While using the data layout works in practice, a better solution 1644 // would be to implement this check directly (make this a virtual function). 1645 // For example, the ABI alignment may change based on software platform while 1646 // this function should only be affected by hardware implementation. 1647 Type *Ty = VT.getTypeForEVT(Context); 1648 if (Alignment >= DL.getABITypeAlignment(Ty)) { 1649 // Assume that an access that meets the ABI-specified alignment is fast. 1650 if (Fast != nullptr) 1651 *Fast = true; 1652 return true; 1653 } 1654 1655 // This is a misaligned access. 1656 return allowsMisalignedMemoryAccesses(VT, AddrSpace, Alignment, Fast); 1657 } 1658 1659 BranchProbability TargetLoweringBase::getPredictableBranchThreshold() const { 1660 return BranchProbability(MinPercentageForPredictableBranch, 100); 1661 } 1662 1663 //===----------------------------------------------------------------------===// 1664 // TargetTransformInfo Helpers 1665 //===----------------------------------------------------------------------===// 1666 1667 int TargetLoweringBase::InstructionOpcodeToISD(unsigned Opcode) const { 1668 enum InstructionOpcodes { 1669 #define HANDLE_INST(NUM, OPCODE, CLASS) OPCODE = NUM, 1670 #define LAST_OTHER_INST(NUM) InstructionOpcodesCount = NUM 1671 #include "llvm/IR/Instruction.def" 1672 }; 1673 switch (static_cast<InstructionOpcodes>(Opcode)) { 1674 case Ret: return 0; 1675 case Br: return 0; 1676 case Switch: return 0; 1677 case IndirectBr: return 0; 1678 case Invoke: return 0; 1679 case Resume: return 0; 1680 case Unreachable: return 0; 1681 case CleanupRet: return 0; 1682 case CatchRet: return 0; 1683 case CatchPad: return 0; 1684 case CatchSwitch: return 0; 1685 case CleanupPad: return 0; 1686 case Add: return ISD::ADD; 1687 case FAdd: return ISD::FADD; 1688 case Sub: return ISD::SUB; 1689 case FSub: return ISD::FSUB; 1690 case Mul: return ISD::MUL; 1691 case FMul: return ISD::FMUL; 1692 case UDiv: return ISD::UDIV; 1693 case SDiv: return ISD::SDIV; 1694 case FDiv: return ISD::FDIV; 1695 case URem: return ISD::UREM; 1696 case SRem: return ISD::SREM; 1697 case FRem: return ISD::FREM; 1698 case Shl: return ISD::SHL; 1699 case LShr: return ISD::SRL; 1700 case AShr: return ISD::SRA; 1701 case And: return ISD::AND; 1702 case Or: return ISD::OR; 1703 case Xor: return ISD::XOR; 1704 case Alloca: return 0; 1705 case Load: return ISD::LOAD; 1706 case Store: return ISD::STORE; 1707 case GetElementPtr: return 0; 1708 case Fence: return 0; 1709 case AtomicCmpXchg: return 0; 1710 case AtomicRMW: return 0; 1711 case Trunc: return ISD::TRUNCATE; 1712 case ZExt: return ISD::ZERO_EXTEND; 1713 case SExt: return ISD::SIGN_EXTEND; 1714 case FPToUI: return ISD::FP_TO_UINT; 1715 case FPToSI: return ISD::FP_TO_SINT; 1716 case UIToFP: return ISD::UINT_TO_FP; 1717 case SIToFP: return ISD::SINT_TO_FP; 1718 case FPTrunc: return ISD::FP_ROUND; 1719 case FPExt: return ISD::FP_EXTEND; 1720 case PtrToInt: return ISD::BITCAST; 1721 case IntToPtr: return ISD::BITCAST; 1722 case BitCast: return ISD::BITCAST; 1723 case AddrSpaceCast: return ISD::ADDRSPACECAST; 1724 case ICmp: return ISD::SETCC; 1725 case FCmp: return ISD::SETCC; 1726 case PHI: return 0; 1727 case Call: return 0; 1728 case Select: return ISD::SELECT; 1729 case UserOp1: return 0; 1730 case UserOp2: return 0; 1731 case VAArg: return 0; 1732 case ExtractElement: return ISD::EXTRACT_VECTOR_ELT; 1733 case InsertElement: return ISD::INSERT_VECTOR_ELT; 1734 case ShuffleVector: return ISD::VECTOR_SHUFFLE; 1735 case ExtractValue: return ISD::MERGE_VALUES; 1736 case InsertValue: return ISD::MERGE_VALUES; 1737 case LandingPad: return 0; 1738 } 1739 1740 llvm_unreachable("Unknown instruction type encountered!"); 1741 } 1742 1743 std::pair<int, MVT> 1744 TargetLoweringBase::getTypeLegalizationCost(const DataLayout &DL, 1745 Type *Ty) const { 1746 LLVMContext &C = Ty->getContext(); 1747 EVT MTy = getValueType(DL, Ty); 1748 1749 int Cost = 1; 1750 // We keep legalizing the type until we find a legal kind. We assume that 1751 // the only operation that costs anything is the split. After splitting 1752 // we need to handle two types. 1753 while (true) { 1754 LegalizeKind LK = getTypeConversion(C, MTy); 1755 1756 if (LK.first == TypeLegal) 1757 return std::make_pair(Cost, MTy.getSimpleVT()); 1758 1759 if (LK.first == TypeSplitVector || LK.first == TypeExpandInteger) 1760 Cost *= 2; 1761 1762 // Do not loop with f128 type. 1763 if (MTy == LK.second) 1764 return std::make_pair(Cost, MTy.getSimpleVT()); 1765 1766 // Keep legalizing the type. 1767 MTy = LK.second; 1768 } 1769 } 1770 1771 Value *TargetLoweringBase::getSafeStackPointerLocation(IRBuilder<> &IRB) const { 1772 if (!TM.getTargetTriple().isAndroid()) 1773 return nullptr; 1774 1775 // Android provides a libc function to retrieve the address of the current 1776 // thread's unsafe stack pointer. 1777 Module *M = IRB.GetInsertBlock()->getParent()->getParent(); 1778 Type *StackPtrTy = Type::getInt8PtrTy(M->getContext()); 1779 Value *Fn = M->getOrInsertFunction("__safestack_pointer_address", 1780 StackPtrTy->getPointerTo(0), nullptr); 1781 return IRB.CreateCall(Fn); 1782 } 1783 1784 //===----------------------------------------------------------------------===// 1785 // Loop Strength Reduction hooks 1786 //===----------------------------------------------------------------------===// 1787 1788 /// isLegalAddressingMode - Return true if the addressing mode represented 1789 /// by AM is legal for this target, for a load/store of the specified type. 1790 bool TargetLoweringBase::isLegalAddressingMode(const DataLayout &DL, 1791 const AddrMode &AM, Type *Ty, 1792 unsigned AS) const { 1793 // The default implementation of this implements a conservative RISCy, r+r and 1794 // r+i addr mode. 1795 1796 // Allows a sign-extended 16-bit immediate field. 1797 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1) 1798 return false; 1799 1800 // No global is ever allowed as a base. 1801 if (AM.BaseGV) 1802 return false; 1803 1804 // Only support r+r, 1805 switch (AM.Scale) { 1806 case 0: // "r+i" or just "i", depending on HasBaseReg. 1807 break; 1808 case 1: 1809 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. 1810 return false; 1811 // Otherwise we have r+r or r+i. 1812 break; 1813 case 2: 1814 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. 1815 return false; 1816 // Allow 2*r as r+r. 1817 break; 1818 default: // Don't allow n * r 1819 return false; 1820 } 1821 1822 return true; 1823 } 1824 1825 //===----------------------------------------------------------------------===// 1826 // Stack Protector 1827 //===----------------------------------------------------------------------===// 1828 1829 // For OpenBSD return its special guard variable. Otherwise return nullptr, 1830 // so that SelectionDAG handle SSP. 1831 Value *TargetLoweringBase::getIRStackGuard(IRBuilder<> &IRB) const { 1832 if (getTargetMachine().getTargetTriple().isOSOpenBSD()) { 1833 Module &M = *IRB.GetInsertBlock()->getParent()->getParent(); 1834 PointerType *PtrTy = Type::getInt8PtrTy(M.getContext()); 1835 return M.getOrInsertGlobal("__guard_local", PtrTy); 1836 } 1837 return nullptr; 1838 } 1839 1840 // Currently only support "standard" __stack_chk_guard. 1841 // TODO: add LOAD_STACK_GUARD support. 1842 void TargetLoweringBase::insertSSPDeclarations(Module &M) const { 1843 M.getOrInsertGlobal("__stack_chk_guard", Type::getInt8PtrTy(M.getContext())); 1844 } 1845 1846 // Currently only support "standard" __stack_chk_guard. 1847 // TODO: add LOAD_STACK_GUARD support. 1848 Value *TargetLoweringBase::getSDagStackGuard(const Module &M) const { 1849 return M.getGlobalVariable("__stack_chk_guard", true); 1850 } 1851 1852 Value *TargetLoweringBase::getSSPStackGuardCheck(const Module &M) const { 1853 return nullptr; 1854 } 1855 1856 unsigned TargetLoweringBase::getMaximumJumpTableSize() const { 1857 return MaximumJumpTableSize; 1858 } 1859 1860 void TargetLoweringBase::setMaximumJumpTableSize(unsigned Val) { 1861 MaximumJumpTableSize = Val; 1862 } 1863