1 //===-- TargetLoweringBase.cpp - Implement the TargetLoweringBase class ---===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This implements the TargetLoweringBase class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "llvm/Target/TargetLowering.h" 15 #include "llvm/ADT/BitVector.h" 16 #include "llvm/ADT/STLExtras.h" 17 #include "llvm/CodeGen/Analysis.h" 18 #include "llvm/CodeGen/MachineFrameInfo.h" 19 #include "llvm/CodeGen/MachineFunction.h" 20 #include "llvm/CodeGen/MachineJumpTableInfo.h" 21 #include "llvm/IR/DataLayout.h" 22 #include "llvm/IR/DerivedTypes.h" 23 #include "llvm/IR/GlobalVariable.h" 24 #include "llvm/MC/MCAsmInfo.h" 25 #include "llvm/MC/MCExpr.h" 26 #include "llvm/Support/CommandLine.h" 27 #include "llvm/Support/ErrorHandling.h" 28 #include "llvm/Support/MathExtras.h" 29 #include "llvm/Target/TargetLoweringObjectFile.h" 30 #include "llvm/Target/TargetMachine.h" 31 #include "llvm/Target/TargetRegisterInfo.h" 32 #include <cctype> 33 using namespace llvm; 34 35 /// InitLibcallNames - Set default libcall names. 36 /// 37 static void InitLibcallNames(const char **Names) { 38 Names[RTLIB::SHL_I16] = "__ashlhi3"; 39 Names[RTLIB::SHL_I32] = "__ashlsi3"; 40 Names[RTLIB::SHL_I64] = "__ashldi3"; 41 Names[RTLIB::SHL_I128] = "__ashlti3"; 42 Names[RTLIB::SRL_I16] = "__lshrhi3"; 43 Names[RTLIB::SRL_I32] = "__lshrsi3"; 44 Names[RTLIB::SRL_I64] = "__lshrdi3"; 45 Names[RTLIB::SRL_I128] = "__lshrti3"; 46 Names[RTLIB::SRA_I16] = "__ashrhi3"; 47 Names[RTLIB::SRA_I32] = "__ashrsi3"; 48 Names[RTLIB::SRA_I64] = "__ashrdi3"; 49 Names[RTLIB::SRA_I128] = "__ashrti3"; 50 Names[RTLIB::MUL_I8] = "__mulqi3"; 51 Names[RTLIB::MUL_I16] = "__mulhi3"; 52 Names[RTLIB::MUL_I32] = "__mulsi3"; 53 Names[RTLIB::MUL_I64] = "__muldi3"; 54 Names[RTLIB::MUL_I128] = "__multi3"; 55 Names[RTLIB::MULO_I32] = "__mulosi4"; 56 Names[RTLIB::MULO_I64] = "__mulodi4"; 57 Names[RTLIB::MULO_I128] = "__muloti4"; 58 Names[RTLIB::SDIV_I8] = "__divqi3"; 59 Names[RTLIB::SDIV_I16] = "__divhi3"; 60 Names[RTLIB::SDIV_I32] = "__divsi3"; 61 Names[RTLIB::SDIV_I64] = "__divdi3"; 62 Names[RTLIB::SDIV_I128] = "__divti3"; 63 Names[RTLIB::UDIV_I8] = "__udivqi3"; 64 Names[RTLIB::UDIV_I16] = "__udivhi3"; 65 Names[RTLIB::UDIV_I32] = "__udivsi3"; 66 Names[RTLIB::UDIV_I64] = "__udivdi3"; 67 Names[RTLIB::UDIV_I128] = "__udivti3"; 68 Names[RTLIB::SREM_I8] = "__modqi3"; 69 Names[RTLIB::SREM_I16] = "__modhi3"; 70 Names[RTLIB::SREM_I32] = "__modsi3"; 71 Names[RTLIB::SREM_I64] = "__moddi3"; 72 Names[RTLIB::SREM_I128] = "__modti3"; 73 Names[RTLIB::UREM_I8] = "__umodqi3"; 74 Names[RTLIB::UREM_I16] = "__umodhi3"; 75 Names[RTLIB::UREM_I32] = "__umodsi3"; 76 Names[RTLIB::UREM_I64] = "__umoddi3"; 77 Names[RTLIB::UREM_I128] = "__umodti3"; 78 79 // These are generally not available. 80 Names[RTLIB::SDIVREM_I8] = 0; 81 Names[RTLIB::SDIVREM_I16] = 0; 82 Names[RTLIB::SDIVREM_I32] = 0; 83 Names[RTLIB::SDIVREM_I64] = 0; 84 Names[RTLIB::SDIVREM_I128] = 0; 85 Names[RTLIB::UDIVREM_I8] = 0; 86 Names[RTLIB::UDIVREM_I16] = 0; 87 Names[RTLIB::UDIVREM_I32] = 0; 88 Names[RTLIB::UDIVREM_I64] = 0; 89 Names[RTLIB::UDIVREM_I128] = 0; 90 91 Names[RTLIB::NEG_I32] = "__negsi2"; 92 Names[RTLIB::NEG_I64] = "__negdi2"; 93 Names[RTLIB::ADD_F32] = "__addsf3"; 94 Names[RTLIB::ADD_F64] = "__adddf3"; 95 Names[RTLIB::ADD_F80] = "__addxf3"; 96 Names[RTLIB::ADD_F128] = "__addtf3"; 97 Names[RTLIB::ADD_PPCF128] = "__gcc_qadd"; 98 Names[RTLIB::SUB_F32] = "__subsf3"; 99 Names[RTLIB::SUB_F64] = "__subdf3"; 100 Names[RTLIB::SUB_F80] = "__subxf3"; 101 Names[RTLIB::SUB_F128] = "__subtf3"; 102 Names[RTLIB::SUB_PPCF128] = "__gcc_qsub"; 103 Names[RTLIB::MUL_F32] = "__mulsf3"; 104 Names[RTLIB::MUL_F64] = "__muldf3"; 105 Names[RTLIB::MUL_F80] = "__mulxf3"; 106 Names[RTLIB::MUL_F128] = "__multf3"; 107 Names[RTLIB::MUL_PPCF128] = "__gcc_qmul"; 108 Names[RTLIB::DIV_F32] = "__divsf3"; 109 Names[RTLIB::DIV_F64] = "__divdf3"; 110 Names[RTLIB::DIV_F80] = "__divxf3"; 111 Names[RTLIB::DIV_F128] = "__divtf3"; 112 Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv"; 113 Names[RTLIB::REM_F32] = "fmodf"; 114 Names[RTLIB::REM_F64] = "fmod"; 115 Names[RTLIB::REM_F80] = "fmodl"; 116 Names[RTLIB::REM_F128] = "fmodl"; 117 Names[RTLIB::REM_PPCF128] = "fmodl"; 118 Names[RTLIB::FMA_F32] = "fmaf"; 119 Names[RTLIB::FMA_F64] = "fma"; 120 Names[RTLIB::FMA_F80] = "fmal"; 121 Names[RTLIB::FMA_F128] = "fmal"; 122 Names[RTLIB::FMA_PPCF128] = "fmal"; 123 Names[RTLIB::POWI_F32] = "__powisf2"; 124 Names[RTLIB::POWI_F64] = "__powidf2"; 125 Names[RTLIB::POWI_F80] = "__powixf2"; 126 Names[RTLIB::POWI_F128] = "__powitf2"; 127 Names[RTLIB::POWI_PPCF128] = "__powitf2"; 128 Names[RTLIB::SQRT_F32] = "sqrtf"; 129 Names[RTLIB::SQRT_F64] = "sqrt"; 130 Names[RTLIB::SQRT_F80] = "sqrtl"; 131 Names[RTLIB::SQRT_F128] = "sqrtl"; 132 Names[RTLIB::SQRT_PPCF128] = "sqrtl"; 133 Names[RTLIB::LOG_F32] = "logf"; 134 Names[RTLIB::LOG_F64] = "log"; 135 Names[RTLIB::LOG_F80] = "logl"; 136 Names[RTLIB::LOG_F128] = "logl"; 137 Names[RTLIB::LOG_PPCF128] = "logl"; 138 Names[RTLIB::LOG2_F32] = "log2f"; 139 Names[RTLIB::LOG2_F64] = "log2"; 140 Names[RTLIB::LOG2_F80] = "log2l"; 141 Names[RTLIB::LOG2_F128] = "log2l"; 142 Names[RTLIB::LOG2_PPCF128] = "log2l"; 143 Names[RTLIB::LOG10_F32] = "log10f"; 144 Names[RTLIB::LOG10_F64] = "log10"; 145 Names[RTLIB::LOG10_F80] = "log10l"; 146 Names[RTLIB::LOG10_F128] = "log10l"; 147 Names[RTLIB::LOG10_PPCF128] = "log10l"; 148 Names[RTLIB::EXP_F32] = "expf"; 149 Names[RTLIB::EXP_F64] = "exp"; 150 Names[RTLIB::EXP_F80] = "expl"; 151 Names[RTLIB::EXP_F128] = "expl"; 152 Names[RTLIB::EXP_PPCF128] = "expl"; 153 Names[RTLIB::EXP2_F32] = "exp2f"; 154 Names[RTLIB::EXP2_F64] = "exp2"; 155 Names[RTLIB::EXP2_F80] = "exp2l"; 156 Names[RTLIB::EXP2_F128] = "exp2l"; 157 Names[RTLIB::EXP2_PPCF128] = "exp2l"; 158 Names[RTLIB::SIN_F32] = "sinf"; 159 Names[RTLIB::SIN_F64] = "sin"; 160 Names[RTLIB::SIN_F80] = "sinl"; 161 Names[RTLIB::SIN_F128] = "sinl"; 162 Names[RTLIB::SIN_PPCF128] = "sinl"; 163 Names[RTLIB::COS_F32] = "cosf"; 164 Names[RTLIB::COS_F64] = "cos"; 165 Names[RTLIB::COS_F80] = "cosl"; 166 Names[RTLIB::COS_F128] = "cosl"; 167 Names[RTLIB::COS_PPCF128] = "cosl"; 168 Names[RTLIB::POW_F32] = "powf"; 169 Names[RTLIB::POW_F64] = "pow"; 170 Names[RTLIB::POW_F80] = "powl"; 171 Names[RTLIB::POW_F128] = "powl"; 172 Names[RTLIB::POW_PPCF128] = "powl"; 173 Names[RTLIB::CEIL_F32] = "ceilf"; 174 Names[RTLIB::CEIL_F64] = "ceil"; 175 Names[RTLIB::CEIL_F80] = "ceill"; 176 Names[RTLIB::CEIL_F128] = "ceill"; 177 Names[RTLIB::CEIL_PPCF128] = "ceill"; 178 Names[RTLIB::TRUNC_F32] = "truncf"; 179 Names[RTLIB::TRUNC_F64] = "trunc"; 180 Names[RTLIB::TRUNC_F80] = "truncl"; 181 Names[RTLIB::TRUNC_F128] = "truncl"; 182 Names[RTLIB::TRUNC_PPCF128] = "truncl"; 183 Names[RTLIB::RINT_F32] = "rintf"; 184 Names[RTLIB::RINT_F64] = "rint"; 185 Names[RTLIB::RINT_F80] = "rintl"; 186 Names[RTLIB::RINT_F128] = "rintl"; 187 Names[RTLIB::RINT_PPCF128] = "rintl"; 188 Names[RTLIB::NEARBYINT_F32] = "nearbyintf"; 189 Names[RTLIB::NEARBYINT_F64] = "nearbyint"; 190 Names[RTLIB::NEARBYINT_F80] = "nearbyintl"; 191 Names[RTLIB::NEARBYINT_F128] = "nearbyintl"; 192 Names[RTLIB::NEARBYINT_PPCF128] = "nearbyintl"; 193 Names[RTLIB::FLOOR_F32] = "floorf"; 194 Names[RTLIB::FLOOR_F64] = "floor"; 195 Names[RTLIB::FLOOR_F80] = "floorl"; 196 Names[RTLIB::FLOOR_F128] = "floorl"; 197 Names[RTLIB::FLOOR_PPCF128] = "floorl"; 198 Names[RTLIB::COPYSIGN_F32] = "copysignf"; 199 Names[RTLIB::COPYSIGN_F64] = "copysign"; 200 Names[RTLIB::COPYSIGN_F80] = "copysignl"; 201 Names[RTLIB::COPYSIGN_F128] = "copysignl"; 202 Names[RTLIB::COPYSIGN_PPCF128] = "copysignl"; 203 Names[RTLIB::FPEXT_F64_F128] = "__extenddftf2"; 204 Names[RTLIB::FPEXT_F32_F128] = "__extendsftf2"; 205 Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2"; 206 Names[RTLIB::FPEXT_F16_F32] = "__gnu_h2f_ieee"; 207 Names[RTLIB::FPROUND_F32_F16] = "__gnu_f2h_ieee"; 208 Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2"; 209 Names[RTLIB::FPROUND_F80_F32] = "__truncxfsf2"; 210 Names[RTLIB::FPROUND_F128_F32] = "__trunctfsf2"; 211 Names[RTLIB::FPROUND_PPCF128_F32] = "__trunctfsf2"; 212 Names[RTLIB::FPROUND_F80_F64] = "__truncxfdf2"; 213 Names[RTLIB::FPROUND_F128_F64] = "__trunctfdf2"; 214 Names[RTLIB::FPROUND_PPCF128_F64] = "__trunctfdf2"; 215 Names[RTLIB::FPTOSINT_F32_I8] = "__fixsfqi"; 216 Names[RTLIB::FPTOSINT_F32_I16] = "__fixsfhi"; 217 Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi"; 218 Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi"; 219 Names[RTLIB::FPTOSINT_F32_I128] = "__fixsfti"; 220 Names[RTLIB::FPTOSINT_F64_I8] = "__fixdfqi"; 221 Names[RTLIB::FPTOSINT_F64_I16] = "__fixdfhi"; 222 Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi"; 223 Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi"; 224 Names[RTLIB::FPTOSINT_F64_I128] = "__fixdfti"; 225 Names[RTLIB::FPTOSINT_F80_I32] = "__fixxfsi"; 226 Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi"; 227 Names[RTLIB::FPTOSINT_F80_I128] = "__fixxfti"; 228 Names[RTLIB::FPTOSINT_F128_I32] = "__fixtfsi"; 229 Names[RTLIB::FPTOSINT_F128_I64] = "__fixtfdi"; 230 Names[RTLIB::FPTOSINT_F128_I128] = "__fixtfti"; 231 Names[RTLIB::FPTOSINT_PPCF128_I32] = "__fixtfsi"; 232 Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi"; 233 Names[RTLIB::FPTOSINT_PPCF128_I128] = "__fixtfti"; 234 Names[RTLIB::FPTOUINT_F32_I8] = "__fixunssfqi"; 235 Names[RTLIB::FPTOUINT_F32_I16] = "__fixunssfhi"; 236 Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi"; 237 Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi"; 238 Names[RTLIB::FPTOUINT_F32_I128] = "__fixunssfti"; 239 Names[RTLIB::FPTOUINT_F64_I8] = "__fixunsdfqi"; 240 Names[RTLIB::FPTOUINT_F64_I16] = "__fixunsdfhi"; 241 Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi"; 242 Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi"; 243 Names[RTLIB::FPTOUINT_F64_I128] = "__fixunsdfti"; 244 Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi"; 245 Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi"; 246 Names[RTLIB::FPTOUINT_F80_I128] = "__fixunsxfti"; 247 Names[RTLIB::FPTOUINT_F128_I32] = "__fixunstfsi"; 248 Names[RTLIB::FPTOUINT_F128_I64] = "__fixunstfdi"; 249 Names[RTLIB::FPTOUINT_F128_I128] = "__fixunstfti"; 250 Names[RTLIB::FPTOUINT_PPCF128_I32] = "__fixunstfsi"; 251 Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi"; 252 Names[RTLIB::FPTOUINT_PPCF128_I128] = "__fixunstfti"; 253 Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf"; 254 Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf"; 255 Names[RTLIB::SINTTOFP_I32_F80] = "__floatsixf"; 256 Names[RTLIB::SINTTOFP_I32_F128] = "__floatsitf"; 257 Names[RTLIB::SINTTOFP_I32_PPCF128] = "__floatsitf"; 258 Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf"; 259 Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf"; 260 Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf"; 261 Names[RTLIB::SINTTOFP_I64_F128] = "__floatditf"; 262 Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf"; 263 Names[RTLIB::SINTTOFP_I128_F32] = "__floattisf"; 264 Names[RTLIB::SINTTOFP_I128_F64] = "__floattidf"; 265 Names[RTLIB::SINTTOFP_I128_F80] = "__floattixf"; 266 Names[RTLIB::SINTTOFP_I128_F128] = "__floattitf"; 267 Names[RTLIB::SINTTOFP_I128_PPCF128] = "__floattitf"; 268 Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf"; 269 Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf"; 270 Names[RTLIB::UINTTOFP_I32_F80] = "__floatunsixf"; 271 Names[RTLIB::UINTTOFP_I32_F128] = "__floatunsitf"; 272 Names[RTLIB::UINTTOFP_I32_PPCF128] = "__floatunsitf"; 273 Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf"; 274 Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf"; 275 Names[RTLIB::UINTTOFP_I64_F80] = "__floatundixf"; 276 Names[RTLIB::UINTTOFP_I64_F128] = "__floatunditf"; 277 Names[RTLIB::UINTTOFP_I64_PPCF128] = "__floatunditf"; 278 Names[RTLIB::UINTTOFP_I128_F32] = "__floatuntisf"; 279 Names[RTLIB::UINTTOFP_I128_F64] = "__floatuntidf"; 280 Names[RTLIB::UINTTOFP_I128_F80] = "__floatuntixf"; 281 Names[RTLIB::UINTTOFP_I128_F128] = "__floatuntitf"; 282 Names[RTLIB::UINTTOFP_I128_PPCF128] = "__floatuntitf"; 283 Names[RTLIB::OEQ_F32] = "__eqsf2"; 284 Names[RTLIB::OEQ_F64] = "__eqdf2"; 285 Names[RTLIB::OEQ_F128] = "__eqtf2"; 286 Names[RTLIB::UNE_F32] = "__nesf2"; 287 Names[RTLIB::UNE_F64] = "__nedf2"; 288 Names[RTLIB::UNE_F128] = "__netf2"; 289 Names[RTLIB::OGE_F32] = "__gesf2"; 290 Names[RTLIB::OGE_F64] = "__gedf2"; 291 Names[RTLIB::OGE_F128] = "__getf2"; 292 Names[RTLIB::OLT_F32] = "__ltsf2"; 293 Names[RTLIB::OLT_F64] = "__ltdf2"; 294 Names[RTLIB::OLT_F128] = "__lttf2"; 295 Names[RTLIB::OLE_F32] = "__lesf2"; 296 Names[RTLIB::OLE_F64] = "__ledf2"; 297 Names[RTLIB::OLE_F128] = "__letf2"; 298 Names[RTLIB::OGT_F32] = "__gtsf2"; 299 Names[RTLIB::OGT_F64] = "__gtdf2"; 300 Names[RTLIB::OGT_F128] = "__gttf2"; 301 Names[RTLIB::UO_F32] = "__unordsf2"; 302 Names[RTLIB::UO_F64] = "__unorddf2"; 303 Names[RTLIB::UO_F128] = "__unordtf2"; 304 Names[RTLIB::O_F32] = "__unordsf2"; 305 Names[RTLIB::O_F64] = "__unorddf2"; 306 Names[RTLIB::O_F128] = "__unordtf2"; 307 Names[RTLIB::MEMCPY] = "memcpy"; 308 Names[RTLIB::MEMMOVE] = "memmove"; 309 Names[RTLIB::MEMSET] = "memset"; 310 Names[RTLIB::UNWIND_RESUME] = "_Unwind_Resume"; 311 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1] = "__sync_val_compare_and_swap_1"; 312 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2] = "__sync_val_compare_and_swap_2"; 313 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4] = "__sync_val_compare_and_swap_4"; 314 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8] = "__sync_val_compare_and_swap_8"; 315 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_1] = "__sync_lock_test_and_set_1"; 316 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_2] = "__sync_lock_test_and_set_2"; 317 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_4] = "__sync_lock_test_and_set_4"; 318 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_8] = "__sync_lock_test_and_set_8"; 319 Names[RTLIB::SYNC_FETCH_AND_ADD_1] = "__sync_fetch_and_add_1"; 320 Names[RTLIB::SYNC_FETCH_AND_ADD_2] = "__sync_fetch_and_add_2"; 321 Names[RTLIB::SYNC_FETCH_AND_ADD_4] = "__sync_fetch_and_add_4"; 322 Names[RTLIB::SYNC_FETCH_AND_ADD_8] = "__sync_fetch_and_add_8"; 323 Names[RTLIB::SYNC_FETCH_AND_SUB_1] = "__sync_fetch_and_sub_1"; 324 Names[RTLIB::SYNC_FETCH_AND_SUB_2] = "__sync_fetch_and_sub_2"; 325 Names[RTLIB::SYNC_FETCH_AND_SUB_4] = "__sync_fetch_and_sub_4"; 326 Names[RTLIB::SYNC_FETCH_AND_SUB_8] = "__sync_fetch_and_sub_8"; 327 Names[RTLIB::SYNC_FETCH_AND_AND_1] = "__sync_fetch_and_and_1"; 328 Names[RTLIB::SYNC_FETCH_AND_AND_2] = "__sync_fetch_and_and_2"; 329 Names[RTLIB::SYNC_FETCH_AND_AND_4] = "__sync_fetch_and_and_4"; 330 Names[RTLIB::SYNC_FETCH_AND_AND_8] = "__sync_fetch_and_and_8"; 331 Names[RTLIB::SYNC_FETCH_AND_OR_1] = "__sync_fetch_and_or_1"; 332 Names[RTLIB::SYNC_FETCH_AND_OR_2] = "__sync_fetch_and_or_2"; 333 Names[RTLIB::SYNC_FETCH_AND_OR_4] = "__sync_fetch_and_or_4"; 334 Names[RTLIB::SYNC_FETCH_AND_OR_8] = "__sync_fetch_and_or_8"; 335 Names[RTLIB::SYNC_FETCH_AND_XOR_1] = "__sync_fetch_and_xor_1"; 336 Names[RTLIB::SYNC_FETCH_AND_XOR_2] = "__sync_fetch_and_xor_2"; 337 Names[RTLIB::SYNC_FETCH_AND_XOR_4] = "__sync_fetch_and_xor_4"; 338 Names[RTLIB::SYNC_FETCH_AND_XOR_8] = "__sync_fetch_and_xor_8"; 339 Names[RTLIB::SYNC_FETCH_AND_NAND_1] = "__sync_fetch_and_nand_1"; 340 Names[RTLIB::SYNC_FETCH_AND_NAND_2] = "__sync_fetch_and_nand_2"; 341 Names[RTLIB::SYNC_FETCH_AND_NAND_4] = "__sync_fetch_and_nand_4"; 342 Names[RTLIB::SYNC_FETCH_AND_NAND_8] = "__sync_fetch_and_nand_8"; 343 344 // These are generally not available. 345 Names[RTLIB::SINCOS_F32] = 0; 346 Names[RTLIB::SINCOS_F64] = 0; 347 Names[RTLIB::SINCOS_F80] = 0; 348 Names[RTLIB::SINCOS_F128] = 0; 349 Names[RTLIB::SINCOS_PPCF128] = 0; 350 } 351 352 /// InitLibcallCallingConvs - Set default libcall CallingConvs. 353 /// 354 static void InitLibcallCallingConvs(CallingConv::ID *CCs) { 355 for (int i = 0; i < RTLIB::UNKNOWN_LIBCALL; ++i) { 356 CCs[i] = CallingConv::C; 357 } 358 } 359 360 /// getFPEXT - Return the FPEXT_*_* value for the given types, or 361 /// UNKNOWN_LIBCALL if there is none. 362 RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) { 363 if (OpVT == MVT::f32) { 364 if (RetVT == MVT::f64) 365 return FPEXT_F32_F64; 366 if (RetVT == MVT::f128) 367 return FPEXT_F32_F128; 368 } else if (OpVT == MVT::f64) { 369 if (RetVT == MVT::f128) 370 return FPEXT_F64_F128; 371 } 372 373 return UNKNOWN_LIBCALL; 374 } 375 376 /// getFPROUND - Return the FPROUND_*_* value for the given types, or 377 /// UNKNOWN_LIBCALL if there is none. 378 RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) { 379 if (RetVT == MVT::f32) { 380 if (OpVT == MVT::f64) 381 return FPROUND_F64_F32; 382 if (OpVT == MVT::f80) 383 return FPROUND_F80_F32; 384 if (OpVT == MVT::f128) 385 return FPROUND_F128_F32; 386 if (OpVT == MVT::ppcf128) 387 return FPROUND_PPCF128_F32; 388 } else if (RetVT == MVT::f64) { 389 if (OpVT == MVT::f80) 390 return FPROUND_F80_F64; 391 if (OpVT == MVT::f128) 392 return FPROUND_F128_F64; 393 if (OpVT == MVT::ppcf128) 394 return FPROUND_PPCF128_F64; 395 } 396 397 return UNKNOWN_LIBCALL; 398 } 399 400 /// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or 401 /// UNKNOWN_LIBCALL if there is none. 402 RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT, EVT RetVT) { 403 if (OpVT == MVT::f32) { 404 if (RetVT == MVT::i8) 405 return FPTOSINT_F32_I8; 406 if (RetVT == MVT::i16) 407 return FPTOSINT_F32_I16; 408 if (RetVT == MVT::i32) 409 return FPTOSINT_F32_I32; 410 if (RetVT == MVT::i64) 411 return FPTOSINT_F32_I64; 412 if (RetVT == MVT::i128) 413 return FPTOSINT_F32_I128; 414 } else if (OpVT == MVT::f64) { 415 if (RetVT == MVT::i8) 416 return FPTOSINT_F64_I8; 417 if (RetVT == MVT::i16) 418 return FPTOSINT_F64_I16; 419 if (RetVT == MVT::i32) 420 return FPTOSINT_F64_I32; 421 if (RetVT == MVT::i64) 422 return FPTOSINT_F64_I64; 423 if (RetVT == MVT::i128) 424 return FPTOSINT_F64_I128; 425 } else if (OpVT == MVT::f80) { 426 if (RetVT == MVT::i32) 427 return FPTOSINT_F80_I32; 428 if (RetVT == MVT::i64) 429 return FPTOSINT_F80_I64; 430 if (RetVT == MVT::i128) 431 return FPTOSINT_F80_I128; 432 } else if (OpVT == MVT::f128) { 433 if (RetVT == MVT::i32) 434 return FPTOSINT_F128_I32; 435 if (RetVT == MVT::i64) 436 return FPTOSINT_F128_I64; 437 if (RetVT == MVT::i128) 438 return FPTOSINT_F128_I128; 439 } else if (OpVT == MVT::ppcf128) { 440 if (RetVT == MVT::i32) 441 return FPTOSINT_PPCF128_I32; 442 if (RetVT == MVT::i64) 443 return FPTOSINT_PPCF128_I64; 444 if (RetVT == MVT::i128) 445 return FPTOSINT_PPCF128_I128; 446 } 447 return UNKNOWN_LIBCALL; 448 } 449 450 /// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or 451 /// UNKNOWN_LIBCALL if there is none. 452 RTLIB::Libcall RTLIB::getFPTOUINT(EVT OpVT, EVT RetVT) { 453 if (OpVT == MVT::f32) { 454 if (RetVT == MVT::i8) 455 return FPTOUINT_F32_I8; 456 if (RetVT == MVT::i16) 457 return FPTOUINT_F32_I16; 458 if (RetVT == MVT::i32) 459 return FPTOUINT_F32_I32; 460 if (RetVT == MVT::i64) 461 return FPTOUINT_F32_I64; 462 if (RetVT == MVT::i128) 463 return FPTOUINT_F32_I128; 464 } else if (OpVT == MVT::f64) { 465 if (RetVT == MVT::i8) 466 return FPTOUINT_F64_I8; 467 if (RetVT == MVT::i16) 468 return FPTOUINT_F64_I16; 469 if (RetVT == MVT::i32) 470 return FPTOUINT_F64_I32; 471 if (RetVT == MVT::i64) 472 return FPTOUINT_F64_I64; 473 if (RetVT == MVT::i128) 474 return FPTOUINT_F64_I128; 475 } else if (OpVT == MVT::f80) { 476 if (RetVT == MVT::i32) 477 return FPTOUINT_F80_I32; 478 if (RetVT == MVT::i64) 479 return FPTOUINT_F80_I64; 480 if (RetVT == MVT::i128) 481 return FPTOUINT_F80_I128; 482 } else if (OpVT == MVT::f128) { 483 if (RetVT == MVT::i32) 484 return FPTOUINT_F128_I32; 485 if (RetVT == MVT::i64) 486 return FPTOUINT_F128_I64; 487 if (RetVT == MVT::i128) 488 return FPTOUINT_F128_I128; 489 } else if (OpVT == MVT::ppcf128) { 490 if (RetVT == MVT::i32) 491 return FPTOUINT_PPCF128_I32; 492 if (RetVT == MVT::i64) 493 return FPTOUINT_PPCF128_I64; 494 if (RetVT == MVT::i128) 495 return FPTOUINT_PPCF128_I128; 496 } 497 return UNKNOWN_LIBCALL; 498 } 499 500 /// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or 501 /// UNKNOWN_LIBCALL if there is none. 502 RTLIB::Libcall RTLIB::getSINTTOFP(EVT OpVT, EVT RetVT) { 503 if (OpVT == MVT::i32) { 504 if (RetVT == MVT::f32) 505 return SINTTOFP_I32_F32; 506 if (RetVT == MVT::f64) 507 return SINTTOFP_I32_F64; 508 if (RetVT == MVT::f80) 509 return SINTTOFP_I32_F80; 510 if (RetVT == MVT::f128) 511 return SINTTOFP_I32_F128; 512 if (RetVT == MVT::ppcf128) 513 return SINTTOFP_I32_PPCF128; 514 } else if (OpVT == MVT::i64) { 515 if (RetVT == MVT::f32) 516 return SINTTOFP_I64_F32; 517 if (RetVT == MVT::f64) 518 return SINTTOFP_I64_F64; 519 if (RetVT == MVT::f80) 520 return SINTTOFP_I64_F80; 521 if (RetVT == MVT::f128) 522 return SINTTOFP_I64_F128; 523 if (RetVT == MVT::ppcf128) 524 return SINTTOFP_I64_PPCF128; 525 } else if (OpVT == MVT::i128) { 526 if (RetVT == MVT::f32) 527 return SINTTOFP_I128_F32; 528 if (RetVT == MVT::f64) 529 return SINTTOFP_I128_F64; 530 if (RetVT == MVT::f80) 531 return SINTTOFP_I128_F80; 532 if (RetVT == MVT::f128) 533 return SINTTOFP_I128_F128; 534 if (RetVT == MVT::ppcf128) 535 return SINTTOFP_I128_PPCF128; 536 } 537 return UNKNOWN_LIBCALL; 538 } 539 540 /// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or 541 /// UNKNOWN_LIBCALL if there is none. 542 RTLIB::Libcall RTLIB::getUINTTOFP(EVT OpVT, EVT RetVT) { 543 if (OpVT == MVT::i32) { 544 if (RetVT == MVT::f32) 545 return UINTTOFP_I32_F32; 546 if (RetVT == MVT::f64) 547 return UINTTOFP_I32_F64; 548 if (RetVT == MVT::f80) 549 return UINTTOFP_I32_F80; 550 if (RetVT == MVT::f128) 551 return UINTTOFP_I32_F128; 552 if (RetVT == MVT::ppcf128) 553 return UINTTOFP_I32_PPCF128; 554 } else if (OpVT == MVT::i64) { 555 if (RetVT == MVT::f32) 556 return UINTTOFP_I64_F32; 557 if (RetVT == MVT::f64) 558 return UINTTOFP_I64_F64; 559 if (RetVT == MVT::f80) 560 return UINTTOFP_I64_F80; 561 if (RetVT == MVT::f128) 562 return UINTTOFP_I64_F128; 563 if (RetVT == MVT::ppcf128) 564 return UINTTOFP_I64_PPCF128; 565 } else if (OpVT == MVT::i128) { 566 if (RetVT == MVT::f32) 567 return UINTTOFP_I128_F32; 568 if (RetVT == MVT::f64) 569 return UINTTOFP_I128_F64; 570 if (RetVT == MVT::f80) 571 return UINTTOFP_I128_F80; 572 if (RetVT == MVT::f128) 573 return UINTTOFP_I128_F128; 574 if (RetVT == MVT::ppcf128) 575 return UINTTOFP_I128_PPCF128; 576 } 577 return UNKNOWN_LIBCALL; 578 } 579 580 /// InitCmpLibcallCCs - Set default comparison libcall CC. 581 /// 582 static void InitCmpLibcallCCs(ISD::CondCode *CCs) { 583 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL); 584 CCs[RTLIB::OEQ_F32] = ISD::SETEQ; 585 CCs[RTLIB::OEQ_F64] = ISD::SETEQ; 586 CCs[RTLIB::OEQ_F128] = ISD::SETEQ; 587 CCs[RTLIB::UNE_F32] = ISD::SETNE; 588 CCs[RTLIB::UNE_F64] = ISD::SETNE; 589 CCs[RTLIB::UNE_F128] = ISD::SETNE; 590 CCs[RTLIB::OGE_F32] = ISD::SETGE; 591 CCs[RTLIB::OGE_F64] = ISD::SETGE; 592 CCs[RTLIB::OGE_F128] = ISD::SETGE; 593 CCs[RTLIB::OLT_F32] = ISD::SETLT; 594 CCs[RTLIB::OLT_F64] = ISD::SETLT; 595 CCs[RTLIB::OLT_F128] = ISD::SETLT; 596 CCs[RTLIB::OLE_F32] = ISD::SETLE; 597 CCs[RTLIB::OLE_F64] = ISD::SETLE; 598 CCs[RTLIB::OLE_F128] = ISD::SETLE; 599 CCs[RTLIB::OGT_F32] = ISD::SETGT; 600 CCs[RTLIB::OGT_F64] = ISD::SETGT; 601 CCs[RTLIB::OGT_F128] = ISD::SETGT; 602 CCs[RTLIB::UO_F32] = ISD::SETNE; 603 CCs[RTLIB::UO_F64] = ISD::SETNE; 604 CCs[RTLIB::UO_F128] = ISD::SETNE; 605 CCs[RTLIB::O_F32] = ISD::SETEQ; 606 CCs[RTLIB::O_F64] = ISD::SETEQ; 607 CCs[RTLIB::O_F128] = ISD::SETEQ; 608 } 609 610 /// NOTE: The constructor takes ownership of TLOF. 611 TargetLoweringBase::TargetLoweringBase(const TargetMachine &tm, 612 const TargetLoweringObjectFile *tlof) 613 : TM(tm), TD(TM.getDataLayout()), TLOF(*tlof) { 614 // All operations default to being supported. 615 memset(OpActions, 0, sizeof(OpActions)); 616 memset(LoadExtActions, 0, sizeof(LoadExtActions)); 617 memset(TruncStoreActions, 0, sizeof(TruncStoreActions)); 618 memset(IndexedModeActions, 0, sizeof(IndexedModeActions)); 619 memset(CondCodeActions, 0, sizeof(CondCodeActions)); 620 621 // Set default actions for various operations. 622 for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) { 623 // Default all indexed load / store to expand. 624 for (unsigned IM = (unsigned)ISD::PRE_INC; 625 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) { 626 setIndexedLoadAction(IM, (MVT::SimpleValueType)VT, Expand); 627 setIndexedStoreAction(IM, (MVT::SimpleValueType)VT, Expand); 628 } 629 630 // These operations default to expand. 631 setOperationAction(ISD::FGETSIGN, (MVT::SimpleValueType)VT, Expand); 632 setOperationAction(ISD::CONCAT_VECTORS, (MVT::SimpleValueType)VT, Expand); 633 } 634 635 // Most targets ignore the @llvm.prefetch intrinsic. 636 setOperationAction(ISD::PREFETCH, MVT::Other, Expand); 637 638 // ConstantFP nodes default to expand. Targets can either change this to 639 // Legal, in which case all fp constants are legal, or use isFPImmLegal() 640 // to optimize expansions for certain constants. 641 setOperationAction(ISD::ConstantFP, MVT::f16, Expand); 642 setOperationAction(ISD::ConstantFP, MVT::f32, Expand); 643 setOperationAction(ISD::ConstantFP, MVT::f64, Expand); 644 setOperationAction(ISD::ConstantFP, MVT::f80, Expand); 645 setOperationAction(ISD::ConstantFP, MVT::f128, Expand); 646 647 // These library functions default to expand. 648 setOperationAction(ISD::FLOG , MVT::f16, Expand); 649 setOperationAction(ISD::FLOG2, MVT::f16, Expand); 650 setOperationAction(ISD::FLOG10, MVT::f16, Expand); 651 setOperationAction(ISD::FEXP , MVT::f16, Expand); 652 setOperationAction(ISD::FEXP2, MVT::f16, Expand); 653 setOperationAction(ISD::FFLOOR, MVT::f16, Expand); 654 setOperationAction(ISD::FNEARBYINT, MVT::f16, Expand); 655 setOperationAction(ISD::FCEIL, MVT::f16, Expand); 656 setOperationAction(ISD::FRINT, MVT::f16, Expand); 657 setOperationAction(ISD::FTRUNC, MVT::f16, Expand); 658 setOperationAction(ISD::FLOG , MVT::f32, Expand); 659 setOperationAction(ISD::FLOG2, MVT::f32, Expand); 660 setOperationAction(ISD::FLOG10, MVT::f32, Expand); 661 setOperationAction(ISD::FEXP , MVT::f32, Expand); 662 setOperationAction(ISD::FEXP2, MVT::f32, Expand); 663 setOperationAction(ISD::FFLOOR, MVT::f32, Expand); 664 setOperationAction(ISD::FNEARBYINT, MVT::f32, Expand); 665 setOperationAction(ISD::FCEIL, MVT::f32, Expand); 666 setOperationAction(ISD::FRINT, MVT::f32, Expand); 667 setOperationAction(ISD::FTRUNC, MVT::f32, Expand); 668 setOperationAction(ISD::FLOG , MVT::f64, Expand); 669 setOperationAction(ISD::FLOG2, MVT::f64, Expand); 670 setOperationAction(ISD::FLOG10, MVT::f64, Expand); 671 setOperationAction(ISD::FEXP , MVT::f64, Expand); 672 setOperationAction(ISD::FEXP2, MVT::f64, Expand); 673 setOperationAction(ISD::FFLOOR, MVT::f64, Expand); 674 setOperationAction(ISD::FNEARBYINT, MVT::f64, Expand); 675 setOperationAction(ISD::FCEIL, MVT::f64, Expand); 676 setOperationAction(ISD::FRINT, MVT::f64, Expand); 677 setOperationAction(ISD::FTRUNC, MVT::f64, Expand); 678 setOperationAction(ISD::FLOG , MVT::f128, Expand); 679 setOperationAction(ISD::FLOG2, MVT::f128, Expand); 680 setOperationAction(ISD::FLOG10, MVT::f128, Expand); 681 setOperationAction(ISD::FEXP , MVT::f128, Expand); 682 setOperationAction(ISD::FEXP2, MVT::f128, Expand); 683 setOperationAction(ISD::FFLOOR, MVT::f128, Expand); 684 setOperationAction(ISD::FNEARBYINT, MVT::f128, Expand); 685 setOperationAction(ISD::FCEIL, MVT::f128, Expand); 686 setOperationAction(ISD::FRINT, MVT::f128, Expand); 687 setOperationAction(ISD::FTRUNC, MVT::f128, Expand); 688 689 // Default ISD::TRAP to expand (which turns it into abort). 690 setOperationAction(ISD::TRAP, MVT::Other, Expand); 691 692 // On most systems, DEBUGTRAP and TRAP have no difference. The "Expand" 693 // here is to inform DAG Legalizer to replace DEBUGTRAP with TRAP. 694 // 695 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Expand); 696 697 IsLittleEndian = TD->isLittleEndian(); 698 PointerTy = MVT::getIntegerVT(8*TD->getPointerSize(0)); 699 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*)); 700 memset(TargetDAGCombineArray, 0, array_lengthof(TargetDAGCombineArray)); 701 maxStoresPerMemset = maxStoresPerMemcpy = maxStoresPerMemmove = 8; 702 maxStoresPerMemsetOptSize = maxStoresPerMemcpyOptSize 703 = maxStoresPerMemmoveOptSize = 4; 704 benefitFromCodePlacementOpt = false; 705 UseUnderscoreSetJmp = false; 706 UseUnderscoreLongJmp = false; 707 SelectIsExpensive = false; 708 IntDivIsCheap = false; 709 Pow2DivIsCheap = false; 710 JumpIsExpensive = false; 711 predictableSelectIsExpensive = false; 712 StackPointerRegisterToSaveRestore = 0; 713 ExceptionPointerRegister = 0; 714 ExceptionSelectorRegister = 0; 715 BooleanContents = UndefinedBooleanContent; 716 BooleanVectorContents = UndefinedBooleanContent; 717 SchedPreferenceInfo = Sched::ILP; 718 JumpBufSize = 0; 719 JumpBufAlignment = 0; 720 MinFunctionAlignment = 0; 721 PrefFunctionAlignment = 0; 722 PrefLoopAlignment = 0; 723 MinStackArgumentAlignment = 1; 724 ShouldFoldAtomicFences = false; 725 InsertFencesForAtomic = false; 726 SupportJumpTables = true; 727 MinimumJumpTableEntries = 4; 728 729 InitLibcallNames(LibcallRoutineNames); 730 InitCmpLibcallCCs(CmpLibcallCCs); 731 InitLibcallCallingConvs(LibcallCallingConvs); 732 } 733 734 TargetLoweringBase::~TargetLoweringBase() { 735 delete &TLOF; 736 } 737 738 MVT TargetLoweringBase::getShiftAmountTy(EVT LHSTy) const { 739 return MVT::getIntegerVT(8*TD->getPointerSize(0)); 740 } 741 742 /// canOpTrap - Returns true if the operation can trap for the value type. 743 /// VT must be a legal type. 744 bool TargetLoweringBase::canOpTrap(unsigned Op, EVT VT) const { 745 assert(isTypeLegal(VT)); 746 switch (Op) { 747 default: 748 return false; 749 case ISD::FDIV: 750 case ISD::FREM: 751 case ISD::SDIV: 752 case ISD::UDIV: 753 case ISD::SREM: 754 case ISD::UREM: 755 return true; 756 } 757 } 758 759 760 static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT, 761 unsigned &NumIntermediates, 762 MVT &RegisterVT, 763 TargetLoweringBase *TLI) { 764 // Figure out the right, legal destination reg to copy into. 765 unsigned NumElts = VT.getVectorNumElements(); 766 MVT EltTy = VT.getVectorElementType(); 767 768 unsigned NumVectorRegs = 1; 769 770 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we 771 // could break down into LHS/RHS like LegalizeDAG does. 772 if (!isPowerOf2_32(NumElts)) { 773 NumVectorRegs = NumElts; 774 NumElts = 1; 775 } 776 777 // Divide the input until we get to a supported size. This will always 778 // end with a scalar if the target doesn't support vectors. 779 while (NumElts > 1 && !TLI->isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) { 780 NumElts >>= 1; 781 NumVectorRegs <<= 1; 782 } 783 784 NumIntermediates = NumVectorRegs; 785 786 MVT NewVT = MVT::getVectorVT(EltTy, NumElts); 787 if (!TLI->isTypeLegal(NewVT)) 788 NewVT = EltTy; 789 IntermediateVT = NewVT; 790 791 unsigned NewVTSize = NewVT.getSizeInBits(); 792 793 // Convert sizes such as i33 to i64. 794 if (!isPowerOf2_32(NewVTSize)) 795 NewVTSize = NextPowerOf2(NewVTSize); 796 797 MVT DestVT = TLI->getRegisterType(NewVT); 798 RegisterVT = DestVT; 799 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16. 800 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits()); 801 802 // Otherwise, promotion or legal types use the same number of registers as 803 // the vector decimated to the appropriate level. 804 return NumVectorRegs; 805 } 806 807 /// isLegalRC - Return true if the value types that can be represented by the 808 /// specified register class are all legal. 809 bool TargetLoweringBase::isLegalRC(const TargetRegisterClass *RC) const { 810 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end(); 811 I != E; ++I) { 812 if (isTypeLegal(*I)) 813 return true; 814 } 815 return false; 816 } 817 818 /// findRepresentativeClass - Return the largest legal super-reg register class 819 /// of the register class for the specified type and its associated "cost". 820 std::pair<const TargetRegisterClass*, uint8_t> 821 TargetLoweringBase::findRepresentativeClass(MVT VT) const { 822 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo(); 823 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy]; 824 if (!RC) 825 return std::make_pair(RC, 0); 826 827 // Compute the set of all super-register classes. 828 BitVector SuperRegRC(TRI->getNumRegClasses()); 829 for (SuperRegClassIterator RCI(RC, TRI); RCI.isValid(); ++RCI) 830 SuperRegRC.setBitsInMask(RCI.getMask()); 831 832 // Find the first legal register class with the largest spill size. 833 const TargetRegisterClass *BestRC = RC; 834 for (int i = SuperRegRC.find_first(); i >= 0; i = SuperRegRC.find_next(i)) { 835 const TargetRegisterClass *SuperRC = TRI->getRegClass(i); 836 // We want the largest possible spill size. 837 if (SuperRC->getSize() <= BestRC->getSize()) 838 continue; 839 if (!isLegalRC(SuperRC)) 840 continue; 841 BestRC = SuperRC; 842 } 843 return std::make_pair(BestRC, 1); 844 } 845 846 /// computeRegisterProperties - Once all of the register classes are added, 847 /// this allows us to compute derived properties we expose. 848 void TargetLoweringBase::computeRegisterProperties() { 849 assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE && 850 "Too many value types for ValueTypeActions to hold!"); 851 852 // Everything defaults to needing one register. 853 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) { 854 NumRegistersForVT[i] = 1; 855 RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i; 856 } 857 // ...except isVoid, which doesn't need any registers. 858 NumRegistersForVT[MVT::isVoid] = 0; 859 860 // Find the largest integer register class. 861 unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE; 862 for (; RegClassForVT[LargestIntReg] == 0; --LargestIntReg) 863 assert(LargestIntReg != MVT::i1 && "No integer registers defined!"); 864 865 // Every integer value type larger than this largest register takes twice as 866 // many registers to represent as the previous ValueType. 867 for (unsigned ExpandedReg = LargestIntReg + 1; 868 ExpandedReg <= MVT::LAST_INTEGER_VALUETYPE; ++ExpandedReg) { 869 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1]; 870 RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg; 871 TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1); 872 ValueTypeActions.setTypeAction((MVT::SimpleValueType)ExpandedReg, 873 TypeExpandInteger); 874 } 875 876 // Inspect all of the ValueType's smaller than the largest integer 877 // register to see which ones need promotion. 878 unsigned LegalIntReg = LargestIntReg; 879 for (unsigned IntReg = LargestIntReg - 1; 880 IntReg >= (unsigned)MVT::i1; --IntReg) { 881 MVT IVT = (MVT::SimpleValueType)IntReg; 882 if (isTypeLegal(IVT)) { 883 LegalIntReg = IntReg; 884 } else { 885 RegisterTypeForVT[IntReg] = TransformToType[IntReg] = 886 (const MVT::SimpleValueType)LegalIntReg; 887 ValueTypeActions.setTypeAction(IVT, TypePromoteInteger); 888 } 889 } 890 891 // ppcf128 type is really two f64's. 892 if (!isTypeLegal(MVT::ppcf128)) { 893 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64]; 894 RegisterTypeForVT[MVT::ppcf128] = MVT::f64; 895 TransformToType[MVT::ppcf128] = MVT::f64; 896 ValueTypeActions.setTypeAction(MVT::ppcf128, TypeExpandFloat); 897 } 898 899 // Decide how to handle f64. If the target does not have native f64 support, 900 // expand it to i64 and we will be generating soft float library calls. 901 if (!isTypeLegal(MVT::f64)) { 902 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64]; 903 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64]; 904 TransformToType[MVT::f64] = MVT::i64; 905 ValueTypeActions.setTypeAction(MVT::f64, TypeSoftenFloat); 906 } 907 908 // Decide how to handle f32. If the target does not have native support for 909 // f32, promote it to f64 if it is legal. Otherwise, expand it to i32. 910 if (!isTypeLegal(MVT::f32)) { 911 if (isTypeLegal(MVT::f64)) { 912 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::f64]; 913 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::f64]; 914 TransformToType[MVT::f32] = MVT::f64; 915 ValueTypeActions.setTypeAction(MVT::f32, TypePromoteInteger); 916 } else { 917 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32]; 918 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32]; 919 TransformToType[MVT::f32] = MVT::i32; 920 ValueTypeActions.setTypeAction(MVT::f32, TypeSoftenFloat); 921 } 922 } 923 924 // Loop over all of the vector value types to see which need transformations. 925 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE; 926 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) { 927 MVT VT = (MVT::SimpleValueType)i; 928 if (isTypeLegal(VT)) continue; 929 930 // Determine if there is a legal wider type. If so, we should promote to 931 // that wider vector type. 932 MVT EltVT = VT.getVectorElementType(); 933 unsigned NElts = VT.getVectorNumElements(); 934 if (NElts != 1 && !shouldSplitVectorElementType(EltVT)) { 935 bool IsLegalWiderType = false; 936 // First try to promote the elements of integer vectors. If no legal 937 // promotion was found, fallback to the widen-vector method. 938 for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) { 939 MVT SVT = (MVT::SimpleValueType)nVT; 940 // Promote vectors of integers to vectors with the same number 941 // of elements, with a wider element type. 942 if (SVT.getVectorElementType().getSizeInBits() > EltVT.getSizeInBits() 943 && SVT.getVectorNumElements() == NElts && 944 isTypeLegal(SVT) && SVT.getScalarType().isInteger()) { 945 TransformToType[i] = SVT; 946 RegisterTypeForVT[i] = SVT; 947 NumRegistersForVT[i] = 1; 948 ValueTypeActions.setTypeAction(VT, TypePromoteInteger); 949 IsLegalWiderType = true; 950 break; 951 } 952 } 953 954 if (IsLegalWiderType) continue; 955 956 // Try to widen the vector. 957 for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) { 958 MVT SVT = (MVT::SimpleValueType)nVT; 959 if (SVT.getVectorElementType() == EltVT && 960 SVT.getVectorNumElements() > NElts && 961 isTypeLegal(SVT)) { 962 TransformToType[i] = SVT; 963 RegisterTypeForVT[i] = SVT; 964 NumRegistersForVT[i] = 1; 965 ValueTypeActions.setTypeAction(VT, TypeWidenVector); 966 IsLegalWiderType = true; 967 break; 968 } 969 } 970 if (IsLegalWiderType) continue; 971 } 972 973 MVT IntermediateVT; 974 MVT RegisterVT; 975 unsigned NumIntermediates; 976 NumRegistersForVT[i] = 977 getVectorTypeBreakdownMVT(VT, IntermediateVT, NumIntermediates, 978 RegisterVT, this); 979 RegisterTypeForVT[i] = RegisterVT; 980 981 MVT NVT = VT.getPow2VectorType(); 982 if (NVT == VT) { 983 // Type is already a power of 2. The default action is to split. 984 TransformToType[i] = MVT::Other; 985 unsigned NumElts = VT.getVectorNumElements(); 986 ValueTypeActions.setTypeAction(VT, 987 NumElts > 1 ? TypeSplitVector : TypeScalarizeVector); 988 } else { 989 TransformToType[i] = NVT; 990 ValueTypeActions.setTypeAction(VT, TypeWidenVector); 991 } 992 } 993 994 // Determine the 'representative' register class for each value type. 995 // An representative register class is the largest (meaning one which is 996 // not a sub-register class / subreg register class) legal register class for 997 // a group of value types. For example, on i386, i8, i16, and i32 998 // representative would be GR32; while on x86_64 it's GR64. 999 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) { 1000 const TargetRegisterClass* RRC; 1001 uint8_t Cost; 1002 tie(RRC, Cost) = findRepresentativeClass((MVT::SimpleValueType)i); 1003 RepRegClassForVT[i] = RRC; 1004 RepRegClassCostForVT[i] = Cost; 1005 } 1006 } 1007 1008 EVT TargetLoweringBase::getSetCCResultType(EVT VT) const { 1009 assert(!VT.isVector() && "No default SetCC type for vectors!"); 1010 return getPointerTy(0).SimpleTy; 1011 } 1012 1013 MVT::SimpleValueType TargetLoweringBase::getCmpLibcallReturnType() const { 1014 return MVT::i32; // return the default value 1015 } 1016 1017 /// getVectorTypeBreakdown - Vector types are broken down into some number of 1018 /// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32 1019 /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack. 1020 /// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86. 1021 /// 1022 /// This method returns the number of registers needed, and the VT for each 1023 /// register. It also returns the VT and quantity of the intermediate values 1024 /// before they are promoted/expanded. 1025 /// 1026 unsigned TargetLoweringBase::getVectorTypeBreakdown(LLVMContext &Context, EVT VT, 1027 EVT &IntermediateVT, 1028 unsigned &NumIntermediates, 1029 MVT &RegisterVT) const { 1030 unsigned NumElts = VT.getVectorNumElements(); 1031 1032 // If there is a wider vector type with the same element type as this one, 1033 // or a promoted vector type that has the same number of elements which 1034 // are wider, then we should convert to that legal vector type. 1035 // This handles things like <2 x float> -> <4 x float> and 1036 // <4 x i1> -> <4 x i32>. 1037 LegalizeTypeAction TA = getTypeAction(Context, VT); 1038 if (NumElts != 1 && (TA == TypeWidenVector || TA == TypePromoteInteger)) { 1039 EVT RegisterEVT = getTypeToTransformTo(Context, VT); 1040 if (isTypeLegal(RegisterEVT)) { 1041 IntermediateVT = RegisterEVT; 1042 RegisterVT = RegisterEVT.getSimpleVT(); 1043 NumIntermediates = 1; 1044 return 1; 1045 } 1046 } 1047 1048 // Figure out the right, legal destination reg to copy into. 1049 EVT EltTy = VT.getVectorElementType(); 1050 1051 unsigned NumVectorRegs = 1; 1052 1053 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we 1054 // could break down into LHS/RHS like LegalizeDAG does. 1055 if (!isPowerOf2_32(NumElts)) { 1056 NumVectorRegs = NumElts; 1057 NumElts = 1; 1058 } 1059 1060 // Divide the input until we get to a supported size. This will always 1061 // end with a scalar if the target doesn't support vectors. 1062 while (NumElts > 1 && !isTypeLegal( 1063 EVT::getVectorVT(Context, EltTy, NumElts))) { 1064 NumElts >>= 1; 1065 NumVectorRegs <<= 1; 1066 } 1067 1068 NumIntermediates = NumVectorRegs; 1069 1070 EVT NewVT = EVT::getVectorVT(Context, EltTy, NumElts); 1071 if (!isTypeLegal(NewVT)) 1072 NewVT = EltTy; 1073 IntermediateVT = NewVT; 1074 1075 MVT DestVT = getRegisterType(Context, NewVT); 1076 RegisterVT = DestVT; 1077 unsigned NewVTSize = NewVT.getSizeInBits(); 1078 1079 // Convert sizes such as i33 to i64. 1080 if (!isPowerOf2_32(NewVTSize)) 1081 NewVTSize = NextPowerOf2(NewVTSize); 1082 1083 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16. 1084 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits()); 1085 1086 // Otherwise, promotion or legal types use the same number of registers as 1087 // the vector decimated to the appropriate level. 1088 return NumVectorRegs; 1089 } 1090 1091 /// Get the EVTs and ArgFlags collections that represent the legalized return 1092 /// type of the given function. This does not require a DAG or a return value, 1093 /// and is suitable for use before any DAGs for the function are constructed. 1094 /// TODO: Move this out of TargetLowering.cpp. 1095 void llvm::GetReturnInfo(Type* ReturnType, AttributeSet attr, 1096 SmallVectorImpl<ISD::OutputArg> &Outs, 1097 const TargetLowering &TLI) { 1098 SmallVector<EVT, 4> ValueVTs; 1099 ComputeValueVTs(TLI, ReturnType, ValueVTs); 1100 unsigned NumValues = ValueVTs.size(); 1101 if (NumValues == 0) return; 1102 1103 for (unsigned j = 0, f = NumValues; j != f; ++j) { 1104 EVT VT = ValueVTs[j]; 1105 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 1106 1107 if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::SExt)) 1108 ExtendKind = ISD::SIGN_EXTEND; 1109 else if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::ZExt)) 1110 ExtendKind = ISD::ZERO_EXTEND; 1111 1112 // FIXME: C calling convention requires the return type to be promoted to 1113 // at least 32-bit. But this is not necessary for non-C calling 1114 // conventions. The frontend should mark functions whose return values 1115 // require promoting with signext or zeroext attributes. 1116 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) { 1117 MVT MinVT = TLI.getRegisterType(ReturnType->getContext(), MVT::i32); 1118 if (VT.bitsLT(MinVT)) 1119 VT = MinVT; 1120 } 1121 1122 unsigned NumParts = TLI.getNumRegisters(ReturnType->getContext(), VT); 1123 MVT PartVT = TLI.getRegisterType(ReturnType->getContext(), VT); 1124 1125 // 'inreg' on function refers to return value 1126 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy(); 1127 if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::InReg)) 1128 Flags.setInReg(); 1129 1130 // Propagate extension type if any 1131 if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::SExt)) 1132 Flags.setSExt(); 1133 else if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::ZExt)) 1134 Flags.setZExt(); 1135 1136 for (unsigned i = 0; i < NumParts; ++i) 1137 Outs.push_back(ISD::OutputArg(Flags, PartVT, /*isFixed=*/true, 0, 0)); 1138 } 1139 } 1140 1141 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 1142 /// function arguments in the caller parameter area. This is the actual 1143 /// alignment, not its logarithm. 1144 unsigned TargetLoweringBase::getByValTypeAlignment(Type *Ty) const { 1145 return TD->getCallFrameTypeAlignment(Ty); 1146 } 1147 1148 //===----------------------------------------------------------------------===// 1149 // TargetTransformInfo Helpers 1150 //===----------------------------------------------------------------------===// 1151 1152 int TargetLoweringBase::InstructionOpcodeToISD(unsigned Opcode) const { 1153 enum InstructionOpcodes { 1154 #define HANDLE_INST(NUM, OPCODE, CLASS) OPCODE = NUM, 1155 #define LAST_OTHER_INST(NUM) InstructionOpcodesCount = NUM 1156 #include "llvm/IR/Instruction.def" 1157 }; 1158 switch (static_cast<InstructionOpcodes>(Opcode)) { 1159 case Ret: return 0; 1160 case Br: return 0; 1161 case Switch: return 0; 1162 case IndirectBr: return 0; 1163 case Invoke: return 0; 1164 case Resume: return 0; 1165 case Unreachable: return 0; 1166 case Add: return ISD::ADD; 1167 case FAdd: return ISD::FADD; 1168 case Sub: return ISD::SUB; 1169 case FSub: return ISD::FSUB; 1170 case Mul: return ISD::MUL; 1171 case FMul: return ISD::FMUL; 1172 case UDiv: return ISD::UDIV; 1173 case SDiv: return ISD::UDIV; 1174 case FDiv: return ISD::FDIV; 1175 case URem: return ISD::UREM; 1176 case SRem: return ISD::SREM; 1177 case FRem: return ISD::FREM; 1178 case Shl: return ISD::SHL; 1179 case LShr: return ISD::SRL; 1180 case AShr: return ISD::SRA; 1181 case And: return ISD::AND; 1182 case Or: return ISD::OR; 1183 case Xor: return ISD::XOR; 1184 case Alloca: return 0; 1185 case Load: return ISD::LOAD; 1186 case Store: return ISD::STORE; 1187 case GetElementPtr: return 0; 1188 case Fence: return 0; 1189 case AtomicCmpXchg: return 0; 1190 case AtomicRMW: return 0; 1191 case Trunc: return ISD::TRUNCATE; 1192 case ZExt: return ISD::ZERO_EXTEND; 1193 case SExt: return ISD::SIGN_EXTEND; 1194 case FPToUI: return ISD::FP_TO_UINT; 1195 case FPToSI: return ISD::FP_TO_SINT; 1196 case UIToFP: return ISD::UINT_TO_FP; 1197 case SIToFP: return ISD::SINT_TO_FP; 1198 case FPTrunc: return ISD::FP_ROUND; 1199 case FPExt: return ISD::FP_EXTEND; 1200 case PtrToInt: return ISD::BITCAST; 1201 case IntToPtr: return ISD::BITCAST; 1202 case BitCast: return ISD::BITCAST; 1203 case ICmp: return ISD::SETCC; 1204 case FCmp: return ISD::SETCC; 1205 case PHI: return 0; 1206 case Call: return 0; 1207 case Select: return ISD::SELECT; 1208 case UserOp1: return 0; 1209 case UserOp2: return 0; 1210 case VAArg: return 0; 1211 case ExtractElement: return ISD::EXTRACT_VECTOR_ELT; 1212 case InsertElement: return ISD::INSERT_VECTOR_ELT; 1213 case ShuffleVector: return ISD::VECTOR_SHUFFLE; 1214 case ExtractValue: return ISD::MERGE_VALUES; 1215 case InsertValue: return ISD::MERGE_VALUES; 1216 case LandingPad: return 0; 1217 } 1218 1219 llvm_unreachable("Unknown instruction type encountered!"); 1220 } 1221 1222 std::pair<unsigned, MVT> 1223 TargetLoweringBase::getTypeLegalizationCost(Type *Ty) const { 1224 LLVMContext &C = Ty->getContext(); 1225 EVT MTy = getValueType(Ty); 1226 1227 unsigned Cost = 1; 1228 // We keep legalizing the type until we find a legal kind. We assume that 1229 // the only operation that costs anything is the split. After splitting 1230 // we need to handle two types. 1231 while (true) { 1232 LegalizeKind LK = getTypeConversion(C, MTy); 1233 1234 if (LK.first == TypeLegal) 1235 return std::make_pair(Cost, MTy.getSimpleVT()); 1236 1237 if (LK.first == TypeSplitVector || LK.first == TypeExpandInteger) 1238 Cost *= 2; 1239 1240 // Keep legalizing the type. 1241 MTy = LK.second; 1242 } 1243 } 1244 1245 //===----------------------------------------------------------------------===// 1246 // Loop Strength Reduction hooks 1247 //===----------------------------------------------------------------------===// 1248 1249 /// isLegalAddressingMode - Return true if the addressing mode represented 1250 /// by AM is legal for this target, for a load/store of the specified type. 1251 bool TargetLoweringBase::isLegalAddressingMode(const AddrMode &AM, 1252 Type *Ty) const { 1253 // The default implementation of this implements a conservative RISCy, r+r and 1254 // r+i addr mode. 1255 1256 // Allows a sign-extended 16-bit immediate field. 1257 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1) 1258 return false; 1259 1260 // No global is ever allowed as a base. 1261 if (AM.BaseGV) 1262 return false; 1263 1264 // Only support r+r, 1265 switch (AM.Scale) { 1266 case 0: // "r+i" or just "i", depending on HasBaseReg. 1267 break; 1268 case 1: 1269 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. 1270 return false; 1271 // Otherwise we have r+r or r+i. 1272 break; 1273 case 2: 1274 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. 1275 return false; 1276 // Allow 2*r as r+r. 1277 break; 1278 } 1279 1280 return true; 1281 } 1282