1 //===-- TargetLoweringBase.cpp - Implement the TargetLoweringBase class ---===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This implements the TargetLoweringBase class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "llvm/Target/TargetLowering.h" 15 #include "llvm/ADT/BitVector.h" 16 #include "llvm/ADT/STLExtras.h" 17 #include "llvm/ADT/Triple.h" 18 #include "llvm/CodeGen/Analysis.h" 19 #include "llvm/CodeGen/MachineFrameInfo.h" 20 #include "llvm/CodeGen/MachineFunction.h" 21 #include "llvm/CodeGen/MachineInstrBuilder.h" 22 #include "llvm/CodeGen/MachineJumpTableInfo.h" 23 #include "llvm/CodeGen/StackMaps.h" 24 #include "llvm/IR/DataLayout.h" 25 #include "llvm/IR/DerivedTypes.h" 26 #include "llvm/IR/GlobalVariable.h" 27 #include "llvm/IR/Mangler.h" 28 #include "llvm/MC/MCAsmInfo.h" 29 #include "llvm/MC/MCContext.h" 30 #include "llvm/MC/MCExpr.h" 31 #include "llvm/Support/CommandLine.h" 32 #include "llvm/Support/ErrorHandling.h" 33 #include "llvm/Support/MathExtras.h" 34 #include "llvm/Target/TargetLoweringObjectFile.h" 35 #include "llvm/Target/TargetMachine.h" 36 #include "llvm/Target/TargetRegisterInfo.h" 37 #include "llvm/Target/TargetSubtargetInfo.h" 38 #include <cctype> 39 using namespace llvm; 40 41 /// InitLibcallNames - Set default libcall names. 42 /// 43 static void InitLibcallNames(const char **Names, const Triple &TT) { 44 Names[RTLIB::SHL_I16] = "__ashlhi3"; 45 Names[RTLIB::SHL_I32] = "__ashlsi3"; 46 Names[RTLIB::SHL_I64] = "__ashldi3"; 47 Names[RTLIB::SHL_I128] = "__ashlti3"; 48 Names[RTLIB::SRL_I16] = "__lshrhi3"; 49 Names[RTLIB::SRL_I32] = "__lshrsi3"; 50 Names[RTLIB::SRL_I64] = "__lshrdi3"; 51 Names[RTLIB::SRL_I128] = "__lshrti3"; 52 Names[RTLIB::SRA_I16] = "__ashrhi3"; 53 Names[RTLIB::SRA_I32] = "__ashrsi3"; 54 Names[RTLIB::SRA_I64] = "__ashrdi3"; 55 Names[RTLIB::SRA_I128] = "__ashrti3"; 56 Names[RTLIB::MUL_I8] = "__mulqi3"; 57 Names[RTLIB::MUL_I16] = "__mulhi3"; 58 Names[RTLIB::MUL_I32] = "__mulsi3"; 59 Names[RTLIB::MUL_I64] = "__muldi3"; 60 Names[RTLIB::MUL_I128] = "__multi3"; 61 Names[RTLIB::MULO_I32] = "__mulosi4"; 62 Names[RTLIB::MULO_I64] = "__mulodi4"; 63 Names[RTLIB::MULO_I128] = "__muloti4"; 64 Names[RTLIB::SDIV_I8] = "__divqi3"; 65 Names[RTLIB::SDIV_I16] = "__divhi3"; 66 Names[RTLIB::SDIV_I32] = "__divsi3"; 67 Names[RTLIB::SDIV_I64] = "__divdi3"; 68 Names[RTLIB::SDIV_I128] = "__divti3"; 69 Names[RTLIB::UDIV_I8] = "__udivqi3"; 70 Names[RTLIB::UDIV_I16] = "__udivhi3"; 71 Names[RTLIB::UDIV_I32] = "__udivsi3"; 72 Names[RTLIB::UDIV_I64] = "__udivdi3"; 73 Names[RTLIB::UDIV_I128] = "__udivti3"; 74 Names[RTLIB::SREM_I8] = "__modqi3"; 75 Names[RTLIB::SREM_I16] = "__modhi3"; 76 Names[RTLIB::SREM_I32] = "__modsi3"; 77 Names[RTLIB::SREM_I64] = "__moddi3"; 78 Names[RTLIB::SREM_I128] = "__modti3"; 79 Names[RTLIB::UREM_I8] = "__umodqi3"; 80 Names[RTLIB::UREM_I16] = "__umodhi3"; 81 Names[RTLIB::UREM_I32] = "__umodsi3"; 82 Names[RTLIB::UREM_I64] = "__umoddi3"; 83 Names[RTLIB::UREM_I128] = "__umodti3"; 84 85 // These are generally not available. 86 Names[RTLIB::SDIVREM_I8] = nullptr; 87 Names[RTLIB::SDIVREM_I16] = nullptr; 88 Names[RTLIB::SDIVREM_I32] = nullptr; 89 Names[RTLIB::SDIVREM_I64] = nullptr; 90 Names[RTLIB::SDIVREM_I128] = nullptr; 91 Names[RTLIB::UDIVREM_I8] = nullptr; 92 Names[RTLIB::UDIVREM_I16] = nullptr; 93 Names[RTLIB::UDIVREM_I32] = nullptr; 94 Names[RTLIB::UDIVREM_I64] = nullptr; 95 Names[RTLIB::UDIVREM_I128] = nullptr; 96 97 Names[RTLIB::NEG_I32] = "__negsi2"; 98 Names[RTLIB::NEG_I64] = "__negdi2"; 99 Names[RTLIB::ADD_F32] = "__addsf3"; 100 Names[RTLIB::ADD_F64] = "__adddf3"; 101 Names[RTLIB::ADD_F80] = "__addxf3"; 102 Names[RTLIB::ADD_F128] = "__addtf3"; 103 Names[RTLIB::ADD_PPCF128] = "__gcc_qadd"; 104 Names[RTLIB::SUB_F32] = "__subsf3"; 105 Names[RTLIB::SUB_F64] = "__subdf3"; 106 Names[RTLIB::SUB_F80] = "__subxf3"; 107 Names[RTLIB::SUB_F128] = "__subtf3"; 108 Names[RTLIB::SUB_PPCF128] = "__gcc_qsub"; 109 Names[RTLIB::MUL_F32] = "__mulsf3"; 110 Names[RTLIB::MUL_F64] = "__muldf3"; 111 Names[RTLIB::MUL_F80] = "__mulxf3"; 112 Names[RTLIB::MUL_F128] = "__multf3"; 113 Names[RTLIB::MUL_PPCF128] = "__gcc_qmul"; 114 Names[RTLIB::DIV_F32] = "__divsf3"; 115 Names[RTLIB::DIV_F64] = "__divdf3"; 116 Names[RTLIB::DIV_F80] = "__divxf3"; 117 Names[RTLIB::DIV_F128] = "__divtf3"; 118 Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv"; 119 Names[RTLIB::REM_F32] = "fmodf"; 120 Names[RTLIB::REM_F64] = "fmod"; 121 Names[RTLIB::REM_F80] = "fmodl"; 122 Names[RTLIB::REM_F128] = "fmodl"; 123 Names[RTLIB::REM_PPCF128] = "fmodl"; 124 Names[RTLIB::FMA_F32] = "fmaf"; 125 Names[RTLIB::FMA_F64] = "fma"; 126 Names[RTLIB::FMA_F80] = "fmal"; 127 Names[RTLIB::FMA_F128] = "fmal"; 128 Names[RTLIB::FMA_PPCF128] = "fmal"; 129 Names[RTLIB::POWI_F32] = "__powisf2"; 130 Names[RTLIB::POWI_F64] = "__powidf2"; 131 Names[RTLIB::POWI_F80] = "__powixf2"; 132 Names[RTLIB::POWI_F128] = "__powitf2"; 133 Names[RTLIB::POWI_PPCF128] = "__powitf2"; 134 Names[RTLIB::SQRT_F32] = "sqrtf"; 135 Names[RTLIB::SQRT_F64] = "sqrt"; 136 Names[RTLIB::SQRT_F80] = "sqrtl"; 137 Names[RTLIB::SQRT_F128] = "sqrtl"; 138 Names[RTLIB::SQRT_PPCF128] = "sqrtl"; 139 Names[RTLIB::LOG_F32] = "logf"; 140 Names[RTLIB::LOG_F64] = "log"; 141 Names[RTLIB::LOG_F80] = "logl"; 142 Names[RTLIB::LOG_F128] = "logl"; 143 Names[RTLIB::LOG_PPCF128] = "logl"; 144 Names[RTLIB::LOG2_F32] = "log2f"; 145 Names[RTLIB::LOG2_F64] = "log2"; 146 Names[RTLIB::LOG2_F80] = "log2l"; 147 Names[RTLIB::LOG2_F128] = "log2l"; 148 Names[RTLIB::LOG2_PPCF128] = "log2l"; 149 Names[RTLIB::LOG10_F32] = "log10f"; 150 Names[RTLIB::LOG10_F64] = "log10"; 151 Names[RTLIB::LOG10_F80] = "log10l"; 152 Names[RTLIB::LOG10_F128] = "log10l"; 153 Names[RTLIB::LOG10_PPCF128] = "log10l"; 154 Names[RTLIB::EXP_F32] = "expf"; 155 Names[RTLIB::EXP_F64] = "exp"; 156 Names[RTLIB::EXP_F80] = "expl"; 157 Names[RTLIB::EXP_F128] = "expl"; 158 Names[RTLIB::EXP_PPCF128] = "expl"; 159 Names[RTLIB::EXP2_F32] = "exp2f"; 160 Names[RTLIB::EXP2_F64] = "exp2"; 161 Names[RTLIB::EXP2_F80] = "exp2l"; 162 Names[RTLIB::EXP2_F128] = "exp2l"; 163 Names[RTLIB::EXP2_PPCF128] = "exp2l"; 164 Names[RTLIB::SIN_F32] = "sinf"; 165 Names[RTLIB::SIN_F64] = "sin"; 166 Names[RTLIB::SIN_F80] = "sinl"; 167 Names[RTLIB::SIN_F128] = "sinl"; 168 Names[RTLIB::SIN_PPCF128] = "sinl"; 169 Names[RTLIB::COS_F32] = "cosf"; 170 Names[RTLIB::COS_F64] = "cos"; 171 Names[RTLIB::COS_F80] = "cosl"; 172 Names[RTLIB::COS_F128] = "cosl"; 173 Names[RTLIB::COS_PPCF128] = "cosl"; 174 Names[RTLIB::POW_F32] = "powf"; 175 Names[RTLIB::POW_F64] = "pow"; 176 Names[RTLIB::POW_F80] = "powl"; 177 Names[RTLIB::POW_F128] = "powl"; 178 Names[RTLIB::POW_PPCF128] = "powl"; 179 Names[RTLIB::CEIL_F32] = "ceilf"; 180 Names[RTLIB::CEIL_F64] = "ceil"; 181 Names[RTLIB::CEIL_F80] = "ceill"; 182 Names[RTLIB::CEIL_F128] = "ceill"; 183 Names[RTLIB::CEIL_PPCF128] = "ceill"; 184 Names[RTLIB::TRUNC_F32] = "truncf"; 185 Names[RTLIB::TRUNC_F64] = "trunc"; 186 Names[RTLIB::TRUNC_F80] = "truncl"; 187 Names[RTLIB::TRUNC_F128] = "truncl"; 188 Names[RTLIB::TRUNC_PPCF128] = "truncl"; 189 Names[RTLIB::RINT_F32] = "rintf"; 190 Names[RTLIB::RINT_F64] = "rint"; 191 Names[RTLIB::RINT_F80] = "rintl"; 192 Names[RTLIB::RINT_F128] = "rintl"; 193 Names[RTLIB::RINT_PPCF128] = "rintl"; 194 Names[RTLIB::NEARBYINT_F32] = "nearbyintf"; 195 Names[RTLIB::NEARBYINT_F64] = "nearbyint"; 196 Names[RTLIB::NEARBYINT_F80] = "nearbyintl"; 197 Names[RTLIB::NEARBYINT_F128] = "nearbyintl"; 198 Names[RTLIB::NEARBYINT_PPCF128] = "nearbyintl"; 199 Names[RTLIB::ROUND_F32] = "roundf"; 200 Names[RTLIB::ROUND_F64] = "round"; 201 Names[RTLIB::ROUND_F80] = "roundl"; 202 Names[RTLIB::ROUND_F128] = "roundl"; 203 Names[RTLIB::ROUND_PPCF128] = "roundl"; 204 Names[RTLIB::FLOOR_F32] = "floorf"; 205 Names[RTLIB::FLOOR_F64] = "floor"; 206 Names[RTLIB::FLOOR_F80] = "floorl"; 207 Names[RTLIB::FLOOR_F128] = "floorl"; 208 Names[RTLIB::FLOOR_PPCF128] = "floorl"; 209 Names[RTLIB::FMIN_F32] = "fminf"; 210 Names[RTLIB::FMIN_F64] = "fmin"; 211 Names[RTLIB::FMIN_F80] = "fminl"; 212 Names[RTLIB::FMIN_F128] = "fminl"; 213 Names[RTLIB::FMIN_PPCF128] = "fminl"; 214 Names[RTLIB::FMAX_F32] = "fmaxf"; 215 Names[RTLIB::FMAX_F64] = "fmax"; 216 Names[RTLIB::FMAX_F80] = "fmaxl"; 217 Names[RTLIB::FMAX_F128] = "fmaxl"; 218 Names[RTLIB::FMAX_PPCF128] = "fmaxl"; 219 Names[RTLIB::ROUND_F32] = "roundf"; 220 Names[RTLIB::ROUND_F64] = "round"; 221 Names[RTLIB::ROUND_F80] = "roundl"; 222 Names[RTLIB::ROUND_F128] = "roundl"; 223 Names[RTLIB::ROUND_PPCF128] = "roundl"; 224 Names[RTLIB::COPYSIGN_F32] = "copysignf"; 225 Names[RTLIB::COPYSIGN_F64] = "copysign"; 226 Names[RTLIB::COPYSIGN_F80] = "copysignl"; 227 Names[RTLIB::COPYSIGN_F128] = "copysignl"; 228 Names[RTLIB::COPYSIGN_PPCF128] = "copysignl"; 229 Names[RTLIB::FPEXT_F64_F128] = "__extenddftf2"; 230 Names[RTLIB::FPEXT_F32_F128] = "__extendsftf2"; 231 Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2"; 232 Names[RTLIB::FPEXT_F16_F32] = "__gnu_h2f_ieee"; 233 Names[RTLIB::FPROUND_F32_F16] = "__gnu_f2h_ieee"; 234 Names[RTLIB::FPROUND_F64_F16] = "__truncdfhf2"; 235 Names[RTLIB::FPROUND_F80_F16] = "__truncxfhf2"; 236 Names[RTLIB::FPROUND_F128_F16] = "__trunctfhf2"; 237 Names[RTLIB::FPROUND_PPCF128_F16] = "__trunctfhf2"; 238 Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2"; 239 Names[RTLIB::FPROUND_F80_F32] = "__truncxfsf2"; 240 Names[RTLIB::FPROUND_F128_F32] = "__trunctfsf2"; 241 Names[RTLIB::FPROUND_PPCF128_F32] = "__trunctfsf2"; 242 Names[RTLIB::FPROUND_F80_F64] = "__truncxfdf2"; 243 Names[RTLIB::FPROUND_F128_F64] = "__trunctfdf2"; 244 Names[RTLIB::FPROUND_PPCF128_F64] = "__trunctfdf2"; 245 Names[RTLIB::FPTOSINT_F32_I8] = "__fixsfqi"; 246 Names[RTLIB::FPTOSINT_F32_I16] = "__fixsfhi"; 247 Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi"; 248 Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi"; 249 Names[RTLIB::FPTOSINT_F32_I128] = "__fixsfti"; 250 Names[RTLIB::FPTOSINT_F64_I8] = "__fixdfqi"; 251 Names[RTLIB::FPTOSINT_F64_I16] = "__fixdfhi"; 252 Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi"; 253 Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi"; 254 Names[RTLIB::FPTOSINT_F64_I128] = "__fixdfti"; 255 Names[RTLIB::FPTOSINT_F80_I32] = "__fixxfsi"; 256 Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi"; 257 Names[RTLIB::FPTOSINT_F80_I128] = "__fixxfti"; 258 Names[RTLIB::FPTOSINT_F128_I32] = "__fixtfsi"; 259 Names[RTLIB::FPTOSINT_F128_I64] = "__fixtfdi"; 260 Names[RTLIB::FPTOSINT_F128_I128] = "__fixtfti"; 261 Names[RTLIB::FPTOSINT_PPCF128_I32] = "__fixtfsi"; 262 Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi"; 263 Names[RTLIB::FPTOSINT_PPCF128_I128] = "__fixtfti"; 264 Names[RTLIB::FPTOUINT_F32_I8] = "__fixunssfqi"; 265 Names[RTLIB::FPTOUINT_F32_I16] = "__fixunssfhi"; 266 Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi"; 267 Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi"; 268 Names[RTLIB::FPTOUINT_F32_I128] = "__fixunssfti"; 269 Names[RTLIB::FPTOUINT_F64_I8] = "__fixunsdfqi"; 270 Names[RTLIB::FPTOUINT_F64_I16] = "__fixunsdfhi"; 271 Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi"; 272 Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi"; 273 Names[RTLIB::FPTOUINT_F64_I128] = "__fixunsdfti"; 274 Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi"; 275 Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi"; 276 Names[RTLIB::FPTOUINT_F80_I128] = "__fixunsxfti"; 277 Names[RTLIB::FPTOUINT_F128_I32] = "__fixunstfsi"; 278 Names[RTLIB::FPTOUINT_F128_I64] = "__fixunstfdi"; 279 Names[RTLIB::FPTOUINT_F128_I128] = "__fixunstfti"; 280 Names[RTLIB::FPTOUINT_PPCF128_I32] = "__fixunstfsi"; 281 Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi"; 282 Names[RTLIB::FPTOUINT_PPCF128_I128] = "__fixunstfti"; 283 Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf"; 284 Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf"; 285 Names[RTLIB::SINTTOFP_I32_F80] = "__floatsixf"; 286 Names[RTLIB::SINTTOFP_I32_F128] = "__floatsitf"; 287 Names[RTLIB::SINTTOFP_I32_PPCF128] = "__floatsitf"; 288 Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf"; 289 Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf"; 290 Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf"; 291 Names[RTLIB::SINTTOFP_I64_F128] = "__floatditf"; 292 Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf"; 293 Names[RTLIB::SINTTOFP_I128_F32] = "__floattisf"; 294 Names[RTLIB::SINTTOFP_I128_F64] = "__floattidf"; 295 Names[RTLIB::SINTTOFP_I128_F80] = "__floattixf"; 296 Names[RTLIB::SINTTOFP_I128_F128] = "__floattitf"; 297 Names[RTLIB::SINTTOFP_I128_PPCF128] = "__floattitf"; 298 Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf"; 299 Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf"; 300 Names[RTLIB::UINTTOFP_I32_F80] = "__floatunsixf"; 301 Names[RTLIB::UINTTOFP_I32_F128] = "__floatunsitf"; 302 Names[RTLIB::UINTTOFP_I32_PPCF128] = "__floatunsitf"; 303 Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf"; 304 Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf"; 305 Names[RTLIB::UINTTOFP_I64_F80] = "__floatundixf"; 306 Names[RTLIB::UINTTOFP_I64_F128] = "__floatunditf"; 307 Names[RTLIB::UINTTOFP_I64_PPCF128] = "__floatunditf"; 308 Names[RTLIB::UINTTOFP_I128_F32] = "__floatuntisf"; 309 Names[RTLIB::UINTTOFP_I128_F64] = "__floatuntidf"; 310 Names[RTLIB::UINTTOFP_I128_F80] = "__floatuntixf"; 311 Names[RTLIB::UINTTOFP_I128_F128] = "__floatuntitf"; 312 Names[RTLIB::UINTTOFP_I128_PPCF128] = "__floatuntitf"; 313 Names[RTLIB::OEQ_F32] = "__eqsf2"; 314 Names[RTLIB::OEQ_F64] = "__eqdf2"; 315 Names[RTLIB::OEQ_F128] = "__eqtf2"; 316 Names[RTLIB::UNE_F32] = "__nesf2"; 317 Names[RTLIB::UNE_F64] = "__nedf2"; 318 Names[RTLIB::UNE_F128] = "__netf2"; 319 Names[RTLIB::OGE_F32] = "__gesf2"; 320 Names[RTLIB::OGE_F64] = "__gedf2"; 321 Names[RTLIB::OGE_F128] = "__getf2"; 322 Names[RTLIB::OLT_F32] = "__ltsf2"; 323 Names[RTLIB::OLT_F64] = "__ltdf2"; 324 Names[RTLIB::OLT_F128] = "__lttf2"; 325 Names[RTLIB::OLE_F32] = "__lesf2"; 326 Names[RTLIB::OLE_F64] = "__ledf2"; 327 Names[RTLIB::OLE_F128] = "__letf2"; 328 Names[RTLIB::OGT_F32] = "__gtsf2"; 329 Names[RTLIB::OGT_F64] = "__gtdf2"; 330 Names[RTLIB::OGT_F128] = "__gttf2"; 331 Names[RTLIB::UO_F32] = "__unordsf2"; 332 Names[RTLIB::UO_F64] = "__unorddf2"; 333 Names[RTLIB::UO_F128] = "__unordtf2"; 334 Names[RTLIB::O_F32] = "__unordsf2"; 335 Names[RTLIB::O_F64] = "__unorddf2"; 336 Names[RTLIB::O_F128] = "__unordtf2"; 337 Names[RTLIB::MEMCPY] = "memcpy"; 338 Names[RTLIB::MEMMOVE] = "memmove"; 339 Names[RTLIB::MEMSET] = "memset"; 340 Names[RTLIB::UNWIND_RESUME] = "_Unwind_Resume"; 341 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1] = "__sync_val_compare_and_swap_1"; 342 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2] = "__sync_val_compare_and_swap_2"; 343 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4] = "__sync_val_compare_and_swap_4"; 344 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8] = "__sync_val_compare_and_swap_8"; 345 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_16] = "__sync_val_compare_and_swap_16"; 346 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_1] = "__sync_lock_test_and_set_1"; 347 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_2] = "__sync_lock_test_and_set_2"; 348 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_4] = "__sync_lock_test_and_set_4"; 349 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_8] = "__sync_lock_test_and_set_8"; 350 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_16] = "__sync_lock_test_and_set_16"; 351 Names[RTLIB::SYNC_FETCH_AND_ADD_1] = "__sync_fetch_and_add_1"; 352 Names[RTLIB::SYNC_FETCH_AND_ADD_2] = "__sync_fetch_and_add_2"; 353 Names[RTLIB::SYNC_FETCH_AND_ADD_4] = "__sync_fetch_and_add_4"; 354 Names[RTLIB::SYNC_FETCH_AND_ADD_8] = "__sync_fetch_and_add_8"; 355 Names[RTLIB::SYNC_FETCH_AND_ADD_16] = "__sync_fetch_and_add_16"; 356 Names[RTLIB::SYNC_FETCH_AND_SUB_1] = "__sync_fetch_and_sub_1"; 357 Names[RTLIB::SYNC_FETCH_AND_SUB_2] = "__sync_fetch_and_sub_2"; 358 Names[RTLIB::SYNC_FETCH_AND_SUB_4] = "__sync_fetch_and_sub_4"; 359 Names[RTLIB::SYNC_FETCH_AND_SUB_8] = "__sync_fetch_and_sub_8"; 360 Names[RTLIB::SYNC_FETCH_AND_SUB_16] = "__sync_fetch_and_sub_16"; 361 Names[RTLIB::SYNC_FETCH_AND_AND_1] = "__sync_fetch_and_and_1"; 362 Names[RTLIB::SYNC_FETCH_AND_AND_2] = "__sync_fetch_and_and_2"; 363 Names[RTLIB::SYNC_FETCH_AND_AND_4] = "__sync_fetch_and_and_4"; 364 Names[RTLIB::SYNC_FETCH_AND_AND_8] = "__sync_fetch_and_and_8"; 365 Names[RTLIB::SYNC_FETCH_AND_AND_16] = "__sync_fetch_and_and_16"; 366 Names[RTLIB::SYNC_FETCH_AND_OR_1] = "__sync_fetch_and_or_1"; 367 Names[RTLIB::SYNC_FETCH_AND_OR_2] = "__sync_fetch_and_or_2"; 368 Names[RTLIB::SYNC_FETCH_AND_OR_4] = "__sync_fetch_and_or_4"; 369 Names[RTLIB::SYNC_FETCH_AND_OR_8] = "__sync_fetch_and_or_8"; 370 Names[RTLIB::SYNC_FETCH_AND_OR_16] = "__sync_fetch_and_or_16"; 371 Names[RTLIB::SYNC_FETCH_AND_XOR_1] = "__sync_fetch_and_xor_1"; 372 Names[RTLIB::SYNC_FETCH_AND_XOR_2] = "__sync_fetch_and_xor_2"; 373 Names[RTLIB::SYNC_FETCH_AND_XOR_4] = "__sync_fetch_and_xor_4"; 374 Names[RTLIB::SYNC_FETCH_AND_XOR_8] = "__sync_fetch_and_xor_8"; 375 Names[RTLIB::SYNC_FETCH_AND_XOR_16] = "__sync_fetch_and_xor_16"; 376 Names[RTLIB::SYNC_FETCH_AND_NAND_1] = "__sync_fetch_and_nand_1"; 377 Names[RTLIB::SYNC_FETCH_AND_NAND_2] = "__sync_fetch_and_nand_2"; 378 Names[RTLIB::SYNC_FETCH_AND_NAND_4] = "__sync_fetch_and_nand_4"; 379 Names[RTLIB::SYNC_FETCH_AND_NAND_8] = "__sync_fetch_and_nand_8"; 380 Names[RTLIB::SYNC_FETCH_AND_NAND_16] = "__sync_fetch_and_nand_16"; 381 Names[RTLIB::SYNC_FETCH_AND_MAX_1] = "__sync_fetch_and_max_1"; 382 Names[RTLIB::SYNC_FETCH_AND_MAX_2] = "__sync_fetch_and_max_2"; 383 Names[RTLIB::SYNC_FETCH_AND_MAX_4] = "__sync_fetch_and_max_4"; 384 Names[RTLIB::SYNC_FETCH_AND_MAX_8] = "__sync_fetch_and_max_8"; 385 Names[RTLIB::SYNC_FETCH_AND_MAX_16] = "__sync_fetch_and_max_16"; 386 Names[RTLIB::SYNC_FETCH_AND_UMAX_1] = "__sync_fetch_and_umax_1"; 387 Names[RTLIB::SYNC_FETCH_AND_UMAX_2] = "__sync_fetch_and_umax_2"; 388 Names[RTLIB::SYNC_FETCH_AND_UMAX_4] = "__sync_fetch_and_umax_4"; 389 Names[RTLIB::SYNC_FETCH_AND_UMAX_8] = "__sync_fetch_and_umax_8"; 390 Names[RTLIB::SYNC_FETCH_AND_UMAX_16] = "__sync_fetch_and_umax_16"; 391 Names[RTLIB::SYNC_FETCH_AND_MIN_1] = "__sync_fetch_and_min_1"; 392 Names[RTLIB::SYNC_FETCH_AND_MIN_2] = "__sync_fetch_and_min_2"; 393 Names[RTLIB::SYNC_FETCH_AND_MIN_4] = "__sync_fetch_and_min_4"; 394 Names[RTLIB::SYNC_FETCH_AND_MIN_8] = "__sync_fetch_and_min_8"; 395 Names[RTLIB::SYNC_FETCH_AND_MIN_16] = "__sync_fetch_and_min_16"; 396 Names[RTLIB::SYNC_FETCH_AND_UMIN_1] = "__sync_fetch_and_umin_1"; 397 Names[RTLIB::SYNC_FETCH_AND_UMIN_2] = "__sync_fetch_and_umin_2"; 398 Names[RTLIB::SYNC_FETCH_AND_UMIN_4] = "__sync_fetch_and_umin_4"; 399 Names[RTLIB::SYNC_FETCH_AND_UMIN_8] = "__sync_fetch_and_umin_8"; 400 Names[RTLIB::SYNC_FETCH_AND_UMIN_16] = "__sync_fetch_and_umin_16"; 401 402 if (TT.getEnvironment() == Triple::GNU) { 403 Names[RTLIB::SINCOS_F32] = "sincosf"; 404 Names[RTLIB::SINCOS_F64] = "sincos"; 405 Names[RTLIB::SINCOS_F80] = "sincosl"; 406 Names[RTLIB::SINCOS_F128] = "sincosl"; 407 Names[RTLIB::SINCOS_PPCF128] = "sincosl"; 408 } else { 409 // These are generally not available. 410 Names[RTLIB::SINCOS_F32] = nullptr; 411 Names[RTLIB::SINCOS_F64] = nullptr; 412 Names[RTLIB::SINCOS_F80] = nullptr; 413 Names[RTLIB::SINCOS_F128] = nullptr; 414 Names[RTLIB::SINCOS_PPCF128] = nullptr; 415 } 416 417 if (!TT.isOSOpenBSD()) { 418 Names[RTLIB::STACKPROTECTOR_CHECK_FAIL] = "__stack_chk_fail"; 419 } else { 420 // These are generally not available. 421 Names[RTLIB::STACKPROTECTOR_CHECK_FAIL] = nullptr; 422 } 423 424 // For f16/f32 conversions, Darwin uses the standard naming scheme, instead 425 // of the gnueabi-style __gnu_*_ieee. 426 // FIXME: What about other targets? 427 if (TT.isOSDarwin()) { 428 Names[RTLIB::FPEXT_F16_F32] = "__extendhfsf2"; 429 Names[RTLIB::FPROUND_F32_F16] = "__truncsfhf2"; 430 } 431 } 432 433 /// InitLibcallCallingConvs - Set default libcall CallingConvs. 434 /// 435 static void InitLibcallCallingConvs(CallingConv::ID *CCs) { 436 for (int i = 0; i < RTLIB::UNKNOWN_LIBCALL; ++i) { 437 CCs[i] = CallingConv::C; 438 } 439 } 440 441 /// getFPEXT - Return the FPEXT_*_* value for the given types, or 442 /// UNKNOWN_LIBCALL if there is none. 443 RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) { 444 if (OpVT == MVT::f16) { 445 if (RetVT == MVT::f32) 446 return FPEXT_F16_F32; 447 } else if (OpVT == MVT::f32) { 448 if (RetVT == MVT::f64) 449 return FPEXT_F32_F64; 450 if (RetVT == MVT::f128) 451 return FPEXT_F32_F128; 452 } else if (OpVT == MVT::f64) { 453 if (RetVT == MVT::f128) 454 return FPEXT_F64_F128; 455 } 456 457 return UNKNOWN_LIBCALL; 458 } 459 460 /// getFPROUND - Return the FPROUND_*_* value for the given types, or 461 /// UNKNOWN_LIBCALL if there is none. 462 RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) { 463 if (RetVT == MVT::f16) { 464 if (OpVT == MVT::f32) 465 return FPROUND_F32_F16; 466 if (OpVT == MVT::f64) 467 return FPROUND_F64_F16; 468 if (OpVT == MVT::f80) 469 return FPROUND_F80_F16; 470 if (OpVT == MVT::f128) 471 return FPROUND_F128_F16; 472 if (OpVT == MVT::ppcf128) 473 return FPROUND_PPCF128_F16; 474 } else if (RetVT == MVT::f32) { 475 if (OpVT == MVT::f64) 476 return FPROUND_F64_F32; 477 if (OpVT == MVT::f80) 478 return FPROUND_F80_F32; 479 if (OpVT == MVT::f128) 480 return FPROUND_F128_F32; 481 if (OpVT == MVT::ppcf128) 482 return FPROUND_PPCF128_F32; 483 } else if (RetVT == MVT::f64) { 484 if (OpVT == MVT::f80) 485 return FPROUND_F80_F64; 486 if (OpVT == MVT::f128) 487 return FPROUND_F128_F64; 488 if (OpVT == MVT::ppcf128) 489 return FPROUND_PPCF128_F64; 490 } 491 492 return UNKNOWN_LIBCALL; 493 } 494 495 /// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or 496 /// UNKNOWN_LIBCALL if there is none. 497 RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT, EVT RetVT) { 498 if (OpVT == MVT::f32) { 499 if (RetVT == MVT::i8) 500 return FPTOSINT_F32_I8; 501 if (RetVT == MVT::i16) 502 return FPTOSINT_F32_I16; 503 if (RetVT == MVT::i32) 504 return FPTOSINT_F32_I32; 505 if (RetVT == MVT::i64) 506 return FPTOSINT_F32_I64; 507 if (RetVT == MVT::i128) 508 return FPTOSINT_F32_I128; 509 } else if (OpVT == MVT::f64) { 510 if (RetVT == MVT::i8) 511 return FPTOSINT_F64_I8; 512 if (RetVT == MVT::i16) 513 return FPTOSINT_F64_I16; 514 if (RetVT == MVT::i32) 515 return FPTOSINT_F64_I32; 516 if (RetVT == MVT::i64) 517 return FPTOSINT_F64_I64; 518 if (RetVT == MVT::i128) 519 return FPTOSINT_F64_I128; 520 } else if (OpVT == MVT::f80) { 521 if (RetVT == MVT::i32) 522 return FPTOSINT_F80_I32; 523 if (RetVT == MVT::i64) 524 return FPTOSINT_F80_I64; 525 if (RetVT == MVT::i128) 526 return FPTOSINT_F80_I128; 527 } else if (OpVT == MVT::f128) { 528 if (RetVT == MVT::i32) 529 return FPTOSINT_F128_I32; 530 if (RetVT == MVT::i64) 531 return FPTOSINT_F128_I64; 532 if (RetVT == MVT::i128) 533 return FPTOSINT_F128_I128; 534 } else if (OpVT == MVT::ppcf128) { 535 if (RetVT == MVT::i32) 536 return FPTOSINT_PPCF128_I32; 537 if (RetVT == MVT::i64) 538 return FPTOSINT_PPCF128_I64; 539 if (RetVT == MVT::i128) 540 return FPTOSINT_PPCF128_I128; 541 } 542 return UNKNOWN_LIBCALL; 543 } 544 545 /// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or 546 /// UNKNOWN_LIBCALL if there is none. 547 RTLIB::Libcall RTLIB::getFPTOUINT(EVT OpVT, EVT RetVT) { 548 if (OpVT == MVT::f32) { 549 if (RetVT == MVT::i8) 550 return FPTOUINT_F32_I8; 551 if (RetVT == MVT::i16) 552 return FPTOUINT_F32_I16; 553 if (RetVT == MVT::i32) 554 return FPTOUINT_F32_I32; 555 if (RetVT == MVT::i64) 556 return FPTOUINT_F32_I64; 557 if (RetVT == MVT::i128) 558 return FPTOUINT_F32_I128; 559 } else if (OpVT == MVT::f64) { 560 if (RetVT == MVT::i8) 561 return FPTOUINT_F64_I8; 562 if (RetVT == MVT::i16) 563 return FPTOUINT_F64_I16; 564 if (RetVT == MVT::i32) 565 return FPTOUINT_F64_I32; 566 if (RetVT == MVT::i64) 567 return FPTOUINT_F64_I64; 568 if (RetVT == MVT::i128) 569 return FPTOUINT_F64_I128; 570 } else if (OpVT == MVT::f80) { 571 if (RetVT == MVT::i32) 572 return FPTOUINT_F80_I32; 573 if (RetVT == MVT::i64) 574 return FPTOUINT_F80_I64; 575 if (RetVT == MVT::i128) 576 return FPTOUINT_F80_I128; 577 } else if (OpVT == MVT::f128) { 578 if (RetVT == MVT::i32) 579 return FPTOUINT_F128_I32; 580 if (RetVT == MVT::i64) 581 return FPTOUINT_F128_I64; 582 if (RetVT == MVT::i128) 583 return FPTOUINT_F128_I128; 584 } else if (OpVT == MVT::ppcf128) { 585 if (RetVT == MVT::i32) 586 return FPTOUINT_PPCF128_I32; 587 if (RetVT == MVT::i64) 588 return FPTOUINT_PPCF128_I64; 589 if (RetVT == MVT::i128) 590 return FPTOUINT_PPCF128_I128; 591 } 592 return UNKNOWN_LIBCALL; 593 } 594 595 /// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or 596 /// UNKNOWN_LIBCALL if there is none. 597 RTLIB::Libcall RTLIB::getSINTTOFP(EVT OpVT, EVT RetVT) { 598 if (OpVT == MVT::i32) { 599 if (RetVT == MVT::f32) 600 return SINTTOFP_I32_F32; 601 if (RetVT == MVT::f64) 602 return SINTTOFP_I32_F64; 603 if (RetVT == MVT::f80) 604 return SINTTOFP_I32_F80; 605 if (RetVT == MVT::f128) 606 return SINTTOFP_I32_F128; 607 if (RetVT == MVT::ppcf128) 608 return SINTTOFP_I32_PPCF128; 609 } else if (OpVT == MVT::i64) { 610 if (RetVT == MVT::f32) 611 return SINTTOFP_I64_F32; 612 if (RetVT == MVT::f64) 613 return SINTTOFP_I64_F64; 614 if (RetVT == MVT::f80) 615 return SINTTOFP_I64_F80; 616 if (RetVT == MVT::f128) 617 return SINTTOFP_I64_F128; 618 if (RetVT == MVT::ppcf128) 619 return SINTTOFP_I64_PPCF128; 620 } else if (OpVT == MVT::i128) { 621 if (RetVT == MVT::f32) 622 return SINTTOFP_I128_F32; 623 if (RetVT == MVT::f64) 624 return SINTTOFP_I128_F64; 625 if (RetVT == MVT::f80) 626 return SINTTOFP_I128_F80; 627 if (RetVT == MVT::f128) 628 return SINTTOFP_I128_F128; 629 if (RetVT == MVT::ppcf128) 630 return SINTTOFP_I128_PPCF128; 631 } 632 return UNKNOWN_LIBCALL; 633 } 634 635 /// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or 636 /// UNKNOWN_LIBCALL if there is none. 637 RTLIB::Libcall RTLIB::getUINTTOFP(EVT OpVT, EVT RetVT) { 638 if (OpVT == MVT::i32) { 639 if (RetVT == MVT::f32) 640 return UINTTOFP_I32_F32; 641 if (RetVT == MVT::f64) 642 return UINTTOFP_I32_F64; 643 if (RetVT == MVT::f80) 644 return UINTTOFP_I32_F80; 645 if (RetVT == MVT::f128) 646 return UINTTOFP_I32_F128; 647 if (RetVT == MVT::ppcf128) 648 return UINTTOFP_I32_PPCF128; 649 } else if (OpVT == MVT::i64) { 650 if (RetVT == MVT::f32) 651 return UINTTOFP_I64_F32; 652 if (RetVT == MVT::f64) 653 return UINTTOFP_I64_F64; 654 if (RetVT == MVT::f80) 655 return UINTTOFP_I64_F80; 656 if (RetVT == MVT::f128) 657 return UINTTOFP_I64_F128; 658 if (RetVT == MVT::ppcf128) 659 return UINTTOFP_I64_PPCF128; 660 } else if (OpVT == MVT::i128) { 661 if (RetVT == MVT::f32) 662 return UINTTOFP_I128_F32; 663 if (RetVT == MVT::f64) 664 return UINTTOFP_I128_F64; 665 if (RetVT == MVT::f80) 666 return UINTTOFP_I128_F80; 667 if (RetVT == MVT::f128) 668 return UINTTOFP_I128_F128; 669 if (RetVT == MVT::ppcf128) 670 return UINTTOFP_I128_PPCF128; 671 } 672 return UNKNOWN_LIBCALL; 673 } 674 675 RTLIB::Libcall RTLIB::getATOMIC(unsigned Opc, MVT VT) { 676 #define OP_TO_LIBCALL(Name, Enum) \ 677 case Name: \ 678 switch (VT.SimpleTy) { \ 679 default: \ 680 return UNKNOWN_LIBCALL; \ 681 case MVT::i8: \ 682 return Enum##_1; \ 683 case MVT::i16: \ 684 return Enum##_2; \ 685 case MVT::i32: \ 686 return Enum##_4; \ 687 case MVT::i64: \ 688 return Enum##_8; \ 689 case MVT::i128: \ 690 return Enum##_16; \ 691 } 692 693 switch (Opc) { 694 OP_TO_LIBCALL(ISD::ATOMIC_SWAP, SYNC_LOCK_TEST_AND_SET) 695 OP_TO_LIBCALL(ISD::ATOMIC_CMP_SWAP, SYNC_VAL_COMPARE_AND_SWAP) 696 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_ADD, SYNC_FETCH_AND_ADD) 697 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_SUB, SYNC_FETCH_AND_SUB) 698 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_AND, SYNC_FETCH_AND_AND) 699 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_OR, SYNC_FETCH_AND_OR) 700 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_XOR, SYNC_FETCH_AND_XOR) 701 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_NAND, SYNC_FETCH_AND_NAND) 702 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_MAX, SYNC_FETCH_AND_MAX) 703 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_UMAX, SYNC_FETCH_AND_UMAX) 704 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_MIN, SYNC_FETCH_AND_MIN) 705 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_UMIN, SYNC_FETCH_AND_UMIN) 706 } 707 708 #undef OP_TO_LIBCALL 709 710 return UNKNOWN_LIBCALL; 711 } 712 713 /// InitCmpLibcallCCs - Set default comparison libcall CC. 714 /// 715 static void InitCmpLibcallCCs(ISD::CondCode *CCs) { 716 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL); 717 CCs[RTLIB::OEQ_F32] = ISD::SETEQ; 718 CCs[RTLIB::OEQ_F64] = ISD::SETEQ; 719 CCs[RTLIB::OEQ_F128] = ISD::SETEQ; 720 CCs[RTLIB::UNE_F32] = ISD::SETNE; 721 CCs[RTLIB::UNE_F64] = ISD::SETNE; 722 CCs[RTLIB::UNE_F128] = ISD::SETNE; 723 CCs[RTLIB::OGE_F32] = ISD::SETGE; 724 CCs[RTLIB::OGE_F64] = ISD::SETGE; 725 CCs[RTLIB::OGE_F128] = ISD::SETGE; 726 CCs[RTLIB::OLT_F32] = ISD::SETLT; 727 CCs[RTLIB::OLT_F64] = ISD::SETLT; 728 CCs[RTLIB::OLT_F128] = ISD::SETLT; 729 CCs[RTLIB::OLE_F32] = ISD::SETLE; 730 CCs[RTLIB::OLE_F64] = ISD::SETLE; 731 CCs[RTLIB::OLE_F128] = ISD::SETLE; 732 CCs[RTLIB::OGT_F32] = ISD::SETGT; 733 CCs[RTLIB::OGT_F64] = ISD::SETGT; 734 CCs[RTLIB::OGT_F128] = ISD::SETGT; 735 CCs[RTLIB::UO_F32] = ISD::SETNE; 736 CCs[RTLIB::UO_F64] = ISD::SETNE; 737 CCs[RTLIB::UO_F128] = ISD::SETNE; 738 CCs[RTLIB::O_F32] = ISD::SETEQ; 739 CCs[RTLIB::O_F64] = ISD::SETEQ; 740 CCs[RTLIB::O_F128] = ISD::SETEQ; 741 } 742 743 /// NOTE: The TargetMachine owns TLOF. 744 TargetLoweringBase::TargetLoweringBase(const TargetMachine &tm) : TM(tm) { 745 initActions(); 746 747 // Perform these initializations only once. 748 IsLittleEndian = getDataLayout()->isLittleEndian(); 749 MaxStoresPerMemset = MaxStoresPerMemcpy = MaxStoresPerMemmove = 8; 750 MaxStoresPerMemsetOptSize = MaxStoresPerMemcpyOptSize 751 = MaxStoresPerMemmoveOptSize = 4; 752 UseUnderscoreSetJmp = false; 753 UseUnderscoreLongJmp = false; 754 SelectIsExpensive = false; 755 HasMultipleConditionRegisters = false; 756 HasExtractBitsInsn = false; 757 IntDivIsCheap = false; 758 FsqrtIsCheap = false; 759 Pow2SDivIsCheap = false; 760 JumpIsExpensive = false; 761 PredictableSelectIsExpensive = false; 762 MaskAndBranchFoldingIsLegal = false; 763 EnableExtLdPromotion = false; 764 HasFloatingPointExceptions = true; 765 StackPointerRegisterToSaveRestore = 0; 766 ExceptionPointerRegister = 0; 767 ExceptionSelectorRegister = 0; 768 BooleanContents = UndefinedBooleanContent; 769 BooleanFloatContents = UndefinedBooleanContent; 770 BooleanVectorContents = UndefinedBooleanContent; 771 SchedPreferenceInfo = Sched::ILP; 772 JumpBufSize = 0; 773 JumpBufAlignment = 0; 774 MinFunctionAlignment = 0; 775 PrefFunctionAlignment = 0; 776 PrefLoopAlignment = 0; 777 MinStackArgumentAlignment = 1; 778 InsertFencesForAtomic = false; 779 MinimumJumpTableEntries = 4; 780 781 InitLibcallNames(LibcallRoutineNames, Triple(TM.getTargetTriple())); 782 InitCmpLibcallCCs(CmpLibcallCCs); 783 InitLibcallCallingConvs(LibcallCallingConvs); 784 } 785 786 void TargetLoweringBase::initActions() { 787 // All operations default to being supported. 788 memset(OpActions, 0, sizeof(OpActions)); 789 memset(LoadExtActions, 0, sizeof(LoadExtActions)); 790 memset(TruncStoreActions, 0, sizeof(TruncStoreActions)); 791 memset(IndexedModeActions, 0, sizeof(IndexedModeActions)); 792 memset(CondCodeActions, 0, sizeof(CondCodeActions)); 793 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*)); 794 memset(TargetDAGCombineArray, 0, array_lengthof(TargetDAGCombineArray)); 795 796 // Set default actions for various operations. 797 for (MVT VT : MVT::all_valuetypes()) { 798 // Default all indexed load / store to expand. 799 for (unsigned IM = (unsigned)ISD::PRE_INC; 800 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) { 801 setIndexedLoadAction(IM, VT, Expand); 802 setIndexedStoreAction(IM, VT, Expand); 803 } 804 805 // Most backends expect to see the node which just returns the value loaded. 806 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Expand); 807 808 // These operations default to expand. 809 setOperationAction(ISD::FGETSIGN, VT, Expand); 810 setOperationAction(ISD::CONCAT_VECTORS, VT, Expand); 811 setOperationAction(ISD::FMINNUM, VT, Expand); 812 setOperationAction(ISD::FMAXNUM, VT, Expand); 813 setOperationAction(ISD::FMAD, VT, Expand); 814 setOperationAction(ISD::SMIN, VT, Expand); 815 setOperationAction(ISD::SMAX, VT, Expand); 816 setOperationAction(ISD::UMIN, VT, Expand); 817 setOperationAction(ISD::UMAX, VT, Expand); 818 819 // Overflow operations default to expand 820 setOperationAction(ISD::SADDO, VT, Expand); 821 setOperationAction(ISD::SSUBO, VT, Expand); 822 setOperationAction(ISD::UADDO, VT, Expand); 823 setOperationAction(ISD::USUBO, VT, Expand); 824 setOperationAction(ISD::SMULO, VT, Expand); 825 setOperationAction(ISD::UMULO, VT, Expand); 826 827 // These library functions default to expand. 828 setOperationAction(ISD::FROUND, VT, Expand); 829 830 // These operations default to expand for vector types. 831 if (VT.isVector()) { 832 setOperationAction(ISD::FCOPYSIGN, VT, Expand); 833 setOperationAction(ISD::ANY_EXTEND_VECTOR_INREG, VT, Expand); 834 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, VT, Expand); 835 setOperationAction(ISD::ZERO_EXTEND_VECTOR_INREG, VT, Expand); 836 } 837 } 838 839 // Most targets ignore the @llvm.prefetch intrinsic. 840 setOperationAction(ISD::PREFETCH, MVT::Other, Expand); 841 842 // ConstantFP nodes default to expand. Targets can either change this to 843 // Legal, in which case all fp constants are legal, or use isFPImmLegal() 844 // to optimize expansions for certain constants. 845 setOperationAction(ISD::ConstantFP, MVT::f16, Expand); 846 setOperationAction(ISD::ConstantFP, MVT::f32, Expand); 847 setOperationAction(ISD::ConstantFP, MVT::f64, Expand); 848 setOperationAction(ISD::ConstantFP, MVT::f80, Expand); 849 setOperationAction(ISD::ConstantFP, MVT::f128, Expand); 850 851 // These library functions default to expand. 852 for (MVT VT : {MVT::f32, MVT::f64, MVT::f128}) { 853 setOperationAction(ISD::FLOG , VT, Expand); 854 setOperationAction(ISD::FLOG2, VT, Expand); 855 setOperationAction(ISD::FLOG10, VT, Expand); 856 setOperationAction(ISD::FEXP , VT, Expand); 857 setOperationAction(ISD::FEXP2, VT, Expand); 858 setOperationAction(ISD::FFLOOR, VT, Expand); 859 setOperationAction(ISD::FMINNUM, VT, Expand); 860 setOperationAction(ISD::FMAXNUM, VT, Expand); 861 setOperationAction(ISD::FNEARBYINT, VT, Expand); 862 setOperationAction(ISD::FCEIL, VT, Expand); 863 setOperationAction(ISD::FRINT, VT, Expand); 864 setOperationAction(ISD::FTRUNC, VT, Expand); 865 setOperationAction(ISD::FROUND, VT, Expand); 866 } 867 868 // Default ISD::TRAP to expand (which turns it into abort). 869 setOperationAction(ISD::TRAP, MVT::Other, Expand); 870 871 // On most systems, DEBUGTRAP and TRAP have no difference. The "Expand" 872 // here is to inform DAG Legalizer to replace DEBUGTRAP with TRAP. 873 // 874 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Expand); 875 } 876 877 MVT TargetLoweringBase::getPointerTy(uint32_t AS) const { 878 return MVT::getIntegerVT(getPointerSizeInBits(AS)); 879 } 880 881 unsigned TargetLoweringBase::getPointerSizeInBits(uint32_t AS) const { 882 return getDataLayout()->getPointerSizeInBits(AS); 883 } 884 885 unsigned TargetLoweringBase::getPointerTypeSizeInBits(Type *Ty) const { 886 assert(Ty->isPointerTy()); 887 return getPointerSizeInBits(Ty->getPointerAddressSpace()); 888 } 889 890 MVT TargetLoweringBase::getScalarShiftAmountTy(EVT LHSTy) const { 891 return MVT::getIntegerVT(8 * getDataLayout()->getPointerSize(0)); 892 } 893 894 EVT TargetLoweringBase::getShiftAmountTy(EVT LHSTy) const { 895 assert(LHSTy.isInteger() && "Shift amount is not an integer type!"); 896 if (LHSTy.isVector()) 897 return LHSTy; 898 return getScalarShiftAmountTy(LHSTy); 899 } 900 901 /// canOpTrap - Returns true if the operation can trap for the value type. 902 /// VT must be a legal type. 903 bool TargetLoweringBase::canOpTrap(unsigned Op, EVT VT) const { 904 assert(isTypeLegal(VT)); 905 switch (Op) { 906 default: 907 return false; 908 case ISD::FDIV: 909 case ISD::FREM: 910 case ISD::SDIV: 911 case ISD::UDIV: 912 case ISD::SREM: 913 case ISD::UREM: 914 return true; 915 } 916 } 917 918 TargetLoweringBase::LegalizeKind 919 TargetLoweringBase::getTypeConversion(LLVMContext &Context, EVT VT) const { 920 // If this is a simple type, use the ComputeRegisterProp mechanism. 921 if (VT.isSimple()) { 922 MVT SVT = VT.getSimpleVT(); 923 assert((unsigned)SVT.SimpleTy < array_lengthof(TransformToType)); 924 MVT NVT = TransformToType[SVT.SimpleTy]; 925 LegalizeTypeAction LA = ValueTypeActions.getTypeAction(SVT); 926 927 assert((LA == TypeLegal || LA == TypeSoftenFloat || 928 ValueTypeActions.getTypeAction(NVT) != TypePromoteInteger) && 929 "Promote may not follow Expand or Promote"); 930 931 if (LA == TypeSplitVector) 932 return LegalizeKind(LA, 933 EVT::getVectorVT(Context, SVT.getVectorElementType(), 934 SVT.getVectorNumElements() / 2)); 935 if (LA == TypeScalarizeVector) 936 return LegalizeKind(LA, SVT.getVectorElementType()); 937 return LegalizeKind(LA, NVT); 938 } 939 940 // Handle Extended Scalar Types. 941 if (!VT.isVector()) { 942 assert(VT.isInteger() && "Float types must be simple"); 943 unsigned BitSize = VT.getSizeInBits(); 944 // First promote to a power-of-two size, then expand if necessary. 945 if (BitSize < 8 || !isPowerOf2_32(BitSize)) { 946 EVT NVT = VT.getRoundIntegerType(Context); 947 assert(NVT != VT && "Unable to round integer VT"); 948 LegalizeKind NextStep = getTypeConversion(Context, NVT); 949 // Avoid multi-step promotion. 950 if (NextStep.first == TypePromoteInteger) 951 return NextStep; 952 // Return rounded integer type. 953 return LegalizeKind(TypePromoteInteger, NVT); 954 } 955 956 return LegalizeKind(TypeExpandInteger, 957 EVT::getIntegerVT(Context, VT.getSizeInBits() / 2)); 958 } 959 960 // Handle vector types. 961 unsigned NumElts = VT.getVectorNumElements(); 962 EVT EltVT = VT.getVectorElementType(); 963 964 // Vectors with only one element are always scalarized. 965 if (NumElts == 1) 966 return LegalizeKind(TypeScalarizeVector, EltVT); 967 968 // Try to widen vector elements until the element type is a power of two and 969 // promote it to a legal type later on, for example: 970 // <3 x i8> -> <4 x i8> -> <4 x i32> 971 if (EltVT.isInteger()) { 972 // Vectors with a number of elements that is not a power of two are always 973 // widened, for example <3 x i8> -> <4 x i8>. 974 if (!VT.isPow2VectorType()) { 975 NumElts = (unsigned)NextPowerOf2(NumElts); 976 EVT NVT = EVT::getVectorVT(Context, EltVT, NumElts); 977 return LegalizeKind(TypeWidenVector, NVT); 978 } 979 980 // Examine the element type. 981 LegalizeKind LK = getTypeConversion(Context, EltVT); 982 983 // If type is to be expanded, split the vector. 984 // <4 x i140> -> <2 x i140> 985 if (LK.first == TypeExpandInteger) 986 return LegalizeKind(TypeSplitVector, 987 EVT::getVectorVT(Context, EltVT, NumElts / 2)); 988 989 // Promote the integer element types until a legal vector type is found 990 // or until the element integer type is too big. If a legal type was not 991 // found, fallback to the usual mechanism of widening/splitting the 992 // vector. 993 EVT OldEltVT = EltVT; 994 while (1) { 995 // Increase the bitwidth of the element to the next pow-of-two 996 // (which is greater than 8 bits). 997 EltVT = EVT::getIntegerVT(Context, 1 + EltVT.getSizeInBits()) 998 .getRoundIntegerType(Context); 999 1000 // Stop trying when getting a non-simple element type. 1001 // Note that vector elements may be greater than legal vector element 1002 // types. Example: X86 XMM registers hold 64bit element on 32bit 1003 // systems. 1004 if (!EltVT.isSimple()) 1005 break; 1006 1007 // Build a new vector type and check if it is legal. 1008 MVT NVT = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts); 1009 // Found a legal promoted vector type. 1010 if (NVT != MVT() && ValueTypeActions.getTypeAction(NVT) == TypeLegal) 1011 return LegalizeKind(TypePromoteInteger, 1012 EVT::getVectorVT(Context, EltVT, NumElts)); 1013 } 1014 1015 // Reset the type to the unexpanded type if we did not find a legal vector 1016 // type with a promoted vector element type. 1017 EltVT = OldEltVT; 1018 } 1019 1020 // Try to widen the vector until a legal type is found. 1021 // If there is no wider legal type, split the vector. 1022 while (1) { 1023 // Round up to the next power of 2. 1024 NumElts = (unsigned)NextPowerOf2(NumElts); 1025 1026 // If there is no simple vector type with this many elements then there 1027 // cannot be a larger legal vector type. Note that this assumes that 1028 // there are no skipped intermediate vector types in the simple types. 1029 if (!EltVT.isSimple()) 1030 break; 1031 MVT LargerVector = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts); 1032 if (LargerVector == MVT()) 1033 break; 1034 1035 // If this type is legal then widen the vector. 1036 if (ValueTypeActions.getTypeAction(LargerVector) == TypeLegal) 1037 return LegalizeKind(TypeWidenVector, LargerVector); 1038 } 1039 1040 // Widen odd vectors to next power of two. 1041 if (!VT.isPow2VectorType()) { 1042 EVT NVT = VT.getPow2VectorType(Context); 1043 return LegalizeKind(TypeWidenVector, NVT); 1044 } 1045 1046 // Vectors with illegal element types are expanded. 1047 EVT NVT = EVT::getVectorVT(Context, EltVT, VT.getVectorNumElements() / 2); 1048 return LegalizeKind(TypeSplitVector, NVT); 1049 } 1050 1051 static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT, 1052 unsigned &NumIntermediates, 1053 MVT &RegisterVT, 1054 TargetLoweringBase *TLI) { 1055 // Figure out the right, legal destination reg to copy into. 1056 unsigned NumElts = VT.getVectorNumElements(); 1057 MVT EltTy = VT.getVectorElementType(); 1058 1059 unsigned NumVectorRegs = 1; 1060 1061 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we 1062 // could break down into LHS/RHS like LegalizeDAG does. 1063 if (!isPowerOf2_32(NumElts)) { 1064 NumVectorRegs = NumElts; 1065 NumElts = 1; 1066 } 1067 1068 // Divide the input until we get to a supported size. This will always 1069 // end with a scalar if the target doesn't support vectors. 1070 while (NumElts > 1 && !TLI->isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) { 1071 NumElts >>= 1; 1072 NumVectorRegs <<= 1; 1073 } 1074 1075 NumIntermediates = NumVectorRegs; 1076 1077 MVT NewVT = MVT::getVectorVT(EltTy, NumElts); 1078 if (!TLI->isTypeLegal(NewVT)) 1079 NewVT = EltTy; 1080 IntermediateVT = NewVT; 1081 1082 unsigned NewVTSize = NewVT.getSizeInBits(); 1083 1084 // Convert sizes such as i33 to i64. 1085 if (!isPowerOf2_32(NewVTSize)) 1086 NewVTSize = NextPowerOf2(NewVTSize); 1087 1088 MVT DestVT = TLI->getRegisterType(NewVT); 1089 RegisterVT = DestVT; 1090 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16. 1091 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits()); 1092 1093 // Otherwise, promotion or legal types use the same number of registers as 1094 // the vector decimated to the appropriate level. 1095 return NumVectorRegs; 1096 } 1097 1098 /// isLegalRC - Return true if the value types that can be represented by the 1099 /// specified register class are all legal. 1100 bool TargetLoweringBase::isLegalRC(const TargetRegisterClass *RC) const { 1101 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end(); 1102 I != E; ++I) { 1103 if (isTypeLegal(*I)) 1104 return true; 1105 } 1106 return false; 1107 } 1108 1109 /// Replace/modify any TargetFrameIndex operands with a targte-dependent 1110 /// sequence of memory operands that is recognized by PrologEpilogInserter. 1111 MachineBasicBlock* 1112 TargetLoweringBase::emitPatchPoint(MachineInstr *MI, 1113 MachineBasicBlock *MBB) const { 1114 MachineFunction &MF = *MI->getParent()->getParent(); 1115 1116 // MI changes inside this loop as we grow operands. 1117 for(unsigned OperIdx = 0; OperIdx != MI->getNumOperands(); ++OperIdx) { 1118 MachineOperand &MO = MI->getOperand(OperIdx); 1119 if (!MO.isFI()) 1120 continue; 1121 1122 // foldMemoryOperand builds a new MI after replacing a single FI operand 1123 // with the canonical set of five x86 addressing-mode operands. 1124 int FI = MO.getIndex(); 1125 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), MI->getDesc()); 1126 1127 // Copy operands before the frame-index. 1128 for (unsigned i = 0; i < OperIdx; ++i) 1129 MIB.addOperand(MI->getOperand(i)); 1130 // Add frame index operands: direct-mem-ref tag, #FI, offset. 1131 MIB.addImm(StackMaps::DirectMemRefOp); 1132 MIB.addOperand(MI->getOperand(OperIdx)); 1133 MIB.addImm(0); 1134 // Copy the operands after the frame index. 1135 for (unsigned i = OperIdx + 1; i != MI->getNumOperands(); ++i) 1136 MIB.addOperand(MI->getOperand(i)); 1137 1138 // Inherit previous memory operands. 1139 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end()); 1140 assert(MIB->mayLoad() && "Folded a stackmap use to a non-load!"); 1141 1142 // Add a new memory operand for this FI. 1143 const MachineFrameInfo &MFI = *MF.getFrameInfo(); 1144 assert(MFI.getObjectOffset(FI) != -1); 1145 1146 unsigned Flags = MachineMemOperand::MOLoad; 1147 if (MI->getOpcode() == TargetOpcode::STATEPOINT) { 1148 Flags |= MachineMemOperand::MOStore; 1149 Flags |= MachineMemOperand::MOVolatile; 1150 } 1151 MachineMemOperand *MMO = MF.getMachineMemOperand( 1152 MachinePointerInfo::getFixedStack(FI), Flags, 1153 TM.getDataLayout()->getPointerSize(), MFI.getObjectAlignment(FI)); 1154 MIB->addMemOperand(MF, MMO); 1155 1156 // Replace the instruction and update the operand index. 1157 MBB->insert(MachineBasicBlock::iterator(MI), MIB); 1158 OperIdx += (MIB->getNumOperands() - MI->getNumOperands()) - 1; 1159 MI->eraseFromParent(); 1160 MI = MIB; 1161 } 1162 return MBB; 1163 } 1164 1165 /// findRepresentativeClass - Return the largest legal super-reg register class 1166 /// of the register class for the specified type and its associated "cost". 1167 // This function is in TargetLowering because it uses RegClassForVT which would 1168 // need to be moved to TargetRegisterInfo and would necessitate moving 1169 // isTypeLegal over as well - a massive change that would just require 1170 // TargetLowering having a TargetRegisterInfo class member that it would use. 1171 std::pair<const TargetRegisterClass *, uint8_t> 1172 TargetLoweringBase::findRepresentativeClass(const TargetRegisterInfo *TRI, 1173 MVT VT) const { 1174 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy]; 1175 if (!RC) 1176 return std::make_pair(RC, 0); 1177 1178 // Compute the set of all super-register classes. 1179 BitVector SuperRegRC(TRI->getNumRegClasses()); 1180 for (SuperRegClassIterator RCI(RC, TRI); RCI.isValid(); ++RCI) 1181 SuperRegRC.setBitsInMask(RCI.getMask()); 1182 1183 // Find the first legal register class with the largest spill size. 1184 const TargetRegisterClass *BestRC = RC; 1185 for (int i = SuperRegRC.find_first(); i >= 0; i = SuperRegRC.find_next(i)) { 1186 const TargetRegisterClass *SuperRC = TRI->getRegClass(i); 1187 // We want the largest possible spill size. 1188 if (SuperRC->getSize() <= BestRC->getSize()) 1189 continue; 1190 if (!isLegalRC(SuperRC)) 1191 continue; 1192 BestRC = SuperRC; 1193 } 1194 return std::make_pair(BestRC, 1); 1195 } 1196 1197 /// computeRegisterProperties - Once all of the register classes are added, 1198 /// this allows us to compute derived properties we expose. 1199 void TargetLoweringBase::computeRegisterProperties( 1200 const TargetRegisterInfo *TRI) { 1201 static_assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE, 1202 "Too many value types for ValueTypeActions to hold!"); 1203 1204 // Everything defaults to needing one register. 1205 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) { 1206 NumRegistersForVT[i] = 1; 1207 RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i; 1208 } 1209 // ...except isVoid, which doesn't need any registers. 1210 NumRegistersForVT[MVT::isVoid] = 0; 1211 1212 // Find the largest integer register class. 1213 unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE; 1214 for (; RegClassForVT[LargestIntReg] == nullptr; --LargestIntReg) 1215 assert(LargestIntReg != MVT::i1 && "No integer registers defined!"); 1216 1217 // Every integer value type larger than this largest register takes twice as 1218 // many registers to represent as the previous ValueType. 1219 for (unsigned ExpandedReg = LargestIntReg + 1; 1220 ExpandedReg <= MVT::LAST_INTEGER_VALUETYPE; ++ExpandedReg) { 1221 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1]; 1222 RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg; 1223 TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1); 1224 ValueTypeActions.setTypeAction((MVT::SimpleValueType)ExpandedReg, 1225 TypeExpandInteger); 1226 } 1227 1228 // Inspect all of the ValueType's smaller than the largest integer 1229 // register to see which ones need promotion. 1230 unsigned LegalIntReg = LargestIntReg; 1231 for (unsigned IntReg = LargestIntReg - 1; 1232 IntReg >= (unsigned)MVT::i1; --IntReg) { 1233 MVT IVT = (MVT::SimpleValueType)IntReg; 1234 if (isTypeLegal(IVT)) { 1235 LegalIntReg = IntReg; 1236 } else { 1237 RegisterTypeForVT[IntReg] = TransformToType[IntReg] = 1238 (const MVT::SimpleValueType)LegalIntReg; 1239 ValueTypeActions.setTypeAction(IVT, TypePromoteInteger); 1240 } 1241 } 1242 1243 // ppcf128 type is really two f64's. 1244 if (!isTypeLegal(MVT::ppcf128)) { 1245 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64]; 1246 RegisterTypeForVT[MVT::ppcf128] = MVT::f64; 1247 TransformToType[MVT::ppcf128] = MVT::f64; 1248 ValueTypeActions.setTypeAction(MVT::ppcf128, TypeExpandFloat); 1249 } 1250 1251 // Decide how to handle f128. If the target does not have native f128 support, 1252 // expand it to i128 and we will be generating soft float library calls. 1253 if (!isTypeLegal(MVT::f128)) { 1254 NumRegistersForVT[MVT::f128] = NumRegistersForVT[MVT::i128]; 1255 RegisterTypeForVT[MVT::f128] = RegisterTypeForVT[MVT::i128]; 1256 TransformToType[MVT::f128] = MVT::i128; 1257 ValueTypeActions.setTypeAction(MVT::f128, TypeSoftenFloat); 1258 } 1259 1260 // Decide how to handle f64. If the target does not have native f64 support, 1261 // expand it to i64 and we will be generating soft float library calls. 1262 if (!isTypeLegal(MVT::f64)) { 1263 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64]; 1264 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64]; 1265 TransformToType[MVT::f64] = MVT::i64; 1266 ValueTypeActions.setTypeAction(MVT::f64, TypeSoftenFloat); 1267 } 1268 1269 // Decide how to handle f32. If the target does not have native f32 support, 1270 // expand it to i32 and we will be generating soft float library calls. 1271 if (!isTypeLegal(MVT::f32)) { 1272 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32]; 1273 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32]; 1274 TransformToType[MVT::f32] = MVT::i32; 1275 ValueTypeActions.setTypeAction(MVT::f32, TypeSoftenFloat); 1276 } 1277 1278 if (!isTypeLegal(MVT::f16)) { 1279 // If the target has native f32 support, promote f16 operations to f32. If 1280 // f32 is not supported, generate soft float library calls. 1281 if (isTypeLegal(MVT::f32)) { 1282 NumRegistersForVT[MVT::f16] = NumRegistersForVT[MVT::f32]; 1283 RegisterTypeForVT[MVT::f16] = RegisterTypeForVT[MVT::f32]; 1284 TransformToType[MVT::f16] = MVT::f32; 1285 ValueTypeActions.setTypeAction(MVT::f16, TypePromoteFloat); 1286 } else { 1287 NumRegistersForVT[MVT::f16] = NumRegistersForVT[MVT::i16]; 1288 RegisterTypeForVT[MVT::f16] = RegisterTypeForVT[MVT::i16]; 1289 TransformToType[MVT::f16] = MVT::i16; 1290 ValueTypeActions.setTypeAction(MVT::f16, TypeSoftenFloat); 1291 } 1292 } 1293 1294 // Loop over all of the vector value types to see which need transformations. 1295 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE; 1296 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) { 1297 MVT VT = (MVT::SimpleValueType) i; 1298 if (isTypeLegal(VT)) 1299 continue; 1300 1301 MVT EltVT = VT.getVectorElementType(); 1302 unsigned NElts = VT.getVectorNumElements(); 1303 bool IsLegalWiderType = false; 1304 LegalizeTypeAction PreferredAction = getPreferredVectorAction(VT); 1305 switch (PreferredAction) { 1306 case TypePromoteInteger: { 1307 // Try to promote the elements of integer vectors. If no legal 1308 // promotion was found, fall through to the widen-vector method. 1309 for (unsigned nVT = i + 1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) { 1310 MVT SVT = (MVT::SimpleValueType) nVT; 1311 // Promote vectors of integers to vectors with the same number 1312 // of elements, with a wider element type. 1313 if (SVT.getVectorElementType().getSizeInBits() > EltVT.getSizeInBits() 1314 && SVT.getVectorNumElements() == NElts && isTypeLegal(SVT) 1315 && SVT.getScalarType().isInteger()) { 1316 TransformToType[i] = SVT; 1317 RegisterTypeForVT[i] = SVT; 1318 NumRegistersForVT[i] = 1; 1319 ValueTypeActions.setTypeAction(VT, TypePromoteInteger); 1320 IsLegalWiderType = true; 1321 break; 1322 } 1323 } 1324 if (IsLegalWiderType) 1325 break; 1326 } 1327 case TypeWidenVector: { 1328 // Try to widen the vector. 1329 for (unsigned nVT = i + 1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) { 1330 MVT SVT = (MVT::SimpleValueType) nVT; 1331 if (SVT.getVectorElementType() == EltVT 1332 && SVT.getVectorNumElements() > NElts && isTypeLegal(SVT)) { 1333 TransformToType[i] = SVT; 1334 RegisterTypeForVT[i] = SVT; 1335 NumRegistersForVT[i] = 1; 1336 ValueTypeActions.setTypeAction(VT, TypeWidenVector); 1337 IsLegalWiderType = true; 1338 break; 1339 } 1340 } 1341 if (IsLegalWiderType) 1342 break; 1343 } 1344 case TypeSplitVector: 1345 case TypeScalarizeVector: { 1346 MVT IntermediateVT; 1347 MVT RegisterVT; 1348 unsigned NumIntermediates; 1349 NumRegistersForVT[i] = getVectorTypeBreakdownMVT(VT, IntermediateVT, 1350 NumIntermediates, RegisterVT, this); 1351 RegisterTypeForVT[i] = RegisterVT; 1352 1353 MVT NVT = VT.getPow2VectorType(); 1354 if (NVT == VT) { 1355 // Type is already a power of 2. The default action is to split. 1356 TransformToType[i] = MVT::Other; 1357 if (PreferredAction == TypeScalarizeVector) 1358 ValueTypeActions.setTypeAction(VT, TypeScalarizeVector); 1359 else if (PreferredAction == TypeSplitVector) 1360 ValueTypeActions.setTypeAction(VT, TypeSplitVector); 1361 else 1362 // Set type action according to the number of elements. 1363 ValueTypeActions.setTypeAction(VT, NElts == 1 ? TypeScalarizeVector 1364 : TypeSplitVector); 1365 } else { 1366 TransformToType[i] = NVT; 1367 ValueTypeActions.setTypeAction(VT, TypeWidenVector); 1368 } 1369 break; 1370 } 1371 default: 1372 llvm_unreachable("Unknown vector legalization action!"); 1373 } 1374 } 1375 1376 // Determine the 'representative' register class for each value type. 1377 // An representative register class is the largest (meaning one which is 1378 // not a sub-register class / subreg register class) legal register class for 1379 // a group of value types. For example, on i386, i8, i16, and i32 1380 // representative would be GR32; while on x86_64 it's GR64. 1381 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) { 1382 const TargetRegisterClass* RRC; 1383 uint8_t Cost; 1384 std::tie(RRC, Cost) = findRepresentativeClass(TRI, (MVT::SimpleValueType)i); 1385 RepRegClassForVT[i] = RRC; 1386 RepRegClassCostForVT[i] = Cost; 1387 } 1388 } 1389 1390 EVT TargetLoweringBase::getSetCCResultType(LLVMContext &, EVT VT) const { 1391 assert(!VT.isVector() && "No default SetCC type for vectors!"); 1392 return getPointerTy(0).SimpleTy; 1393 } 1394 1395 MVT::SimpleValueType TargetLoweringBase::getCmpLibcallReturnType() const { 1396 return MVT::i32; // return the default value 1397 } 1398 1399 /// getVectorTypeBreakdown - Vector types are broken down into some number of 1400 /// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32 1401 /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack. 1402 /// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86. 1403 /// 1404 /// This method returns the number of registers needed, and the VT for each 1405 /// register. It also returns the VT and quantity of the intermediate values 1406 /// before they are promoted/expanded. 1407 /// 1408 unsigned TargetLoweringBase::getVectorTypeBreakdown(LLVMContext &Context, EVT VT, 1409 EVT &IntermediateVT, 1410 unsigned &NumIntermediates, 1411 MVT &RegisterVT) const { 1412 unsigned NumElts = VT.getVectorNumElements(); 1413 1414 // If there is a wider vector type with the same element type as this one, 1415 // or a promoted vector type that has the same number of elements which 1416 // are wider, then we should convert to that legal vector type. 1417 // This handles things like <2 x float> -> <4 x float> and 1418 // <4 x i1> -> <4 x i32>. 1419 LegalizeTypeAction TA = getTypeAction(Context, VT); 1420 if (NumElts != 1 && (TA == TypeWidenVector || TA == TypePromoteInteger)) { 1421 EVT RegisterEVT = getTypeToTransformTo(Context, VT); 1422 if (isTypeLegal(RegisterEVT)) { 1423 IntermediateVT = RegisterEVT; 1424 RegisterVT = RegisterEVT.getSimpleVT(); 1425 NumIntermediates = 1; 1426 return 1; 1427 } 1428 } 1429 1430 // Figure out the right, legal destination reg to copy into. 1431 EVT EltTy = VT.getVectorElementType(); 1432 1433 unsigned NumVectorRegs = 1; 1434 1435 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we 1436 // could break down into LHS/RHS like LegalizeDAG does. 1437 if (!isPowerOf2_32(NumElts)) { 1438 NumVectorRegs = NumElts; 1439 NumElts = 1; 1440 } 1441 1442 // Divide the input until we get to a supported size. This will always 1443 // end with a scalar if the target doesn't support vectors. 1444 while (NumElts > 1 && !isTypeLegal( 1445 EVT::getVectorVT(Context, EltTy, NumElts))) { 1446 NumElts >>= 1; 1447 NumVectorRegs <<= 1; 1448 } 1449 1450 NumIntermediates = NumVectorRegs; 1451 1452 EVT NewVT = EVT::getVectorVT(Context, EltTy, NumElts); 1453 if (!isTypeLegal(NewVT)) 1454 NewVT = EltTy; 1455 IntermediateVT = NewVT; 1456 1457 MVT DestVT = getRegisterType(Context, NewVT); 1458 RegisterVT = DestVT; 1459 unsigned NewVTSize = NewVT.getSizeInBits(); 1460 1461 // Convert sizes such as i33 to i64. 1462 if (!isPowerOf2_32(NewVTSize)) 1463 NewVTSize = NextPowerOf2(NewVTSize); 1464 1465 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16. 1466 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits()); 1467 1468 // Otherwise, promotion or legal types use the same number of registers as 1469 // the vector decimated to the appropriate level. 1470 return NumVectorRegs; 1471 } 1472 1473 /// Get the EVTs and ArgFlags collections that represent the legalized return 1474 /// type of the given function. This does not require a DAG or a return value, 1475 /// and is suitable for use before any DAGs for the function are constructed. 1476 /// TODO: Move this out of TargetLowering.cpp. 1477 void llvm::GetReturnInfo(Type* ReturnType, AttributeSet attr, 1478 SmallVectorImpl<ISD::OutputArg> &Outs, 1479 const TargetLowering &TLI) { 1480 SmallVector<EVT, 4> ValueVTs; 1481 ComputeValueVTs(TLI, ReturnType, ValueVTs); 1482 unsigned NumValues = ValueVTs.size(); 1483 if (NumValues == 0) return; 1484 1485 for (unsigned j = 0, f = NumValues; j != f; ++j) { 1486 EVT VT = ValueVTs[j]; 1487 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 1488 1489 if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::SExt)) 1490 ExtendKind = ISD::SIGN_EXTEND; 1491 else if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::ZExt)) 1492 ExtendKind = ISD::ZERO_EXTEND; 1493 1494 // FIXME: C calling convention requires the return type to be promoted to 1495 // at least 32-bit. But this is not necessary for non-C calling 1496 // conventions. The frontend should mark functions whose return values 1497 // require promoting with signext or zeroext attributes. 1498 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) { 1499 MVT MinVT = TLI.getRegisterType(ReturnType->getContext(), MVT::i32); 1500 if (VT.bitsLT(MinVT)) 1501 VT = MinVT; 1502 } 1503 1504 unsigned NumParts = TLI.getNumRegisters(ReturnType->getContext(), VT); 1505 MVT PartVT = TLI.getRegisterType(ReturnType->getContext(), VT); 1506 1507 // 'inreg' on function refers to return value 1508 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy(); 1509 if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::InReg)) 1510 Flags.setInReg(); 1511 1512 // Propagate extension type if any 1513 if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::SExt)) 1514 Flags.setSExt(); 1515 else if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::ZExt)) 1516 Flags.setZExt(); 1517 1518 for (unsigned i = 0; i < NumParts; ++i) 1519 Outs.push_back(ISD::OutputArg(Flags, PartVT, VT, /*isFixed=*/true, 0, 0)); 1520 } 1521 } 1522 1523 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 1524 /// function arguments in the caller parameter area. This is the actual 1525 /// alignment, not its logarithm. 1526 unsigned TargetLoweringBase::getByValTypeAlignment(Type *Ty) const { 1527 return getDataLayout()->getABITypeAlignment(Ty); 1528 } 1529 1530 //===----------------------------------------------------------------------===// 1531 // TargetTransformInfo Helpers 1532 //===----------------------------------------------------------------------===// 1533 1534 int TargetLoweringBase::InstructionOpcodeToISD(unsigned Opcode) const { 1535 enum InstructionOpcodes { 1536 #define HANDLE_INST(NUM, OPCODE, CLASS) OPCODE = NUM, 1537 #define LAST_OTHER_INST(NUM) InstructionOpcodesCount = NUM 1538 #include "llvm/IR/Instruction.def" 1539 }; 1540 switch (static_cast<InstructionOpcodes>(Opcode)) { 1541 case Ret: return 0; 1542 case Br: return 0; 1543 case Switch: return 0; 1544 case IndirectBr: return 0; 1545 case Invoke: return 0; 1546 case Resume: return 0; 1547 case Unreachable: return 0; 1548 case Add: return ISD::ADD; 1549 case FAdd: return ISD::FADD; 1550 case Sub: return ISD::SUB; 1551 case FSub: return ISD::FSUB; 1552 case Mul: return ISD::MUL; 1553 case FMul: return ISD::FMUL; 1554 case UDiv: return ISD::UDIV; 1555 case SDiv: return ISD::SDIV; 1556 case FDiv: return ISD::FDIV; 1557 case URem: return ISD::UREM; 1558 case SRem: return ISD::SREM; 1559 case FRem: return ISD::FREM; 1560 case Shl: return ISD::SHL; 1561 case LShr: return ISD::SRL; 1562 case AShr: return ISD::SRA; 1563 case And: return ISD::AND; 1564 case Or: return ISD::OR; 1565 case Xor: return ISD::XOR; 1566 case Alloca: return 0; 1567 case Load: return ISD::LOAD; 1568 case Store: return ISD::STORE; 1569 case GetElementPtr: return 0; 1570 case Fence: return 0; 1571 case AtomicCmpXchg: return 0; 1572 case AtomicRMW: return 0; 1573 case Trunc: return ISD::TRUNCATE; 1574 case ZExt: return ISD::ZERO_EXTEND; 1575 case SExt: return ISD::SIGN_EXTEND; 1576 case FPToUI: return ISD::FP_TO_UINT; 1577 case FPToSI: return ISD::FP_TO_SINT; 1578 case UIToFP: return ISD::UINT_TO_FP; 1579 case SIToFP: return ISD::SINT_TO_FP; 1580 case FPTrunc: return ISD::FP_ROUND; 1581 case FPExt: return ISD::FP_EXTEND; 1582 case PtrToInt: return ISD::BITCAST; 1583 case IntToPtr: return ISD::BITCAST; 1584 case BitCast: return ISD::BITCAST; 1585 case AddrSpaceCast: return ISD::ADDRSPACECAST; 1586 case ICmp: return ISD::SETCC; 1587 case FCmp: return ISD::SETCC; 1588 case PHI: return 0; 1589 case Call: return 0; 1590 case Select: return ISD::SELECT; 1591 case UserOp1: return 0; 1592 case UserOp2: return 0; 1593 case VAArg: return 0; 1594 case ExtractElement: return ISD::EXTRACT_VECTOR_ELT; 1595 case InsertElement: return ISD::INSERT_VECTOR_ELT; 1596 case ShuffleVector: return ISD::VECTOR_SHUFFLE; 1597 case ExtractValue: return ISD::MERGE_VALUES; 1598 case InsertValue: return ISD::MERGE_VALUES; 1599 case LandingPad: return 0; 1600 } 1601 1602 llvm_unreachable("Unknown instruction type encountered!"); 1603 } 1604 1605 std::pair<unsigned, MVT> 1606 TargetLoweringBase::getTypeLegalizationCost(Type *Ty) const { 1607 LLVMContext &C = Ty->getContext(); 1608 EVT MTy = getValueType(Ty); 1609 1610 unsigned Cost = 1; 1611 // We keep legalizing the type until we find a legal kind. We assume that 1612 // the only operation that costs anything is the split. After splitting 1613 // we need to handle two types. 1614 while (true) { 1615 LegalizeKind LK = getTypeConversion(C, MTy); 1616 1617 if (LK.first == TypeLegal) 1618 return std::make_pair(Cost, MTy.getSimpleVT()); 1619 1620 if (LK.first == TypeSplitVector || LK.first == TypeExpandInteger) 1621 Cost *= 2; 1622 1623 // Keep legalizing the type. 1624 MTy = LK.second; 1625 } 1626 } 1627 1628 //===----------------------------------------------------------------------===// 1629 // Loop Strength Reduction hooks 1630 //===----------------------------------------------------------------------===// 1631 1632 /// isLegalAddressingMode - Return true if the addressing mode represented 1633 /// by AM is legal for this target, for a load/store of the specified type. 1634 bool TargetLoweringBase::isLegalAddressingMode(const AddrMode &AM, 1635 Type *Ty) const { 1636 // The default implementation of this implements a conservative RISCy, r+r and 1637 // r+i addr mode. 1638 1639 // Allows a sign-extended 16-bit immediate field. 1640 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1) 1641 return false; 1642 1643 // No global is ever allowed as a base. 1644 if (AM.BaseGV) 1645 return false; 1646 1647 // Only support r+r, 1648 switch (AM.Scale) { 1649 case 0: // "r+i" or just "i", depending on HasBaseReg. 1650 break; 1651 case 1: 1652 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. 1653 return false; 1654 // Otherwise we have r+r or r+i. 1655 break; 1656 case 2: 1657 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. 1658 return false; 1659 // Allow 2*r as r+r. 1660 break; 1661 default: // Don't allow n * r 1662 return false; 1663 } 1664 1665 return true; 1666 } 1667