1 //===- TargetLoweringBase.cpp - Implement the TargetLoweringBase class ----===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This implements the TargetLoweringBase class. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "llvm/ADT/BitVector.h" 14 #include "llvm/ADT/STLExtras.h" 15 #include "llvm/ADT/SmallVector.h" 16 #include "llvm/ADT/StringExtras.h" 17 #include "llvm/ADT/StringRef.h" 18 #include "llvm/ADT/Triple.h" 19 #include "llvm/ADT/Twine.h" 20 #include "llvm/Analysis/Loads.h" 21 #include "llvm/Analysis/TargetTransformInfo.h" 22 #include "llvm/CodeGen/Analysis.h" 23 #include "llvm/CodeGen/ISDOpcodes.h" 24 #include "llvm/CodeGen/MachineBasicBlock.h" 25 #include "llvm/CodeGen/MachineFrameInfo.h" 26 #include "llvm/CodeGen/MachineFunction.h" 27 #include "llvm/CodeGen/MachineInstr.h" 28 #include "llvm/CodeGen/MachineInstrBuilder.h" 29 #include "llvm/CodeGen/MachineMemOperand.h" 30 #include "llvm/CodeGen/MachineOperand.h" 31 #include "llvm/CodeGen/MachineRegisterInfo.h" 32 #include "llvm/CodeGen/RuntimeLibcalls.h" 33 #include "llvm/CodeGen/StackMaps.h" 34 #include "llvm/CodeGen/TargetLowering.h" 35 #include "llvm/CodeGen/TargetOpcodes.h" 36 #include "llvm/CodeGen/TargetRegisterInfo.h" 37 #include "llvm/CodeGen/ValueTypes.h" 38 #include "llvm/IR/Attributes.h" 39 #include "llvm/IR/CallingConv.h" 40 #include "llvm/IR/DataLayout.h" 41 #include "llvm/IR/DerivedTypes.h" 42 #include "llvm/IR/Function.h" 43 #include "llvm/IR/GlobalValue.h" 44 #include "llvm/IR/GlobalVariable.h" 45 #include "llvm/IR/IRBuilder.h" 46 #include "llvm/IR/Module.h" 47 #include "llvm/IR/Type.h" 48 #include "llvm/Support/BranchProbability.h" 49 #include "llvm/Support/Casting.h" 50 #include "llvm/Support/CommandLine.h" 51 #include "llvm/Support/Compiler.h" 52 #include "llvm/Support/ErrorHandling.h" 53 #include "llvm/Support/MachineValueType.h" 54 #include "llvm/Support/MathExtras.h" 55 #include "llvm/Target/TargetMachine.h" 56 #include "llvm/Transforms/Utils/SizeOpts.h" 57 #include <algorithm> 58 #include <cassert> 59 #include <cstddef> 60 #include <cstdint> 61 #include <cstring> 62 #include <iterator> 63 #include <string> 64 #include <tuple> 65 #include <utility> 66 67 using namespace llvm; 68 69 static cl::opt<bool> JumpIsExpensiveOverride( 70 "jump-is-expensive", cl::init(false), 71 cl::desc("Do not create extra branches to split comparison logic."), 72 cl::Hidden); 73 74 static cl::opt<unsigned> MinimumJumpTableEntries 75 ("min-jump-table-entries", cl::init(4), cl::Hidden, 76 cl::desc("Set minimum number of entries to use a jump table.")); 77 78 static cl::opt<unsigned> MaximumJumpTableSize 79 ("max-jump-table-size", cl::init(UINT_MAX), cl::Hidden, 80 cl::desc("Set maximum size of jump tables.")); 81 82 /// Minimum jump table density for normal functions. 83 static cl::opt<unsigned> 84 JumpTableDensity("jump-table-density", cl::init(10), cl::Hidden, 85 cl::desc("Minimum density for building a jump table in " 86 "a normal function")); 87 88 /// Minimum jump table density for -Os or -Oz functions. 89 static cl::opt<unsigned> OptsizeJumpTableDensity( 90 "optsize-jump-table-density", cl::init(40), cl::Hidden, 91 cl::desc("Minimum density for building a jump table in " 92 "an optsize function")); 93 94 // FIXME: This option is only to test if the strict fp operation processed 95 // correctly by preventing mutating strict fp operation to normal fp operation 96 // during development. When the backend supports strict float operation, this 97 // option will be meaningless. 98 static cl::opt<bool> DisableStrictNodeMutation("disable-strictnode-mutation", 99 cl::desc("Don't mutate strict-float node to a legalize node"), 100 cl::init(false), cl::Hidden); 101 102 static bool darwinHasSinCos(const Triple &TT) { 103 assert(TT.isOSDarwin() && "should be called with darwin triple"); 104 // Don't bother with 32 bit x86. 105 if (TT.getArch() == Triple::x86) 106 return false; 107 // Macos < 10.9 has no sincos_stret. 108 if (TT.isMacOSX()) 109 return !TT.isMacOSXVersionLT(10, 9) && TT.isArch64Bit(); 110 // iOS < 7.0 has no sincos_stret. 111 if (TT.isiOS()) 112 return !TT.isOSVersionLT(7, 0); 113 // Any other darwin such as WatchOS/TvOS is new enough. 114 return true; 115 } 116 117 // Although this default value is arbitrary, it is not random. It is assumed 118 // that a condition that evaluates the same way by a higher percentage than this 119 // is best represented as control flow. Therefore, the default value N should be 120 // set such that the win from N% correct executions is greater than the loss 121 // from (100 - N)% mispredicted executions for the majority of intended targets. 122 static cl::opt<int> MinPercentageForPredictableBranch( 123 "min-predictable-branch", cl::init(99), 124 cl::desc("Minimum percentage (0-100) that a condition must be either true " 125 "or false to assume that the condition is predictable"), 126 cl::Hidden); 127 128 void TargetLoweringBase::InitLibcalls(const Triple &TT) { 129 #define HANDLE_LIBCALL(code, name) \ 130 setLibcallName(RTLIB::code, name); 131 #include "llvm/IR/RuntimeLibcalls.def" 132 #undef HANDLE_LIBCALL 133 // Initialize calling conventions to their default. 134 for (int LC = 0; LC < RTLIB::UNKNOWN_LIBCALL; ++LC) 135 setLibcallCallingConv((RTLIB::Libcall)LC, CallingConv::C); 136 137 // For IEEE quad-precision libcall names, PPC uses "kf" instead of "tf". 138 if (TT.getArch() == Triple::ppc || TT.isPPC64()) { 139 setLibcallName(RTLIB::ADD_F128, "__addkf3"); 140 setLibcallName(RTLIB::SUB_F128, "__subkf3"); 141 setLibcallName(RTLIB::MUL_F128, "__mulkf3"); 142 setLibcallName(RTLIB::DIV_F128, "__divkf3"); 143 setLibcallName(RTLIB::FPEXT_F32_F128, "__extendsfkf2"); 144 setLibcallName(RTLIB::FPEXT_F64_F128, "__extenddfkf2"); 145 setLibcallName(RTLIB::FPROUND_F128_F32, "__trunckfsf2"); 146 setLibcallName(RTLIB::FPROUND_F128_F64, "__trunckfdf2"); 147 setLibcallName(RTLIB::FPTOSINT_F128_I32, "__fixkfsi"); 148 setLibcallName(RTLIB::FPTOSINT_F128_I64, "__fixkfdi"); 149 setLibcallName(RTLIB::FPTOUINT_F128_I32, "__fixunskfsi"); 150 setLibcallName(RTLIB::FPTOUINT_F128_I64, "__fixunskfdi"); 151 setLibcallName(RTLIB::SINTTOFP_I32_F128, "__floatsikf"); 152 setLibcallName(RTLIB::SINTTOFP_I64_F128, "__floatdikf"); 153 setLibcallName(RTLIB::UINTTOFP_I32_F128, "__floatunsikf"); 154 setLibcallName(RTLIB::UINTTOFP_I64_F128, "__floatundikf"); 155 setLibcallName(RTLIB::OEQ_F128, "__eqkf2"); 156 setLibcallName(RTLIB::UNE_F128, "__nekf2"); 157 setLibcallName(RTLIB::OGE_F128, "__gekf2"); 158 setLibcallName(RTLIB::OLT_F128, "__ltkf2"); 159 setLibcallName(RTLIB::OLE_F128, "__lekf2"); 160 setLibcallName(RTLIB::OGT_F128, "__gtkf2"); 161 setLibcallName(RTLIB::UO_F128, "__unordkf2"); 162 } 163 164 // A few names are different on particular architectures or environments. 165 if (TT.isOSDarwin()) { 166 // For f16/f32 conversions, Darwin uses the standard naming scheme, instead 167 // of the gnueabi-style __gnu_*_ieee. 168 // FIXME: What about other targets? 169 setLibcallName(RTLIB::FPEXT_F16_F32, "__extendhfsf2"); 170 setLibcallName(RTLIB::FPROUND_F32_F16, "__truncsfhf2"); 171 172 // Some darwins have an optimized __bzero/bzero function. 173 switch (TT.getArch()) { 174 case Triple::x86: 175 case Triple::x86_64: 176 if (TT.isMacOSX() && !TT.isMacOSXVersionLT(10, 6)) 177 setLibcallName(RTLIB::BZERO, "__bzero"); 178 break; 179 case Triple::aarch64: 180 case Triple::aarch64_32: 181 setLibcallName(RTLIB::BZERO, "bzero"); 182 break; 183 default: 184 break; 185 } 186 187 if (darwinHasSinCos(TT)) { 188 setLibcallName(RTLIB::SINCOS_STRET_F32, "__sincosf_stret"); 189 setLibcallName(RTLIB::SINCOS_STRET_F64, "__sincos_stret"); 190 if (TT.isWatchABI()) { 191 setLibcallCallingConv(RTLIB::SINCOS_STRET_F32, 192 CallingConv::ARM_AAPCS_VFP); 193 setLibcallCallingConv(RTLIB::SINCOS_STRET_F64, 194 CallingConv::ARM_AAPCS_VFP); 195 } 196 } 197 } else { 198 setLibcallName(RTLIB::FPEXT_F16_F32, "__gnu_h2f_ieee"); 199 setLibcallName(RTLIB::FPROUND_F32_F16, "__gnu_f2h_ieee"); 200 } 201 202 if (TT.isGNUEnvironment() || TT.isOSFuchsia() || 203 (TT.isAndroid() && !TT.isAndroidVersionLT(9))) { 204 setLibcallName(RTLIB::SINCOS_F32, "sincosf"); 205 setLibcallName(RTLIB::SINCOS_F64, "sincos"); 206 setLibcallName(RTLIB::SINCOS_F80, "sincosl"); 207 setLibcallName(RTLIB::SINCOS_F128, "sincosl"); 208 setLibcallName(RTLIB::SINCOS_PPCF128, "sincosl"); 209 } 210 211 if (TT.isPS4CPU()) { 212 setLibcallName(RTLIB::SINCOS_F32, "sincosf"); 213 setLibcallName(RTLIB::SINCOS_F64, "sincos"); 214 } 215 216 if (TT.isOSOpenBSD()) { 217 setLibcallName(RTLIB::STACKPROTECTOR_CHECK_FAIL, nullptr); 218 } 219 } 220 221 /// getFPEXT - Return the FPEXT_*_* value for the given types, or 222 /// UNKNOWN_LIBCALL if there is none. 223 RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) { 224 if (OpVT == MVT::f16) { 225 if (RetVT == MVT::f32) 226 return FPEXT_F16_F32; 227 } else if (OpVT == MVT::f32) { 228 if (RetVT == MVT::f64) 229 return FPEXT_F32_F64; 230 if (RetVT == MVT::f128) 231 return FPEXT_F32_F128; 232 if (RetVT == MVT::ppcf128) 233 return FPEXT_F32_PPCF128; 234 } else if (OpVT == MVT::f64) { 235 if (RetVT == MVT::f128) 236 return FPEXT_F64_F128; 237 else if (RetVT == MVT::ppcf128) 238 return FPEXT_F64_PPCF128; 239 } else if (OpVT == MVT::f80) { 240 if (RetVT == MVT::f128) 241 return FPEXT_F80_F128; 242 } 243 244 return UNKNOWN_LIBCALL; 245 } 246 247 /// getFPROUND - Return the FPROUND_*_* value for the given types, or 248 /// UNKNOWN_LIBCALL if there is none. 249 RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) { 250 if (RetVT == MVT::f16) { 251 if (OpVT == MVT::f32) 252 return FPROUND_F32_F16; 253 if (OpVT == MVT::f64) 254 return FPROUND_F64_F16; 255 if (OpVT == MVT::f80) 256 return FPROUND_F80_F16; 257 if (OpVT == MVT::f128) 258 return FPROUND_F128_F16; 259 if (OpVT == MVT::ppcf128) 260 return FPROUND_PPCF128_F16; 261 } else if (RetVT == MVT::f32) { 262 if (OpVT == MVT::f64) 263 return FPROUND_F64_F32; 264 if (OpVT == MVT::f80) 265 return FPROUND_F80_F32; 266 if (OpVT == MVT::f128) 267 return FPROUND_F128_F32; 268 if (OpVT == MVT::ppcf128) 269 return FPROUND_PPCF128_F32; 270 } else if (RetVT == MVT::f64) { 271 if (OpVT == MVT::f80) 272 return FPROUND_F80_F64; 273 if (OpVT == MVT::f128) 274 return FPROUND_F128_F64; 275 if (OpVT == MVT::ppcf128) 276 return FPROUND_PPCF128_F64; 277 } else if (RetVT == MVT::f80) { 278 if (OpVT == MVT::f128) 279 return FPROUND_F128_F80; 280 } 281 282 return UNKNOWN_LIBCALL; 283 } 284 285 /// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or 286 /// UNKNOWN_LIBCALL if there is none. 287 RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT, EVT RetVT) { 288 if (OpVT == MVT::f32) { 289 if (RetVT == MVT::i32) 290 return FPTOSINT_F32_I32; 291 if (RetVT == MVT::i64) 292 return FPTOSINT_F32_I64; 293 if (RetVT == MVT::i128) 294 return FPTOSINT_F32_I128; 295 } else if (OpVT == MVT::f64) { 296 if (RetVT == MVT::i32) 297 return FPTOSINT_F64_I32; 298 if (RetVT == MVT::i64) 299 return FPTOSINT_F64_I64; 300 if (RetVT == MVT::i128) 301 return FPTOSINT_F64_I128; 302 } else if (OpVT == MVT::f80) { 303 if (RetVT == MVT::i32) 304 return FPTOSINT_F80_I32; 305 if (RetVT == MVT::i64) 306 return FPTOSINT_F80_I64; 307 if (RetVT == MVT::i128) 308 return FPTOSINT_F80_I128; 309 } else if (OpVT == MVT::f128) { 310 if (RetVT == MVT::i32) 311 return FPTOSINT_F128_I32; 312 if (RetVT == MVT::i64) 313 return FPTOSINT_F128_I64; 314 if (RetVT == MVT::i128) 315 return FPTOSINT_F128_I128; 316 } else if (OpVT == MVT::ppcf128) { 317 if (RetVT == MVT::i32) 318 return FPTOSINT_PPCF128_I32; 319 if (RetVT == MVT::i64) 320 return FPTOSINT_PPCF128_I64; 321 if (RetVT == MVT::i128) 322 return FPTOSINT_PPCF128_I128; 323 } 324 return UNKNOWN_LIBCALL; 325 } 326 327 /// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or 328 /// UNKNOWN_LIBCALL if there is none. 329 RTLIB::Libcall RTLIB::getFPTOUINT(EVT OpVT, EVT RetVT) { 330 if (OpVT == MVT::f32) { 331 if (RetVT == MVT::i32) 332 return FPTOUINT_F32_I32; 333 if (RetVT == MVT::i64) 334 return FPTOUINT_F32_I64; 335 if (RetVT == MVT::i128) 336 return FPTOUINT_F32_I128; 337 } else if (OpVT == MVT::f64) { 338 if (RetVT == MVT::i32) 339 return FPTOUINT_F64_I32; 340 if (RetVT == MVT::i64) 341 return FPTOUINT_F64_I64; 342 if (RetVT == MVT::i128) 343 return FPTOUINT_F64_I128; 344 } else if (OpVT == MVT::f80) { 345 if (RetVT == MVT::i32) 346 return FPTOUINT_F80_I32; 347 if (RetVT == MVT::i64) 348 return FPTOUINT_F80_I64; 349 if (RetVT == MVT::i128) 350 return FPTOUINT_F80_I128; 351 } else if (OpVT == MVT::f128) { 352 if (RetVT == MVT::i32) 353 return FPTOUINT_F128_I32; 354 if (RetVT == MVT::i64) 355 return FPTOUINT_F128_I64; 356 if (RetVT == MVT::i128) 357 return FPTOUINT_F128_I128; 358 } else if (OpVT == MVT::ppcf128) { 359 if (RetVT == MVT::i32) 360 return FPTOUINT_PPCF128_I32; 361 if (RetVT == MVT::i64) 362 return FPTOUINT_PPCF128_I64; 363 if (RetVT == MVT::i128) 364 return FPTOUINT_PPCF128_I128; 365 } 366 return UNKNOWN_LIBCALL; 367 } 368 369 /// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or 370 /// UNKNOWN_LIBCALL if there is none. 371 RTLIB::Libcall RTLIB::getSINTTOFP(EVT OpVT, EVT RetVT) { 372 if (OpVT == MVT::i32) { 373 if (RetVT == MVT::f32) 374 return SINTTOFP_I32_F32; 375 if (RetVT == MVT::f64) 376 return SINTTOFP_I32_F64; 377 if (RetVT == MVT::f80) 378 return SINTTOFP_I32_F80; 379 if (RetVT == MVT::f128) 380 return SINTTOFP_I32_F128; 381 if (RetVT == MVT::ppcf128) 382 return SINTTOFP_I32_PPCF128; 383 } else if (OpVT == MVT::i64) { 384 if (RetVT == MVT::f32) 385 return SINTTOFP_I64_F32; 386 if (RetVT == MVT::f64) 387 return SINTTOFP_I64_F64; 388 if (RetVT == MVT::f80) 389 return SINTTOFP_I64_F80; 390 if (RetVT == MVT::f128) 391 return SINTTOFP_I64_F128; 392 if (RetVT == MVT::ppcf128) 393 return SINTTOFP_I64_PPCF128; 394 } else if (OpVT == MVT::i128) { 395 if (RetVT == MVT::f32) 396 return SINTTOFP_I128_F32; 397 if (RetVT == MVT::f64) 398 return SINTTOFP_I128_F64; 399 if (RetVT == MVT::f80) 400 return SINTTOFP_I128_F80; 401 if (RetVT == MVT::f128) 402 return SINTTOFP_I128_F128; 403 if (RetVT == MVT::ppcf128) 404 return SINTTOFP_I128_PPCF128; 405 } 406 return UNKNOWN_LIBCALL; 407 } 408 409 /// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or 410 /// UNKNOWN_LIBCALL if there is none. 411 RTLIB::Libcall RTLIB::getUINTTOFP(EVT OpVT, EVT RetVT) { 412 if (OpVT == MVT::i32) { 413 if (RetVT == MVT::f32) 414 return UINTTOFP_I32_F32; 415 if (RetVT == MVT::f64) 416 return UINTTOFP_I32_F64; 417 if (RetVT == MVT::f80) 418 return UINTTOFP_I32_F80; 419 if (RetVT == MVT::f128) 420 return UINTTOFP_I32_F128; 421 if (RetVT == MVT::ppcf128) 422 return UINTTOFP_I32_PPCF128; 423 } else if (OpVT == MVT::i64) { 424 if (RetVT == MVT::f32) 425 return UINTTOFP_I64_F32; 426 if (RetVT == MVT::f64) 427 return UINTTOFP_I64_F64; 428 if (RetVT == MVT::f80) 429 return UINTTOFP_I64_F80; 430 if (RetVT == MVT::f128) 431 return UINTTOFP_I64_F128; 432 if (RetVT == MVT::ppcf128) 433 return UINTTOFP_I64_PPCF128; 434 } else if (OpVT == MVT::i128) { 435 if (RetVT == MVT::f32) 436 return UINTTOFP_I128_F32; 437 if (RetVT == MVT::f64) 438 return UINTTOFP_I128_F64; 439 if (RetVT == MVT::f80) 440 return UINTTOFP_I128_F80; 441 if (RetVT == MVT::f128) 442 return UINTTOFP_I128_F128; 443 if (RetVT == MVT::ppcf128) 444 return UINTTOFP_I128_PPCF128; 445 } 446 return UNKNOWN_LIBCALL; 447 } 448 449 RTLIB::Libcall RTLIB::getSYNC(unsigned Opc, MVT VT) { 450 #define OP_TO_LIBCALL(Name, Enum) \ 451 case Name: \ 452 switch (VT.SimpleTy) { \ 453 default: \ 454 return UNKNOWN_LIBCALL; \ 455 case MVT::i8: \ 456 return Enum##_1; \ 457 case MVT::i16: \ 458 return Enum##_2; \ 459 case MVT::i32: \ 460 return Enum##_4; \ 461 case MVT::i64: \ 462 return Enum##_8; \ 463 case MVT::i128: \ 464 return Enum##_16; \ 465 } 466 467 switch (Opc) { 468 OP_TO_LIBCALL(ISD::ATOMIC_SWAP, SYNC_LOCK_TEST_AND_SET) 469 OP_TO_LIBCALL(ISD::ATOMIC_CMP_SWAP, SYNC_VAL_COMPARE_AND_SWAP) 470 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_ADD, SYNC_FETCH_AND_ADD) 471 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_SUB, SYNC_FETCH_AND_SUB) 472 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_AND, SYNC_FETCH_AND_AND) 473 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_OR, SYNC_FETCH_AND_OR) 474 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_XOR, SYNC_FETCH_AND_XOR) 475 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_NAND, SYNC_FETCH_AND_NAND) 476 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_MAX, SYNC_FETCH_AND_MAX) 477 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_UMAX, SYNC_FETCH_AND_UMAX) 478 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_MIN, SYNC_FETCH_AND_MIN) 479 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_UMIN, SYNC_FETCH_AND_UMIN) 480 } 481 482 #undef OP_TO_LIBCALL 483 484 return UNKNOWN_LIBCALL; 485 } 486 487 RTLIB::Libcall RTLIB::getMEMCPY_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize) { 488 switch (ElementSize) { 489 case 1: 490 return MEMCPY_ELEMENT_UNORDERED_ATOMIC_1; 491 case 2: 492 return MEMCPY_ELEMENT_UNORDERED_ATOMIC_2; 493 case 4: 494 return MEMCPY_ELEMENT_UNORDERED_ATOMIC_4; 495 case 8: 496 return MEMCPY_ELEMENT_UNORDERED_ATOMIC_8; 497 case 16: 498 return MEMCPY_ELEMENT_UNORDERED_ATOMIC_16; 499 default: 500 return UNKNOWN_LIBCALL; 501 } 502 } 503 504 RTLIB::Libcall RTLIB::getMEMMOVE_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize) { 505 switch (ElementSize) { 506 case 1: 507 return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_1; 508 case 2: 509 return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_2; 510 case 4: 511 return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_4; 512 case 8: 513 return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_8; 514 case 16: 515 return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_16; 516 default: 517 return UNKNOWN_LIBCALL; 518 } 519 } 520 521 RTLIB::Libcall RTLIB::getMEMSET_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize) { 522 switch (ElementSize) { 523 case 1: 524 return MEMSET_ELEMENT_UNORDERED_ATOMIC_1; 525 case 2: 526 return MEMSET_ELEMENT_UNORDERED_ATOMIC_2; 527 case 4: 528 return MEMSET_ELEMENT_UNORDERED_ATOMIC_4; 529 case 8: 530 return MEMSET_ELEMENT_UNORDERED_ATOMIC_8; 531 case 16: 532 return MEMSET_ELEMENT_UNORDERED_ATOMIC_16; 533 default: 534 return UNKNOWN_LIBCALL; 535 } 536 } 537 538 /// InitCmpLibcallCCs - Set default comparison libcall CC. 539 static void InitCmpLibcallCCs(ISD::CondCode *CCs) { 540 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL); 541 CCs[RTLIB::OEQ_F32] = ISD::SETEQ; 542 CCs[RTLIB::OEQ_F64] = ISD::SETEQ; 543 CCs[RTLIB::OEQ_F128] = ISD::SETEQ; 544 CCs[RTLIB::OEQ_PPCF128] = ISD::SETEQ; 545 CCs[RTLIB::UNE_F32] = ISD::SETNE; 546 CCs[RTLIB::UNE_F64] = ISD::SETNE; 547 CCs[RTLIB::UNE_F128] = ISD::SETNE; 548 CCs[RTLIB::UNE_PPCF128] = ISD::SETNE; 549 CCs[RTLIB::OGE_F32] = ISD::SETGE; 550 CCs[RTLIB::OGE_F64] = ISD::SETGE; 551 CCs[RTLIB::OGE_F128] = ISD::SETGE; 552 CCs[RTLIB::OGE_PPCF128] = ISD::SETGE; 553 CCs[RTLIB::OLT_F32] = ISD::SETLT; 554 CCs[RTLIB::OLT_F64] = ISD::SETLT; 555 CCs[RTLIB::OLT_F128] = ISD::SETLT; 556 CCs[RTLIB::OLT_PPCF128] = ISD::SETLT; 557 CCs[RTLIB::OLE_F32] = ISD::SETLE; 558 CCs[RTLIB::OLE_F64] = ISD::SETLE; 559 CCs[RTLIB::OLE_F128] = ISD::SETLE; 560 CCs[RTLIB::OLE_PPCF128] = ISD::SETLE; 561 CCs[RTLIB::OGT_F32] = ISD::SETGT; 562 CCs[RTLIB::OGT_F64] = ISD::SETGT; 563 CCs[RTLIB::OGT_F128] = ISD::SETGT; 564 CCs[RTLIB::OGT_PPCF128] = ISD::SETGT; 565 CCs[RTLIB::UO_F32] = ISD::SETNE; 566 CCs[RTLIB::UO_F64] = ISD::SETNE; 567 CCs[RTLIB::UO_F128] = ISD::SETNE; 568 CCs[RTLIB::UO_PPCF128] = ISD::SETNE; 569 } 570 571 /// NOTE: The TargetMachine owns TLOF. 572 TargetLoweringBase::TargetLoweringBase(const TargetMachine &tm) : TM(tm) { 573 initActions(); 574 575 // Perform these initializations only once. 576 MaxStoresPerMemset = MaxStoresPerMemcpy = MaxStoresPerMemmove = 577 MaxLoadsPerMemcmp = 8; 578 MaxGluedStoresPerMemcpy = 0; 579 MaxStoresPerMemsetOptSize = MaxStoresPerMemcpyOptSize = 580 MaxStoresPerMemmoveOptSize = MaxLoadsPerMemcmpOptSize = 4; 581 HasMultipleConditionRegisters = false; 582 HasExtractBitsInsn = false; 583 JumpIsExpensive = JumpIsExpensiveOverride; 584 PredictableSelectIsExpensive = false; 585 EnableExtLdPromotion = false; 586 StackPointerRegisterToSaveRestore = 0; 587 BooleanContents = UndefinedBooleanContent; 588 BooleanFloatContents = UndefinedBooleanContent; 589 BooleanVectorContents = UndefinedBooleanContent; 590 SchedPreferenceInfo = Sched::ILP; 591 GatherAllAliasesMaxDepth = 18; 592 IsStrictFPEnabled = DisableStrictNodeMutation; 593 // TODO: the default will be switched to 0 in the next commit, along 594 // with the Target-specific changes necessary. 595 MaxAtomicSizeInBitsSupported = 1024; 596 597 MinCmpXchgSizeInBits = 0; 598 SupportsUnalignedAtomics = false; 599 600 std::fill(std::begin(LibcallRoutineNames), std::end(LibcallRoutineNames), nullptr); 601 602 InitLibcalls(TM.getTargetTriple()); 603 InitCmpLibcallCCs(CmpLibcallCCs); 604 } 605 606 void TargetLoweringBase::initActions() { 607 // All operations default to being supported. 608 memset(OpActions, 0, sizeof(OpActions)); 609 memset(LoadExtActions, 0, sizeof(LoadExtActions)); 610 memset(TruncStoreActions, 0, sizeof(TruncStoreActions)); 611 memset(IndexedModeActions, 0, sizeof(IndexedModeActions)); 612 memset(CondCodeActions, 0, sizeof(CondCodeActions)); 613 std::fill(std::begin(RegClassForVT), std::end(RegClassForVT), nullptr); 614 std::fill(std::begin(TargetDAGCombineArray), 615 std::end(TargetDAGCombineArray), 0); 616 617 for (MVT VT : MVT::fp_valuetypes()) { 618 MVT IntVT = MVT::getIntegerVT(VT.getFixedSizeInBits()); 619 if (IntVT.isValid()) { 620 setOperationAction(ISD::ATOMIC_SWAP, VT, Promote); 621 AddPromotedToType(ISD::ATOMIC_SWAP, VT, IntVT); 622 } 623 } 624 625 // Set default actions for various operations. 626 for (MVT VT : MVT::all_valuetypes()) { 627 // Default all indexed load / store to expand. 628 for (unsigned IM = (unsigned)ISD::PRE_INC; 629 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) { 630 setIndexedLoadAction(IM, VT, Expand); 631 setIndexedStoreAction(IM, VT, Expand); 632 setIndexedMaskedLoadAction(IM, VT, Expand); 633 setIndexedMaskedStoreAction(IM, VT, Expand); 634 } 635 636 // Most backends expect to see the node which just returns the value loaded. 637 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Expand); 638 639 // These operations default to expand. 640 setOperationAction(ISD::FGETSIGN, VT, Expand); 641 setOperationAction(ISD::CONCAT_VECTORS, VT, Expand); 642 setOperationAction(ISD::FMINNUM, VT, Expand); 643 setOperationAction(ISD::FMAXNUM, VT, Expand); 644 setOperationAction(ISD::FMINNUM_IEEE, VT, Expand); 645 setOperationAction(ISD::FMAXNUM_IEEE, VT, Expand); 646 setOperationAction(ISD::FMINIMUM, VT, Expand); 647 setOperationAction(ISD::FMAXIMUM, VT, Expand); 648 setOperationAction(ISD::FMAD, VT, Expand); 649 setOperationAction(ISD::SMIN, VT, Expand); 650 setOperationAction(ISD::SMAX, VT, Expand); 651 setOperationAction(ISD::UMIN, VT, Expand); 652 setOperationAction(ISD::UMAX, VT, Expand); 653 setOperationAction(ISD::ABS, VT, Expand); 654 setOperationAction(ISD::FSHL, VT, Expand); 655 setOperationAction(ISD::FSHR, VT, Expand); 656 setOperationAction(ISD::SADDSAT, VT, Expand); 657 setOperationAction(ISD::UADDSAT, VT, Expand); 658 setOperationAction(ISD::SSUBSAT, VT, Expand); 659 setOperationAction(ISD::USUBSAT, VT, Expand); 660 setOperationAction(ISD::SSHLSAT, VT, Expand); 661 setOperationAction(ISD::USHLSAT, VT, Expand); 662 setOperationAction(ISD::SMULFIX, VT, Expand); 663 setOperationAction(ISD::SMULFIXSAT, VT, Expand); 664 setOperationAction(ISD::UMULFIX, VT, Expand); 665 setOperationAction(ISD::UMULFIXSAT, VT, Expand); 666 setOperationAction(ISD::SDIVFIX, VT, Expand); 667 setOperationAction(ISD::SDIVFIXSAT, VT, Expand); 668 setOperationAction(ISD::UDIVFIX, VT, Expand); 669 setOperationAction(ISD::UDIVFIXSAT, VT, Expand); 670 671 // Overflow operations default to expand 672 setOperationAction(ISD::SADDO, VT, Expand); 673 setOperationAction(ISD::SSUBO, VT, Expand); 674 setOperationAction(ISD::UADDO, VT, Expand); 675 setOperationAction(ISD::USUBO, VT, Expand); 676 setOperationAction(ISD::SMULO, VT, Expand); 677 setOperationAction(ISD::UMULO, VT, Expand); 678 679 // ADDCARRY operations default to expand 680 setOperationAction(ISD::ADDCARRY, VT, Expand); 681 setOperationAction(ISD::SUBCARRY, VT, Expand); 682 setOperationAction(ISD::SETCCCARRY, VT, Expand); 683 setOperationAction(ISD::SADDO_CARRY, VT, Expand); 684 setOperationAction(ISD::SSUBO_CARRY, VT, Expand); 685 686 // ADDC/ADDE/SUBC/SUBE default to expand. 687 setOperationAction(ISD::ADDC, VT, Expand); 688 setOperationAction(ISD::ADDE, VT, Expand); 689 setOperationAction(ISD::SUBC, VT, Expand); 690 setOperationAction(ISD::SUBE, VT, Expand); 691 692 // These default to Expand so they will be expanded to CTLZ/CTTZ by default. 693 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand); 694 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand); 695 696 setOperationAction(ISD::BITREVERSE, VT, Expand); 697 setOperationAction(ISD::PARITY, VT, Expand); 698 699 // These library functions default to expand. 700 setOperationAction(ISD::FROUND, VT, Expand); 701 setOperationAction(ISD::FROUNDEVEN, VT, Expand); 702 setOperationAction(ISD::FPOWI, VT, Expand); 703 704 // These operations default to expand for vector types. 705 if (VT.isVector()) { 706 setOperationAction(ISD::FCOPYSIGN, VT, Expand); 707 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand); 708 setOperationAction(ISD::ANY_EXTEND_VECTOR_INREG, VT, Expand); 709 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, VT, Expand); 710 setOperationAction(ISD::ZERO_EXTEND_VECTOR_INREG, VT, Expand); 711 setOperationAction(ISD::SPLAT_VECTOR, VT, Expand); 712 } 713 714 // Constrained floating-point operations default to expand. 715 #define DAG_INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC, DAGN) \ 716 setOperationAction(ISD::STRICT_##DAGN, VT, Expand); 717 #include "llvm/IR/ConstrainedOps.def" 718 719 // For most targets @llvm.get.dynamic.area.offset just returns 0. 720 setOperationAction(ISD::GET_DYNAMIC_AREA_OFFSET, VT, Expand); 721 722 // Vector reduction default to expand. 723 setOperationAction(ISD::VECREDUCE_FADD, VT, Expand); 724 setOperationAction(ISD::VECREDUCE_FMUL, VT, Expand); 725 setOperationAction(ISD::VECREDUCE_ADD, VT, Expand); 726 setOperationAction(ISD::VECREDUCE_MUL, VT, Expand); 727 setOperationAction(ISD::VECREDUCE_AND, VT, Expand); 728 setOperationAction(ISD::VECREDUCE_OR, VT, Expand); 729 setOperationAction(ISD::VECREDUCE_XOR, VT, Expand); 730 setOperationAction(ISD::VECREDUCE_SMAX, VT, Expand); 731 setOperationAction(ISD::VECREDUCE_SMIN, VT, Expand); 732 setOperationAction(ISD::VECREDUCE_UMAX, VT, Expand); 733 setOperationAction(ISD::VECREDUCE_UMIN, VT, Expand); 734 setOperationAction(ISD::VECREDUCE_FMAX, VT, Expand); 735 setOperationAction(ISD::VECREDUCE_FMIN, VT, Expand); 736 setOperationAction(ISD::VECREDUCE_SEQ_FADD, VT, Expand); 737 setOperationAction(ISD::VECREDUCE_SEQ_FMUL, VT, Expand); 738 } 739 740 // Most targets ignore the @llvm.prefetch intrinsic. 741 setOperationAction(ISD::PREFETCH, MVT::Other, Expand); 742 743 // Most targets also ignore the @llvm.readcyclecounter intrinsic. 744 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Expand); 745 746 // ConstantFP nodes default to expand. Targets can either change this to 747 // Legal, in which case all fp constants are legal, or use isFPImmLegal() 748 // to optimize expansions for certain constants. 749 setOperationAction(ISD::ConstantFP, MVT::f16, Expand); 750 setOperationAction(ISD::ConstantFP, MVT::f32, Expand); 751 setOperationAction(ISD::ConstantFP, MVT::f64, Expand); 752 setOperationAction(ISD::ConstantFP, MVT::f80, Expand); 753 setOperationAction(ISD::ConstantFP, MVT::f128, Expand); 754 755 // These library functions default to expand. 756 for (MVT VT : {MVT::f32, MVT::f64, MVT::f128}) { 757 setOperationAction(ISD::FCBRT, VT, Expand); 758 setOperationAction(ISD::FLOG , VT, Expand); 759 setOperationAction(ISD::FLOG2, VT, Expand); 760 setOperationAction(ISD::FLOG10, VT, Expand); 761 setOperationAction(ISD::FEXP , VT, Expand); 762 setOperationAction(ISD::FEXP2, VT, Expand); 763 setOperationAction(ISD::FFLOOR, VT, Expand); 764 setOperationAction(ISD::FNEARBYINT, VT, Expand); 765 setOperationAction(ISD::FCEIL, VT, Expand); 766 setOperationAction(ISD::FRINT, VT, Expand); 767 setOperationAction(ISD::FTRUNC, VT, Expand); 768 setOperationAction(ISD::FROUND, VT, Expand); 769 setOperationAction(ISD::FROUNDEVEN, VT, Expand); 770 setOperationAction(ISD::LROUND, VT, Expand); 771 setOperationAction(ISD::LLROUND, VT, Expand); 772 setOperationAction(ISD::LRINT, VT, Expand); 773 setOperationAction(ISD::LLRINT, VT, Expand); 774 } 775 776 // Default ISD::TRAP to expand (which turns it into abort). 777 setOperationAction(ISD::TRAP, MVT::Other, Expand); 778 779 // On most systems, DEBUGTRAP and TRAP have no difference. The "Expand" 780 // here is to inform DAG Legalizer to replace DEBUGTRAP with TRAP. 781 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Expand); 782 } 783 784 MVT TargetLoweringBase::getScalarShiftAmountTy(const DataLayout &DL, 785 EVT) const { 786 return MVT::getIntegerVT(DL.getPointerSizeInBits(0)); 787 } 788 789 EVT TargetLoweringBase::getShiftAmountTy(EVT LHSTy, const DataLayout &DL, 790 bool LegalTypes) const { 791 assert(LHSTy.isInteger() && "Shift amount is not an integer type!"); 792 if (LHSTy.isVector()) 793 return LHSTy; 794 return LegalTypes ? getScalarShiftAmountTy(DL, LHSTy) 795 : getPointerTy(DL); 796 } 797 798 bool TargetLoweringBase::canOpTrap(unsigned Op, EVT VT) const { 799 assert(isTypeLegal(VT)); 800 switch (Op) { 801 default: 802 return false; 803 case ISD::SDIV: 804 case ISD::UDIV: 805 case ISD::SREM: 806 case ISD::UREM: 807 return true; 808 } 809 } 810 811 bool TargetLoweringBase::isFreeAddrSpaceCast(unsigned SrcAS, 812 unsigned DestAS) const { 813 return TM.isNoopAddrSpaceCast(SrcAS, DestAS); 814 } 815 816 void TargetLoweringBase::setJumpIsExpensive(bool isExpensive) { 817 // If the command-line option was specified, ignore this request. 818 if (!JumpIsExpensiveOverride.getNumOccurrences()) 819 JumpIsExpensive = isExpensive; 820 } 821 822 TargetLoweringBase::LegalizeKind 823 TargetLoweringBase::getTypeConversion(LLVMContext &Context, EVT VT) const { 824 // If this is a simple type, use the ComputeRegisterProp mechanism. 825 if (VT.isSimple()) { 826 MVT SVT = VT.getSimpleVT(); 827 assert((unsigned)SVT.SimpleTy < array_lengthof(TransformToType)); 828 MVT NVT = TransformToType[SVT.SimpleTy]; 829 LegalizeTypeAction LA = ValueTypeActions.getTypeAction(SVT); 830 831 assert((LA == TypeLegal || LA == TypeSoftenFloat || 832 LA == TypeSoftPromoteHalf || 833 (NVT.isVector() || 834 ValueTypeActions.getTypeAction(NVT) != TypePromoteInteger)) && 835 "Promote may not follow Expand or Promote"); 836 837 if (LA == TypeSplitVector) 838 return LegalizeKind(LA, EVT(SVT).getHalfNumVectorElementsVT(Context)); 839 if (LA == TypeScalarizeVector) 840 return LegalizeKind(LA, SVT.getVectorElementType()); 841 return LegalizeKind(LA, NVT); 842 } 843 844 // Handle Extended Scalar Types. 845 if (!VT.isVector()) { 846 assert(VT.isInteger() && "Float types must be simple"); 847 unsigned BitSize = VT.getSizeInBits(); 848 // First promote to a power-of-two size, then expand if necessary. 849 if (BitSize < 8 || !isPowerOf2_32(BitSize)) { 850 EVT NVT = VT.getRoundIntegerType(Context); 851 assert(NVT != VT && "Unable to round integer VT"); 852 LegalizeKind NextStep = getTypeConversion(Context, NVT); 853 // Avoid multi-step promotion. 854 if (NextStep.first == TypePromoteInteger) 855 return NextStep; 856 // Return rounded integer type. 857 return LegalizeKind(TypePromoteInteger, NVT); 858 } 859 860 return LegalizeKind(TypeExpandInteger, 861 EVT::getIntegerVT(Context, VT.getSizeInBits() / 2)); 862 } 863 864 // Handle vector types. 865 ElementCount NumElts = VT.getVectorElementCount(); 866 EVT EltVT = VT.getVectorElementType(); 867 868 // Vectors with only one element are always scalarized. 869 if (NumElts.isScalar()) 870 return LegalizeKind(TypeScalarizeVector, EltVT); 871 872 if (VT.getVectorElementCount() == ElementCount::getScalable(1)) 873 report_fatal_error("Cannot legalize this vector"); 874 875 // Try to widen vector elements until the element type is a power of two and 876 // promote it to a legal type later on, for example: 877 // <3 x i8> -> <4 x i8> -> <4 x i32> 878 if (EltVT.isInteger()) { 879 // Vectors with a number of elements that is not a power of two are always 880 // widened, for example <3 x i8> -> <4 x i8>. 881 if (!VT.isPow2VectorType()) { 882 NumElts = NumElts.coefficientNextPowerOf2(); 883 EVT NVT = EVT::getVectorVT(Context, EltVT, NumElts); 884 return LegalizeKind(TypeWidenVector, NVT); 885 } 886 887 // Examine the element type. 888 LegalizeKind LK = getTypeConversion(Context, EltVT); 889 890 // If type is to be expanded, split the vector. 891 // <4 x i140> -> <2 x i140> 892 if (LK.first == TypeExpandInteger) 893 return LegalizeKind(TypeSplitVector, 894 VT.getHalfNumVectorElementsVT(Context)); 895 896 // Promote the integer element types until a legal vector type is found 897 // or until the element integer type is too big. If a legal type was not 898 // found, fallback to the usual mechanism of widening/splitting the 899 // vector. 900 EVT OldEltVT = EltVT; 901 while (true) { 902 // Increase the bitwidth of the element to the next pow-of-two 903 // (which is greater than 8 bits). 904 EltVT = EVT::getIntegerVT(Context, 1 + EltVT.getSizeInBits()) 905 .getRoundIntegerType(Context); 906 907 // Stop trying when getting a non-simple element type. 908 // Note that vector elements may be greater than legal vector element 909 // types. Example: X86 XMM registers hold 64bit element on 32bit 910 // systems. 911 if (!EltVT.isSimple()) 912 break; 913 914 // Build a new vector type and check if it is legal. 915 MVT NVT = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts); 916 // Found a legal promoted vector type. 917 if (NVT != MVT() && ValueTypeActions.getTypeAction(NVT) == TypeLegal) 918 return LegalizeKind(TypePromoteInteger, 919 EVT::getVectorVT(Context, EltVT, NumElts)); 920 } 921 922 // Reset the type to the unexpanded type if we did not find a legal vector 923 // type with a promoted vector element type. 924 EltVT = OldEltVT; 925 } 926 927 // Try to widen the vector until a legal type is found. 928 // If there is no wider legal type, split the vector. 929 while (true) { 930 // Round up to the next power of 2. 931 NumElts = NumElts.coefficientNextPowerOf2(); 932 933 // If there is no simple vector type with this many elements then there 934 // cannot be a larger legal vector type. Note that this assumes that 935 // there are no skipped intermediate vector types in the simple types. 936 if (!EltVT.isSimple()) 937 break; 938 MVT LargerVector = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts); 939 if (LargerVector == MVT()) 940 break; 941 942 // If this type is legal then widen the vector. 943 if (ValueTypeActions.getTypeAction(LargerVector) == TypeLegal) 944 return LegalizeKind(TypeWidenVector, LargerVector); 945 } 946 947 // Widen odd vectors to next power of two. 948 if (!VT.isPow2VectorType()) { 949 EVT NVT = VT.getPow2VectorType(Context); 950 return LegalizeKind(TypeWidenVector, NVT); 951 } 952 953 // Vectors with illegal element types are expanded. 954 EVT NVT = EVT::getVectorVT(Context, EltVT, 955 VT.getVectorElementCount().divideCoefficientBy(2)); 956 return LegalizeKind(TypeSplitVector, NVT); 957 } 958 959 static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT, 960 unsigned &NumIntermediates, 961 MVT &RegisterVT, 962 TargetLoweringBase *TLI) { 963 // Figure out the right, legal destination reg to copy into. 964 ElementCount EC = VT.getVectorElementCount(); 965 MVT EltTy = VT.getVectorElementType(); 966 967 unsigned NumVectorRegs = 1; 968 969 // Scalable vectors cannot be scalarized, so splitting or widening is 970 // required. 971 if (VT.isScalableVector() && !isPowerOf2_32(EC.getKnownMinValue())) 972 llvm_unreachable( 973 "Splitting or widening of non-power-of-2 MVTs is not implemented."); 974 975 // FIXME: We don't support non-power-of-2-sized vectors for now. 976 // Ideally we could break down into LHS/RHS like LegalizeDAG does. 977 if (!isPowerOf2_32(EC.getKnownMinValue())) { 978 // Split EC to unit size (scalable property is preserved). 979 NumVectorRegs = EC.getKnownMinValue(); 980 EC = ElementCount::getFixed(1); 981 } 982 983 // Divide the input until we get to a supported size. This will 984 // always end up with an EC that represent a scalar or a scalable 985 // scalar. 986 while (EC.getKnownMinValue() > 1 && 987 !TLI->isTypeLegal(MVT::getVectorVT(EltTy, EC))) { 988 EC = EC.divideCoefficientBy(2); 989 NumVectorRegs <<= 1; 990 } 991 992 NumIntermediates = NumVectorRegs; 993 994 MVT NewVT = MVT::getVectorVT(EltTy, EC); 995 if (!TLI->isTypeLegal(NewVT)) 996 NewVT = EltTy; 997 IntermediateVT = NewVT; 998 999 unsigned LaneSizeInBits = NewVT.getScalarSizeInBits(); 1000 1001 // Convert sizes such as i33 to i64. 1002 if (!isPowerOf2_32(LaneSizeInBits)) 1003 LaneSizeInBits = NextPowerOf2(LaneSizeInBits); 1004 1005 MVT DestVT = TLI->getRegisterType(NewVT); 1006 RegisterVT = DestVT; 1007 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16. 1008 return NumVectorRegs * (LaneSizeInBits / DestVT.getScalarSizeInBits()); 1009 1010 // Otherwise, promotion or legal types use the same number of registers as 1011 // the vector decimated to the appropriate level. 1012 return NumVectorRegs; 1013 } 1014 1015 /// isLegalRC - Return true if the value types that can be represented by the 1016 /// specified register class are all legal. 1017 bool TargetLoweringBase::isLegalRC(const TargetRegisterInfo &TRI, 1018 const TargetRegisterClass &RC) const { 1019 for (auto I = TRI.legalclasstypes_begin(RC); *I != MVT::Other; ++I) 1020 if (isTypeLegal(*I)) 1021 return true; 1022 return false; 1023 } 1024 1025 /// Replace/modify any TargetFrameIndex operands with a targte-dependent 1026 /// sequence of memory operands that is recognized by PrologEpilogInserter. 1027 MachineBasicBlock * 1028 TargetLoweringBase::emitPatchPoint(MachineInstr &InitialMI, 1029 MachineBasicBlock *MBB) const { 1030 MachineInstr *MI = &InitialMI; 1031 MachineFunction &MF = *MI->getMF(); 1032 MachineFrameInfo &MFI = MF.getFrameInfo(); 1033 1034 // We're handling multiple types of operands here: 1035 // PATCHPOINT MetaArgs - live-in, read only, direct 1036 // STATEPOINT Deopt Spill - live-through, read only, indirect 1037 // STATEPOINT Deopt Alloca - live-through, read only, direct 1038 // (We're currently conservative and mark the deopt slots read/write in 1039 // practice.) 1040 // STATEPOINT GC Spill - live-through, read/write, indirect 1041 // STATEPOINT GC Alloca - live-through, read/write, direct 1042 // The live-in vs live-through is handled already (the live through ones are 1043 // all stack slots), but we need to handle the different type of stackmap 1044 // operands and memory effects here. 1045 1046 if (!llvm::any_of(MI->operands(), 1047 [](MachineOperand &Operand) { return Operand.isFI(); })) 1048 return MBB; 1049 1050 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), MI->getDesc()); 1051 1052 // Inherit previous memory operands. 1053 MIB.cloneMemRefs(*MI); 1054 1055 for (unsigned i = 0; i < MI->getNumOperands(); ++i) { 1056 MachineOperand &MO = MI->getOperand(i); 1057 if (!MO.isFI()) { 1058 // Index of Def operand this Use it tied to. 1059 // Since Defs are coming before Uses, if Use is tied, then 1060 // index of Def must be smaller that index of that Use. 1061 // Also, Defs preserve their position in new MI. 1062 unsigned TiedTo = i; 1063 if (MO.isReg() && MO.isTied()) 1064 TiedTo = MI->findTiedOperandIdx(i); 1065 MIB.add(MO); 1066 if (TiedTo < i) 1067 MIB->tieOperands(TiedTo, MIB->getNumOperands() - 1); 1068 continue; 1069 } 1070 1071 // foldMemoryOperand builds a new MI after replacing a single FI operand 1072 // with the canonical set of five x86 addressing-mode operands. 1073 int FI = MO.getIndex(); 1074 1075 // Add frame index operands recognized by stackmaps.cpp 1076 if (MFI.isStatepointSpillSlotObjectIndex(FI)) { 1077 // indirect-mem-ref tag, size, #FI, offset. 1078 // Used for spills inserted by StatepointLowering. This codepath is not 1079 // used for patchpoints/stackmaps at all, for these spilling is done via 1080 // foldMemoryOperand callback only. 1081 assert(MI->getOpcode() == TargetOpcode::STATEPOINT && "sanity"); 1082 MIB.addImm(StackMaps::IndirectMemRefOp); 1083 MIB.addImm(MFI.getObjectSize(FI)); 1084 MIB.add(MO); 1085 MIB.addImm(0); 1086 } else { 1087 // direct-mem-ref tag, #FI, offset. 1088 // Used by patchpoint, and direct alloca arguments to statepoints 1089 MIB.addImm(StackMaps::DirectMemRefOp); 1090 MIB.add(MO); 1091 MIB.addImm(0); 1092 } 1093 1094 assert(MIB->mayLoad() && "Folded a stackmap use to a non-load!"); 1095 1096 // Add a new memory operand for this FI. 1097 assert(MFI.getObjectOffset(FI) != -1); 1098 1099 // Note: STATEPOINT MMOs are added during SelectionDAG. STACKMAP, and 1100 // PATCHPOINT should be updated to do the same. (TODO) 1101 if (MI->getOpcode() != TargetOpcode::STATEPOINT) { 1102 auto Flags = MachineMemOperand::MOLoad; 1103 MachineMemOperand *MMO = MF.getMachineMemOperand( 1104 MachinePointerInfo::getFixedStack(MF, FI), Flags, 1105 MF.getDataLayout().getPointerSize(), MFI.getObjectAlign(FI)); 1106 MIB->addMemOperand(MF, MMO); 1107 } 1108 } 1109 MBB->insert(MachineBasicBlock::iterator(MI), MIB); 1110 MI->eraseFromParent(); 1111 return MBB; 1112 } 1113 1114 MachineBasicBlock * 1115 TargetLoweringBase::emitXRayCustomEvent(MachineInstr &MI, 1116 MachineBasicBlock *MBB) const { 1117 assert(MI.getOpcode() == TargetOpcode::PATCHABLE_EVENT_CALL && 1118 "Called emitXRayCustomEvent on the wrong MI!"); 1119 auto &MF = *MI.getMF(); 1120 auto MIB = BuildMI(MF, MI.getDebugLoc(), MI.getDesc()); 1121 for (unsigned OpIdx = 0; OpIdx != MI.getNumOperands(); ++OpIdx) 1122 MIB.add(MI.getOperand(OpIdx)); 1123 1124 MBB->insert(MachineBasicBlock::iterator(MI), MIB); 1125 MI.eraseFromParent(); 1126 return MBB; 1127 } 1128 1129 MachineBasicBlock * 1130 TargetLoweringBase::emitXRayTypedEvent(MachineInstr &MI, 1131 MachineBasicBlock *MBB) const { 1132 assert(MI.getOpcode() == TargetOpcode::PATCHABLE_TYPED_EVENT_CALL && 1133 "Called emitXRayTypedEvent on the wrong MI!"); 1134 auto &MF = *MI.getMF(); 1135 auto MIB = BuildMI(MF, MI.getDebugLoc(), MI.getDesc()); 1136 for (unsigned OpIdx = 0; OpIdx != MI.getNumOperands(); ++OpIdx) 1137 MIB.add(MI.getOperand(OpIdx)); 1138 1139 MBB->insert(MachineBasicBlock::iterator(MI), MIB); 1140 MI.eraseFromParent(); 1141 return MBB; 1142 } 1143 1144 /// findRepresentativeClass - Return the largest legal super-reg register class 1145 /// of the register class for the specified type and its associated "cost". 1146 // This function is in TargetLowering because it uses RegClassForVT which would 1147 // need to be moved to TargetRegisterInfo and would necessitate moving 1148 // isTypeLegal over as well - a massive change that would just require 1149 // TargetLowering having a TargetRegisterInfo class member that it would use. 1150 std::pair<const TargetRegisterClass *, uint8_t> 1151 TargetLoweringBase::findRepresentativeClass(const TargetRegisterInfo *TRI, 1152 MVT VT) const { 1153 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy]; 1154 if (!RC) 1155 return std::make_pair(RC, 0); 1156 1157 // Compute the set of all super-register classes. 1158 BitVector SuperRegRC(TRI->getNumRegClasses()); 1159 for (SuperRegClassIterator RCI(RC, TRI); RCI.isValid(); ++RCI) 1160 SuperRegRC.setBitsInMask(RCI.getMask()); 1161 1162 // Find the first legal register class with the largest spill size. 1163 const TargetRegisterClass *BestRC = RC; 1164 for (unsigned i : SuperRegRC.set_bits()) { 1165 const TargetRegisterClass *SuperRC = TRI->getRegClass(i); 1166 // We want the largest possible spill size. 1167 if (TRI->getSpillSize(*SuperRC) <= TRI->getSpillSize(*BestRC)) 1168 continue; 1169 if (!isLegalRC(*TRI, *SuperRC)) 1170 continue; 1171 BestRC = SuperRC; 1172 } 1173 return std::make_pair(BestRC, 1); 1174 } 1175 1176 /// computeRegisterProperties - Once all of the register classes are added, 1177 /// this allows us to compute derived properties we expose. 1178 void TargetLoweringBase::computeRegisterProperties( 1179 const TargetRegisterInfo *TRI) { 1180 static_assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE, 1181 "Too many value types for ValueTypeActions to hold!"); 1182 1183 // Everything defaults to needing one register. 1184 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) { 1185 NumRegistersForVT[i] = 1; 1186 RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i; 1187 } 1188 // ...except isVoid, which doesn't need any registers. 1189 NumRegistersForVT[MVT::isVoid] = 0; 1190 1191 // Find the largest integer register class. 1192 unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE; 1193 for (; RegClassForVT[LargestIntReg] == nullptr; --LargestIntReg) 1194 assert(LargestIntReg != MVT::i1 && "No integer registers defined!"); 1195 1196 // Every integer value type larger than this largest register takes twice as 1197 // many registers to represent as the previous ValueType. 1198 for (unsigned ExpandedReg = LargestIntReg + 1; 1199 ExpandedReg <= MVT::LAST_INTEGER_VALUETYPE; ++ExpandedReg) { 1200 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1]; 1201 RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg; 1202 TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1); 1203 ValueTypeActions.setTypeAction((MVT::SimpleValueType)ExpandedReg, 1204 TypeExpandInteger); 1205 } 1206 1207 // Inspect all of the ValueType's smaller than the largest integer 1208 // register to see which ones need promotion. 1209 unsigned LegalIntReg = LargestIntReg; 1210 for (unsigned IntReg = LargestIntReg - 1; 1211 IntReg >= (unsigned)MVT::i1; --IntReg) { 1212 MVT IVT = (MVT::SimpleValueType)IntReg; 1213 if (isTypeLegal(IVT)) { 1214 LegalIntReg = IntReg; 1215 } else { 1216 RegisterTypeForVT[IntReg] = TransformToType[IntReg] = 1217 (MVT::SimpleValueType)LegalIntReg; 1218 ValueTypeActions.setTypeAction(IVT, TypePromoteInteger); 1219 } 1220 } 1221 1222 // ppcf128 type is really two f64's. 1223 if (!isTypeLegal(MVT::ppcf128)) { 1224 if (isTypeLegal(MVT::f64)) { 1225 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64]; 1226 RegisterTypeForVT[MVT::ppcf128] = MVT::f64; 1227 TransformToType[MVT::ppcf128] = MVT::f64; 1228 ValueTypeActions.setTypeAction(MVT::ppcf128, TypeExpandFloat); 1229 } else { 1230 NumRegistersForVT[MVT::ppcf128] = NumRegistersForVT[MVT::i128]; 1231 RegisterTypeForVT[MVT::ppcf128] = RegisterTypeForVT[MVT::i128]; 1232 TransformToType[MVT::ppcf128] = MVT::i128; 1233 ValueTypeActions.setTypeAction(MVT::ppcf128, TypeSoftenFloat); 1234 } 1235 } 1236 1237 // Decide how to handle f128. If the target does not have native f128 support, 1238 // expand it to i128 and we will be generating soft float library calls. 1239 if (!isTypeLegal(MVT::f128)) { 1240 NumRegistersForVT[MVT::f128] = NumRegistersForVT[MVT::i128]; 1241 RegisterTypeForVT[MVT::f128] = RegisterTypeForVT[MVT::i128]; 1242 TransformToType[MVT::f128] = MVT::i128; 1243 ValueTypeActions.setTypeAction(MVT::f128, TypeSoftenFloat); 1244 } 1245 1246 // Decide how to handle f64. If the target does not have native f64 support, 1247 // expand it to i64 and we will be generating soft float library calls. 1248 if (!isTypeLegal(MVT::f64)) { 1249 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64]; 1250 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64]; 1251 TransformToType[MVT::f64] = MVT::i64; 1252 ValueTypeActions.setTypeAction(MVT::f64, TypeSoftenFloat); 1253 } 1254 1255 // Decide how to handle f32. If the target does not have native f32 support, 1256 // expand it to i32 and we will be generating soft float library calls. 1257 if (!isTypeLegal(MVT::f32)) { 1258 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32]; 1259 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32]; 1260 TransformToType[MVT::f32] = MVT::i32; 1261 ValueTypeActions.setTypeAction(MVT::f32, TypeSoftenFloat); 1262 } 1263 1264 // Decide how to handle f16. If the target does not have native f16 support, 1265 // promote it to f32, because there are no f16 library calls (except for 1266 // conversions). 1267 if (!isTypeLegal(MVT::f16)) { 1268 // Allow targets to control how we legalize half. 1269 if (softPromoteHalfType()) { 1270 NumRegistersForVT[MVT::f16] = NumRegistersForVT[MVT::i16]; 1271 RegisterTypeForVT[MVT::f16] = RegisterTypeForVT[MVT::i16]; 1272 TransformToType[MVT::f16] = MVT::f32; 1273 ValueTypeActions.setTypeAction(MVT::f16, TypeSoftPromoteHalf); 1274 } else { 1275 NumRegistersForVT[MVT::f16] = NumRegistersForVT[MVT::f32]; 1276 RegisterTypeForVT[MVT::f16] = RegisterTypeForVT[MVT::f32]; 1277 TransformToType[MVT::f16] = MVT::f32; 1278 ValueTypeActions.setTypeAction(MVT::f16, TypePromoteFloat); 1279 } 1280 } 1281 1282 // Loop over all of the vector value types to see which need transformations. 1283 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE; 1284 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) { 1285 MVT VT = (MVT::SimpleValueType) i; 1286 if (isTypeLegal(VT)) 1287 continue; 1288 1289 MVT EltVT = VT.getVectorElementType(); 1290 ElementCount EC = VT.getVectorElementCount(); 1291 bool IsLegalWiderType = false; 1292 bool IsScalable = VT.isScalableVector(); 1293 LegalizeTypeAction PreferredAction = getPreferredVectorAction(VT); 1294 switch (PreferredAction) { 1295 case TypePromoteInteger: { 1296 MVT::SimpleValueType EndVT = IsScalable ? 1297 MVT::LAST_INTEGER_SCALABLE_VECTOR_VALUETYPE : 1298 MVT::LAST_INTEGER_FIXEDLEN_VECTOR_VALUETYPE; 1299 // Try to promote the elements of integer vectors. If no legal 1300 // promotion was found, fall through to the widen-vector method. 1301 for (unsigned nVT = i + 1; 1302 (MVT::SimpleValueType)nVT <= EndVT; ++nVT) { 1303 MVT SVT = (MVT::SimpleValueType) nVT; 1304 // Promote vectors of integers to vectors with the same number 1305 // of elements, with a wider element type. 1306 if (SVT.getScalarSizeInBits() > EltVT.getFixedSizeInBits() && 1307 SVT.getVectorElementCount() == EC && isTypeLegal(SVT)) { 1308 TransformToType[i] = SVT; 1309 RegisterTypeForVT[i] = SVT; 1310 NumRegistersForVT[i] = 1; 1311 ValueTypeActions.setTypeAction(VT, TypePromoteInteger); 1312 IsLegalWiderType = true; 1313 break; 1314 } 1315 } 1316 if (IsLegalWiderType) 1317 break; 1318 LLVM_FALLTHROUGH; 1319 } 1320 1321 case TypeWidenVector: 1322 if (isPowerOf2_32(EC.getKnownMinValue())) { 1323 // Try to widen the vector. 1324 for (unsigned nVT = i + 1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) { 1325 MVT SVT = (MVT::SimpleValueType) nVT; 1326 if (SVT.getVectorElementType() == EltVT && 1327 SVT.isScalableVector() == IsScalable && 1328 SVT.getVectorElementCount().getKnownMinValue() > 1329 EC.getKnownMinValue() && 1330 isTypeLegal(SVT)) { 1331 TransformToType[i] = SVT; 1332 RegisterTypeForVT[i] = SVT; 1333 NumRegistersForVT[i] = 1; 1334 ValueTypeActions.setTypeAction(VT, TypeWidenVector); 1335 IsLegalWiderType = true; 1336 break; 1337 } 1338 } 1339 if (IsLegalWiderType) 1340 break; 1341 } else { 1342 // Only widen to the next power of 2 to keep consistency with EVT. 1343 MVT NVT = VT.getPow2VectorType(); 1344 if (isTypeLegal(NVT)) { 1345 TransformToType[i] = NVT; 1346 ValueTypeActions.setTypeAction(VT, TypeWidenVector); 1347 RegisterTypeForVT[i] = NVT; 1348 NumRegistersForVT[i] = 1; 1349 break; 1350 } 1351 } 1352 LLVM_FALLTHROUGH; 1353 1354 case TypeSplitVector: 1355 case TypeScalarizeVector: { 1356 MVT IntermediateVT; 1357 MVT RegisterVT; 1358 unsigned NumIntermediates; 1359 unsigned NumRegisters = getVectorTypeBreakdownMVT(VT, IntermediateVT, 1360 NumIntermediates, RegisterVT, this); 1361 NumRegistersForVT[i] = NumRegisters; 1362 assert(NumRegistersForVT[i] == NumRegisters && 1363 "NumRegistersForVT size cannot represent NumRegisters!"); 1364 RegisterTypeForVT[i] = RegisterVT; 1365 1366 MVT NVT = VT.getPow2VectorType(); 1367 if (NVT == VT) { 1368 // Type is already a power of 2. The default action is to split. 1369 TransformToType[i] = MVT::Other; 1370 if (PreferredAction == TypeScalarizeVector) 1371 ValueTypeActions.setTypeAction(VT, TypeScalarizeVector); 1372 else if (PreferredAction == TypeSplitVector) 1373 ValueTypeActions.setTypeAction(VT, TypeSplitVector); 1374 else if (EC.getKnownMinValue() > 1) 1375 ValueTypeActions.setTypeAction(VT, TypeSplitVector); 1376 else 1377 ValueTypeActions.setTypeAction(VT, EC.isScalable() 1378 ? TypeScalarizeScalableVector 1379 : TypeScalarizeVector); 1380 } else { 1381 TransformToType[i] = NVT; 1382 ValueTypeActions.setTypeAction(VT, TypeWidenVector); 1383 } 1384 break; 1385 } 1386 default: 1387 llvm_unreachable("Unknown vector legalization action!"); 1388 } 1389 } 1390 1391 // Determine the 'representative' register class for each value type. 1392 // An representative register class is the largest (meaning one which is 1393 // not a sub-register class / subreg register class) legal register class for 1394 // a group of value types. For example, on i386, i8, i16, and i32 1395 // representative would be GR32; while on x86_64 it's GR64. 1396 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) { 1397 const TargetRegisterClass* RRC; 1398 uint8_t Cost; 1399 std::tie(RRC, Cost) = findRepresentativeClass(TRI, (MVT::SimpleValueType)i); 1400 RepRegClassForVT[i] = RRC; 1401 RepRegClassCostForVT[i] = Cost; 1402 } 1403 } 1404 1405 EVT TargetLoweringBase::getSetCCResultType(const DataLayout &DL, LLVMContext &, 1406 EVT VT) const { 1407 assert(!VT.isVector() && "No default SetCC type for vectors!"); 1408 return getPointerTy(DL).SimpleTy; 1409 } 1410 1411 MVT::SimpleValueType TargetLoweringBase::getCmpLibcallReturnType() const { 1412 return MVT::i32; // return the default value 1413 } 1414 1415 /// getVectorTypeBreakdown - Vector types are broken down into some number of 1416 /// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32 1417 /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack. 1418 /// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86. 1419 /// 1420 /// This method returns the number of registers needed, and the VT for each 1421 /// register. It also returns the VT and quantity of the intermediate values 1422 /// before they are promoted/expanded. 1423 unsigned TargetLoweringBase::getVectorTypeBreakdown(LLVMContext &Context, EVT VT, 1424 EVT &IntermediateVT, 1425 unsigned &NumIntermediates, 1426 MVT &RegisterVT) const { 1427 ElementCount EltCnt = VT.getVectorElementCount(); 1428 1429 // If there is a wider vector type with the same element type as this one, 1430 // or a promoted vector type that has the same number of elements which 1431 // are wider, then we should convert to that legal vector type. 1432 // This handles things like <2 x float> -> <4 x float> and 1433 // <4 x i1> -> <4 x i32>. 1434 LegalizeTypeAction TA = getTypeAction(Context, VT); 1435 if (EltCnt.getKnownMinValue() != 1 && 1436 (TA == TypeWidenVector || TA == TypePromoteInteger)) { 1437 EVT RegisterEVT = getTypeToTransformTo(Context, VT); 1438 if (isTypeLegal(RegisterEVT)) { 1439 IntermediateVT = RegisterEVT; 1440 RegisterVT = RegisterEVT.getSimpleVT(); 1441 NumIntermediates = 1; 1442 return 1; 1443 } 1444 } 1445 1446 // Figure out the right, legal destination reg to copy into. 1447 EVT EltTy = VT.getVectorElementType(); 1448 1449 unsigned NumVectorRegs = 1; 1450 1451 // Scalable vectors cannot be scalarized, so handle the legalisation of the 1452 // types like done elsewhere in SelectionDAG. 1453 if (VT.isScalableVector() && !isPowerOf2_32(EltCnt.getKnownMinValue())) { 1454 LegalizeKind LK; 1455 EVT PartVT = VT; 1456 do { 1457 // Iterate until we've found a legal (part) type to hold VT. 1458 LK = getTypeConversion(Context, PartVT); 1459 PartVT = LK.second; 1460 } while (LK.first != TypeLegal); 1461 1462 NumIntermediates = VT.getVectorElementCount().getKnownMinValue() / 1463 PartVT.getVectorElementCount().getKnownMinValue(); 1464 1465 // FIXME: This code needs to be extended to handle more complex vector 1466 // breakdowns, like nxv7i64 -> nxv8i64 -> 4 x nxv2i64. Currently the only 1467 // supported cases are vectors that are broken down into equal parts 1468 // such as nxv6i64 -> 3 x nxv2i64. 1469 assert((PartVT.getVectorElementCount() * NumIntermediates) == 1470 VT.getVectorElementCount() && 1471 "Expected an integer multiple of PartVT"); 1472 IntermediateVT = PartVT; 1473 RegisterVT = getRegisterType(Context, IntermediateVT); 1474 return NumIntermediates; 1475 } 1476 1477 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally 1478 // we could break down into LHS/RHS like LegalizeDAG does. 1479 if (!isPowerOf2_32(EltCnt.getKnownMinValue())) { 1480 NumVectorRegs = EltCnt.getKnownMinValue(); 1481 EltCnt = ElementCount::getFixed(1); 1482 } 1483 1484 // Divide the input until we get to a supported size. This will always 1485 // end with a scalar if the target doesn't support vectors. 1486 while (EltCnt.getKnownMinValue() > 1 && 1487 !isTypeLegal(EVT::getVectorVT(Context, EltTy, EltCnt))) { 1488 EltCnt = EltCnt.divideCoefficientBy(2); 1489 NumVectorRegs <<= 1; 1490 } 1491 1492 NumIntermediates = NumVectorRegs; 1493 1494 EVT NewVT = EVT::getVectorVT(Context, EltTy, EltCnt); 1495 if (!isTypeLegal(NewVT)) 1496 NewVT = EltTy; 1497 IntermediateVT = NewVT; 1498 1499 MVT DestVT = getRegisterType(Context, NewVT); 1500 RegisterVT = DestVT; 1501 1502 if (EVT(DestVT).bitsLT(NewVT)) { // Value is expanded, e.g. i64 -> i16. 1503 TypeSize NewVTSize = NewVT.getSizeInBits(); 1504 // Convert sizes such as i33 to i64. 1505 if (!isPowerOf2_32(NewVTSize.getKnownMinSize())) 1506 NewVTSize = NewVTSize.coefficientNextPowerOf2(); 1507 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits()); 1508 } 1509 1510 // Otherwise, promotion or legal types use the same number of registers as 1511 // the vector decimated to the appropriate level. 1512 return NumVectorRegs; 1513 } 1514 1515 bool TargetLoweringBase::isSuitableForJumpTable(const SwitchInst *SI, 1516 uint64_t NumCases, 1517 uint64_t Range, 1518 ProfileSummaryInfo *PSI, 1519 BlockFrequencyInfo *BFI) const { 1520 // FIXME: This function check the maximum table size and density, but the 1521 // minimum size is not checked. It would be nice if the minimum size is 1522 // also combined within this function. Currently, the minimum size check is 1523 // performed in findJumpTable() in SelectionDAGBuiler and 1524 // getEstimatedNumberOfCaseClusters() in BasicTTIImpl. 1525 const bool OptForSize = 1526 SI->getParent()->getParent()->hasOptSize() || 1527 llvm::shouldOptimizeForSize(SI->getParent(), PSI, BFI); 1528 const unsigned MinDensity = getMinimumJumpTableDensity(OptForSize); 1529 const unsigned MaxJumpTableSize = getMaximumJumpTableSize(); 1530 1531 // Check whether the number of cases is small enough and 1532 // the range is dense enough for a jump table. 1533 return (OptForSize || Range <= MaxJumpTableSize) && 1534 (NumCases * 100 >= Range * MinDensity); 1535 } 1536 1537 /// Get the EVTs and ArgFlags collections that represent the legalized return 1538 /// type of the given function. This does not require a DAG or a return value, 1539 /// and is suitable for use before any DAGs for the function are constructed. 1540 /// TODO: Move this out of TargetLowering.cpp. 1541 void llvm::GetReturnInfo(CallingConv::ID CC, Type *ReturnType, 1542 AttributeList attr, 1543 SmallVectorImpl<ISD::OutputArg> &Outs, 1544 const TargetLowering &TLI, const DataLayout &DL) { 1545 SmallVector<EVT, 4> ValueVTs; 1546 ComputeValueVTs(TLI, DL, ReturnType, ValueVTs); 1547 unsigned NumValues = ValueVTs.size(); 1548 if (NumValues == 0) return; 1549 1550 for (unsigned j = 0, f = NumValues; j != f; ++j) { 1551 EVT VT = ValueVTs[j]; 1552 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 1553 1554 if (attr.hasAttribute(AttributeList::ReturnIndex, Attribute::SExt)) 1555 ExtendKind = ISD::SIGN_EXTEND; 1556 else if (attr.hasAttribute(AttributeList::ReturnIndex, Attribute::ZExt)) 1557 ExtendKind = ISD::ZERO_EXTEND; 1558 1559 // FIXME: C calling convention requires the return type to be promoted to 1560 // at least 32-bit. But this is not necessary for non-C calling 1561 // conventions. The frontend should mark functions whose return values 1562 // require promoting with signext or zeroext attributes. 1563 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) { 1564 MVT MinVT = TLI.getRegisterType(ReturnType->getContext(), MVT::i32); 1565 if (VT.bitsLT(MinVT)) 1566 VT = MinVT; 1567 } 1568 1569 unsigned NumParts = 1570 TLI.getNumRegistersForCallingConv(ReturnType->getContext(), CC, VT); 1571 MVT PartVT = 1572 TLI.getRegisterTypeForCallingConv(ReturnType->getContext(), CC, VT); 1573 1574 // 'inreg' on function refers to return value 1575 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy(); 1576 if (attr.hasAttribute(AttributeList::ReturnIndex, Attribute::InReg)) 1577 Flags.setInReg(); 1578 1579 // Propagate extension type if any 1580 if (attr.hasAttribute(AttributeList::ReturnIndex, Attribute::SExt)) 1581 Flags.setSExt(); 1582 else if (attr.hasAttribute(AttributeList::ReturnIndex, Attribute::ZExt)) 1583 Flags.setZExt(); 1584 1585 for (unsigned i = 0; i < NumParts; ++i) 1586 Outs.push_back(ISD::OutputArg(Flags, PartVT, VT, /*isfixed=*/true, 0, 0)); 1587 } 1588 } 1589 1590 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 1591 /// function arguments in the caller parameter area. This is the actual 1592 /// alignment, not its logarithm. 1593 unsigned TargetLoweringBase::getByValTypeAlignment(Type *Ty, 1594 const DataLayout &DL) const { 1595 return DL.getABITypeAlign(Ty).value(); 1596 } 1597 1598 bool TargetLoweringBase::allowsMemoryAccessForAlignment( 1599 LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace, 1600 Align Alignment, MachineMemOperand::Flags Flags, bool *Fast) const { 1601 // Check if the specified alignment is sufficient based on the data layout. 1602 // TODO: While using the data layout works in practice, a better solution 1603 // would be to implement this check directly (make this a virtual function). 1604 // For example, the ABI alignment may change based on software platform while 1605 // this function should only be affected by hardware implementation. 1606 Type *Ty = VT.getTypeForEVT(Context); 1607 if (Alignment >= DL.getABITypeAlign(Ty)) { 1608 // Assume that an access that meets the ABI-specified alignment is fast. 1609 if (Fast != nullptr) 1610 *Fast = true; 1611 return true; 1612 } 1613 1614 // This is a misaligned access. 1615 return allowsMisalignedMemoryAccesses(VT, AddrSpace, Alignment.value(), Flags, 1616 Fast); 1617 } 1618 1619 bool TargetLoweringBase::allowsMemoryAccessForAlignment( 1620 LLVMContext &Context, const DataLayout &DL, EVT VT, 1621 const MachineMemOperand &MMO, bool *Fast) const { 1622 return allowsMemoryAccessForAlignment(Context, DL, VT, MMO.getAddrSpace(), 1623 MMO.getAlign(), MMO.getFlags(), Fast); 1624 } 1625 1626 bool TargetLoweringBase::allowsMemoryAccess(LLVMContext &Context, 1627 const DataLayout &DL, EVT VT, 1628 unsigned AddrSpace, Align Alignment, 1629 MachineMemOperand::Flags Flags, 1630 bool *Fast) const { 1631 return allowsMemoryAccessForAlignment(Context, DL, VT, AddrSpace, Alignment, 1632 Flags, Fast); 1633 } 1634 1635 bool TargetLoweringBase::allowsMemoryAccess(LLVMContext &Context, 1636 const DataLayout &DL, EVT VT, 1637 const MachineMemOperand &MMO, 1638 bool *Fast) const { 1639 return allowsMemoryAccess(Context, DL, VT, MMO.getAddrSpace(), MMO.getAlign(), 1640 MMO.getFlags(), Fast); 1641 } 1642 1643 BranchProbability TargetLoweringBase::getPredictableBranchThreshold() const { 1644 return BranchProbability(MinPercentageForPredictableBranch, 100); 1645 } 1646 1647 //===----------------------------------------------------------------------===// 1648 // TargetTransformInfo Helpers 1649 //===----------------------------------------------------------------------===// 1650 1651 int TargetLoweringBase::InstructionOpcodeToISD(unsigned Opcode) const { 1652 enum InstructionOpcodes { 1653 #define HANDLE_INST(NUM, OPCODE, CLASS) OPCODE = NUM, 1654 #define LAST_OTHER_INST(NUM) InstructionOpcodesCount = NUM 1655 #include "llvm/IR/Instruction.def" 1656 }; 1657 switch (static_cast<InstructionOpcodes>(Opcode)) { 1658 case Ret: return 0; 1659 case Br: return 0; 1660 case Switch: return 0; 1661 case IndirectBr: return 0; 1662 case Invoke: return 0; 1663 case CallBr: return 0; 1664 case Resume: return 0; 1665 case Unreachable: return 0; 1666 case CleanupRet: return 0; 1667 case CatchRet: return 0; 1668 case CatchPad: return 0; 1669 case CatchSwitch: return 0; 1670 case CleanupPad: return 0; 1671 case FNeg: return ISD::FNEG; 1672 case Add: return ISD::ADD; 1673 case FAdd: return ISD::FADD; 1674 case Sub: return ISD::SUB; 1675 case FSub: return ISD::FSUB; 1676 case Mul: return ISD::MUL; 1677 case FMul: return ISD::FMUL; 1678 case UDiv: return ISD::UDIV; 1679 case SDiv: return ISD::SDIV; 1680 case FDiv: return ISD::FDIV; 1681 case URem: return ISD::UREM; 1682 case SRem: return ISD::SREM; 1683 case FRem: return ISD::FREM; 1684 case Shl: return ISD::SHL; 1685 case LShr: return ISD::SRL; 1686 case AShr: return ISD::SRA; 1687 case And: return ISD::AND; 1688 case Or: return ISD::OR; 1689 case Xor: return ISD::XOR; 1690 case Alloca: return 0; 1691 case Load: return ISD::LOAD; 1692 case Store: return ISD::STORE; 1693 case GetElementPtr: return 0; 1694 case Fence: return 0; 1695 case AtomicCmpXchg: return 0; 1696 case AtomicRMW: return 0; 1697 case Trunc: return ISD::TRUNCATE; 1698 case ZExt: return ISD::ZERO_EXTEND; 1699 case SExt: return ISD::SIGN_EXTEND; 1700 case FPToUI: return ISD::FP_TO_UINT; 1701 case FPToSI: return ISD::FP_TO_SINT; 1702 case UIToFP: return ISD::UINT_TO_FP; 1703 case SIToFP: return ISD::SINT_TO_FP; 1704 case FPTrunc: return ISD::FP_ROUND; 1705 case FPExt: return ISD::FP_EXTEND; 1706 case PtrToInt: return ISD::BITCAST; 1707 case IntToPtr: return ISD::BITCAST; 1708 case BitCast: return ISD::BITCAST; 1709 case AddrSpaceCast: return ISD::ADDRSPACECAST; 1710 case ICmp: return ISD::SETCC; 1711 case FCmp: return ISD::SETCC; 1712 case PHI: return 0; 1713 case Call: return 0; 1714 case Select: return ISD::SELECT; 1715 case UserOp1: return 0; 1716 case UserOp2: return 0; 1717 case VAArg: return 0; 1718 case ExtractElement: return ISD::EXTRACT_VECTOR_ELT; 1719 case InsertElement: return ISD::INSERT_VECTOR_ELT; 1720 case ShuffleVector: return ISD::VECTOR_SHUFFLE; 1721 case ExtractValue: return ISD::MERGE_VALUES; 1722 case InsertValue: return ISD::MERGE_VALUES; 1723 case LandingPad: return 0; 1724 case Freeze: return ISD::FREEZE; 1725 } 1726 1727 llvm_unreachable("Unknown instruction type encountered!"); 1728 } 1729 1730 std::pair<int, MVT> 1731 TargetLoweringBase::getTypeLegalizationCost(const DataLayout &DL, 1732 Type *Ty) const { 1733 LLVMContext &C = Ty->getContext(); 1734 EVT MTy = getValueType(DL, Ty); 1735 1736 int Cost = 1; 1737 // We keep legalizing the type until we find a legal kind. We assume that 1738 // the only operation that costs anything is the split. After splitting 1739 // we need to handle two types. 1740 while (true) { 1741 LegalizeKind LK = getTypeConversion(C, MTy); 1742 1743 if (LK.first == TypeLegal) 1744 return std::make_pair(Cost, MTy.getSimpleVT()); 1745 1746 if (LK.first == TypeSplitVector || LK.first == TypeExpandInteger) 1747 Cost *= 2; 1748 1749 // Do not loop with f128 type. 1750 if (MTy == LK.second) 1751 return std::make_pair(Cost, MTy.getSimpleVT()); 1752 1753 // Keep legalizing the type. 1754 MTy = LK.second; 1755 } 1756 } 1757 1758 Value *TargetLoweringBase::getDefaultSafeStackPointerLocation(IRBuilder<> &IRB, 1759 bool UseTLS) const { 1760 // compiler-rt provides a variable with a magic name. Targets that do not 1761 // link with compiler-rt may also provide such a variable. 1762 Module *M = IRB.GetInsertBlock()->getParent()->getParent(); 1763 const char *UnsafeStackPtrVar = "__safestack_unsafe_stack_ptr"; 1764 auto UnsafeStackPtr = 1765 dyn_cast_or_null<GlobalVariable>(M->getNamedValue(UnsafeStackPtrVar)); 1766 1767 Type *StackPtrTy = Type::getInt8PtrTy(M->getContext()); 1768 1769 if (!UnsafeStackPtr) { 1770 auto TLSModel = UseTLS ? 1771 GlobalValue::InitialExecTLSModel : 1772 GlobalValue::NotThreadLocal; 1773 // The global variable is not defined yet, define it ourselves. 1774 // We use the initial-exec TLS model because we do not support the 1775 // variable living anywhere other than in the main executable. 1776 UnsafeStackPtr = new GlobalVariable( 1777 *M, StackPtrTy, false, GlobalValue::ExternalLinkage, nullptr, 1778 UnsafeStackPtrVar, nullptr, TLSModel); 1779 } else { 1780 // The variable exists, check its type and attributes. 1781 if (UnsafeStackPtr->getValueType() != StackPtrTy) 1782 report_fatal_error(Twine(UnsafeStackPtrVar) + " must have void* type"); 1783 if (UseTLS != UnsafeStackPtr->isThreadLocal()) 1784 report_fatal_error(Twine(UnsafeStackPtrVar) + " must " + 1785 (UseTLS ? "" : "not ") + "be thread-local"); 1786 } 1787 return UnsafeStackPtr; 1788 } 1789 1790 Value *TargetLoweringBase::getSafeStackPointerLocation(IRBuilder<> &IRB) const { 1791 if (!TM.getTargetTriple().isAndroid()) 1792 return getDefaultSafeStackPointerLocation(IRB, true); 1793 1794 // Android provides a libc function to retrieve the address of the current 1795 // thread's unsafe stack pointer. 1796 Module *M = IRB.GetInsertBlock()->getParent()->getParent(); 1797 Type *StackPtrTy = Type::getInt8PtrTy(M->getContext()); 1798 FunctionCallee Fn = M->getOrInsertFunction("__safestack_pointer_address", 1799 StackPtrTy->getPointerTo(0)); 1800 return IRB.CreateCall(Fn); 1801 } 1802 1803 //===----------------------------------------------------------------------===// 1804 // Loop Strength Reduction hooks 1805 //===----------------------------------------------------------------------===// 1806 1807 /// isLegalAddressingMode - Return true if the addressing mode represented 1808 /// by AM is legal for this target, for a load/store of the specified type. 1809 bool TargetLoweringBase::isLegalAddressingMode(const DataLayout &DL, 1810 const AddrMode &AM, Type *Ty, 1811 unsigned AS, Instruction *I) const { 1812 // The default implementation of this implements a conservative RISCy, r+r and 1813 // r+i addr mode. 1814 1815 // Allows a sign-extended 16-bit immediate field. 1816 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1) 1817 return false; 1818 1819 // No global is ever allowed as a base. 1820 if (AM.BaseGV) 1821 return false; 1822 1823 // Only support r+r, 1824 switch (AM.Scale) { 1825 case 0: // "r+i" or just "i", depending on HasBaseReg. 1826 break; 1827 case 1: 1828 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. 1829 return false; 1830 // Otherwise we have r+r or r+i. 1831 break; 1832 case 2: 1833 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. 1834 return false; 1835 // Allow 2*r as r+r. 1836 break; 1837 default: // Don't allow n * r 1838 return false; 1839 } 1840 1841 return true; 1842 } 1843 1844 //===----------------------------------------------------------------------===// 1845 // Stack Protector 1846 //===----------------------------------------------------------------------===// 1847 1848 // For OpenBSD return its special guard variable. Otherwise return nullptr, 1849 // so that SelectionDAG handle SSP. 1850 Value *TargetLoweringBase::getIRStackGuard(IRBuilder<> &IRB) const { 1851 if (getTargetMachine().getTargetTriple().isOSOpenBSD()) { 1852 Module &M = *IRB.GetInsertBlock()->getParent()->getParent(); 1853 PointerType *PtrTy = Type::getInt8PtrTy(M.getContext()); 1854 Constant *C = M.getOrInsertGlobal("__guard_local", PtrTy); 1855 if (GlobalVariable *G = dyn_cast_or_null<GlobalVariable>(C)) 1856 G->setVisibility(GlobalValue::HiddenVisibility); 1857 return C; 1858 } 1859 return nullptr; 1860 } 1861 1862 // Currently only support "standard" __stack_chk_guard. 1863 // TODO: add LOAD_STACK_GUARD support. 1864 void TargetLoweringBase::insertSSPDeclarations(Module &M) const { 1865 if (!M.getNamedValue("__stack_chk_guard")) 1866 new GlobalVariable(M, Type::getInt8PtrTy(M.getContext()), false, 1867 GlobalVariable::ExternalLinkage, 1868 nullptr, "__stack_chk_guard"); 1869 } 1870 1871 // Currently only support "standard" __stack_chk_guard. 1872 // TODO: add LOAD_STACK_GUARD support. 1873 Value *TargetLoweringBase::getSDagStackGuard(const Module &M) const { 1874 return M.getNamedValue("__stack_chk_guard"); 1875 } 1876 1877 Function *TargetLoweringBase::getSSPStackGuardCheck(const Module &M) const { 1878 return nullptr; 1879 } 1880 1881 unsigned TargetLoweringBase::getMinimumJumpTableEntries() const { 1882 return MinimumJumpTableEntries; 1883 } 1884 1885 void TargetLoweringBase::setMinimumJumpTableEntries(unsigned Val) { 1886 MinimumJumpTableEntries = Val; 1887 } 1888 1889 unsigned TargetLoweringBase::getMinimumJumpTableDensity(bool OptForSize) const { 1890 return OptForSize ? OptsizeJumpTableDensity : JumpTableDensity; 1891 } 1892 1893 unsigned TargetLoweringBase::getMaximumJumpTableSize() const { 1894 return MaximumJumpTableSize; 1895 } 1896 1897 void TargetLoweringBase::setMaximumJumpTableSize(unsigned Val) { 1898 MaximumJumpTableSize = Val; 1899 } 1900 1901 bool TargetLoweringBase::isJumpTableRelative() const { 1902 return getTargetMachine().isPositionIndependent(); 1903 } 1904 1905 //===----------------------------------------------------------------------===// 1906 // Reciprocal Estimates 1907 //===----------------------------------------------------------------------===// 1908 1909 /// Get the reciprocal estimate attribute string for a function that will 1910 /// override the target defaults. 1911 static StringRef getRecipEstimateForFunc(MachineFunction &MF) { 1912 const Function &F = MF.getFunction(); 1913 return F.getFnAttribute("reciprocal-estimates").getValueAsString(); 1914 } 1915 1916 /// Construct a string for the given reciprocal operation of the given type. 1917 /// This string should match the corresponding option to the front-end's 1918 /// "-mrecip" flag assuming those strings have been passed through in an 1919 /// attribute string. For example, "vec-divf" for a division of a vXf32. 1920 static std::string getReciprocalOpName(bool IsSqrt, EVT VT) { 1921 std::string Name = VT.isVector() ? "vec-" : ""; 1922 1923 Name += IsSqrt ? "sqrt" : "div"; 1924 1925 // TODO: Handle "half" or other float types? 1926 if (VT.getScalarType() == MVT::f64) { 1927 Name += "d"; 1928 } else { 1929 assert(VT.getScalarType() == MVT::f32 && 1930 "Unexpected FP type for reciprocal estimate"); 1931 Name += "f"; 1932 } 1933 1934 return Name; 1935 } 1936 1937 /// Return the character position and value (a single numeric character) of a 1938 /// customized refinement operation in the input string if it exists. Return 1939 /// false if there is no customized refinement step count. 1940 static bool parseRefinementStep(StringRef In, size_t &Position, 1941 uint8_t &Value) { 1942 const char RefStepToken = ':'; 1943 Position = In.find(RefStepToken); 1944 if (Position == StringRef::npos) 1945 return false; 1946 1947 StringRef RefStepString = In.substr(Position + 1); 1948 // Allow exactly one numeric character for the additional refinement 1949 // step parameter. 1950 if (RefStepString.size() == 1) { 1951 char RefStepChar = RefStepString[0]; 1952 if (RefStepChar >= '0' && RefStepChar <= '9') { 1953 Value = RefStepChar - '0'; 1954 return true; 1955 } 1956 } 1957 report_fatal_error("Invalid refinement step for -recip."); 1958 } 1959 1960 /// For the input attribute string, return one of the ReciprocalEstimate enum 1961 /// status values (enabled, disabled, or not specified) for this operation on 1962 /// the specified data type. 1963 static int getOpEnabled(bool IsSqrt, EVT VT, StringRef Override) { 1964 if (Override.empty()) 1965 return TargetLoweringBase::ReciprocalEstimate::Unspecified; 1966 1967 SmallVector<StringRef, 4> OverrideVector; 1968 Override.split(OverrideVector, ','); 1969 unsigned NumArgs = OverrideVector.size(); 1970 1971 // Check if "all", "none", or "default" was specified. 1972 if (NumArgs == 1) { 1973 // Look for an optional setting of the number of refinement steps needed 1974 // for this type of reciprocal operation. 1975 size_t RefPos; 1976 uint8_t RefSteps; 1977 if (parseRefinementStep(Override, RefPos, RefSteps)) { 1978 // Split the string for further processing. 1979 Override = Override.substr(0, RefPos); 1980 } 1981 1982 // All reciprocal types are enabled. 1983 if (Override == "all") 1984 return TargetLoweringBase::ReciprocalEstimate::Enabled; 1985 1986 // All reciprocal types are disabled. 1987 if (Override == "none") 1988 return TargetLoweringBase::ReciprocalEstimate::Disabled; 1989 1990 // Target defaults for enablement are used. 1991 if (Override == "default") 1992 return TargetLoweringBase::ReciprocalEstimate::Unspecified; 1993 } 1994 1995 // The attribute string may omit the size suffix ('f'/'d'). 1996 std::string VTName = getReciprocalOpName(IsSqrt, VT); 1997 std::string VTNameNoSize = VTName; 1998 VTNameNoSize.pop_back(); 1999 static const char DisabledPrefix = '!'; 2000 2001 for (StringRef RecipType : OverrideVector) { 2002 size_t RefPos; 2003 uint8_t RefSteps; 2004 if (parseRefinementStep(RecipType, RefPos, RefSteps)) 2005 RecipType = RecipType.substr(0, RefPos); 2006 2007 // Ignore the disablement token for string matching. 2008 bool IsDisabled = RecipType[0] == DisabledPrefix; 2009 if (IsDisabled) 2010 RecipType = RecipType.substr(1); 2011 2012 if (RecipType.equals(VTName) || RecipType.equals(VTNameNoSize)) 2013 return IsDisabled ? TargetLoweringBase::ReciprocalEstimate::Disabled 2014 : TargetLoweringBase::ReciprocalEstimate::Enabled; 2015 } 2016 2017 return TargetLoweringBase::ReciprocalEstimate::Unspecified; 2018 } 2019 2020 /// For the input attribute string, return the customized refinement step count 2021 /// for this operation on the specified data type. If the step count does not 2022 /// exist, return the ReciprocalEstimate enum value for unspecified. 2023 static int getOpRefinementSteps(bool IsSqrt, EVT VT, StringRef Override) { 2024 if (Override.empty()) 2025 return TargetLoweringBase::ReciprocalEstimate::Unspecified; 2026 2027 SmallVector<StringRef, 4> OverrideVector; 2028 Override.split(OverrideVector, ','); 2029 unsigned NumArgs = OverrideVector.size(); 2030 2031 // Check if "all", "default", or "none" was specified. 2032 if (NumArgs == 1) { 2033 // Look for an optional setting of the number of refinement steps needed 2034 // for this type of reciprocal operation. 2035 size_t RefPos; 2036 uint8_t RefSteps; 2037 if (!parseRefinementStep(Override, RefPos, RefSteps)) 2038 return TargetLoweringBase::ReciprocalEstimate::Unspecified; 2039 2040 // Split the string for further processing. 2041 Override = Override.substr(0, RefPos); 2042 assert(Override != "none" && 2043 "Disabled reciprocals, but specifed refinement steps?"); 2044 2045 // If this is a general override, return the specified number of steps. 2046 if (Override == "all" || Override == "default") 2047 return RefSteps; 2048 } 2049 2050 // The attribute string may omit the size suffix ('f'/'d'). 2051 std::string VTName = getReciprocalOpName(IsSqrt, VT); 2052 std::string VTNameNoSize = VTName; 2053 VTNameNoSize.pop_back(); 2054 2055 for (StringRef RecipType : OverrideVector) { 2056 size_t RefPos; 2057 uint8_t RefSteps; 2058 if (!parseRefinementStep(RecipType, RefPos, RefSteps)) 2059 continue; 2060 2061 RecipType = RecipType.substr(0, RefPos); 2062 if (RecipType.equals(VTName) || RecipType.equals(VTNameNoSize)) 2063 return RefSteps; 2064 } 2065 2066 return TargetLoweringBase::ReciprocalEstimate::Unspecified; 2067 } 2068 2069 int TargetLoweringBase::getRecipEstimateSqrtEnabled(EVT VT, 2070 MachineFunction &MF) const { 2071 return getOpEnabled(true, VT, getRecipEstimateForFunc(MF)); 2072 } 2073 2074 int TargetLoweringBase::getRecipEstimateDivEnabled(EVT VT, 2075 MachineFunction &MF) const { 2076 return getOpEnabled(false, VT, getRecipEstimateForFunc(MF)); 2077 } 2078 2079 int TargetLoweringBase::getSqrtRefinementSteps(EVT VT, 2080 MachineFunction &MF) const { 2081 return getOpRefinementSteps(true, VT, getRecipEstimateForFunc(MF)); 2082 } 2083 2084 int TargetLoweringBase::getDivRefinementSteps(EVT VT, 2085 MachineFunction &MF) const { 2086 return getOpRefinementSteps(false, VT, getRecipEstimateForFunc(MF)); 2087 } 2088 2089 void TargetLoweringBase::finalizeLowering(MachineFunction &MF) const { 2090 MF.getRegInfo().freezeReservedRegs(MF); 2091 } 2092 2093 MachineMemOperand::Flags 2094 TargetLoweringBase::getLoadMemOperandFlags(const LoadInst &LI, 2095 const DataLayout &DL) const { 2096 MachineMemOperand::Flags Flags = MachineMemOperand::MOLoad; 2097 if (LI.isVolatile()) 2098 Flags |= MachineMemOperand::MOVolatile; 2099 2100 if (LI.hasMetadata(LLVMContext::MD_nontemporal)) 2101 Flags |= MachineMemOperand::MONonTemporal; 2102 2103 if (LI.hasMetadata(LLVMContext::MD_invariant_load)) 2104 Flags |= MachineMemOperand::MOInvariant; 2105 2106 if (isDereferenceablePointer(LI.getPointerOperand(), LI.getType(), DL)) 2107 Flags |= MachineMemOperand::MODereferenceable; 2108 2109 Flags |= getTargetMMOFlags(LI); 2110 return Flags; 2111 } 2112 2113 MachineMemOperand::Flags 2114 TargetLoweringBase::getStoreMemOperandFlags(const StoreInst &SI, 2115 const DataLayout &DL) const { 2116 MachineMemOperand::Flags Flags = MachineMemOperand::MOStore; 2117 2118 if (SI.isVolatile()) 2119 Flags |= MachineMemOperand::MOVolatile; 2120 2121 if (SI.hasMetadata(LLVMContext::MD_nontemporal)) 2122 Flags |= MachineMemOperand::MONonTemporal; 2123 2124 // FIXME: Not preserving dereferenceable 2125 Flags |= getTargetMMOFlags(SI); 2126 return Flags; 2127 } 2128 2129 MachineMemOperand::Flags 2130 TargetLoweringBase::getAtomicMemOperandFlags(const Instruction &AI, 2131 const DataLayout &DL) const { 2132 auto Flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore; 2133 2134 if (const AtomicRMWInst *RMW = dyn_cast<AtomicRMWInst>(&AI)) { 2135 if (RMW->isVolatile()) 2136 Flags |= MachineMemOperand::MOVolatile; 2137 } else if (const AtomicCmpXchgInst *CmpX = dyn_cast<AtomicCmpXchgInst>(&AI)) { 2138 if (CmpX->isVolatile()) 2139 Flags |= MachineMemOperand::MOVolatile; 2140 } else 2141 llvm_unreachable("not an atomic instruction"); 2142 2143 // FIXME: Not preserving dereferenceable 2144 Flags |= getTargetMMOFlags(AI); 2145 return Flags; 2146 } 2147 2148 //===----------------------------------------------------------------------===// 2149 // GlobalISel Hooks 2150 //===----------------------------------------------------------------------===// 2151 2152 bool TargetLoweringBase::shouldLocalize(const MachineInstr &MI, 2153 const TargetTransformInfo *TTI) const { 2154 auto &MF = *MI.getMF(); 2155 auto &MRI = MF.getRegInfo(); 2156 // Assuming a spill and reload of a value has a cost of 1 instruction each, 2157 // this helper function computes the maximum number of uses we should consider 2158 // for remat. E.g. on arm64 global addresses take 2 insts to materialize. We 2159 // break even in terms of code size when the original MI has 2 users vs 2160 // choosing to potentially spill. Any more than 2 users we we have a net code 2161 // size increase. This doesn't take into account register pressure though. 2162 auto maxUses = [](unsigned RematCost) { 2163 // A cost of 1 means remats are basically free. 2164 if (RematCost == 1) 2165 return UINT_MAX; 2166 if (RematCost == 2) 2167 return 2U; 2168 2169 // Remat is too expensive, only sink if there's one user. 2170 if (RematCost > 2) 2171 return 1U; 2172 llvm_unreachable("Unexpected remat cost"); 2173 }; 2174 2175 // Helper to walk through uses and terminate if we've reached a limit. Saves 2176 // us spending time traversing uses if all we want to know is if it's >= min. 2177 auto isUsesAtMost = [&](unsigned Reg, unsigned MaxUses) { 2178 unsigned NumUses = 0; 2179 auto UI = MRI.use_instr_nodbg_begin(Reg), UE = MRI.use_instr_nodbg_end(); 2180 for (; UI != UE && NumUses < MaxUses; ++UI) { 2181 NumUses++; 2182 } 2183 // If we haven't reached the end yet then there are more than MaxUses users. 2184 return UI == UE; 2185 }; 2186 2187 switch (MI.getOpcode()) { 2188 default: 2189 return false; 2190 // Constants-like instructions should be close to their users. 2191 // We don't want long live-ranges for them. 2192 case TargetOpcode::G_CONSTANT: 2193 case TargetOpcode::G_FCONSTANT: 2194 case TargetOpcode::G_FRAME_INDEX: 2195 case TargetOpcode::G_INTTOPTR: 2196 return true; 2197 case TargetOpcode::G_GLOBAL_VALUE: { 2198 unsigned RematCost = TTI->getGISelRematGlobalCost(); 2199 Register Reg = MI.getOperand(0).getReg(); 2200 unsigned MaxUses = maxUses(RematCost); 2201 if (MaxUses == UINT_MAX) 2202 return true; // Remats are "free" so always localize. 2203 bool B = isUsesAtMost(Reg, MaxUses); 2204 return B; 2205 } 2206 } 2207 } 2208