1 //===-- TargetLoweringBase.cpp - Implement the TargetLoweringBase class ---===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This implements the TargetLoweringBase class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "llvm/Target/TargetLowering.h" 15 #include "llvm/ADT/BitVector.h" 16 #include "llvm/ADT/STLExtras.h" 17 #include "llvm/ADT/Triple.h" 18 #include "llvm/CodeGen/Analysis.h" 19 #include "llvm/CodeGen/MachineFrameInfo.h" 20 #include "llvm/CodeGen/MachineFunction.h" 21 #include "llvm/CodeGen/MachineInstrBuilder.h" 22 #include "llvm/CodeGen/MachineJumpTableInfo.h" 23 #include "llvm/CodeGen/StackMaps.h" 24 #include "llvm/IR/DataLayout.h" 25 #include "llvm/IR/DerivedTypes.h" 26 #include "llvm/IR/GlobalVariable.h" 27 #include "llvm/IR/Mangler.h" 28 #include "llvm/MC/MCAsmInfo.h" 29 #include "llvm/MC/MCContext.h" 30 #include "llvm/MC/MCExpr.h" 31 #include "llvm/Support/BranchProbability.h" 32 #include "llvm/Support/CommandLine.h" 33 #include "llvm/Support/ErrorHandling.h" 34 #include "llvm/Support/MathExtras.h" 35 #include "llvm/Target/TargetLoweringObjectFile.h" 36 #include "llvm/Target/TargetMachine.h" 37 #include "llvm/Target/TargetRegisterInfo.h" 38 #include "llvm/Target/TargetSubtargetInfo.h" 39 #include <cctype> 40 using namespace llvm; 41 42 static cl::opt<bool> JumpIsExpensiveOverride( 43 "jump-is-expensive", cl::init(false), 44 cl::desc("Do not create extra branches to split comparison logic."), 45 cl::Hidden); 46 47 // Although this default value is arbitrary, it is not random. It is assumed 48 // that a condition that evaluates the same way by a higher percentage than this 49 // is best represented as control flow. Therefore, the default value N should be 50 // set such that the win from N% correct executions is greater than the loss 51 // from (100 - N)% mispredicted executions for the majority of intended targets. 52 static cl::opt<int> MinPercentageForPredictableBranch( 53 "min-predictable-branch", cl::init(99), 54 cl::desc("Minimum percentage (0-100) that a condition must be either true " 55 "or false to assume that the condition is predictable"), 56 cl::Hidden); 57 58 /// InitLibcallNames - Set default libcall names. 59 /// 60 static void InitLibcallNames(const char **Names, const Triple &TT) { 61 Names[RTLIB::SHL_I16] = "__ashlhi3"; 62 Names[RTLIB::SHL_I32] = "__ashlsi3"; 63 Names[RTLIB::SHL_I64] = "__ashldi3"; 64 Names[RTLIB::SHL_I128] = "__ashlti3"; 65 Names[RTLIB::SRL_I16] = "__lshrhi3"; 66 Names[RTLIB::SRL_I32] = "__lshrsi3"; 67 Names[RTLIB::SRL_I64] = "__lshrdi3"; 68 Names[RTLIB::SRL_I128] = "__lshrti3"; 69 Names[RTLIB::SRA_I16] = "__ashrhi3"; 70 Names[RTLIB::SRA_I32] = "__ashrsi3"; 71 Names[RTLIB::SRA_I64] = "__ashrdi3"; 72 Names[RTLIB::SRA_I128] = "__ashrti3"; 73 Names[RTLIB::MUL_I8] = "__mulqi3"; 74 Names[RTLIB::MUL_I16] = "__mulhi3"; 75 Names[RTLIB::MUL_I32] = "__mulsi3"; 76 Names[RTLIB::MUL_I64] = "__muldi3"; 77 Names[RTLIB::MUL_I128] = "__multi3"; 78 Names[RTLIB::MULO_I32] = "__mulosi4"; 79 Names[RTLIB::MULO_I64] = "__mulodi4"; 80 Names[RTLIB::MULO_I128] = "__muloti4"; 81 Names[RTLIB::SDIV_I8] = "__divqi3"; 82 Names[RTLIB::SDIV_I16] = "__divhi3"; 83 Names[RTLIB::SDIV_I32] = "__divsi3"; 84 Names[RTLIB::SDIV_I64] = "__divdi3"; 85 Names[RTLIB::SDIV_I128] = "__divti3"; 86 Names[RTLIB::UDIV_I8] = "__udivqi3"; 87 Names[RTLIB::UDIV_I16] = "__udivhi3"; 88 Names[RTLIB::UDIV_I32] = "__udivsi3"; 89 Names[RTLIB::UDIV_I64] = "__udivdi3"; 90 Names[RTLIB::UDIV_I128] = "__udivti3"; 91 Names[RTLIB::SREM_I8] = "__modqi3"; 92 Names[RTLIB::SREM_I16] = "__modhi3"; 93 Names[RTLIB::SREM_I32] = "__modsi3"; 94 Names[RTLIB::SREM_I64] = "__moddi3"; 95 Names[RTLIB::SREM_I128] = "__modti3"; 96 Names[RTLIB::UREM_I8] = "__umodqi3"; 97 Names[RTLIB::UREM_I16] = "__umodhi3"; 98 Names[RTLIB::UREM_I32] = "__umodsi3"; 99 Names[RTLIB::UREM_I64] = "__umoddi3"; 100 Names[RTLIB::UREM_I128] = "__umodti3"; 101 102 Names[RTLIB::NEG_I32] = "__negsi2"; 103 Names[RTLIB::NEG_I64] = "__negdi2"; 104 Names[RTLIB::ADD_F32] = "__addsf3"; 105 Names[RTLIB::ADD_F64] = "__adddf3"; 106 Names[RTLIB::ADD_F80] = "__addxf3"; 107 Names[RTLIB::ADD_F128] = "__addtf3"; 108 Names[RTLIB::ADD_PPCF128] = "__gcc_qadd"; 109 Names[RTLIB::SUB_F32] = "__subsf3"; 110 Names[RTLIB::SUB_F64] = "__subdf3"; 111 Names[RTLIB::SUB_F80] = "__subxf3"; 112 Names[RTLIB::SUB_F128] = "__subtf3"; 113 Names[RTLIB::SUB_PPCF128] = "__gcc_qsub"; 114 Names[RTLIB::MUL_F32] = "__mulsf3"; 115 Names[RTLIB::MUL_F64] = "__muldf3"; 116 Names[RTLIB::MUL_F80] = "__mulxf3"; 117 Names[RTLIB::MUL_F128] = "__multf3"; 118 Names[RTLIB::MUL_PPCF128] = "__gcc_qmul"; 119 Names[RTLIB::DIV_F32] = "__divsf3"; 120 Names[RTLIB::DIV_F64] = "__divdf3"; 121 Names[RTLIB::DIV_F80] = "__divxf3"; 122 Names[RTLIB::DIV_F128] = "__divtf3"; 123 Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv"; 124 Names[RTLIB::REM_F32] = "fmodf"; 125 Names[RTLIB::REM_F64] = "fmod"; 126 Names[RTLIB::REM_F80] = "fmodl"; 127 Names[RTLIB::REM_F128] = "fmodl"; 128 Names[RTLIB::REM_PPCF128] = "fmodl"; 129 Names[RTLIB::FMA_F32] = "fmaf"; 130 Names[RTLIB::FMA_F64] = "fma"; 131 Names[RTLIB::FMA_F80] = "fmal"; 132 Names[RTLIB::FMA_F128] = "fmal"; 133 Names[RTLIB::FMA_PPCF128] = "fmal"; 134 Names[RTLIB::POWI_F32] = "__powisf2"; 135 Names[RTLIB::POWI_F64] = "__powidf2"; 136 Names[RTLIB::POWI_F80] = "__powixf2"; 137 Names[RTLIB::POWI_F128] = "__powitf2"; 138 Names[RTLIB::POWI_PPCF128] = "__powitf2"; 139 Names[RTLIB::SQRT_F32] = "sqrtf"; 140 Names[RTLIB::SQRT_F64] = "sqrt"; 141 Names[RTLIB::SQRT_F80] = "sqrtl"; 142 Names[RTLIB::SQRT_F128] = "sqrtl"; 143 Names[RTLIB::SQRT_PPCF128] = "sqrtl"; 144 Names[RTLIB::LOG_F32] = "logf"; 145 Names[RTLIB::LOG_F64] = "log"; 146 Names[RTLIB::LOG_F80] = "logl"; 147 Names[RTLIB::LOG_F128] = "logl"; 148 Names[RTLIB::LOG_PPCF128] = "logl"; 149 Names[RTLIB::LOG2_F32] = "log2f"; 150 Names[RTLIB::LOG2_F64] = "log2"; 151 Names[RTLIB::LOG2_F80] = "log2l"; 152 Names[RTLIB::LOG2_F128] = "log2l"; 153 Names[RTLIB::LOG2_PPCF128] = "log2l"; 154 Names[RTLIB::LOG10_F32] = "log10f"; 155 Names[RTLIB::LOG10_F64] = "log10"; 156 Names[RTLIB::LOG10_F80] = "log10l"; 157 Names[RTLIB::LOG10_F128] = "log10l"; 158 Names[RTLIB::LOG10_PPCF128] = "log10l"; 159 Names[RTLIB::EXP_F32] = "expf"; 160 Names[RTLIB::EXP_F64] = "exp"; 161 Names[RTLIB::EXP_F80] = "expl"; 162 Names[RTLIB::EXP_F128] = "expl"; 163 Names[RTLIB::EXP_PPCF128] = "expl"; 164 Names[RTLIB::EXP2_F32] = "exp2f"; 165 Names[RTLIB::EXP2_F64] = "exp2"; 166 Names[RTLIB::EXP2_F80] = "exp2l"; 167 Names[RTLIB::EXP2_F128] = "exp2l"; 168 Names[RTLIB::EXP2_PPCF128] = "exp2l"; 169 Names[RTLIB::SIN_F32] = "sinf"; 170 Names[RTLIB::SIN_F64] = "sin"; 171 Names[RTLIB::SIN_F80] = "sinl"; 172 Names[RTLIB::SIN_F128] = "sinl"; 173 Names[RTLIB::SIN_PPCF128] = "sinl"; 174 Names[RTLIB::COS_F32] = "cosf"; 175 Names[RTLIB::COS_F64] = "cos"; 176 Names[RTLIB::COS_F80] = "cosl"; 177 Names[RTLIB::COS_F128] = "cosl"; 178 Names[RTLIB::COS_PPCF128] = "cosl"; 179 Names[RTLIB::POW_F32] = "powf"; 180 Names[RTLIB::POW_F64] = "pow"; 181 Names[RTLIB::POW_F80] = "powl"; 182 Names[RTLIB::POW_F128] = "powl"; 183 Names[RTLIB::POW_PPCF128] = "powl"; 184 Names[RTLIB::CEIL_F32] = "ceilf"; 185 Names[RTLIB::CEIL_F64] = "ceil"; 186 Names[RTLIB::CEIL_F80] = "ceill"; 187 Names[RTLIB::CEIL_F128] = "ceill"; 188 Names[RTLIB::CEIL_PPCF128] = "ceill"; 189 Names[RTLIB::TRUNC_F32] = "truncf"; 190 Names[RTLIB::TRUNC_F64] = "trunc"; 191 Names[RTLIB::TRUNC_F80] = "truncl"; 192 Names[RTLIB::TRUNC_F128] = "truncl"; 193 Names[RTLIB::TRUNC_PPCF128] = "truncl"; 194 Names[RTLIB::RINT_F32] = "rintf"; 195 Names[RTLIB::RINT_F64] = "rint"; 196 Names[RTLIB::RINT_F80] = "rintl"; 197 Names[RTLIB::RINT_F128] = "rintl"; 198 Names[RTLIB::RINT_PPCF128] = "rintl"; 199 Names[RTLIB::NEARBYINT_F32] = "nearbyintf"; 200 Names[RTLIB::NEARBYINT_F64] = "nearbyint"; 201 Names[RTLIB::NEARBYINT_F80] = "nearbyintl"; 202 Names[RTLIB::NEARBYINT_F128] = "nearbyintl"; 203 Names[RTLIB::NEARBYINT_PPCF128] = "nearbyintl"; 204 Names[RTLIB::ROUND_F32] = "roundf"; 205 Names[RTLIB::ROUND_F64] = "round"; 206 Names[RTLIB::ROUND_F80] = "roundl"; 207 Names[RTLIB::ROUND_F128] = "roundl"; 208 Names[RTLIB::ROUND_PPCF128] = "roundl"; 209 Names[RTLIB::FLOOR_F32] = "floorf"; 210 Names[RTLIB::FLOOR_F64] = "floor"; 211 Names[RTLIB::FLOOR_F80] = "floorl"; 212 Names[RTLIB::FLOOR_F128] = "floorl"; 213 Names[RTLIB::FLOOR_PPCF128] = "floorl"; 214 Names[RTLIB::FMIN_F32] = "fminf"; 215 Names[RTLIB::FMIN_F64] = "fmin"; 216 Names[RTLIB::FMIN_F80] = "fminl"; 217 Names[RTLIB::FMIN_F128] = "fminl"; 218 Names[RTLIB::FMIN_PPCF128] = "fminl"; 219 Names[RTLIB::FMAX_F32] = "fmaxf"; 220 Names[RTLIB::FMAX_F64] = "fmax"; 221 Names[RTLIB::FMAX_F80] = "fmaxl"; 222 Names[RTLIB::FMAX_F128] = "fmaxl"; 223 Names[RTLIB::FMAX_PPCF128] = "fmaxl"; 224 Names[RTLIB::ROUND_F32] = "roundf"; 225 Names[RTLIB::ROUND_F64] = "round"; 226 Names[RTLIB::ROUND_F80] = "roundl"; 227 Names[RTLIB::ROUND_F128] = "roundl"; 228 Names[RTLIB::ROUND_PPCF128] = "roundl"; 229 Names[RTLIB::COPYSIGN_F32] = "copysignf"; 230 Names[RTLIB::COPYSIGN_F64] = "copysign"; 231 Names[RTLIB::COPYSIGN_F80] = "copysignl"; 232 Names[RTLIB::COPYSIGN_F128] = "copysignl"; 233 Names[RTLIB::COPYSIGN_PPCF128] = "copysignl"; 234 Names[RTLIB::FPEXT_F32_PPCF128] = "__gcc_stoq"; 235 Names[RTLIB::FPEXT_F64_PPCF128] = "__gcc_dtoq"; 236 Names[RTLIB::FPEXT_F64_F128] = "__extenddftf2"; 237 Names[RTLIB::FPEXT_F32_F128] = "__extendsftf2"; 238 Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2"; 239 if (TT.isOSDarwin()) { 240 // For f16/f32 conversions, Darwin uses the standard naming scheme, instead 241 // of the gnueabi-style __gnu_*_ieee. 242 // FIXME: What about other targets? 243 Names[RTLIB::FPEXT_F16_F32] = "__extendhfsf2"; 244 Names[RTLIB::FPROUND_F32_F16] = "__truncsfhf2"; 245 } else { 246 Names[RTLIB::FPEXT_F16_F32] = "__gnu_h2f_ieee"; 247 Names[RTLIB::FPROUND_F32_F16] = "__gnu_f2h_ieee"; 248 } 249 Names[RTLIB::FPROUND_F64_F16] = "__truncdfhf2"; 250 Names[RTLIB::FPROUND_F80_F16] = "__truncxfhf2"; 251 Names[RTLIB::FPROUND_F128_F16] = "__trunctfhf2"; 252 Names[RTLIB::FPROUND_PPCF128_F16] = "__trunctfhf2"; 253 Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2"; 254 Names[RTLIB::FPROUND_F80_F32] = "__truncxfsf2"; 255 Names[RTLIB::FPROUND_F128_F32] = "__trunctfsf2"; 256 Names[RTLIB::FPROUND_PPCF128_F32] = "__gcc_qtos"; 257 Names[RTLIB::FPROUND_F80_F64] = "__truncxfdf2"; 258 Names[RTLIB::FPROUND_F128_F64] = "__trunctfdf2"; 259 Names[RTLIB::FPROUND_PPCF128_F64] = "__gcc_qtod"; 260 Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi"; 261 Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi"; 262 Names[RTLIB::FPTOSINT_F32_I128] = "__fixsfti"; 263 Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi"; 264 Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi"; 265 Names[RTLIB::FPTOSINT_F64_I128] = "__fixdfti"; 266 Names[RTLIB::FPTOSINT_F80_I32] = "__fixxfsi"; 267 Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi"; 268 Names[RTLIB::FPTOSINT_F80_I128] = "__fixxfti"; 269 Names[RTLIB::FPTOSINT_F128_I32] = "__fixtfsi"; 270 Names[RTLIB::FPTOSINT_F128_I64] = "__fixtfdi"; 271 Names[RTLIB::FPTOSINT_F128_I128] = "__fixtfti"; 272 Names[RTLIB::FPTOSINT_PPCF128_I32] = "__gcc_qtou"; 273 Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi"; 274 Names[RTLIB::FPTOSINT_PPCF128_I128] = "__fixtfti"; 275 Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi"; 276 Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi"; 277 Names[RTLIB::FPTOUINT_F32_I128] = "__fixunssfti"; 278 Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi"; 279 Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi"; 280 Names[RTLIB::FPTOUINT_F64_I128] = "__fixunsdfti"; 281 Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi"; 282 Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi"; 283 Names[RTLIB::FPTOUINT_F80_I128] = "__fixunsxfti"; 284 Names[RTLIB::FPTOUINT_F128_I32] = "__fixunstfsi"; 285 Names[RTLIB::FPTOUINT_F128_I64] = "__fixunstfdi"; 286 Names[RTLIB::FPTOUINT_F128_I128] = "__fixunstfti"; 287 Names[RTLIB::FPTOUINT_PPCF128_I32] = "__fixunstfsi"; 288 Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi"; 289 Names[RTLIB::FPTOUINT_PPCF128_I128] = "__fixunstfti"; 290 Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf"; 291 Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf"; 292 Names[RTLIB::SINTTOFP_I32_F80] = "__floatsixf"; 293 Names[RTLIB::SINTTOFP_I32_F128] = "__floatsitf"; 294 Names[RTLIB::SINTTOFP_I32_PPCF128] = "__gcc_itoq"; 295 Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf"; 296 Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf"; 297 Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf"; 298 Names[RTLIB::SINTTOFP_I64_F128] = "__floatditf"; 299 Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf"; 300 Names[RTLIB::SINTTOFP_I128_F32] = "__floattisf"; 301 Names[RTLIB::SINTTOFP_I128_F64] = "__floattidf"; 302 Names[RTLIB::SINTTOFP_I128_F80] = "__floattixf"; 303 Names[RTLIB::SINTTOFP_I128_F128] = "__floattitf"; 304 Names[RTLIB::SINTTOFP_I128_PPCF128] = "__floattitf"; 305 Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf"; 306 Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf"; 307 Names[RTLIB::UINTTOFP_I32_F80] = "__floatunsixf"; 308 Names[RTLIB::UINTTOFP_I32_F128] = "__floatunsitf"; 309 Names[RTLIB::UINTTOFP_I32_PPCF128] = "__gcc_utoq"; 310 Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf"; 311 Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf"; 312 Names[RTLIB::UINTTOFP_I64_F80] = "__floatundixf"; 313 Names[RTLIB::UINTTOFP_I64_F128] = "__floatunditf"; 314 Names[RTLIB::UINTTOFP_I64_PPCF128] = "__floatunditf"; 315 Names[RTLIB::UINTTOFP_I128_F32] = "__floatuntisf"; 316 Names[RTLIB::UINTTOFP_I128_F64] = "__floatuntidf"; 317 Names[RTLIB::UINTTOFP_I128_F80] = "__floatuntixf"; 318 Names[RTLIB::UINTTOFP_I128_F128] = "__floatuntitf"; 319 Names[RTLIB::UINTTOFP_I128_PPCF128] = "__floatuntitf"; 320 Names[RTLIB::OEQ_F32] = "__eqsf2"; 321 Names[RTLIB::OEQ_F64] = "__eqdf2"; 322 Names[RTLIB::OEQ_F128] = "__eqtf2"; 323 Names[RTLIB::OEQ_PPCF128] = "__gcc_qeq"; 324 Names[RTLIB::UNE_F32] = "__nesf2"; 325 Names[RTLIB::UNE_F64] = "__nedf2"; 326 Names[RTLIB::UNE_F128] = "__netf2"; 327 Names[RTLIB::UNE_PPCF128] = "__gcc_qne"; 328 Names[RTLIB::OGE_F32] = "__gesf2"; 329 Names[RTLIB::OGE_F64] = "__gedf2"; 330 Names[RTLIB::OGE_F128] = "__getf2"; 331 Names[RTLIB::OGE_PPCF128] = "__gcc_qge"; 332 Names[RTLIB::OLT_F32] = "__ltsf2"; 333 Names[RTLIB::OLT_F64] = "__ltdf2"; 334 Names[RTLIB::OLT_F128] = "__lttf2"; 335 Names[RTLIB::OLT_PPCF128] = "__gcc_qlt"; 336 Names[RTLIB::OLE_F32] = "__lesf2"; 337 Names[RTLIB::OLE_F64] = "__ledf2"; 338 Names[RTLIB::OLE_F128] = "__letf2"; 339 Names[RTLIB::OLE_PPCF128] = "__gcc_qle"; 340 Names[RTLIB::OGT_F32] = "__gtsf2"; 341 Names[RTLIB::OGT_F64] = "__gtdf2"; 342 Names[RTLIB::OGT_F128] = "__gttf2"; 343 Names[RTLIB::OGT_PPCF128] = "__gcc_qgt"; 344 Names[RTLIB::UO_F32] = "__unordsf2"; 345 Names[RTLIB::UO_F64] = "__unorddf2"; 346 Names[RTLIB::UO_F128] = "__unordtf2"; 347 Names[RTLIB::UO_PPCF128] = "__gcc_qunord"; 348 Names[RTLIB::O_F32] = "__unordsf2"; 349 Names[RTLIB::O_F64] = "__unorddf2"; 350 Names[RTLIB::O_F128] = "__unordtf2"; 351 Names[RTLIB::O_PPCF128] = "__gcc_qunord"; 352 Names[RTLIB::MEMCPY] = "memcpy"; 353 Names[RTLIB::MEMMOVE] = "memmove"; 354 Names[RTLIB::MEMSET] = "memset"; 355 Names[RTLIB::UNWIND_RESUME] = "_Unwind_Resume"; 356 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1] = "__sync_val_compare_and_swap_1"; 357 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2] = "__sync_val_compare_and_swap_2"; 358 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4] = "__sync_val_compare_and_swap_4"; 359 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8] = "__sync_val_compare_and_swap_8"; 360 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_16] = "__sync_val_compare_and_swap_16"; 361 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_1] = "__sync_lock_test_and_set_1"; 362 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_2] = "__sync_lock_test_and_set_2"; 363 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_4] = "__sync_lock_test_and_set_4"; 364 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_8] = "__sync_lock_test_and_set_8"; 365 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_16] = "__sync_lock_test_and_set_16"; 366 Names[RTLIB::SYNC_FETCH_AND_ADD_1] = "__sync_fetch_and_add_1"; 367 Names[RTLIB::SYNC_FETCH_AND_ADD_2] = "__sync_fetch_and_add_2"; 368 Names[RTLIB::SYNC_FETCH_AND_ADD_4] = "__sync_fetch_and_add_4"; 369 Names[RTLIB::SYNC_FETCH_AND_ADD_8] = "__sync_fetch_and_add_8"; 370 Names[RTLIB::SYNC_FETCH_AND_ADD_16] = "__sync_fetch_and_add_16"; 371 Names[RTLIB::SYNC_FETCH_AND_SUB_1] = "__sync_fetch_and_sub_1"; 372 Names[RTLIB::SYNC_FETCH_AND_SUB_2] = "__sync_fetch_and_sub_2"; 373 Names[RTLIB::SYNC_FETCH_AND_SUB_4] = "__sync_fetch_and_sub_4"; 374 Names[RTLIB::SYNC_FETCH_AND_SUB_8] = "__sync_fetch_and_sub_8"; 375 Names[RTLIB::SYNC_FETCH_AND_SUB_16] = "__sync_fetch_and_sub_16"; 376 Names[RTLIB::SYNC_FETCH_AND_AND_1] = "__sync_fetch_and_and_1"; 377 Names[RTLIB::SYNC_FETCH_AND_AND_2] = "__sync_fetch_and_and_2"; 378 Names[RTLIB::SYNC_FETCH_AND_AND_4] = "__sync_fetch_and_and_4"; 379 Names[RTLIB::SYNC_FETCH_AND_AND_8] = "__sync_fetch_and_and_8"; 380 Names[RTLIB::SYNC_FETCH_AND_AND_16] = "__sync_fetch_and_and_16"; 381 Names[RTLIB::SYNC_FETCH_AND_OR_1] = "__sync_fetch_and_or_1"; 382 Names[RTLIB::SYNC_FETCH_AND_OR_2] = "__sync_fetch_and_or_2"; 383 Names[RTLIB::SYNC_FETCH_AND_OR_4] = "__sync_fetch_and_or_4"; 384 Names[RTLIB::SYNC_FETCH_AND_OR_8] = "__sync_fetch_and_or_8"; 385 Names[RTLIB::SYNC_FETCH_AND_OR_16] = "__sync_fetch_and_or_16"; 386 Names[RTLIB::SYNC_FETCH_AND_XOR_1] = "__sync_fetch_and_xor_1"; 387 Names[RTLIB::SYNC_FETCH_AND_XOR_2] = "__sync_fetch_and_xor_2"; 388 Names[RTLIB::SYNC_FETCH_AND_XOR_4] = "__sync_fetch_and_xor_4"; 389 Names[RTLIB::SYNC_FETCH_AND_XOR_8] = "__sync_fetch_and_xor_8"; 390 Names[RTLIB::SYNC_FETCH_AND_XOR_16] = "__sync_fetch_and_xor_16"; 391 Names[RTLIB::SYNC_FETCH_AND_NAND_1] = "__sync_fetch_and_nand_1"; 392 Names[RTLIB::SYNC_FETCH_AND_NAND_2] = "__sync_fetch_and_nand_2"; 393 Names[RTLIB::SYNC_FETCH_AND_NAND_4] = "__sync_fetch_and_nand_4"; 394 Names[RTLIB::SYNC_FETCH_AND_NAND_8] = "__sync_fetch_and_nand_8"; 395 Names[RTLIB::SYNC_FETCH_AND_NAND_16] = "__sync_fetch_and_nand_16"; 396 Names[RTLIB::SYNC_FETCH_AND_MAX_1] = "__sync_fetch_and_max_1"; 397 Names[RTLIB::SYNC_FETCH_AND_MAX_2] = "__sync_fetch_and_max_2"; 398 Names[RTLIB::SYNC_FETCH_AND_MAX_4] = "__sync_fetch_and_max_4"; 399 Names[RTLIB::SYNC_FETCH_AND_MAX_8] = "__sync_fetch_and_max_8"; 400 Names[RTLIB::SYNC_FETCH_AND_MAX_16] = "__sync_fetch_and_max_16"; 401 Names[RTLIB::SYNC_FETCH_AND_UMAX_1] = "__sync_fetch_and_umax_1"; 402 Names[RTLIB::SYNC_FETCH_AND_UMAX_2] = "__sync_fetch_and_umax_2"; 403 Names[RTLIB::SYNC_FETCH_AND_UMAX_4] = "__sync_fetch_and_umax_4"; 404 Names[RTLIB::SYNC_FETCH_AND_UMAX_8] = "__sync_fetch_and_umax_8"; 405 Names[RTLIB::SYNC_FETCH_AND_UMAX_16] = "__sync_fetch_and_umax_16"; 406 Names[RTLIB::SYNC_FETCH_AND_MIN_1] = "__sync_fetch_and_min_1"; 407 Names[RTLIB::SYNC_FETCH_AND_MIN_2] = "__sync_fetch_and_min_2"; 408 Names[RTLIB::SYNC_FETCH_AND_MIN_4] = "__sync_fetch_and_min_4"; 409 Names[RTLIB::SYNC_FETCH_AND_MIN_8] = "__sync_fetch_and_min_8"; 410 Names[RTLIB::SYNC_FETCH_AND_MIN_16] = "__sync_fetch_and_min_16"; 411 Names[RTLIB::SYNC_FETCH_AND_UMIN_1] = "__sync_fetch_and_umin_1"; 412 Names[RTLIB::SYNC_FETCH_AND_UMIN_2] = "__sync_fetch_and_umin_2"; 413 Names[RTLIB::SYNC_FETCH_AND_UMIN_4] = "__sync_fetch_and_umin_4"; 414 Names[RTLIB::SYNC_FETCH_AND_UMIN_8] = "__sync_fetch_and_umin_8"; 415 Names[RTLIB::SYNC_FETCH_AND_UMIN_16] = "__sync_fetch_and_umin_16"; 416 417 Names[RTLIB::ATOMIC_LOAD] = "__atomic_load"; 418 Names[RTLIB::ATOMIC_LOAD_1] = "__atomic_load_1"; 419 Names[RTLIB::ATOMIC_LOAD_2] = "__atomic_load_2"; 420 Names[RTLIB::ATOMIC_LOAD_4] = "__atomic_load_4"; 421 Names[RTLIB::ATOMIC_LOAD_8] = "__atomic_load_8"; 422 Names[RTLIB::ATOMIC_LOAD_16] = "__atomic_load_16"; 423 424 Names[RTLIB::ATOMIC_STORE] = "__atomic_store"; 425 Names[RTLIB::ATOMIC_STORE_1] = "__atomic_store_1"; 426 Names[RTLIB::ATOMIC_STORE_2] = "__atomic_store_2"; 427 Names[RTLIB::ATOMIC_STORE_4] = "__atomic_store_4"; 428 Names[RTLIB::ATOMIC_STORE_8] = "__atomic_store_8"; 429 Names[RTLIB::ATOMIC_STORE_16] = "__atomic_store_16"; 430 431 Names[RTLIB::ATOMIC_EXCHANGE] = "__atomic_exchange"; 432 Names[RTLIB::ATOMIC_EXCHANGE_1] = "__atomic_exchange_1"; 433 Names[RTLIB::ATOMIC_EXCHANGE_2] = "__atomic_exchange_2"; 434 Names[RTLIB::ATOMIC_EXCHANGE_4] = "__atomic_exchange_4"; 435 Names[RTLIB::ATOMIC_EXCHANGE_8] = "__atomic_exchange_8"; 436 Names[RTLIB::ATOMIC_EXCHANGE_16] = "__atomic_exchange_16"; 437 438 Names[RTLIB::ATOMIC_COMPARE_EXCHANGE] = "__atomic_compare_exchange"; 439 Names[RTLIB::ATOMIC_COMPARE_EXCHANGE_1] = "__atomic_compare_exchange_1"; 440 Names[RTLIB::ATOMIC_COMPARE_EXCHANGE_2] = "__atomic_compare_exchange_2"; 441 Names[RTLIB::ATOMIC_COMPARE_EXCHANGE_4] = "__atomic_compare_exchange_4"; 442 Names[RTLIB::ATOMIC_COMPARE_EXCHANGE_8] = "__atomic_compare_exchange_8"; 443 Names[RTLIB::ATOMIC_COMPARE_EXCHANGE_16] = "__atomic_compare_exchange_16"; 444 445 Names[RTLIB::ATOMIC_FETCH_ADD_1] = "__atomic_fetch_add_1"; 446 Names[RTLIB::ATOMIC_FETCH_ADD_2] = "__atomic_fetch_add_2"; 447 Names[RTLIB::ATOMIC_FETCH_ADD_4] = "__atomic_fetch_add_4"; 448 Names[RTLIB::ATOMIC_FETCH_ADD_8] = "__atomic_fetch_add_8"; 449 Names[RTLIB::ATOMIC_FETCH_ADD_16] = "__atomic_fetch_add_16"; 450 Names[RTLIB::ATOMIC_FETCH_SUB_1] = "__atomic_fetch_sub_1"; 451 Names[RTLIB::ATOMIC_FETCH_SUB_2] = "__atomic_fetch_sub_2"; 452 Names[RTLIB::ATOMIC_FETCH_SUB_4] = "__atomic_fetch_sub_4"; 453 Names[RTLIB::ATOMIC_FETCH_SUB_8] = "__atomic_fetch_sub_8"; 454 Names[RTLIB::ATOMIC_FETCH_SUB_16] = "__atomic_fetch_sub_16"; 455 Names[RTLIB::ATOMIC_FETCH_AND_1] = "__atomic_fetch_and_1"; 456 Names[RTLIB::ATOMIC_FETCH_AND_2] = "__atomic_fetch_and_2"; 457 Names[RTLIB::ATOMIC_FETCH_AND_4] = "__atomic_fetch_and_4"; 458 Names[RTLIB::ATOMIC_FETCH_AND_8] = "__atomic_fetch_and_8"; 459 Names[RTLIB::ATOMIC_FETCH_AND_16] = "__atomic_fetch_and_16"; 460 Names[RTLIB::ATOMIC_FETCH_OR_1] = "__atomic_fetch_or_1"; 461 Names[RTLIB::ATOMIC_FETCH_OR_2] = "__atomic_fetch_or_2"; 462 Names[RTLIB::ATOMIC_FETCH_OR_4] = "__atomic_fetch_or_4"; 463 Names[RTLIB::ATOMIC_FETCH_OR_8] = "__atomic_fetch_or_8"; 464 Names[RTLIB::ATOMIC_FETCH_OR_16] = "__atomic_fetch_or_16"; 465 Names[RTLIB::ATOMIC_FETCH_XOR_1] = "__atomic_fetch_xor_1"; 466 Names[RTLIB::ATOMIC_FETCH_XOR_2] = "__atomic_fetch_xor_2"; 467 Names[RTLIB::ATOMIC_FETCH_XOR_4] = "__atomic_fetch_xor_4"; 468 Names[RTLIB::ATOMIC_FETCH_XOR_8] = "__atomic_fetch_xor_8"; 469 Names[RTLIB::ATOMIC_FETCH_XOR_16] = "__atomic_fetch_xor_16"; 470 Names[RTLIB::ATOMIC_FETCH_NAND_1] = "__atomic_fetch_nand_1"; 471 Names[RTLIB::ATOMIC_FETCH_NAND_2] = "__atomic_fetch_nand_2"; 472 Names[RTLIB::ATOMIC_FETCH_NAND_4] = "__atomic_fetch_nand_4"; 473 Names[RTLIB::ATOMIC_FETCH_NAND_8] = "__atomic_fetch_nand_8"; 474 Names[RTLIB::ATOMIC_FETCH_NAND_16] = "__atomic_fetch_nand_16"; 475 476 if (TT.isGNUEnvironment()) { 477 Names[RTLIB::SINCOS_F32] = "sincosf"; 478 Names[RTLIB::SINCOS_F64] = "sincos"; 479 Names[RTLIB::SINCOS_F80] = "sincosl"; 480 Names[RTLIB::SINCOS_F128] = "sincosl"; 481 Names[RTLIB::SINCOS_PPCF128] = "sincosl"; 482 } 483 484 if (!TT.isOSOpenBSD()) { 485 Names[RTLIB::STACKPROTECTOR_CHECK_FAIL] = "__stack_chk_fail"; 486 } 487 488 Names[RTLIB::DEOPTIMIZE] = "__llvm_deoptimize"; 489 } 490 491 /// Set default libcall CallingConvs. 492 static void InitLibcallCallingConvs(CallingConv::ID *CCs) { 493 for (int LC = 0; LC < RTLIB::UNKNOWN_LIBCALL; ++LC) 494 CCs[LC] = CallingConv::C; 495 } 496 497 /// getFPEXT - Return the FPEXT_*_* value for the given types, or 498 /// UNKNOWN_LIBCALL if there is none. 499 RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) { 500 if (OpVT == MVT::f16) { 501 if (RetVT == MVT::f32) 502 return FPEXT_F16_F32; 503 } else if (OpVT == MVT::f32) { 504 if (RetVT == MVT::f64) 505 return FPEXT_F32_F64; 506 if (RetVT == MVT::f128) 507 return FPEXT_F32_F128; 508 if (RetVT == MVT::ppcf128) 509 return FPEXT_F32_PPCF128; 510 } else if (OpVT == MVT::f64) { 511 if (RetVT == MVT::f128) 512 return FPEXT_F64_F128; 513 else if (RetVT == MVT::ppcf128) 514 return FPEXT_F64_PPCF128; 515 } 516 517 return UNKNOWN_LIBCALL; 518 } 519 520 /// getFPROUND - Return the FPROUND_*_* value for the given types, or 521 /// UNKNOWN_LIBCALL if there is none. 522 RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) { 523 if (RetVT == MVT::f16) { 524 if (OpVT == MVT::f32) 525 return FPROUND_F32_F16; 526 if (OpVT == MVT::f64) 527 return FPROUND_F64_F16; 528 if (OpVT == MVT::f80) 529 return FPROUND_F80_F16; 530 if (OpVT == MVT::f128) 531 return FPROUND_F128_F16; 532 if (OpVT == MVT::ppcf128) 533 return FPROUND_PPCF128_F16; 534 } else if (RetVT == MVT::f32) { 535 if (OpVT == MVT::f64) 536 return FPROUND_F64_F32; 537 if (OpVT == MVT::f80) 538 return FPROUND_F80_F32; 539 if (OpVT == MVT::f128) 540 return FPROUND_F128_F32; 541 if (OpVT == MVT::ppcf128) 542 return FPROUND_PPCF128_F32; 543 } else if (RetVT == MVT::f64) { 544 if (OpVT == MVT::f80) 545 return FPROUND_F80_F64; 546 if (OpVT == MVT::f128) 547 return FPROUND_F128_F64; 548 if (OpVT == MVT::ppcf128) 549 return FPROUND_PPCF128_F64; 550 } 551 552 return UNKNOWN_LIBCALL; 553 } 554 555 /// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or 556 /// UNKNOWN_LIBCALL if there is none. 557 RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT, EVT RetVT) { 558 if (OpVT == MVT::f32) { 559 if (RetVT == MVT::i32) 560 return FPTOSINT_F32_I32; 561 if (RetVT == MVT::i64) 562 return FPTOSINT_F32_I64; 563 if (RetVT == MVT::i128) 564 return FPTOSINT_F32_I128; 565 } else if (OpVT == MVT::f64) { 566 if (RetVT == MVT::i32) 567 return FPTOSINT_F64_I32; 568 if (RetVT == MVT::i64) 569 return FPTOSINT_F64_I64; 570 if (RetVT == MVT::i128) 571 return FPTOSINT_F64_I128; 572 } else if (OpVT == MVT::f80) { 573 if (RetVT == MVT::i32) 574 return FPTOSINT_F80_I32; 575 if (RetVT == MVT::i64) 576 return FPTOSINT_F80_I64; 577 if (RetVT == MVT::i128) 578 return FPTOSINT_F80_I128; 579 } else if (OpVT == MVT::f128) { 580 if (RetVT == MVT::i32) 581 return FPTOSINT_F128_I32; 582 if (RetVT == MVT::i64) 583 return FPTOSINT_F128_I64; 584 if (RetVT == MVT::i128) 585 return FPTOSINT_F128_I128; 586 } else if (OpVT == MVT::ppcf128) { 587 if (RetVT == MVT::i32) 588 return FPTOSINT_PPCF128_I32; 589 if (RetVT == MVT::i64) 590 return FPTOSINT_PPCF128_I64; 591 if (RetVT == MVT::i128) 592 return FPTOSINT_PPCF128_I128; 593 } 594 return UNKNOWN_LIBCALL; 595 } 596 597 /// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or 598 /// UNKNOWN_LIBCALL if there is none. 599 RTLIB::Libcall RTLIB::getFPTOUINT(EVT OpVT, EVT RetVT) { 600 if (OpVT == MVT::f32) { 601 if (RetVT == MVT::i32) 602 return FPTOUINT_F32_I32; 603 if (RetVT == MVT::i64) 604 return FPTOUINT_F32_I64; 605 if (RetVT == MVT::i128) 606 return FPTOUINT_F32_I128; 607 } else if (OpVT == MVT::f64) { 608 if (RetVT == MVT::i32) 609 return FPTOUINT_F64_I32; 610 if (RetVT == MVT::i64) 611 return FPTOUINT_F64_I64; 612 if (RetVT == MVT::i128) 613 return FPTOUINT_F64_I128; 614 } else if (OpVT == MVT::f80) { 615 if (RetVT == MVT::i32) 616 return FPTOUINT_F80_I32; 617 if (RetVT == MVT::i64) 618 return FPTOUINT_F80_I64; 619 if (RetVT == MVT::i128) 620 return FPTOUINT_F80_I128; 621 } else if (OpVT == MVT::f128) { 622 if (RetVT == MVT::i32) 623 return FPTOUINT_F128_I32; 624 if (RetVT == MVT::i64) 625 return FPTOUINT_F128_I64; 626 if (RetVT == MVT::i128) 627 return FPTOUINT_F128_I128; 628 } else if (OpVT == MVT::ppcf128) { 629 if (RetVT == MVT::i32) 630 return FPTOUINT_PPCF128_I32; 631 if (RetVT == MVT::i64) 632 return FPTOUINT_PPCF128_I64; 633 if (RetVT == MVT::i128) 634 return FPTOUINT_PPCF128_I128; 635 } 636 return UNKNOWN_LIBCALL; 637 } 638 639 /// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or 640 /// UNKNOWN_LIBCALL if there is none. 641 RTLIB::Libcall RTLIB::getSINTTOFP(EVT OpVT, EVT RetVT) { 642 if (OpVT == MVT::i32) { 643 if (RetVT == MVT::f32) 644 return SINTTOFP_I32_F32; 645 if (RetVT == MVT::f64) 646 return SINTTOFP_I32_F64; 647 if (RetVT == MVT::f80) 648 return SINTTOFP_I32_F80; 649 if (RetVT == MVT::f128) 650 return SINTTOFP_I32_F128; 651 if (RetVT == MVT::ppcf128) 652 return SINTTOFP_I32_PPCF128; 653 } else if (OpVT == MVT::i64) { 654 if (RetVT == MVT::f32) 655 return SINTTOFP_I64_F32; 656 if (RetVT == MVT::f64) 657 return SINTTOFP_I64_F64; 658 if (RetVT == MVT::f80) 659 return SINTTOFP_I64_F80; 660 if (RetVT == MVT::f128) 661 return SINTTOFP_I64_F128; 662 if (RetVT == MVT::ppcf128) 663 return SINTTOFP_I64_PPCF128; 664 } else if (OpVT == MVT::i128) { 665 if (RetVT == MVT::f32) 666 return SINTTOFP_I128_F32; 667 if (RetVT == MVT::f64) 668 return SINTTOFP_I128_F64; 669 if (RetVT == MVT::f80) 670 return SINTTOFP_I128_F80; 671 if (RetVT == MVT::f128) 672 return SINTTOFP_I128_F128; 673 if (RetVT == MVT::ppcf128) 674 return SINTTOFP_I128_PPCF128; 675 } 676 return UNKNOWN_LIBCALL; 677 } 678 679 /// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or 680 /// UNKNOWN_LIBCALL if there is none. 681 RTLIB::Libcall RTLIB::getUINTTOFP(EVT OpVT, EVT RetVT) { 682 if (OpVT == MVT::i32) { 683 if (RetVT == MVT::f32) 684 return UINTTOFP_I32_F32; 685 if (RetVT == MVT::f64) 686 return UINTTOFP_I32_F64; 687 if (RetVT == MVT::f80) 688 return UINTTOFP_I32_F80; 689 if (RetVT == MVT::f128) 690 return UINTTOFP_I32_F128; 691 if (RetVT == MVT::ppcf128) 692 return UINTTOFP_I32_PPCF128; 693 } else if (OpVT == MVT::i64) { 694 if (RetVT == MVT::f32) 695 return UINTTOFP_I64_F32; 696 if (RetVT == MVT::f64) 697 return UINTTOFP_I64_F64; 698 if (RetVT == MVT::f80) 699 return UINTTOFP_I64_F80; 700 if (RetVT == MVT::f128) 701 return UINTTOFP_I64_F128; 702 if (RetVT == MVT::ppcf128) 703 return UINTTOFP_I64_PPCF128; 704 } else if (OpVT == MVT::i128) { 705 if (RetVT == MVT::f32) 706 return UINTTOFP_I128_F32; 707 if (RetVT == MVT::f64) 708 return UINTTOFP_I128_F64; 709 if (RetVT == MVT::f80) 710 return UINTTOFP_I128_F80; 711 if (RetVT == MVT::f128) 712 return UINTTOFP_I128_F128; 713 if (RetVT == MVT::ppcf128) 714 return UINTTOFP_I128_PPCF128; 715 } 716 return UNKNOWN_LIBCALL; 717 } 718 719 RTLIB::Libcall RTLIB::getSYNC(unsigned Opc, MVT VT) { 720 #define OP_TO_LIBCALL(Name, Enum) \ 721 case Name: \ 722 switch (VT.SimpleTy) { \ 723 default: \ 724 return UNKNOWN_LIBCALL; \ 725 case MVT::i8: \ 726 return Enum##_1; \ 727 case MVT::i16: \ 728 return Enum##_2; \ 729 case MVT::i32: \ 730 return Enum##_4; \ 731 case MVT::i64: \ 732 return Enum##_8; \ 733 case MVT::i128: \ 734 return Enum##_16; \ 735 } 736 737 switch (Opc) { 738 OP_TO_LIBCALL(ISD::ATOMIC_SWAP, SYNC_LOCK_TEST_AND_SET) 739 OP_TO_LIBCALL(ISD::ATOMIC_CMP_SWAP, SYNC_VAL_COMPARE_AND_SWAP) 740 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_ADD, SYNC_FETCH_AND_ADD) 741 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_SUB, SYNC_FETCH_AND_SUB) 742 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_AND, SYNC_FETCH_AND_AND) 743 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_OR, SYNC_FETCH_AND_OR) 744 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_XOR, SYNC_FETCH_AND_XOR) 745 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_NAND, SYNC_FETCH_AND_NAND) 746 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_MAX, SYNC_FETCH_AND_MAX) 747 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_UMAX, SYNC_FETCH_AND_UMAX) 748 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_MIN, SYNC_FETCH_AND_MIN) 749 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_UMIN, SYNC_FETCH_AND_UMIN) 750 } 751 752 #undef OP_TO_LIBCALL 753 754 return UNKNOWN_LIBCALL; 755 } 756 757 /// InitCmpLibcallCCs - Set default comparison libcall CC. 758 /// 759 static void InitCmpLibcallCCs(ISD::CondCode *CCs) { 760 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL); 761 CCs[RTLIB::OEQ_F32] = ISD::SETEQ; 762 CCs[RTLIB::OEQ_F64] = ISD::SETEQ; 763 CCs[RTLIB::OEQ_F128] = ISD::SETEQ; 764 CCs[RTLIB::OEQ_PPCF128] = ISD::SETEQ; 765 CCs[RTLIB::UNE_F32] = ISD::SETNE; 766 CCs[RTLIB::UNE_F64] = ISD::SETNE; 767 CCs[RTLIB::UNE_F128] = ISD::SETNE; 768 CCs[RTLIB::UNE_PPCF128] = ISD::SETNE; 769 CCs[RTLIB::OGE_F32] = ISD::SETGE; 770 CCs[RTLIB::OGE_F64] = ISD::SETGE; 771 CCs[RTLIB::OGE_F128] = ISD::SETGE; 772 CCs[RTLIB::OGE_PPCF128] = ISD::SETGE; 773 CCs[RTLIB::OLT_F32] = ISD::SETLT; 774 CCs[RTLIB::OLT_F64] = ISD::SETLT; 775 CCs[RTLIB::OLT_F128] = ISD::SETLT; 776 CCs[RTLIB::OLT_PPCF128] = ISD::SETLT; 777 CCs[RTLIB::OLE_F32] = ISD::SETLE; 778 CCs[RTLIB::OLE_F64] = ISD::SETLE; 779 CCs[RTLIB::OLE_F128] = ISD::SETLE; 780 CCs[RTLIB::OLE_PPCF128] = ISD::SETLE; 781 CCs[RTLIB::OGT_F32] = ISD::SETGT; 782 CCs[RTLIB::OGT_F64] = ISD::SETGT; 783 CCs[RTLIB::OGT_F128] = ISD::SETGT; 784 CCs[RTLIB::OGT_PPCF128] = ISD::SETGT; 785 CCs[RTLIB::UO_F32] = ISD::SETNE; 786 CCs[RTLIB::UO_F64] = ISD::SETNE; 787 CCs[RTLIB::UO_F128] = ISD::SETNE; 788 CCs[RTLIB::UO_PPCF128] = ISD::SETNE; 789 CCs[RTLIB::O_F32] = ISD::SETEQ; 790 CCs[RTLIB::O_F64] = ISD::SETEQ; 791 CCs[RTLIB::O_F128] = ISD::SETEQ; 792 CCs[RTLIB::O_PPCF128] = ISD::SETEQ; 793 } 794 795 /// NOTE: The TargetMachine owns TLOF. 796 TargetLoweringBase::TargetLoweringBase(const TargetMachine &tm) : TM(tm) { 797 initActions(); 798 799 // Perform these initializations only once. 800 MaxStoresPerMemset = MaxStoresPerMemcpy = MaxStoresPerMemmove = 8; 801 MaxStoresPerMemsetOptSize = MaxStoresPerMemcpyOptSize 802 = MaxStoresPerMemmoveOptSize = 4; 803 UseUnderscoreSetJmp = false; 804 UseUnderscoreLongJmp = false; 805 SelectIsExpensive = false; 806 HasMultipleConditionRegisters = false; 807 HasExtractBitsInsn = false; 808 JumpIsExpensive = JumpIsExpensiveOverride; 809 PredictableSelectIsExpensive = false; 810 MaskAndBranchFoldingIsLegal = false; 811 EnableExtLdPromotion = false; 812 HasFloatingPointExceptions = true; 813 StackPointerRegisterToSaveRestore = 0; 814 BooleanContents = UndefinedBooleanContent; 815 BooleanFloatContents = UndefinedBooleanContent; 816 BooleanVectorContents = UndefinedBooleanContent; 817 SchedPreferenceInfo = Sched::ILP; 818 JumpBufSize = 0; 819 JumpBufAlignment = 0; 820 MinFunctionAlignment = 0; 821 PrefFunctionAlignment = 0; 822 PrefLoopAlignment = 0; 823 GatherAllAliasesMaxDepth = 6; 824 MinStackArgumentAlignment = 1; 825 MinimumJumpTableEntries = 4; 826 // TODO: the default will be switched to 0 in the next commit, along 827 // with the Target-specific changes necessary. 828 MaxAtomicSizeInBitsSupported = 1024; 829 830 MinCmpXchgSizeInBits = 0; 831 832 std::fill(std::begin(LibcallRoutineNames), std::end(LibcallRoutineNames), nullptr); 833 834 InitLibcallNames(LibcallRoutineNames, TM.getTargetTriple()); 835 InitCmpLibcallCCs(CmpLibcallCCs); 836 InitLibcallCallingConvs(LibcallCallingConvs); 837 } 838 839 void TargetLoweringBase::initActions() { 840 // All operations default to being supported. 841 memset(OpActions, 0, sizeof(OpActions)); 842 memset(LoadExtActions, 0, sizeof(LoadExtActions)); 843 memset(TruncStoreActions, 0, sizeof(TruncStoreActions)); 844 memset(IndexedModeActions, 0, sizeof(IndexedModeActions)); 845 memset(CondCodeActions, 0, sizeof(CondCodeActions)); 846 std::fill(std::begin(RegClassForVT), std::end(RegClassForVT), nullptr); 847 std::fill(std::begin(TargetDAGCombineArray), 848 std::end(TargetDAGCombineArray), 0); 849 850 // Set default actions for various operations. 851 for (MVT VT : MVT::all_valuetypes()) { 852 // Default all indexed load / store to expand. 853 for (unsigned IM = (unsigned)ISD::PRE_INC; 854 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) { 855 setIndexedLoadAction(IM, VT, Expand); 856 setIndexedStoreAction(IM, VT, Expand); 857 } 858 859 // Most backends expect to see the node which just returns the value loaded. 860 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Expand); 861 862 // These operations default to expand. 863 setOperationAction(ISD::FGETSIGN, VT, Expand); 864 setOperationAction(ISD::CONCAT_VECTORS, VT, Expand); 865 setOperationAction(ISD::FMINNUM, VT, Expand); 866 setOperationAction(ISD::FMAXNUM, VT, Expand); 867 setOperationAction(ISD::FMINNAN, VT, Expand); 868 setOperationAction(ISD::FMAXNAN, VT, Expand); 869 setOperationAction(ISD::FMAD, VT, Expand); 870 setOperationAction(ISD::SMIN, VT, Expand); 871 setOperationAction(ISD::SMAX, VT, Expand); 872 setOperationAction(ISD::UMIN, VT, Expand); 873 setOperationAction(ISD::UMAX, VT, Expand); 874 875 // Overflow operations default to expand 876 setOperationAction(ISD::SADDO, VT, Expand); 877 setOperationAction(ISD::SSUBO, VT, Expand); 878 setOperationAction(ISD::UADDO, VT, Expand); 879 setOperationAction(ISD::USUBO, VT, Expand); 880 setOperationAction(ISD::SMULO, VT, Expand); 881 setOperationAction(ISD::UMULO, VT, Expand); 882 883 // These default to Expand so they will be expanded to CTLZ/CTTZ by default. 884 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand); 885 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand); 886 887 setOperationAction(ISD::BITREVERSE, VT, Expand); 888 889 // These library functions default to expand. 890 setOperationAction(ISD::FROUND, VT, Expand); 891 892 // These operations default to expand for vector types. 893 if (VT.isVector()) { 894 setOperationAction(ISD::FCOPYSIGN, VT, Expand); 895 setOperationAction(ISD::ANY_EXTEND_VECTOR_INREG, VT, Expand); 896 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, VT, Expand); 897 setOperationAction(ISD::ZERO_EXTEND_VECTOR_INREG, VT, Expand); 898 } 899 900 // For most targets @llvm.get.dynamic.area.offset just returns 0. 901 setOperationAction(ISD::GET_DYNAMIC_AREA_OFFSET, VT, Expand); 902 } 903 904 // Most targets ignore the @llvm.prefetch intrinsic. 905 setOperationAction(ISD::PREFETCH, MVT::Other, Expand); 906 907 // Most targets also ignore the @llvm.readcyclecounter intrinsic. 908 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Expand); 909 910 // ConstantFP nodes default to expand. Targets can either change this to 911 // Legal, in which case all fp constants are legal, or use isFPImmLegal() 912 // to optimize expansions for certain constants. 913 setOperationAction(ISD::ConstantFP, MVT::f16, Expand); 914 setOperationAction(ISD::ConstantFP, MVT::f32, Expand); 915 setOperationAction(ISD::ConstantFP, MVT::f64, Expand); 916 setOperationAction(ISD::ConstantFP, MVT::f80, Expand); 917 setOperationAction(ISD::ConstantFP, MVT::f128, Expand); 918 919 // These library functions default to expand. 920 for (MVT VT : {MVT::f32, MVT::f64, MVT::f128}) { 921 setOperationAction(ISD::FLOG , VT, Expand); 922 setOperationAction(ISD::FLOG2, VT, Expand); 923 setOperationAction(ISD::FLOG10, VT, Expand); 924 setOperationAction(ISD::FEXP , VT, Expand); 925 setOperationAction(ISD::FEXP2, VT, Expand); 926 setOperationAction(ISD::FFLOOR, VT, Expand); 927 setOperationAction(ISD::FNEARBYINT, VT, Expand); 928 setOperationAction(ISD::FCEIL, VT, Expand); 929 setOperationAction(ISD::FRINT, VT, Expand); 930 setOperationAction(ISD::FTRUNC, VT, Expand); 931 setOperationAction(ISD::FROUND, VT, Expand); 932 } 933 934 // Default ISD::TRAP to expand (which turns it into abort). 935 setOperationAction(ISD::TRAP, MVT::Other, Expand); 936 937 // On most systems, DEBUGTRAP and TRAP have no difference. The "Expand" 938 // here is to inform DAG Legalizer to replace DEBUGTRAP with TRAP. 939 // 940 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Expand); 941 } 942 943 MVT TargetLoweringBase::getScalarShiftAmountTy(const DataLayout &DL, 944 EVT) const { 945 return MVT::getIntegerVT(8 * DL.getPointerSize(0)); 946 } 947 948 EVT TargetLoweringBase::getShiftAmountTy(EVT LHSTy, 949 const DataLayout &DL) const { 950 assert(LHSTy.isInteger() && "Shift amount is not an integer type!"); 951 if (LHSTy.isVector()) 952 return LHSTy; 953 return getScalarShiftAmountTy(DL, LHSTy); 954 } 955 956 bool TargetLoweringBase::canOpTrap(unsigned Op, EVT VT) const { 957 assert(isTypeLegal(VT)); 958 switch (Op) { 959 default: 960 return false; 961 case ISD::SDIV: 962 case ISD::UDIV: 963 case ISD::SREM: 964 case ISD::UREM: 965 return true; 966 } 967 } 968 969 void TargetLoweringBase::setJumpIsExpensive(bool isExpensive) { 970 // If the command-line option was specified, ignore this request. 971 if (!JumpIsExpensiveOverride.getNumOccurrences()) 972 JumpIsExpensive = isExpensive; 973 } 974 975 TargetLoweringBase::LegalizeKind 976 TargetLoweringBase::getTypeConversion(LLVMContext &Context, EVT VT) const { 977 // If this is a simple type, use the ComputeRegisterProp mechanism. 978 if (VT.isSimple()) { 979 MVT SVT = VT.getSimpleVT(); 980 assert((unsigned)SVT.SimpleTy < array_lengthof(TransformToType)); 981 MVT NVT = TransformToType[SVT.SimpleTy]; 982 LegalizeTypeAction LA = ValueTypeActions.getTypeAction(SVT); 983 984 assert((LA == TypeLegal || LA == TypeSoftenFloat || 985 ValueTypeActions.getTypeAction(NVT) != TypePromoteInteger) && 986 "Promote may not follow Expand or Promote"); 987 988 if (LA == TypeSplitVector) 989 return LegalizeKind(LA, 990 EVT::getVectorVT(Context, SVT.getVectorElementType(), 991 SVT.getVectorNumElements() / 2)); 992 if (LA == TypeScalarizeVector) 993 return LegalizeKind(LA, SVT.getVectorElementType()); 994 return LegalizeKind(LA, NVT); 995 } 996 997 // Handle Extended Scalar Types. 998 if (!VT.isVector()) { 999 assert(VT.isInteger() && "Float types must be simple"); 1000 unsigned BitSize = VT.getSizeInBits(); 1001 // First promote to a power-of-two size, then expand if necessary. 1002 if (BitSize < 8 || !isPowerOf2_32(BitSize)) { 1003 EVT NVT = VT.getRoundIntegerType(Context); 1004 assert(NVT != VT && "Unable to round integer VT"); 1005 LegalizeKind NextStep = getTypeConversion(Context, NVT); 1006 // Avoid multi-step promotion. 1007 if (NextStep.first == TypePromoteInteger) 1008 return NextStep; 1009 // Return rounded integer type. 1010 return LegalizeKind(TypePromoteInteger, NVT); 1011 } 1012 1013 return LegalizeKind(TypeExpandInteger, 1014 EVT::getIntegerVT(Context, VT.getSizeInBits() / 2)); 1015 } 1016 1017 // Handle vector types. 1018 unsigned NumElts = VT.getVectorNumElements(); 1019 EVT EltVT = VT.getVectorElementType(); 1020 1021 // Vectors with only one element are always scalarized. 1022 if (NumElts == 1) 1023 return LegalizeKind(TypeScalarizeVector, EltVT); 1024 1025 // Try to widen vector elements until the element type is a power of two and 1026 // promote it to a legal type later on, for example: 1027 // <3 x i8> -> <4 x i8> -> <4 x i32> 1028 if (EltVT.isInteger()) { 1029 // Vectors with a number of elements that is not a power of two are always 1030 // widened, for example <3 x i8> -> <4 x i8>. 1031 if (!VT.isPow2VectorType()) { 1032 NumElts = (unsigned)NextPowerOf2(NumElts); 1033 EVT NVT = EVT::getVectorVT(Context, EltVT, NumElts); 1034 return LegalizeKind(TypeWidenVector, NVT); 1035 } 1036 1037 // Examine the element type. 1038 LegalizeKind LK = getTypeConversion(Context, EltVT); 1039 1040 // If type is to be expanded, split the vector. 1041 // <4 x i140> -> <2 x i140> 1042 if (LK.first == TypeExpandInteger) 1043 return LegalizeKind(TypeSplitVector, 1044 EVT::getVectorVT(Context, EltVT, NumElts / 2)); 1045 1046 // Promote the integer element types until a legal vector type is found 1047 // or until the element integer type is too big. If a legal type was not 1048 // found, fallback to the usual mechanism of widening/splitting the 1049 // vector. 1050 EVT OldEltVT = EltVT; 1051 while (1) { 1052 // Increase the bitwidth of the element to the next pow-of-two 1053 // (which is greater than 8 bits). 1054 EltVT = EVT::getIntegerVT(Context, 1 + EltVT.getSizeInBits()) 1055 .getRoundIntegerType(Context); 1056 1057 // Stop trying when getting a non-simple element type. 1058 // Note that vector elements may be greater than legal vector element 1059 // types. Example: X86 XMM registers hold 64bit element on 32bit 1060 // systems. 1061 if (!EltVT.isSimple()) 1062 break; 1063 1064 // Build a new vector type and check if it is legal. 1065 MVT NVT = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts); 1066 // Found a legal promoted vector type. 1067 if (NVT != MVT() && ValueTypeActions.getTypeAction(NVT) == TypeLegal) 1068 return LegalizeKind(TypePromoteInteger, 1069 EVT::getVectorVT(Context, EltVT, NumElts)); 1070 } 1071 1072 // Reset the type to the unexpanded type if we did not find a legal vector 1073 // type with a promoted vector element type. 1074 EltVT = OldEltVT; 1075 } 1076 1077 // Try to widen the vector until a legal type is found. 1078 // If there is no wider legal type, split the vector. 1079 while (1) { 1080 // Round up to the next power of 2. 1081 NumElts = (unsigned)NextPowerOf2(NumElts); 1082 1083 // If there is no simple vector type with this many elements then there 1084 // cannot be a larger legal vector type. Note that this assumes that 1085 // there are no skipped intermediate vector types in the simple types. 1086 if (!EltVT.isSimple()) 1087 break; 1088 MVT LargerVector = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts); 1089 if (LargerVector == MVT()) 1090 break; 1091 1092 // If this type is legal then widen the vector. 1093 if (ValueTypeActions.getTypeAction(LargerVector) == TypeLegal) 1094 return LegalizeKind(TypeWidenVector, LargerVector); 1095 } 1096 1097 // Widen odd vectors to next power of two. 1098 if (!VT.isPow2VectorType()) { 1099 EVT NVT = VT.getPow2VectorType(Context); 1100 return LegalizeKind(TypeWidenVector, NVT); 1101 } 1102 1103 // Vectors with illegal element types are expanded. 1104 EVT NVT = EVT::getVectorVT(Context, EltVT, VT.getVectorNumElements() / 2); 1105 return LegalizeKind(TypeSplitVector, NVT); 1106 } 1107 1108 static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT, 1109 unsigned &NumIntermediates, 1110 MVT &RegisterVT, 1111 TargetLoweringBase *TLI) { 1112 // Figure out the right, legal destination reg to copy into. 1113 unsigned NumElts = VT.getVectorNumElements(); 1114 MVT EltTy = VT.getVectorElementType(); 1115 1116 unsigned NumVectorRegs = 1; 1117 1118 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we 1119 // could break down into LHS/RHS like LegalizeDAG does. 1120 if (!isPowerOf2_32(NumElts)) { 1121 NumVectorRegs = NumElts; 1122 NumElts = 1; 1123 } 1124 1125 // Divide the input until we get to a supported size. This will always 1126 // end with a scalar if the target doesn't support vectors. 1127 while (NumElts > 1 && !TLI->isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) { 1128 NumElts >>= 1; 1129 NumVectorRegs <<= 1; 1130 } 1131 1132 NumIntermediates = NumVectorRegs; 1133 1134 MVT NewVT = MVT::getVectorVT(EltTy, NumElts); 1135 if (!TLI->isTypeLegal(NewVT)) 1136 NewVT = EltTy; 1137 IntermediateVT = NewVT; 1138 1139 unsigned NewVTSize = NewVT.getSizeInBits(); 1140 1141 // Convert sizes such as i33 to i64. 1142 if (!isPowerOf2_32(NewVTSize)) 1143 NewVTSize = NextPowerOf2(NewVTSize); 1144 1145 MVT DestVT = TLI->getRegisterType(NewVT); 1146 RegisterVT = DestVT; 1147 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16. 1148 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits()); 1149 1150 // Otherwise, promotion or legal types use the same number of registers as 1151 // the vector decimated to the appropriate level. 1152 return NumVectorRegs; 1153 } 1154 1155 /// isLegalRC - Return true if the value types that can be represented by the 1156 /// specified register class are all legal. 1157 bool TargetLoweringBase::isLegalRC(const TargetRegisterClass *RC) const { 1158 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end(); 1159 I != E; ++I) { 1160 if (isTypeLegal(*I)) 1161 return true; 1162 } 1163 return false; 1164 } 1165 1166 /// Replace/modify any TargetFrameIndex operands with a targte-dependent 1167 /// sequence of memory operands that is recognized by PrologEpilogInserter. 1168 MachineBasicBlock * 1169 TargetLoweringBase::emitPatchPoint(MachineInstr &InitialMI, 1170 MachineBasicBlock *MBB) const { 1171 MachineInstr *MI = &InitialMI; 1172 MachineFunction &MF = *MI->getParent()->getParent(); 1173 MachineFrameInfo &MFI = MF.getFrameInfo(); 1174 1175 // We're handling multiple types of operands here: 1176 // PATCHPOINT MetaArgs - live-in, read only, direct 1177 // STATEPOINT Deopt Spill - live-through, read only, indirect 1178 // STATEPOINT Deopt Alloca - live-through, read only, direct 1179 // (We're currently conservative and mark the deopt slots read/write in 1180 // practice.) 1181 // STATEPOINT GC Spill - live-through, read/write, indirect 1182 // STATEPOINT GC Alloca - live-through, read/write, direct 1183 // The live-in vs live-through is handled already (the live through ones are 1184 // all stack slots), but we need to handle the different type of stackmap 1185 // operands and memory effects here. 1186 1187 // MI changes inside this loop as we grow operands. 1188 for(unsigned OperIdx = 0; OperIdx != MI->getNumOperands(); ++OperIdx) { 1189 MachineOperand &MO = MI->getOperand(OperIdx); 1190 if (!MO.isFI()) 1191 continue; 1192 1193 // foldMemoryOperand builds a new MI after replacing a single FI operand 1194 // with the canonical set of five x86 addressing-mode operands. 1195 int FI = MO.getIndex(); 1196 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), MI->getDesc()); 1197 1198 // Copy operands before the frame-index. 1199 for (unsigned i = 0; i < OperIdx; ++i) 1200 MIB.addOperand(MI->getOperand(i)); 1201 // Add frame index operands recognized by stackmaps.cpp 1202 if (MFI.isStatepointSpillSlotObjectIndex(FI)) { 1203 // indirect-mem-ref tag, size, #FI, offset. 1204 // Used for spills inserted by StatepointLowering. This codepath is not 1205 // used for patchpoints/stackmaps at all, for these spilling is done via 1206 // foldMemoryOperand callback only. 1207 assert(MI->getOpcode() == TargetOpcode::STATEPOINT && "sanity"); 1208 MIB.addImm(StackMaps::IndirectMemRefOp); 1209 MIB.addImm(MFI.getObjectSize(FI)); 1210 MIB.addOperand(MI->getOperand(OperIdx)); 1211 MIB.addImm(0); 1212 } else { 1213 // direct-mem-ref tag, #FI, offset. 1214 // Used by patchpoint, and direct alloca arguments to statepoints 1215 MIB.addImm(StackMaps::DirectMemRefOp); 1216 MIB.addOperand(MI->getOperand(OperIdx)); 1217 MIB.addImm(0); 1218 } 1219 // Copy the operands after the frame index. 1220 for (unsigned i = OperIdx + 1; i != MI->getNumOperands(); ++i) 1221 MIB.addOperand(MI->getOperand(i)); 1222 1223 // Inherit previous memory operands. 1224 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end()); 1225 assert(MIB->mayLoad() && "Folded a stackmap use to a non-load!"); 1226 1227 // Add a new memory operand for this FI. 1228 assert(MFI.getObjectOffset(FI) != -1); 1229 1230 auto Flags = MachineMemOperand::MOLoad; 1231 if (MI->getOpcode() == TargetOpcode::STATEPOINT) { 1232 Flags |= MachineMemOperand::MOStore; 1233 Flags |= MachineMemOperand::MOVolatile; 1234 } 1235 MachineMemOperand *MMO = MF.getMachineMemOperand( 1236 MachinePointerInfo::getFixedStack(MF, FI), Flags, 1237 MF.getDataLayout().getPointerSize(), MFI.getObjectAlignment(FI)); 1238 MIB->addMemOperand(MF, MMO); 1239 1240 // Replace the instruction and update the operand index. 1241 MBB->insert(MachineBasicBlock::iterator(MI), MIB); 1242 OperIdx += (MIB->getNumOperands() - MI->getNumOperands()) - 1; 1243 MI->eraseFromParent(); 1244 MI = MIB; 1245 } 1246 return MBB; 1247 } 1248 1249 /// findRepresentativeClass - Return the largest legal super-reg register class 1250 /// of the register class for the specified type and its associated "cost". 1251 // This function is in TargetLowering because it uses RegClassForVT which would 1252 // need to be moved to TargetRegisterInfo and would necessitate moving 1253 // isTypeLegal over as well - a massive change that would just require 1254 // TargetLowering having a TargetRegisterInfo class member that it would use. 1255 std::pair<const TargetRegisterClass *, uint8_t> 1256 TargetLoweringBase::findRepresentativeClass(const TargetRegisterInfo *TRI, 1257 MVT VT) const { 1258 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy]; 1259 if (!RC) 1260 return std::make_pair(RC, 0); 1261 1262 // Compute the set of all super-register classes. 1263 BitVector SuperRegRC(TRI->getNumRegClasses()); 1264 for (SuperRegClassIterator RCI(RC, TRI); RCI.isValid(); ++RCI) 1265 SuperRegRC.setBitsInMask(RCI.getMask()); 1266 1267 // Find the first legal register class with the largest spill size. 1268 const TargetRegisterClass *BestRC = RC; 1269 for (int i = SuperRegRC.find_first(); i >= 0; i = SuperRegRC.find_next(i)) { 1270 const TargetRegisterClass *SuperRC = TRI->getRegClass(i); 1271 // We want the largest possible spill size. 1272 if (SuperRC->getSize() <= BestRC->getSize()) 1273 continue; 1274 if (!isLegalRC(SuperRC)) 1275 continue; 1276 BestRC = SuperRC; 1277 } 1278 return std::make_pair(BestRC, 1); 1279 } 1280 1281 /// computeRegisterProperties - Once all of the register classes are added, 1282 /// this allows us to compute derived properties we expose. 1283 void TargetLoweringBase::computeRegisterProperties( 1284 const TargetRegisterInfo *TRI) { 1285 static_assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE, 1286 "Too many value types for ValueTypeActions to hold!"); 1287 1288 // Everything defaults to needing one register. 1289 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) { 1290 NumRegistersForVT[i] = 1; 1291 RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i; 1292 } 1293 // ...except isVoid, which doesn't need any registers. 1294 NumRegistersForVT[MVT::isVoid] = 0; 1295 1296 // Find the largest integer register class. 1297 unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE; 1298 for (; RegClassForVT[LargestIntReg] == nullptr; --LargestIntReg) 1299 assert(LargestIntReg != MVT::i1 && "No integer registers defined!"); 1300 1301 // Every integer value type larger than this largest register takes twice as 1302 // many registers to represent as the previous ValueType. 1303 for (unsigned ExpandedReg = LargestIntReg + 1; 1304 ExpandedReg <= MVT::LAST_INTEGER_VALUETYPE; ++ExpandedReg) { 1305 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1]; 1306 RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg; 1307 TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1); 1308 ValueTypeActions.setTypeAction((MVT::SimpleValueType)ExpandedReg, 1309 TypeExpandInteger); 1310 } 1311 1312 // Inspect all of the ValueType's smaller than the largest integer 1313 // register to see which ones need promotion. 1314 unsigned LegalIntReg = LargestIntReg; 1315 for (unsigned IntReg = LargestIntReg - 1; 1316 IntReg >= (unsigned)MVT::i1; --IntReg) { 1317 MVT IVT = (MVT::SimpleValueType)IntReg; 1318 if (isTypeLegal(IVT)) { 1319 LegalIntReg = IntReg; 1320 } else { 1321 RegisterTypeForVT[IntReg] = TransformToType[IntReg] = 1322 (const MVT::SimpleValueType)LegalIntReg; 1323 ValueTypeActions.setTypeAction(IVT, TypePromoteInteger); 1324 } 1325 } 1326 1327 // ppcf128 type is really two f64's. 1328 if (!isTypeLegal(MVT::ppcf128)) { 1329 if (isTypeLegal(MVT::f64)) { 1330 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64]; 1331 RegisterTypeForVT[MVT::ppcf128] = MVT::f64; 1332 TransformToType[MVT::ppcf128] = MVT::f64; 1333 ValueTypeActions.setTypeAction(MVT::ppcf128, TypeExpandFloat); 1334 } else { 1335 NumRegistersForVT[MVT::ppcf128] = NumRegistersForVT[MVT::i128]; 1336 RegisterTypeForVT[MVT::ppcf128] = RegisterTypeForVT[MVT::i128]; 1337 TransformToType[MVT::ppcf128] = MVT::i128; 1338 ValueTypeActions.setTypeAction(MVT::ppcf128, TypeSoftenFloat); 1339 } 1340 } 1341 1342 // Decide how to handle f128. If the target does not have native f128 support, 1343 // expand it to i128 and we will be generating soft float library calls. 1344 if (!isTypeLegal(MVT::f128)) { 1345 NumRegistersForVT[MVT::f128] = NumRegistersForVT[MVT::i128]; 1346 RegisterTypeForVT[MVT::f128] = RegisterTypeForVT[MVT::i128]; 1347 TransformToType[MVT::f128] = MVT::i128; 1348 ValueTypeActions.setTypeAction(MVT::f128, TypeSoftenFloat); 1349 } 1350 1351 // Decide how to handle f64. If the target does not have native f64 support, 1352 // expand it to i64 and we will be generating soft float library calls. 1353 if (!isTypeLegal(MVT::f64)) { 1354 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64]; 1355 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64]; 1356 TransformToType[MVT::f64] = MVT::i64; 1357 ValueTypeActions.setTypeAction(MVT::f64, TypeSoftenFloat); 1358 } 1359 1360 // Decide how to handle f32. If the target does not have native f32 support, 1361 // expand it to i32 and we will be generating soft float library calls. 1362 if (!isTypeLegal(MVT::f32)) { 1363 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32]; 1364 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32]; 1365 TransformToType[MVT::f32] = MVT::i32; 1366 ValueTypeActions.setTypeAction(MVT::f32, TypeSoftenFloat); 1367 } 1368 1369 // Decide how to handle f16. If the target does not have native f16 support, 1370 // promote it to f32, because there are no f16 library calls (except for 1371 // conversions). 1372 if (!isTypeLegal(MVT::f16)) { 1373 NumRegistersForVT[MVT::f16] = NumRegistersForVT[MVT::f32]; 1374 RegisterTypeForVT[MVT::f16] = RegisterTypeForVT[MVT::f32]; 1375 TransformToType[MVT::f16] = MVT::f32; 1376 ValueTypeActions.setTypeAction(MVT::f16, TypePromoteFloat); 1377 } 1378 1379 // Loop over all of the vector value types to see which need transformations. 1380 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE; 1381 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) { 1382 MVT VT = (MVT::SimpleValueType) i; 1383 if (isTypeLegal(VT)) 1384 continue; 1385 1386 MVT EltVT = VT.getVectorElementType(); 1387 unsigned NElts = VT.getVectorNumElements(); 1388 bool IsLegalWiderType = false; 1389 LegalizeTypeAction PreferredAction = getPreferredVectorAction(VT); 1390 switch (PreferredAction) { 1391 case TypePromoteInteger: { 1392 // Try to promote the elements of integer vectors. If no legal 1393 // promotion was found, fall through to the widen-vector method. 1394 for (unsigned nVT = i + 1; nVT <= MVT::LAST_INTEGER_VECTOR_VALUETYPE; ++nVT) { 1395 MVT SVT = (MVT::SimpleValueType) nVT; 1396 // Promote vectors of integers to vectors with the same number 1397 // of elements, with a wider element type. 1398 if (SVT.getScalarSizeInBits() > EltVT.getSizeInBits() && 1399 SVT.getVectorNumElements() == NElts && isTypeLegal(SVT)) { 1400 TransformToType[i] = SVT; 1401 RegisterTypeForVT[i] = SVT; 1402 NumRegistersForVT[i] = 1; 1403 ValueTypeActions.setTypeAction(VT, TypePromoteInteger); 1404 IsLegalWiderType = true; 1405 break; 1406 } 1407 } 1408 if (IsLegalWiderType) 1409 break; 1410 } 1411 case TypeWidenVector: { 1412 // Try to widen the vector. 1413 for (unsigned nVT = i + 1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) { 1414 MVT SVT = (MVT::SimpleValueType) nVT; 1415 if (SVT.getVectorElementType() == EltVT 1416 && SVT.getVectorNumElements() > NElts && isTypeLegal(SVT)) { 1417 TransformToType[i] = SVT; 1418 RegisterTypeForVT[i] = SVT; 1419 NumRegistersForVT[i] = 1; 1420 ValueTypeActions.setTypeAction(VT, TypeWidenVector); 1421 IsLegalWiderType = true; 1422 break; 1423 } 1424 } 1425 if (IsLegalWiderType) 1426 break; 1427 } 1428 case TypeSplitVector: 1429 case TypeScalarizeVector: { 1430 MVT IntermediateVT; 1431 MVT RegisterVT; 1432 unsigned NumIntermediates; 1433 NumRegistersForVT[i] = getVectorTypeBreakdownMVT(VT, IntermediateVT, 1434 NumIntermediates, RegisterVT, this); 1435 RegisterTypeForVT[i] = RegisterVT; 1436 1437 MVT NVT = VT.getPow2VectorType(); 1438 if (NVT == VT) { 1439 // Type is already a power of 2. The default action is to split. 1440 TransformToType[i] = MVT::Other; 1441 if (PreferredAction == TypeScalarizeVector) 1442 ValueTypeActions.setTypeAction(VT, TypeScalarizeVector); 1443 else if (PreferredAction == TypeSplitVector) 1444 ValueTypeActions.setTypeAction(VT, TypeSplitVector); 1445 else 1446 // Set type action according to the number of elements. 1447 ValueTypeActions.setTypeAction(VT, NElts == 1 ? TypeScalarizeVector 1448 : TypeSplitVector); 1449 } else { 1450 TransformToType[i] = NVT; 1451 ValueTypeActions.setTypeAction(VT, TypeWidenVector); 1452 } 1453 break; 1454 } 1455 default: 1456 llvm_unreachable("Unknown vector legalization action!"); 1457 } 1458 } 1459 1460 // Determine the 'representative' register class for each value type. 1461 // An representative register class is the largest (meaning one which is 1462 // not a sub-register class / subreg register class) legal register class for 1463 // a group of value types. For example, on i386, i8, i16, and i32 1464 // representative would be GR32; while on x86_64 it's GR64. 1465 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) { 1466 const TargetRegisterClass* RRC; 1467 uint8_t Cost; 1468 std::tie(RRC, Cost) = findRepresentativeClass(TRI, (MVT::SimpleValueType)i); 1469 RepRegClassForVT[i] = RRC; 1470 RepRegClassCostForVT[i] = Cost; 1471 } 1472 } 1473 1474 EVT TargetLoweringBase::getSetCCResultType(const DataLayout &DL, LLVMContext &, 1475 EVT VT) const { 1476 assert(!VT.isVector() && "No default SetCC type for vectors!"); 1477 return getPointerTy(DL).SimpleTy; 1478 } 1479 1480 MVT::SimpleValueType TargetLoweringBase::getCmpLibcallReturnType() const { 1481 return MVT::i32; // return the default value 1482 } 1483 1484 /// getVectorTypeBreakdown - Vector types are broken down into some number of 1485 /// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32 1486 /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack. 1487 /// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86. 1488 /// 1489 /// This method returns the number of registers needed, and the VT for each 1490 /// register. It also returns the VT and quantity of the intermediate values 1491 /// before they are promoted/expanded. 1492 /// 1493 unsigned TargetLoweringBase::getVectorTypeBreakdown(LLVMContext &Context, EVT VT, 1494 EVT &IntermediateVT, 1495 unsigned &NumIntermediates, 1496 MVT &RegisterVT) const { 1497 unsigned NumElts = VT.getVectorNumElements(); 1498 1499 // If there is a wider vector type with the same element type as this one, 1500 // or a promoted vector type that has the same number of elements which 1501 // are wider, then we should convert to that legal vector type. 1502 // This handles things like <2 x float> -> <4 x float> and 1503 // <4 x i1> -> <4 x i32>. 1504 LegalizeTypeAction TA = getTypeAction(Context, VT); 1505 if (NumElts != 1 && (TA == TypeWidenVector || TA == TypePromoteInteger)) { 1506 EVT RegisterEVT = getTypeToTransformTo(Context, VT); 1507 if (isTypeLegal(RegisterEVT)) { 1508 IntermediateVT = RegisterEVT; 1509 RegisterVT = RegisterEVT.getSimpleVT(); 1510 NumIntermediates = 1; 1511 return 1; 1512 } 1513 } 1514 1515 // Figure out the right, legal destination reg to copy into. 1516 EVT EltTy = VT.getVectorElementType(); 1517 1518 unsigned NumVectorRegs = 1; 1519 1520 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we 1521 // could break down into LHS/RHS like LegalizeDAG does. 1522 if (!isPowerOf2_32(NumElts)) { 1523 NumVectorRegs = NumElts; 1524 NumElts = 1; 1525 } 1526 1527 // Divide the input until we get to a supported size. This will always 1528 // end with a scalar if the target doesn't support vectors. 1529 while (NumElts > 1 && !isTypeLegal( 1530 EVT::getVectorVT(Context, EltTy, NumElts))) { 1531 NumElts >>= 1; 1532 NumVectorRegs <<= 1; 1533 } 1534 1535 NumIntermediates = NumVectorRegs; 1536 1537 EVT NewVT = EVT::getVectorVT(Context, EltTy, NumElts); 1538 if (!isTypeLegal(NewVT)) 1539 NewVT = EltTy; 1540 IntermediateVT = NewVT; 1541 1542 MVT DestVT = getRegisterType(Context, NewVT); 1543 RegisterVT = DestVT; 1544 unsigned NewVTSize = NewVT.getSizeInBits(); 1545 1546 // Convert sizes such as i33 to i64. 1547 if (!isPowerOf2_32(NewVTSize)) 1548 NewVTSize = NextPowerOf2(NewVTSize); 1549 1550 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16. 1551 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits()); 1552 1553 // Otherwise, promotion or legal types use the same number of registers as 1554 // the vector decimated to the appropriate level. 1555 return NumVectorRegs; 1556 } 1557 1558 /// Get the EVTs and ArgFlags collections that represent the legalized return 1559 /// type of the given function. This does not require a DAG or a return value, 1560 /// and is suitable for use before any DAGs for the function are constructed. 1561 /// TODO: Move this out of TargetLowering.cpp. 1562 void llvm::GetReturnInfo(Type *ReturnType, AttributeSet attr, 1563 SmallVectorImpl<ISD::OutputArg> &Outs, 1564 const TargetLowering &TLI, const DataLayout &DL) { 1565 SmallVector<EVT, 4> ValueVTs; 1566 ComputeValueVTs(TLI, DL, ReturnType, ValueVTs); 1567 unsigned NumValues = ValueVTs.size(); 1568 if (NumValues == 0) return; 1569 1570 for (unsigned j = 0, f = NumValues; j != f; ++j) { 1571 EVT VT = ValueVTs[j]; 1572 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 1573 1574 if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::SExt)) 1575 ExtendKind = ISD::SIGN_EXTEND; 1576 else if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::ZExt)) 1577 ExtendKind = ISD::ZERO_EXTEND; 1578 1579 // FIXME: C calling convention requires the return type to be promoted to 1580 // at least 32-bit. But this is not necessary for non-C calling 1581 // conventions. The frontend should mark functions whose return values 1582 // require promoting with signext or zeroext attributes. 1583 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) { 1584 MVT MinVT = TLI.getRegisterType(ReturnType->getContext(), MVT::i32); 1585 if (VT.bitsLT(MinVT)) 1586 VT = MinVT; 1587 } 1588 1589 unsigned NumParts = TLI.getNumRegisters(ReturnType->getContext(), VT); 1590 MVT PartVT = TLI.getRegisterType(ReturnType->getContext(), VT); 1591 1592 // 'inreg' on function refers to return value 1593 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy(); 1594 if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::InReg)) 1595 Flags.setInReg(); 1596 1597 // Propagate extension type if any 1598 if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::SExt)) 1599 Flags.setSExt(); 1600 else if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::ZExt)) 1601 Flags.setZExt(); 1602 1603 for (unsigned i = 0; i < NumParts; ++i) 1604 Outs.push_back(ISD::OutputArg(Flags, PartVT, VT, /*isFixed=*/true, 0, 0)); 1605 } 1606 } 1607 1608 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 1609 /// function arguments in the caller parameter area. This is the actual 1610 /// alignment, not its logarithm. 1611 unsigned TargetLoweringBase::getByValTypeAlignment(Type *Ty, 1612 const DataLayout &DL) const { 1613 return DL.getABITypeAlignment(Ty); 1614 } 1615 1616 bool TargetLoweringBase::allowsMemoryAccess(LLVMContext &Context, 1617 const DataLayout &DL, EVT VT, 1618 unsigned AddrSpace, 1619 unsigned Alignment, 1620 bool *Fast) const { 1621 // Check if the specified alignment is sufficient based on the data layout. 1622 // TODO: While using the data layout works in practice, a better solution 1623 // would be to implement this check directly (make this a virtual function). 1624 // For example, the ABI alignment may change based on software platform while 1625 // this function should only be affected by hardware implementation. 1626 Type *Ty = VT.getTypeForEVT(Context); 1627 if (Alignment >= DL.getABITypeAlignment(Ty)) { 1628 // Assume that an access that meets the ABI-specified alignment is fast. 1629 if (Fast != nullptr) 1630 *Fast = true; 1631 return true; 1632 } 1633 1634 // This is a misaligned access. 1635 return allowsMisalignedMemoryAccesses(VT, AddrSpace, Alignment, Fast); 1636 } 1637 1638 BranchProbability TargetLoweringBase::getPredictableBranchThreshold() const { 1639 return BranchProbability(MinPercentageForPredictableBranch, 100); 1640 } 1641 1642 //===----------------------------------------------------------------------===// 1643 // TargetTransformInfo Helpers 1644 //===----------------------------------------------------------------------===// 1645 1646 int TargetLoweringBase::InstructionOpcodeToISD(unsigned Opcode) const { 1647 enum InstructionOpcodes { 1648 #define HANDLE_INST(NUM, OPCODE, CLASS) OPCODE = NUM, 1649 #define LAST_OTHER_INST(NUM) InstructionOpcodesCount = NUM 1650 #include "llvm/IR/Instruction.def" 1651 }; 1652 switch (static_cast<InstructionOpcodes>(Opcode)) { 1653 case Ret: return 0; 1654 case Br: return 0; 1655 case Switch: return 0; 1656 case IndirectBr: return 0; 1657 case Invoke: return 0; 1658 case Resume: return 0; 1659 case Unreachable: return 0; 1660 case CleanupRet: return 0; 1661 case CatchRet: return 0; 1662 case CatchPad: return 0; 1663 case CatchSwitch: return 0; 1664 case CleanupPad: return 0; 1665 case Add: return ISD::ADD; 1666 case FAdd: return ISD::FADD; 1667 case Sub: return ISD::SUB; 1668 case FSub: return ISD::FSUB; 1669 case Mul: return ISD::MUL; 1670 case FMul: return ISD::FMUL; 1671 case UDiv: return ISD::UDIV; 1672 case SDiv: return ISD::SDIV; 1673 case FDiv: return ISD::FDIV; 1674 case URem: return ISD::UREM; 1675 case SRem: return ISD::SREM; 1676 case FRem: return ISD::FREM; 1677 case Shl: return ISD::SHL; 1678 case LShr: return ISD::SRL; 1679 case AShr: return ISD::SRA; 1680 case And: return ISD::AND; 1681 case Or: return ISD::OR; 1682 case Xor: return ISD::XOR; 1683 case Alloca: return 0; 1684 case Load: return ISD::LOAD; 1685 case Store: return ISD::STORE; 1686 case GetElementPtr: return 0; 1687 case Fence: return 0; 1688 case AtomicCmpXchg: return 0; 1689 case AtomicRMW: return 0; 1690 case Trunc: return ISD::TRUNCATE; 1691 case ZExt: return ISD::ZERO_EXTEND; 1692 case SExt: return ISD::SIGN_EXTEND; 1693 case FPToUI: return ISD::FP_TO_UINT; 1694 case FPToSI: return ISD::FP_TO_SINT; 1695 case UIToFP: return ISD::UINT_TO_FP; 1696 case SIToFP: return ISD::SINT_TO_FP; 1697 case FPTrunc: return ISD::FP_ROUND; 1698 case FPExt: return ISD::FP_EXTEND; 1699 case PtrToInt: return ISD::BITCAST; 1700 case IntToPtr: return ISD::BITCAST; 1701 case BitCast: return ISD::BITCAST; 1702 case AddrSpaceCast: return ISD::ADDRSPACECAST; 1703 case ICmp: return ISD::SETCC; 1704 case FCmp: return ISD::SETCC; 1705 case PHI: return 0; 1706 case Call: return 0; 1707 case Select: return ISD::SELECT; 1708 case UserOp1: return 0; 1709 case UserOp2: return 0; 1710 case VAArg: return 0; 1711 case ExtractElement: return ISD::EXTRACT_VECTOR_ELT; 1712 case InsertElement: return ISD::INSERT_VECTOR_ELT; 1713 case ShuffleVector: return ISD::VECTOR_SHUFFLE; 1714 case ExtractValue: return ISD::MERGE_VALUES; 1715 case InsertValue: return ISD::MERGE_VALUES; 1716 case LandingPad: return 0; 1717 } 1718 1719 llvm_unreachable("Unknown instruction type encountered!"); 1720 } 1721 1722 std::pair<int, MVT> 1723 TargetLoweringBase::getTypeLegalizationCost(const DataLayout &DL, 1724 Type *Ty) const { 1725 LLVMContext &C = Ty->getContext(); 1726 EVT MTy = getValueType(DL, Ty); 1727 1728 int Cost = 1; 1729 // We keep legalizing the type until we find a legal kind. We assume that 1730 // the only operation that costs anything is the split. After splitting 1731 // we need to handle two types. 1732 while (true) { 1733 LegalizeKind LK = getTypeConversion(C, MTy); 1734 1735 if (LK.first == TypeLegal) 1736 return std::make_pair(Cost, MTy.getSimpleVT()); 1737 1738 if (LK.first == TypeSplitVector || LK.first == TypeExpandInteger) 1739 Cost *= 2; 1740 1741 // Do not loop with f128 type. 1742 if (MTy == LK.second) 1743 return std::make_pair(Cost, MTy.getSimpleVT()); 1744 1745 // Keep legalizing the type. 1746 MTy = LK.second; 1747 } 1748 } 1749 1750 Value *TargetLoweringBase::getSafeStackPointerLocation(IRBuilder<> &IRB) const { 1751 if (!TM.getTargetTriple().isAndroid()) 1752 return nullptr; 1753 1754 // Android provides a libc function to retrieve the address of the current 1755 // thread's unsafe stack pointer. 1756 Module *M = IRB.GetInsertBlock()->getParent()->getParent(); 1757 Type *StackPtrTy = Type::getInt8PtrTy(M->getContext()); 1758 Value *Fn = M->getOrInsertFunction("__safestack_pointer_address", 1759 StackPtrTy->getPointerTo(0), nullptr); 1760 return IRB.CreateCall(Fn); 1761 } 1762 1763 //===----------------------------------------------------------------------===// 1764 // Loop Strength Reduction hooks 1765 //===----------------------------------------------------------------------===// 1766 1767 /// isLegalAddressingMode - Return true if the addressing mode represented 1768 /// by AM is legal for this target, for a load/store of the specified type. 1769 bool TargetLoweringBase::isLegalAddressingMode(const DataLayout &DL, 1770 const AddrMode &AM, Type *Ty, 1771 unsigned AS) const { 1772 // The default implementation of this implements a conservative RISCy, r+r and 1773 // r+i addr mode. 1774 1775 // Allows a sign-extended 16-bit immediate field. 1776 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1) 1777 return false; 1778 1779 // No global is ever allowed as a base. 1780 if (AM.BaseGV) 1781 return false; 1782 1783 // Only support r+r, 1784 switch (AM.Scale) { 1785 case 0: // "r+i" or just "i", depending on HasBaseReg. 1786 break; 1787 case 1: 1788 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. 1789 return false; 1790 // Otherwise we have r+r or r+i. 1791 break; 1792 case 2: 1793 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. 1794 return false; 1795 // Allow 2*r as r+r. 1796 break; 1797 default: // Don't allow n * r 1798 return false; 1799 } 1800 1801 return true; 1802 } 1803 1804 //===----------------------------------------------------------------------===// 1805 // Stack Protector 1806 //===----------------------------------------------------------------------===// 1807 1808 // For OpenBSD return its special guard variable. Otherwise return nullptr, 1809 // so that SelectionDAG handle SSP. 1810 Value *TargetLoweringBase::getIRStackGuard(IRBuilder<> &IRB) const { 1811 if (getTargetMachine().getTargetTriple().isOSOpenBSD()) { 1812 Module &M = *IRB.GetInsertBlock()->getParent()->getParent(); 1813 PointerType *PtrTy = Type::getInt8PtrTy(M.getContext()); 1814 return M.getOrInsertGlobal("__guard_local", PtrTy); 1815 } 1816 return nullptr; 1817 } 1818 1819 // Currently only support "standard" __stack_chk_guard. 1820 // TODO: add LOAD_STACK_GUARD support. 1821 void TargetLoweringBase::insertSSPDeclarations(Module &M) const { 1822 M.getOrInsertGlobal("__stack_chk_guard", Type::getInt8PtrTy(M.getContext())); 1823 } 1824 1825 // Currently only support "standard" __stack_chk_guard. 1826 // TODO: add LOAD_STACK_GUARD support. 1827 Value *TargetLoweringBase::getSDagStackGuard(const Module &M) const { 1828 return M.getGlobalVariable("__stack_chk_guard", true); 1829 } 1830 1831 Value *TargetLoweringBase::getSSPStackGuardCheck(const Module &M) const { 1832 return nullptr; 1833 } 1834