1 //===-- TargetLoweringBase.cpp - Implement the TargetLoweringBase class ---===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This implements the TargetLoweringBase class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "llvm/Target/TargetLowering.h" 15 #include "llvm/ADT/BitVector.h" 16 #include "llvm/ADT/STLExtras.h" 17 #include "llvm/ADT/Triple.h" 18 #include "llvm/CodeGen/Analysis.h" 19 #include "llvm/CodeGen/MachineFrameInfo.h" 20 #include "llvm/CodeGen/MachineFunction.h" 21 #include "llvm/CodeGen/MachineInstrBuilder.h" 22 #include "llvm/CodeGen/MachineJumpTableInfo.h" 23 #include "llvm/CodeGen/StackMaps.h" 24 #include "llvm/IR/DataLayout.h" 25 #include "llvm/IR/DerivedTypes.h" 26 #include "llvm/IR/GlobalVariable.h" 27 #include "llvm/IR/Mangler.h" 28 #include "llvm/MC/MCAsmInfo.h" 29 #include "llvm/MC/MCContext.h" 30 #include "llvm/MC/MCExpr.h" 31 #include "llvm/Support/CommandLine.h" 32 #include "llvm/Support/ErrorHandling.h" 33 #include "llvm/Support/MathExtras.h" 34 #include "llvm/Target/TargetLoweringObjectFile.h" 35 #include "llvm/Target/TargetMachine.h" 36 #include "llvm/Target/TargetRegisterInfo.h" 37 #include <cctype> 38 using namespace llvm; 39 40 /// InitLibcallNames - Set default libcall names. 41 /// 42 static void InitLibcallNames(const char **Names, const Triple &TT) { 43 Names[RTLIB::SHL_I16] = "__ashlhi3"; 44 Names[RTLIB::SHL_I32] = "__ashlsi3"; 45 Names[RTLIB::SHL_I64] = "__ashldi3"; 46 Names[RTLIB::SHL_I128] = "__ashlti3"; 47 Names[RTLIB::SRL_I16] = "__lshrhi3"; 48 Names[RTLIB::SRL_I32] = "__lshrsi3"; 49 Names[RTLIB::SRL_I64] = "__lshrdi3"; 50 Names[RTLIB::SRL_I128] = "__lshrti3"; 51 Names[RTLIB::SRA_I16] = "__ashrhi3"; 52 Names[RTLIB::SRA_I32] = "__ashrsi3"; 53 Names[RTLIB::SRA_I64] = "__ashrdi3"; 54 Names[RTLIB::SRA_I128] = "__ashrti3"; 55 Names[RTLIB::MUL_I8] = "__mulqi3"; 56 Names[RTLIB::MUL_I16] = "__mulhi3"; 57 Names[RTLIB::MUL_I32] = "__mulsi3"; 58 Names[RTLIB::MUL_I64] = "__muldi3"; 59 Names[RTLIB::MUL_I128] = "__multi3"; 60 Names[RTLIB::MULO_I32] = "__mulosi4"; 61 Names[RTLIB::MULO_I64] = "__mulodi4"; 62 Names[RTLIB::MULO_I128] = "__muloti4"; 63 Names[RTLIB::SDIV_I8] = "__divqi3"; 64 Names[RTLIB::SDIV_I16] = "__divhi3"; 65 Names[RTLIB::SDIV_I32] = "__divsi3"; 66 Names[RTLIB::SDIV_I64] = "__divdi3"; 67 Names[RTLIB::SDIV_I128] = "__divti3"; 68 Names[RTLIB::UDIV_I8] = "__udivqi3"; 69 Names[RTLIB::UDIV_I16] = "__udivhi3"; 70 Names[RTLIB::UDIV_I32] = "__udivsi3"; 71 Names[RTLIB::UDIV_I64] = "__udivdi3"; 72 Names[RTLIB::UDIV_I128] = "__udivti3"; 73 Names[RTLIB::SREM_I8] = "__modqi3"; 74 Names[RTLIB::SREM_I16] = "__modhi3"; 75 Names[RTLIB::SREM_I32] = "__modsi3"; 76 Names[RTLIB::SREM_I64] = "__moddi3"; 77 Names[RTLIB::SREM_I128] = "__modti3"; 78 Names[RTLIB::UREM_I8] = "__umodqi3"; 79 Names[RTLIB::UREM_I16] = "__umodhi3"; 80 Names[RTLIB::UREM_I32] = "__umodsi3"; 81 Names[RTLIB::UREM_I64] = "__umoddi3"; 82 Names[RTLIB::UREM_I128] = "__umodti3"; 83 84 // These are generally not available. 85 Names[RTLIB::SDIVREM_I8] = nullptr; 86 Names[RTLIB::SDIVREM_I16] = nullptr; 87 Names[RTLIB::SDIVREM_I32] = nullptr; 88 Names[RTLIB::SDIVREM_I64] = nullptr; 89 Names[RTLIB::SDIVREM_I128] = nullptr; 90 Names[RTLIB::UDIVREM_I8] = nullptr; 91 Names[RTLIB::UDIVREM_I16] = nullptr; 92 Names[RTLIB::UDIVREM_I32] = nullptr; 93 Names[RTLIB::UDIVREM_I64] = nullptr; 94 Names[RTLIB::UDIVREM_I128] = nullptr; 95 96 Names[RTLIB::NEG_I32] = "__negsi2"; 97 Names[RTLIB::NEG_I64] = "__negdi2"; 98 Names[RTLIB::ADD_F32] = "__addsf3"; 99 Names[RTLIB::ADD_F64] = "__adddf3"; 100 Names[RTLIB::ADD_F80] = "__addxf3"; 101 Names[RTLIB::ADD_F128] = "__addtf3"; 102 Names[RTLIB::ADD_PPCF128] = "__gcc_qadd"; 103 Names[RTLIB::SUB_F32] = "__subsf3"; 104 Names[RTLIB::SUB_F64] = "__subdf3"; 105 Names[RTLIB::SUB_F80] = "__subxf3"; 106 Names[RTLIB::SUB_F128] = "__subtf3"; 107 Names[RTLIB::SUB_PPCF128] = "__gcc_qsub"; 108 Names[RTLIB::MUL_F32] = "__mulsf3"; 109 Names[RTLIB::MUL_F64] = "__muldf3"; 110 Names[RTLIB::MUL_F80] = "__mulxf3"; 111 Names[RTLIB::MUL_F128] = "__multf3"; 112 Names[RTLIB::MUL_PPCF128] = "__gcc_qmul"; 113 Names[RTLIB::DIV_F32] = "__divsf3"; 114 Names[RTLIB::DIV_F64] = "__divdf3"; 115 Names[RTLIB::DIV_F80] = "__divxf3"; 116 Names[RTLIB::DIV_F128] = "__divtf3"; 117 Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv"; 118 Names[RTLIB::REM_F32] = "fmodf"; 119 Names[RTLIB::REM_F64] = "fmod"; 120 Names[RTLIB::REM_F80] = "fmodl"; 121 Names[RTLIB::REM_F128] = "fmodl"; 122 Names[RTLIB::REM_PPCF128] = "fmodl"; 123 Names[RTLIB::FMA_F32] = "fmaf"; 124 Names[RTLIB::FMA_F64] = "fma"; 125 Names[RTLIB::FMA_F80] = "fmal"; 126 Names[RTLIB::FMA_F128] = "fmal"; 127 Names[RTLIB::FMA_PPCF128] = "fmal"; 128 Names[RTLIB::POWI_F32] = "__powisf2"; 129 Names[RTLIB::POWI_F64] = "__powidf2"; 130 Names[RTLIB::POWI_F80] = "__powixf2"; 131 Names[RTLIB::POWI_F128] = "__powitf2"; 132 Names[RTLIB::POWI_PPCF128] = "__powitf2"; 133 Names[RTLIB::SQRT_F32] = "sqrtf"; 134 Names[RTLIB::SQRT_F64] = "sqrt"; 135 Names[RTLIB::SQRT_F80] = "sqrtl"; 136 Names[RTLIB::SQRT_F128] = "sqrtl"; 137 Names[RTLIB::SQRT_PPCF128] = "sqrtl"; 138 Names[RTLIB::LOG_F32] = "logf"; 139 Names[RTLIB::LOG_F64] = "log"; 140 Names[RTLIB::LOG_F80] = "logl"; 141 Names[RTLIB::LOG_F128] = "logl"; 142 Names[RTLIB::LOG_PPCF128] = "logl"; 143 Names[RTLIB::LOG2_F32] = "log2f"; 144 Names[RTLIB::LOG2_F64] = "log2"; 145 Names[RTLIB::LOG2_F80] = "log2l"; 146 Names[RTLIB::LOG2_F128] = "log2l"; 147 Names[RTLIB::LOG2_PPCF128] = "log2l"; 148 Names[RTLIB::LOG10_F32] = "log10f"; 149 Names[RTLIB::LOG10_F64] = "log10"; 150 Names[RTLIB::LOG10_F80] = "log10l"; 151 Names[RTLIB::LOG10_F128] = "log10l"; 152 Names[RTLIB::LOG10_PPCF128] = "log10l"; 153 Names[RTLIB::EXP_F32] = "expf"; 154 Names[RTLIB::EXP_F64] = "exp"; 155 Names[RTLIB::EXP_F80] = "expl"; 156 Names[RTLIB::EXP_F128] = "expl"; 157 Names[RTLIB::EXP_PPCF128] = "expl"; 158 Names[RTLIB::EXP2_F32] = "exp2f"; 159 Names[RTLIB::EXP2_F64] = "exp2"; 160 Names[RTLIB::EXP2_F80] = "exp2l"; 161 Names[RTLIB::EXP2_F128] = "exp2l"; 162 Names[RTLIB::EXP2_PPCF128] = "exp2l"; 163 Names[RTLIB::SIN_F32] = "sinf"; 164 Names[RTLIB::SIN_F64] = "sin"; 165 Names[RTLIB::SIN_F80] = "sinl"; 166 Names[RTLIB::SIN_F128] = "sinl"; 167 Names[RTLIB::SIN_PPCF128] = "sinl"; 168 Names[RTLIB::COS_F32] = "cosf"; 169 Names[RTLIB::COS_F64] = "cos"; 170 Names[RTLIB::COS_F80] = "cosl"; 171 Names[RTLIB::COS_F128] = "cosl"; 172 Names[RTLIB::COS_PPCF128] = "cosl"; 173 Names[RTLIB::POW_F32] = "powf"; 174 Names[RTLIB::POW_F64] = "pow"; 175 Names[RTLIB::POW_F80] = "powl"; 176 Names[RTLIB::POW_F128] = "powl"; 177 Names[RTLIB::POW_PPCF128] = "powl"; 178 Names[RTLIB::CEIL_F32] = "ceilf"; 179 Names[RTLIB::CEIL_F64] = "ceil"; 180 Names[RTLIB::CEIL_F80] = "ceill"; 181 Names[RTLIB::CEIL_F128] = "ceill"; 182 Names[RTLIB::CEIL_PPCF128] = "ceill"; 183 Names[RTLIB::TRUNC_F32] = "truncf"; 184 Names[RTLIB::TRUNC_F64] = "trunc"; 185 Names[RTLIB::TRUNC_F80] = "truncl"; 186 Names[RTLIB::TRUNC_F128] = "truncl"; 187 Names[RTLIB::TRUNC_PPCF128] = "truncl"; 188 Names[RTLIB::RINT_F32] = "rintf"; 189 Names[RTLIB::RINT_F64] = "rint"; 190 Names[RTLIB::RINT_F80] = "rintl"; 191 Names[RTLIB::RINT_F128] = "rintl"; 192 Names[RTLIB::RINT_PPCF128] = "rintl"; 193 Names[RTLIB::NEARBYINT_F32] = "nearbyintf"; 194 Names[RTLIB::NEARBYINT_F64] = "nearbyint"; 195 Names[RTLIB::NEARBYINT_F80] = "nearbyintl"; 196 Names[RTLIB::NEARBYINT_F128] = "nearbyintl"; 197 Names[RTLIB::NEARBYINT_PPCF128] = "nearbyintl"; 198 Names[RTLIB::ROUND_F32] = "roundf"; 199 Names[RTLIB::ROUND_F64] = "round"; 200 Names[RTLIB::ROUND_F80] = "roundl"; 201 Names[RTLIB::ROUND_F128] = "roundl"; 202 Names[RTLIB::ROUND_PPCF128] = "roundl"; 203 Names[RTLIB::FLOOR_F32] = "floorf"; 204 Names[RTLIB::FLOOR_F64] = "floor"; 205 Names[RTLIB::FLOOR_F80] = "floorl"; 206 Names[RTLIB::FLOOR_F128] = "floorl"; 207 Names[RTLIB::FLOOR_PPCF128] = "floorl"; 208 Names[RTLIB::ROUND_F32] = "roundf"; 209 Names[RTLIB::ROUND_F64] = "round"; 210 Names[RTLIB::ROUND_F80] = "roundl"; 211 Names[RTLIB::ROUND_F128] = "roundl"; 212 Names[RTLIB::ROUND_PPCF128] = "roundl"; 213 Names[RTLIB::COPYSIGN_F32] = "copysignf"; 214 Names[RTLIB::COPYSIGN_F64] = "copysign"; 215 Names[RTLIB::COPYSIGN_F80] = "copysignl"; 216 Names[RTLIB::COPYSIGN_F128] = "copysignl"; 217 Names[RTLIB::COPYSIGN_PPCF128] = "copysignl"; 218 Names[RTLIB::FPEXT_F64_F128] = "__extenddftf2"; 219 Names[RTLIB::FPEXT_F32_F128] = "__extendsftf2"; 220 Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2"; 221 Names[RTLIB::FPEXT_F16_F32] = "__gnu_h2f_ieee"; 222 Names[RTLIB::FPROUND_F32_F16] = "__gnu_f2h_ieee"; 223 Names[RTLIB::FPROUND_F64_F16] = "__truncdfhf2"; 224 Names[RTLIB::FPROUND_F80_F16] = "__truncxfhf2"; 225 Names[RTLIB::FPROUND_F128_F16] = "__trunctfhf2"; 226 Names[RTLIB::FPROUND_PPCF128_F16] = "__trunctfhf2"; 227 Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2"; 228 Names[RTLIB::FPROUND_F80_F32] = "__truncxfsf2"; 229 Names[RTLIB::FPROUND_F128_F32] = "__trunctfsf2"; 230 Names[RTLIB::FPROUND_PPCF128_F32] = "__trunctfsf2"; 231 Names[RTLIB::FPROUND_F80_F64] = "__truncxfdf2"; 232 Names[RTLIB::FPROUND_F128_F64] = "__trunctfdf2"; 233 Names[RTLIB::FPROUND_PPCF128_F64] = "__trunctfdf2"; 234 Names[RTLIB::FPTOSINT_F32_I8] = "__fixsfqi"; 235 Names[RTLIB::FPTOSINT_F32_I16] = "__fixsfhi"; 236 Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi"; 237 Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi"; 238 Names[RTLIB::FPTOSINT_F32_I128] = "__fixsfti"; 239 Names[RTLIB::FPTOSINT_F64_I8] = "__fixdfqi"; 240 Names[RTLIB::FPTOSINT_F64_I16] = "__fixdfhi"; 241 Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi"; 242 Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi"; 243 Names[RTLIB::FPTOSINT_F64_I128] = "__fixdfti"; 244 Names[RTLIB::FPTOSINT_F80_I32] = "__fixxfsi"; 245 Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi"; 246 Names[RTLIB::FPTOSINT_F80_I128] = "__fixxfti"; 247 Names[RTLIB::FPTOSINT_F128_I32] = "__fixtfsi"; 248 Names[RTLIB::FPTOSINT_F128_I64] = "__fixtfdi"; 249 Names[RTLIB::FPTOSINT_F128_I128] = "__fixtfti"; 250 Names[RTLIB::FPTOSINT_PPCF128_I32] = "__fixtfsi"; 251 Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi"; 252 Names[RTLIB::FPTOSINT_PPCF128_I128] = "__fixtfti"; 253 Names[RTLIB::FPTOUINT_F32_I8] = "__fixunssfqi"; 254 Names[RTLIB::FPTOUINT_F32_I16] = "__fixunssfhi"; 255 Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi"; 256 Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi"; 257 Names[RTLIB::FPTOUINT_F32_I128] = "__fixunssfti"; 258 Names[RTLIB::FPTOUINT_F64_I8] = "__fixunsdfqi"; 259 Names[RTLIB::FPTOUINT_F64_I16] = "__fixunsdfhi"; 260 Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi"; 261 Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi"; 262 Names[RTLIB::FPTOUINT_F64_I128] = "__fixunsdfti"; 263 Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi"; 264 Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi"; 265 Names[RTLIB::FPTOUINT_F80_I128] = "__fixunsxfti"; 266 Names[RTLIB::FPTOUINT_F128_I32] = "__fixunstfsi"; 267 Names[RTLIB::FPTOUINT_F128_I64] = "__fixunstfdi"; 268 Names[RTLIB::FPTOUINT_F128_I128] = "__fixunstfti"; 269 Names[RTLIB::FPTOUINT_PPCF128_I32] = "__fixunstfsi"; 270 Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi"; 271 Names[RTLIB::FPTOUINT_PPCF128_I128] = "__fixunstfti"; 272 Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf"; 273 Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf"; 274 Names[RTLIB::SINTTOFP_I32_F80] = "__floatsixf"; 275 Names[RTLIB::SINTTOFP_I32_F128] = "__floatsitf"; 276 Names[RTLIB::SINTTOFP_I32_PPCF128] = "__floatsitf"; 277 Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf"; 278 Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf"; 279 Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf"; 280 Names[RTLIB::SINTTOFP_I64_F128] = "__floatditf"; 281 Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf"; 282 Names[RTLIB::SINTTOFP_I128_F32] = "__floattisf"; 283 Names[RTLIB::SINTTOFP_I128_F64] = "__floattidf"; 284 Names[RTLIB::SINTTOFP_I128_F80] = "__floattixf"; 285 Names[RTLIB::SINTTOFP_I128_F128] = "__floattitf"; 286 Names[RTLIB::SINTTOFP_I128_PPCF128] = "__floattitf"; 287 Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf"; 288 Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf"; 289 Names[RTLIB::UINTTOFP_I32_F80] = "__floatunsixf"; 290 Names[RTLIB::UINTTOFP_I32_F128] = "__floatunsitf"; 291 Names[RTLIB::UINTTOFP_I32_PPCF128] = "__floatunsitf"; 292 Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf"; 293 Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf"; 294 Names[RTLIB::UINTTOFP_I64_F80] = "__floatundixf"; 295 Names[RTLIB::UINTTOFP_I64_F128] = "__floatunditf"; 296 Names[RTLIB::UINTTOFP_I64_PPCF128] = "__floatunditf"; 297 Names[RTLIB::UINTTOFP_I128_F32] = "__floatuntisf"; 298 Names[RTLIB::UINTTOFP_I128_F64] = "__floatuntidf"; 299 Names[RTLIB::UINTTOFP_I128_F80] = "__floatuntixf"; 300 Names[RTLIB::UINTTOFP_I128_F128] = "__floatuntitf"; 301 Names[RTLIB::UINTTOFP_I128_PPCF128] = "__floatuntitf"; 302 Names[RTLIB::OEQ_F32] = "__eqsf2"; 303 Names[RTLIB::OEQ_F64] = "__eqdf2"; 304 Names[RTLIB::OEQ_F128] = "__eqtf2"; 305 Names[RTLIB::UNE_F32] = "__nesf2"; 306 Names[RTLIB::UNE_F64] = "__nedf2"; 307 Names[RTLIB::UNE_F128] = "__netf2"; 308 Names[RTLIB::OGE_F32] = "__gesf2"; 309 Names[RTLIB::OGE_F64] = "__gedf2"; 310 Names[RTLIB::OGE_F128] = "__getf2"; 311 Names[RTLIB::OLT_F32] = "__ltsf2"; 312 Names[RTLIB::OLT_F64] = "__ltdf2"; 313 Names[RTLIB::OLT_F128] = "__lttf2"; 314 Names[RTLIB::OLE_F32] = "__lesf2"; 315 Names[RTLIB::OLE_F64] = "__ledf2"; 316 Names[RTLIB::OLE_F128] = "__letf2"; 317 Names[RTLIB::OGT_F32] = "__gtsf2"; 318 Names[RTLIB::OGT_F64] = "__gtdf2"; 319 Names[RTLIB::OGT_F128] = "__gttf2"; 320 Names[RTLIB::UO_F32] = "__unordsf2"; 321 Names[RTLIB::UO_F64] = "__unorddf2"; 322 Names[RTLIB::UO_F128] = "__unordtf2"; 323 Names[RTLIB::O_F32] = "__unordsf2"; 324 Names[RTLIB::O_F64] = "__unorddf2"; 325 Names[RTLIB::O_F128] = "__unordtf2"; 326 Names[RTLIB::MEMCPY] = "memcpy"; 327 Names[RTLIB::MEMMOVE] = "memmove"; 328 Names[RTLIB::MEMSET] = "memset"; 329 Names[RTLIB::UNWIND_RESUME] = "_Unwind_Resume"; 330 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1] = "__sync_val_compare_and_swap_1"; 331 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2] = "__sync_val_compare_and_swap_2"; 332 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4] = "__sync_val_compare_and_swap_4"; 333 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8] = "__sync_val_compare_and_swap_8"; 334 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_16] = "__sync_val_compare_and_swap_16"; 335 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_1] = "__sync_lock_test_and_set_1"; 336 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_2] = "__sync_lock_test_and_set_2"; 337 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_4] = "__sync_lock_test_and_set_4"; 338 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_8] = "__sync_lock_test_and_set_8"; 339 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_16] = "__sync_lock_test_and_set_16"; 340 Names[RTLIB::SYNC_FETCH_AND_ADD_1] = "__sync_fetch_and_add_1"; 341 Names[RTLIB::SYNC_FETCH_AND_ADD_2] = "__sync_fetch_and_add_2"; 342 Names[RTLIB::SYNC_FETCH_AND_ADD_4] = "__sync_fetch_and_add_4"; 343 Names[RTLIB::SYNC_FETCH_AND_ADD_8] = "__sync_fetch_and_add_8"; 344 Names[RTLIB::SYNC_FETCH_AND_ADD_16] = "__sync_fetch_and_add_16"; 345 Names[RTLIB::SYNC_FETCH_AND_SUB_1] = "__sync_fetch_and_sub_1"; 346 Names[RTLIB::SYNC_FETCH_AND_SUB_2] = "__sync_fetch_and_sub_2"; 347 Names[RTLIB::SYNC_FETCH_AND_SUB_4] = "__sync_fetch_and_sub_4"; 348 Names[RTLIB::SYNC_FETCH_AND_SUB_8] = "__sync_fetch_and_sub_8"; 349 Names[RTLIB::SYNC_FETCH_AND_SUB_16] = "__sync_fetch_and_sub_16"; 350 Names[RTLIB::SYNC_FETCH_AND_AND_1] = "__sync_fetch_and_and_1"; 351 Names[RTLIB::SYNC_FETCH_AND_AND_2] = "__sync_fetch_and_and_2"; 352 Names[RTLIB::SYNC_FETCH_AND_AND_4] = "__sync_fetch_and_and_4"; 353 Names[RTLIB::SYNC_FETCH_AND_AND_8] = "__sync_fetch_and_and_8"; 354 Names[RTLIB::SYNC_FETCH_AND_AND_16] = "__sync_fetch_and_and_16"; 355 Names[RTLIB::SYNC_FETCH_AND_OR_1] = "__sync_fetch_and_or_1"; 356 Names[RTLIB::SYNC_FETCH_AND_OR_2] = "__sync_fetch_and_or_2"; 357 Names[RTLIB::SYNC_FETCH_AND_OR_4] = "__sync_fetch_and_or_4"; 358 Names[RTLIB::SYNC_FETCH_AND_OR_8] = "__sync_fetch_and_or_8"; 359 Names[RTLIB::SYNC_FETCH_AND_OR_16] = "__sync_fetch_and_or_16"; 360 Names[RTLIB::SYNC_FETCH_AND_XOR_1] = "__sync_fetch_and_xor_1"; 361 Names[RTLIB::SYNC_FETCH_AND_XOR_2] = "__sync_fetch_and_xor_2"; 362 Names[RTLIB::SYNC_FETCH_AND_XOR_4] = "__sync_fetch_and_xor_4"; 363 Names[RTLIB::SYNC_FETCH_AND_XOR_8] = "__sync_fetch_and_xor_8"; 364 Names[RTLIB::SYNC_FETCH_AND_XOR_16] = "__sync_fetch_and_xor_16"; 365 Names[RTLIB::SYNC_FETCH_AND_NAND_1] = "__sync_fetch_and_nand_1"; 366 Names[RTLIB::SYNC_FETCH_AND_NAND_2] = "__sync_fetch_and_nand_2"; 367 Names[RTLIB::SYNC_FETCH_AND_NAND_4] = "__sync_fetch_and_nand_4"; 368 Names[RTLIB::SYNC_FETCH_AND_NAND_8] = "__sync_fetch_and_nand_8"; 369 Names[RTLIB::SYNC_FETCH_AND_NAND_16] = "__sync_fetch_and_nand_16"; 370 Names[RTLIB::SYNC_FETCH_AND_MAX_1] = "__sync_fetch_and_max_1"; 371 Names[RTLIB::SYNC_FETCH_AND_MAX_2] = "__sync_fetch_and_max_2"; 372 Names[RTLIB::SYNC_FETCH_AND_MAX_4] = "__sync_fetch_and_max_4"; 373 Names[RTLIB::SYNC_FETCH_AND_MAX_8] = "__sync_fetch_and_max_8"; 374 Names[RTLIB::SYNC_FETCH_AND_MAX_16] = "__sync_fetch_and_max_16"; 375 Names[RTLIB::SYNC_FETCH_AND_UMAX_1] = "__sync_fetch_and_umax_1"; 376 Names[RTLIB::SYNC_FETCH_AND_UMAX_2] = "__sync_fetch_and_umax_2"; 377 Names[RTLIB::SYNC_FETCH_AND_UMAX_4] = "__sync_fetch_and_umax_4"; 378 Names[RTLIB::SYNC_FETCH_AND_UMAX_8] = "__sync_fetch_and_umax_8"; 379 Names[RTLIB::SYNC_FETCH_AND_UMAX_16] = "__sync_fetch_and_umax_16"; 380 Names[RTLIB::SYNC_FETCH_AND_MIN_1] = "__sync_fetch_and_min_1"; 381 Names[RTLIB::SYNC_FETCH_AND_MIN_2] = "__sync_fetch_and_min_2"; 382 Names[RTLIB::SYNC_FETCH_AND_MIN_4] = "__sync_fetch_and_min_4"; 383 Names[RTLIB::SYNC_FETCH_AND_MIN_8] = "__sync_fetch_and_min_8"; 384 Names[RTLIB::SYNC_FETCH_AND_MIN_16] = "__sync_fetch_and_min_16"; 385 Names[RTLIB::SYNC_FETCH_AND_UMIN_1] = "__sync_fetch_and_umin_1"; 386 Names[RTLIB::SYNC_FETCH_AND_UMIN_2] = "__sync_fetch_and_umin_2"; 387 Names[RTLIB::SYNC_FETCH_AND_UMIN_4] = "__sync_fetch_and_umin_4"; 388 Names[RTLIB::SYNC_FETCH_AND_UMIN_8] = "__sync_fetch_and_umin_8"; 389 Names[RTLIB::SYNC_FETCH_AND_UMIN_16] = "__sync_fetch_and_umin_16"; 390 391 if (TT.getEnvironment() == Triple::GNU) { 392 Names[RTLIB::SINCOS_F32] = "sincosf"; 393 Names[RTLIB::SINCOS_F64] = "sincos"; 394 Names[RTLIB::SINCOS_F80] = "sincosl"; 395 Names[RTLIB::SINCOS_F128] = "sincosl"; 396 Names[RTLIB::SINCOS_PPCF128] = "sincosl"; 397 } else { 398 // These are generally not available. 399 Names[RTLIB::SINCOS_F32] = nullptr; 400 Names[RTLIB::SINCOS_F64] = nullptr; 401 Names[RTLIB::SINCOS_F80] = nullptr; 402 Names[RTLIB::SINCOS_F128] = nullptr; 403 Names[RTLIB::SINCOS_PPCF128] = nullptr; 404 } 405 406 if (TT.getOS() != Triple::OpenBSD) { 407 Names[RTLIB::STACKPROTECTOR_CHECK_FAIL] = "__stack_chk_fail"; 408 } else { 409 // These are generally not available. 410 Names[RTLIB::STACKPROTECTOR_CHECK_FAIL] = nullptr; 411 } 412 } 413 414 /// InitLibcallCallingConvs - Set default libcall CallingConvs. 415 /// 416 static void InitLibcallCallingConvs(CallingConv::ID *CCs) { 417 for (int i = 0; i < RTLIB::UNKNOWN_LIBCALL; ++i) { 418 CCs[i] = CallingConv::C; 419 } 420 } 421 422 /// getFPEXT - Return the FPEXT_*_* value for the given types, or 423 /// UNKNOWN_LIBCALL if there is none. 424 RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) { 425 if (OpVT == MVT::f32) { 426 if (RetVT == MVT::f64) 427 return FPEXT_F32_F64; 428 if (RetVT == MVT::f128) 429 return FPEXT_F32_F128; 430 } else if (OpVT == MVT::f64) { 431 if (RetVT == MVT::f128) 432 return FPEXT_F64_F128; 433 } 434 435 return UNKNOWN_LIBCALL; 436 } 437 438 /// getFPROUND - Return the FPROUND_*_* value for the given types, or 439 /// UNKNOWN_LIBCALL if there is none. 440 RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) { 441 if (RetVT == MVT::f16) { 442 if (OpVT == MVT::f32) 443 return FPROUND_F32_F16; 444 if (OpVT == MVT::f64) 445 return FPROUND_F64_F16; 446 if (OpVT == MVT::f80) 447 return FPROUND_F80_F16; 448 if (OpVT == MVT::f128) 449 return FPROUND_F128_F16; 450 if (OpVT == MVT::ppcf128) 451 return FPROUND_PPCF128_F16; 452 } else if (RetVT == MVT::f32) { 453 if (OpVT == MVT::f64) 454 return FPROUND_F64_F32; 455 if (OpVT == MVT::f80) 456 return FPROUND_F80_F32; 457 if (OpVT == MVT::f128) 458 return FPROUND_F128_F32; 459 if (OpVT == MVT::ppcf128) 460 return FPROUND_PPCF128_F32; 461 } else if (RetVT == MVT::f64) { 462 if (OpVT == MVT::f80) 463 return FPROUND_F80_F64; 464 if (OpVT == MVT::f128) 465 return FPROUND_F128_F64; 466 if (OpVT == MVT::ppcf128) 467 return FPROUND_PPCF128_F64; 468 } 469 470 return UNKNOWN_LIBCALL; 471 } 472 473 /// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or 474 /// UNKNOWN_LIBCALL if there is none. 475 RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT, EVT RetVT) { 476 if (OpVT == MVT::f32) { 477 if (RetVT == MVT::i8) 478 return FPTOSINT_F32_I8; 479 if (RetVT == MVT::i16) 480 return FPTOSINT_F32_I16; 481 if (RetVT == MVT::i32) 482 return FPTOSINT_F32_I32; 483 if (RetVT == MVT::i64) 484 return FPTOSINT_F32_I64; 485 if (RetVT == MVT::i128) 486 return FPTOSINT_F32_I128; 487 } else if (OpVT == MVT::f64) { 488 if (RetVT == MVT::i8) 489 return FPTOSINT_F64_I8; 490 if (RetVT == MVT::i16) 491 return FPTOSINT_F64_I16; 492 if (RetVT == MVT::i32) 493 return FPTOSINT_F64_I32; 494 if (RetVT == MVT::i64) 495 return FPTOSINT_F64_I64; 496 if (RetVT == MVT::i128) 497 return FPTOSINT_F64_I128; 498 } else if (OpVT == MVT::f80) { 499 if (RetVT == MVT::i32) 500 return FPTOSINT_F80_I32; 501 if (RetVT == MVT::i64) 502 return FPTOSINT_F80_I64; 503 if (RetVT == MVT::i128) 504 return FPTOSINT_F80_I128; 505 } else if (OpVT == MVT::f128) { 506 if (RetVT == MVT::i32) 507 return FPTOSINT_F128_I32; 508 if (RetVT == MVT::i64) 509 return FPTOSINT_F128_I64; 510 if (RetVT == MVT::i128) 511 return FPTOSINT_F128_I128; 512 } else if (OpVT == MVT::ppcf128) { 513 if (RetVT == MVT::i32) 514 return FPTOSINT_PPCF128_I32; 515 if (RetVT == MVT::i64) 516 return FPTOSINT_PPCF128_I64; 517 if (RetVT == MVT::i128) 518 return FPTOSINT_PPCF128_I128; 519 } 520 return UNKNOWN_LIBCALL; 521 } 522 523 /// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or 524 /// UNKNOWN_LIBCALL if there is none. 525 RTLIB::Libcall RTLIB::getFPTOUINT(EVT OpVT, EVT RetVT) { 526 if (OpVT == MVT::f32) { 527 if (RetVT == MVT::i8) 528 return FPTOUINT_F32_I8; 529 if (RetVT == MVT::i16) 530 return FPTOUINT_F32_I16; 531 if (RetVT == MVT::i32) 532 return FPTOUINT_F32_I32; 533 if (RetVT == MVT::i64) 534 return FPTOUINT_F32_I64; 535 if (RetVT == MVT::i128) 536 return FPTOUINT_F32_I128; 537 } else if (OpVT == MVT::f64) { 538 if (RetVT == MVT::i8) 539 return FPTOUINT_F64_I8; 540 if (RetVT == MVT::i16) 541 return FPTOUINT_F64_I16; 542 if (RetVT == MVT::i32) 543 return FPTOUINT_F64_I32; 544 if (RetVT == MVT::i64) 545 return FPTOUINT_F64_I64; 546 if (RetVT == MVT::i128) 547 return FPTOUINT_F64_I128; 548 } else if (OpVT == MVT::f80) { 549 if (RetVT == MVT::i32) 550 return FPTOUINT_F80_I32; 551 if (RetVT == MVT::i64) 552 return FPTOUINT_F80_I64; 553 if (RetVT == MVT::i128) 554 return FPTOUINT_F80_I128; 555 } else if (OpVT == MVT::f128) { 556 if (RetVT == MVT::i32) 557 return FPTOUINT_F128_I32; 558 if (RetVT == MVT::i64) 559 return FPTOUINT_F128_I64; 560 if (RetVT == MVT::i128) 561 return FPTOUINT_F128_I128; 562 } else if (OpVT == MVT::ppcf128) { 563 if (RetVT == MVT::i32) 564 return FPTOUINT_PPCF128_I32; 565 if (RetVT == MVT::i64) 566 return FPTOUINT_PPCF128_I64; 567 if (RetVT == MVT::i128) 568 return FPTOUINT_PPCF128_I128; 569 } 570 return UNKNOWN_LIBCALL; 571 } 572 573 /// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or 574 /// UNKNOWN_LIBCALL if there is none. 575 RTLIB::Libcall RTLIB::getSINTTOFP(EVT OpVT, EVT RetVT) { 576 if (OpVT == MVT::i32) { 577 if (RetVT == MVT::f32) 578 return SINTTOFP_I32_F32; 579 if (RetVT == MVT::f64) 580 return SINTTOFP_I32_F64; 581 if (RetVT == MVT::f80) 582 return SINTTOFP_I32_F80; 583 if (RetVT == MVT::f128) 584 return SINTTOFP_I32_F128; 585 if (RetVT == MVT::ppcf128) 586 return SINTTOFP_I32_PPCF128; 587 } else if (OpVT == MVT::i64) { 588 if (RetVT == MVT::f32) 589 return SINTTOFP_I64_F32; 590 if (RetVT == MVT::f64) 591 return SINTTOFP_I64_F64; 592 if (RetVT == MVT::f80) 593 return SINTTOFP_I64_F80; 594 if (RetVT == MVT::f128) 595 return SINTTOFP_I64_F128; 596 if (RetVT == MVT::ppcf128) 597 return SINTTOFP_I64_PPCF128; 598 } else if (OpVT == MVT::i128) { 599 if (RetVT == MVT::f32) 600 return SINTTOFP_I128_F32; 601 if (RetVT == MVT::f64) 602 return SINTTOFP_I128_F64; 603 if (RetVT == MVT::f80) 604 return SINTTOFP_I128_F80; 605 if (RetVT == MVT::f128) 606 return SINTTOFP_I128_F128; 607 if (RetVT == MVT::ppcf128) 608 return SINTTOFP_I128_PPCF128; 609 } 610 return UNKNOWN_LIBCALL; 611 } 612 613 /// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or 614 /// UNKNOWN_LIBCALL if there is none. 615 RTLIB::Libcall RTLIB::getUINTTOFP(EVT OpVT, EVT RetVT) { 616 if (OpVT == MVT::i32) { 617 if (RetVT == MVT::f32) 618 return UINTTOFP_I32_F32; 619 if (RetVT == MVT::f64) 620 return UINTTOFP_I32_F64; 621 if (RetVT == MVT::f80) 622 return UINTTOFP_I32_F80; 623 if (RetVT == MVT::f128) 624 return UINTTOFP_I32_F128; 625 if (RetVT == MVT::ppcf128) 626 return UINTTOFP_I32_PPCF128; 627 } else if (OpVT == MVT::i64) { 628 if (RetVT == MVT::f32) 629 return UINTTOFP_I64_F32; 630 if (RetVT == MVT::f64) 631 return UINTTOFP_I64_F64; 632 if (RetVT == MVT::f80) 633 return UINTTOFP_I64_F80; 634 if (RetVT == MVT::f128) 635 return UINTTOFP_I64_F128; 636 if (RetVT == MVT::ppcf128) 637 return UINTTOFP_I64_PPCF128; 638 } else if (OpVT == MVT::i128) { 639 if (RetVT == MVT::f32) 640 return UINTTOFP_I128_F32; 641 if (RetVT == MVT::f64) 642 return UINTTOFP_I128_F64; 643 if (RetVT == MVT::f80) 644 return UINTTOFP_I128_F80; 645 if (RetVT == MVT::f128) 646 return UINTTOFP_I128_F128; 647 if (RetVT == MVT::ppcf128) 648 return UINTTOFP_I128_PPCF128; 649 } 650 return UNKNOWN_LIBCALL; 651 } 652 653 /// InitCmpLibcallCCs - Set default comparison libcall CC. 654 /// 655 static void InitCmpLibcallCCs(ISD::CondCode *CCs) { 656 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL); 657 CCs[RTLIB::OEQ_F32] = ISD::SETEQ; 658 CCs[RTLIB::OEQ_F64] = ISD::SETEQ; 659 CCs[RTLIB::OEQ_F128] = ISD::SETEQ; 660 CCs[RTLIB::UNE_F32] = ISD::SETNE; 661 CCs[RTLIB::UNE_F64] = ISD::SETNE; 662 CCs[RTLIB::UNE_F128] = ISD::SETNE; 663 CCs[RTLIB::OGE_F32] = ISD::SETGE; 664 CCs[RTLIB::OGE_F64] = ISD::SETGE; 665 CCs[RTLIB::OGE_F128] = ISD::SETGE; 666 CCs[RTLIB::OLT_F32] = ISD::SETLT; 667 CCs[RTLIB::OLT_F64] = ISD::SETLT; 668 CCs[RTLIB::OLT_F128] = ISD::SETLT; 669 CCs[RTLIB::OLE_F32] = ISD::SETLE; 670 CCs[RTLIB::OLE_F64] = ISD::SETLE; 671 CCs[RTLIB::OLE_F128] = ISD::SETLE; 672 CCs[RTLIB::OGT_F32] = ISD::SETGT; 673 CCs[RTLIB::OGT_F64] = ISD::SETGT; 674 CCs[RTLIB::OGT_F128] = ISD::SETGT; 675 CCs[RTLIB::UO_F32] = ISD::SETNE; 676 CCs[RTLIB::UO_F64] = ISD::SETNE; 677 CCs[RTLIB::UO_F128] = ISD::SETNE; 678 CCs[RTLIB::O_F32] = ISD::SETEQ; 679 CCs[RTLIB::O_F64] = ISD::SETEQ; 680 CCs[RTLIB::O_F128] = ISD::SETEQ; 681 } 682 683 /// NOTE: The constructor takes ownership of TLOF. 684 TargetLoweringBase::TargetLoweringBase(const TargetMachine &tm, 685 const TargetLoweringObjectFile *tlof) 686 : TM(tm), DL(TM.getDataLayout()), TLOF(*tlof) { 687 initActions(); 688 689 // Perform these initializations only once. 690 IsLittleEndian = DL->isLittleEndian(); 691 MaxStoresPerMemset = MaxStoresPerMemcpy = MaxStoresPerMemmove = 8; 692 MaxStoresPerMemsetOptSize = MaxStoresPerMemcpyOptSize 693 = MaxStoresPerMemmoveOptSize = 4; 694 UseUnderscoreSetJmp = false; 695 UseUnderscoreLongJmp = false; 696 SelectIsExpensive = false; 697 HasMultipleConditionRegisters = false; 698 HasExtractBitsInsn = false; 699 IntDivIsCheap = false; 700 Pow2DivIsCheap = false; 701 JumpIsExpensive = false; 702 PredictableSelectIsExpensive = false; 703 MaskAndBranchFoldingIsLegal = false; 704 StackPointerRegisterToSaveRestore = 0; 705 ExceptionPointerRegister = 0; 706 ExceptionSelectorRegister = 0; 707 BooleanContents = UndefinedBooleanContent; 708 BooleanFloatContents = UndefinedBooleanContent; 709 BooleanVectorContents = UndefinedBooleanContent; 710 SchedPreferenceInfo = Sched::ILP; 711 JumpBufSize = 0; 712 JumpBufAlignment = 0; 713 MinFunctionAlignment = 0; 714 PrefFunctionAlignment = 0; 715 PrefLoopAlignment = 0; 716 MinStackArgumentAlignment = 1; 717 InsertFencesForAtomic = false; 718 SupportJumpTables = true; 719 MinimumJumpTableEntries = 4; 720 721 InitLibcallNames(LibcallRoutineNames, Triple(TM.getTargetTriple())); 722 InitCmpLibcallCCs(CmpLibcallCCs); 723 InitLibcallCallingConvs(LibcallCallingConvs); 724 } 725 726 TargetLoweringBase::~TargetLoweringBase() { 727 delete &TLOF; 728 } 729 730 void TargetLoweringBase::initActions() { 731 // All operations default to being supported. 732 memset(OpActions, 0, sizeof(OpActions)); 733 memset(LoadExtActions, 0, sizeof(LoadExtActions)); 734 memset(TruncStoreActions, 0, sizeof(TruncStoreActions)); 735 memset(IndexedModeActions, 0, sizeof(IndexedModeActions)); 736 memset(CondCodeActions, 0, sizeof(CondCodeActions)); 737 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*)); 738 memset(TargetDAGCombineArray, 0, array_lengthof(TargetDAGCombineArray)); 739 740 // Set default actions for various operations. 741 for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) { 742 // Default all indexed load / store to expand. 743 for (unsigned IM = (unsigned)ISD::PRE_INC; 744 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) { 745 setIndexedLoadAction(IM, (MVT::SimpleValueType)VT, Expand); 746 setIndexedStoreAction(IM, (MVT::SimpleValueType)VT, Expand); 747 } 748 749 // Most backends expect to see the node which just returns the value loaded. 750 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, 751 (MVT::SimpleValueType)VT, Expand); 752 753 // These operations default to expand. 754 setOperationAction(ISD::FGETSIGN, (MVT::SimpleValueType)VT, Expand); 755 setOperationAction(ISD::CONCAT_VECTORS, (MVT::SimpleValueType)VT, Expand); 756 757 // These library functions default to expand. 758 setOperationAction(ISD::FROUND, (MVT::SimpleValueType)VT, Expand); 759 760 // These operations default to expand for vector types. 761 if (VT >= MVT::FIRST_VECTOR_VALUETYPE && 762 VT <= MVT::LAST_VECTOR_VALUETYPE) { 763 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand); 764 setOperationAction(ISD::ANY_EXTEND_VECTOR_INREG, 765 (MVT::SimpleValueType)VT, Expand); 766 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, 767 (MVT::SimpleValueType)VT, Expand); 768 setOperationAction(ISD::ZERO_EXTEND_VECTOR_INREG, 769 (MVT::SimpleValueType)VT, Expand); 770 } 771 } 772 773 // Most targets ignore the @llvm.prefetch intrinsic. 774 setOperationAction(ISD::PREFETCH, MVT::Other, Expand); 775 776 // ConstantFP nodes default to expand. Targets can either change this to 777 // Legal, in which case all fp constants are legal, or use isFPImmLegal() 778 // to optimize expansions for certain constants. 779 setOperationAction(ISD::ConstantFP, MVT::f16, Expand); 780 setOperationAction(ISD::ConstantFP, MVT::f32, Expand); 781 setOperationAction(ISD::ConstantFP, MVT::f64, Expand); 782 setOperationAction(ISD::ConstantFP, MVT::f80, Expand); 783 setOperationAction(ISD::ConstantFP, MVT::f128, Expand); 784 785 // These library functions default to expand. 786 setOperationAction(ISD::FLOG , MVT::f16, Expand); 787 setOperationAction(ISD::FLOG2, MVT::f16, Expand); 788 setOperationAction(ISD::FLOG10, MVT::f16, Expand); 789 setOperationAction(ISD::FEXP , MVT::f16, Expand); 790 setOperationAction(ISD::FEXP2, MVT::f16, Expand); 791 setOperationAction(ISD::FFLOOR, MVT::f16, Expand); 792 setOperationAction(ISD::FNEARBYINT, MVT::f16, Expand); 793 setOperationAction(ISD::FCEIL, MVT::f16, Expand); 794 setOperationAction(ISD::FRINT, MVT::f16, Expand); 795 setOperationAction(ISD::FTRUNC, MVT::f16, Expand); 796 setOperationAction(ISD::FROUND, MVT::f16, Expand); 797 setOperationAction(ISD::FLOG , MVT::f32, Expand); 798 setOperationAction(ISD::FLOG2, MVT::f32, Expand); 799 setOperationAction(ISD::FLOG10, MVT::f32, Expand); 800 setOperationAction(ISD::FEXP , MVT::f32, Expand); 801 setOperationAction(ISD::FEXP2, MVT::f32, Expand); 802 setOperationAction(ISD::FFLOOR, MVT::f32, Expand); 803 setOperationAction(ISD::FNEARBYINT, MVT::f32, Expand); 804 setOperationAction(ISD::FCEIL, MVT::f32, Expand); 805 setOperationAction(ISD::FRINT, MVT::f32, Expand); 806 setOperationAction(ISD::FTRUNC, MVT::f32, Expand); 807 setOperationAction(ISD::FROUND, MVT::f32, Expand); 808 setOperationAction(ISD::FLOG , MVT::f64, Expand); 809 setOperationAction(ISD::FLOG2, MVT::f64, Expand); 810 setOperationAction(ISD::FLOG10, MVT::f64, Expand); 811 setOperationAction(ISD::FEXP , MVT::f64, Expand); 812 setOperationAction(ISD::FEXP2, MVT::f64, Expand); 813 setOperationAction(ISD::FFLOOR, MVT::f64, Expand); 814 setOperationAction(ISD::FNEARBYINT, MVT::f64, Expand); 815 setOperationAction(ISD::FCEIL, MVT::f64, Expand); 816 setOperationAction(ISD::FRINT, MVT::f64, Expand); 817 setOperationAction(ISD::FTRUNC, MVT::f64, Expand); 818 setOperationAction(ISD::FROUND, MVT::f64, Expand); 819 setOperationAction(ISD::FLOG , MVT::f128, Expand); 820 setOperationAction(ISD::FLOG2, MVT::f128, Expand); 821 setOperationAction(ISD::FLOG10, MVT::f128, Expand); 822 setOperationAction(ISD::FEXP , MVT::f128, Expand); 823 setOperationAction(ISD::FEXP2, MVT::f128, Expand); 824 setOperationAction(ISD::FFLOOR, MVT::f128, Expand); 825 setOperationAction(ISD::FNEARBYINT, MVT::f128, Expand); 826 setOperationAction(ISD::FCEIL, MVT::f128, Expand); 827 setOperationAction(ISD::FRINT, MVT::f128, Expand); 828 setOperationAction(ISD::FTRUNC, MVT::f128, Expand); 829 setOperationAction(ISD::FROUND, MVT::f128, Expand); 830 831 // Default ISD::TRAP to expand (which turns it into abort). 832 setOperationAction(ISD::TRAP, MVT::Other, Expand); 833 834 // On most systems, DEBUGTRAP and TRAP have no difference. The "Expand" 835 // here is to inform DAG Legalizer to replace DEBUGTRAP with TRAP. 836 // 837 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Expand); 838 } 839 840 MVT TargetLoweringBase::getPointerTy(uint32_t AS) const { 841 return MVT::getIntegerVT(getPointerSizeInBits(AS)); 842 } 843 844 unsigned TargetLoweringBase::getPointerSizeInBits(uint32_t AS) const { 845 return DL->getPointerSizeInBits(AS); 846 } 847 848 unsigned TargetLoweringBase::getPointerTypeSizeInBits(Type *Ty) const { 849 assert(Ty->isPointerTy()); 850 return getPointerSizeInBits(Ty->getPointerAddressSpace()); 851 } 852 853 MVT TargetLoweringBase::getScalarShiftAmountTy(EVT LHSTy) const { 854 return MVT::getIntegerVT(8*DL->getPointerSize(0)); 855 } 856 857 EVT TargetLoweringBase::getShiftAmountTy(EVT LHSTy) const { 858 assert(LHSTy.isInteger() && "Shift amount is not an integer type!"); 859 if (LHSTy.isVector()) 860 return LHSTy; 861 return getScalarShiftAmountTy(LHSTy); 862 } 863 864 /// canOpTrap - Returns true if the operation can trap for the value type. 865 /// VT must be a legal type. 866 bool TargetLoweringBase::canOpTrap(unsigned Op, EVT VT) const { 867 assert(isTypeLegal(VT)); 868 switch (Op) { 869 default: 870 return false; 871 case ISD::FDIV: 872 case ISD::FREM: 873 case ISD::SDIV: 874 case ISD::UDIV: 875 case ISD::SREM: 876 case ISD::UREM: 877 return true; 878 } 879 } 880 881 882 static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT, 883 unsigned &NumIntermediates, 884 MVT &RegisterVT, 885 TargetLoweringBase *TLI) { 886 // Figure out the right, legal destination reg to copy into. 887 unsigned NumElts = VT.getVectorNumElements(); 888 MVT EltTy = VT.getVectorElementType(); 889 890 unsigned NumVectorRegs = 1; 891 892 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we 893 // could break down into LHS/RHS like LegalizeDAG does. 894 if (!isPowerOf2_32(NumElts)) { 895 NumVectorRegs = NumElts; 896 NumElts = 1; 897 } 898 899 // Divide the input until we get to a supported size. This will always 900 // end with a scalar if the target doesn't support vectors. 901 while (NumElts > 1 && !TLI->isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) { 902 NumElts >>= 1; 903 NumVectorRegs <<= 1; 904 } 905 906 NumIntermediates = NumVectorRegs; 907 908 MVT NewVT = MVT::getVectorVT(EltTy, NumElts); 909 if (!TLI->isTypeLegal(NewVT)) 910 NewVT = EltTy; 911 IntermediateVT = NewVT; 912 913 unsigned NewVTSize = NewVT.getSizeInBits(); 914 915 // Convert sizes such as i33 to i64. 916 if (!isPowerOf2_32(NewVTSize)) 917 NewVTSize = NextPowerOf2(NewVTSize); 918 919 MVT DestVT = TLI->getRegisterType(NewVT); 920 RegisterVT = DestVT; 921 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16. 922 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits()); 923 924 // Otherwise, promotion or legal types use the same number of registers as 925 // the vector decimated to the appropriate level. 926 return NumVectorRegs; 927 } 928 929 /// isLegalRC - Return true if the value types that can be represented by the 930 /// specified register class are all legal. 931 bool TargetLoweringBase::isLegalRC(const TargetRegisterClass *RC) const { 932 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end(); 933 I != E; ++I) { 934 if (isTypeLegal(*I)) 935 return true; 936 } 937 return false; 938 } 939 940 /// Replace/modify any TargetFrameIndex operands with a targte-dependent 941 /// sequence of memory operands that is recognized by PrologEpilogInserter. 942 MachineBasicBlock* 943 TargetLoweringBase::emitPatchPoint(MachineInstr *MI, 944 MachineBasicBlock *MBB) const { 945 MachineFunction &MF = *MI->getParent()->getParent(); 946 947 // MI changes inside this loop as we grow operands. 948 for(unsigned OperIdx = 0; OperIdx != MI->getNumOperands(); ++OperIdx) { 949 MachineOperand &MO = MI->getOperand(OperIdx); 950 if (!MO.isFI()) 951 continue; 952 953 // foldMemoryOperand builds a new MI after replacing a single FI operand 954 // with the canonical set of five x86 addressing-mode operands. 955 int FI = MO.getIndex(); 956 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), MI->getDesc()); 957 958 // Copy operands before the frame-index. 959 for (unsigned i = 0; i < OperIdx; ++i) 960 MIB.addOperand(MI->getOperand(i)); 961 // Add frame index operands: direct-mem-ref tag, #FI, offset. 962 MIB.addImm(StackMaps::DirectMemRefOp); 963 MIB.addOperand(MI->getOperand(OperIdx)); 964 MIB.addImm(0); 965 // Copy the operands after the frame index. 966 for (unsigned i = OperIdx + 1; i != MI->getNumOperands(); ++i) 967 MIB.addOperand(MI->getOperand(i)); 968 969 // Inherit previous memory operands. 970 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end()); 971 assert(MIB->mayLoad() && "Folded a stackmap use to a non-load!"); 972 973 // Add a new memory operand for this FI. 974 const MachineFrameInfo &MFI = *MF.getFrameInfo(); 975 assert(MFI.getObjectOffset(FI) != -1); 976 MachineMemOperand *MMO = 977 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FI), 978 MachineMemOperand::MOLoad, 979 TM.getDataLayout()->getPointerSize(), 980 MFI.getObjectAlignment(FI)); 981 MIB->addMemOperand(MF, MMO); 982 983 // Replace the instruction and update the operand index. 984 MBB->insert(MachineBasicBlock::iterator(MI), MIB); 985 OperIdx += (MIB->getNumOperands() - MI->getNumOperands()) - 1; 986 MI->eraseFromParent(); 987 MI = MIB; 988 } 989 return MBB; 990 } 991 992 /// findRepresentativeClass - Return the largest legal super-reg register class 993 /// of the register class for the specified type and its associated "cost". 994 std::pair<const TargetRegisterClass*, uint8_t> 995 TargetLoweringBase::findRepresentativeClass(MVT VT) const { 996 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo(); 997 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy]; 998 if (!RC) 999 return std::make_pair(RC, 0); 1000 1001 // Compute the set of all super-register classes. 1002 BitVector SuperRegRC(TRI->getNumRegClasses()); 1003 for (SuperRegClassIterator RCI(RC, TRI); RCI.isValid(); ++RCI) 1004 SuperRegRC.setBitsInMask(RCI.getMask()); 1005 1006 // Find the first legal register class with the largest spill size. 1007 const TargetRegisterClass *BestRC = RC; 1008 for (int i = SuperRegRC.find_first(); i >= 0; i = SuperRegRC.find_next(i)) { 1009 const TargetRegisterClass *SuperRC = TRI->getRegClass(i); 1010 // We want the largest possible spill size. 1011 if (SuperRC->getSize() <= BestRC->getSize()) 1012 continue; 1013 if (!isLegalRC(SuperRC)) 1014 continue; 1015 BestRC = SuperRC; 1016 } 1017 return std::make_pair(BestRC, 1); 1018 } 1019 1020 /// computeRegisterProperties - Once all of the register classes are added, 1021 /// this allows us to compute derived properties we expose. 1022 void TargetLoweringBase::computeRegisterProperties() { 1023 assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE && 1024 "Too many value types for ValueTypeActions to hold!"); 1025 1026 // Everything defaults to needing one register. 1027 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) { 1028 NumRegistersForVT[i] = 1; 1029 RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i; 1030 } 1031 // ...except isVoid, which doesn't need any registers. 1032 NumRegistersForVT[MVT::isVoid] = 0; 1033 1034 // Find the largest integer register class. 1035 unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE; 1036 for (; RegClassForVT[LargestIntReg] == nullptr; --LargestIntReg) 1037 assert(LargestIntReg != MVT::i1 && "No integer registers defined!"); 1038 1039 // Every integer value type larger than this largest register takes twice as 1040 // many registers to represent as the previous ValueType. 1041 for (unsigned ExpandedReg = LargestIntReg + 1; 1042 ExpandedReg <= MVT::LAST_INTEGER_VALUETYPE; ++ExpandedReg) { 1043 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1]; 1044 RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg; 1045 TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1); 1046 ValueTypeActions.setTypeAction((MVT::SimpleValueType)ExpandedReg, 1047 TypeExpandInteger); 1048 } 1049 1050 // Inspect all of the ValueType's smaller than the largest integer 1051 // register to see which ones need promotion. 1052 unsigned LegalIntReg = LargestIntReg; 1053 for (unsigned IntReg = LargestIntReg - 1; 1054 IntReg >= (unsigned)MVT::i1; --IntReg) { 1055 MVT IVT = (MVT::SimpleValueType)IntReg; 1056 if (isTypeLegal(IVT)) { 1057 LegalIntReg = IntReg; 1058 } else { 1059 RegisterTypeForVT[IntReg] = TransformToType[IntReg] = 1060 (const MVT::SimpleValueType)LegalIntReg; 1061 ValueTypeActions.setTypeAction(IVT, TypePromoteInteger); 1062 } 1063 } 1064 1065 // ppcf128 type is really two f64's. 1066 if (!isTypeLegal(MVT::ppcf128)) { 1067 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64]; 1068 RegisterTypeForVT[MVT::ppcf128] = MVT::f64; 1069 TransformToType[MVT::ppcf128] = MVT::f64; 1070 ValueTypeActions.setTypeAction(MVT::ppcf128, TypeExpandFloat); 1071 } 1072 1073 // Decide how to handle f128. If the target does not have native f128 support, 1074 // expand it to i128 and we will be generating soft float library calls. 1075 if (!isTypeLegal(MVT::f128)) { 1076 NumRegistersForVT[MVT::f128] = NumRegistersForVT[MVT::i128]; 1077 RegisterTypeForVT[MVT::f128] = RegisterTypeForVT[MVT::i128]; 1078 TransformToType[MVT::f128] = MVT::i128; 1079 ValueTypeActions.setTypeAction(MVT::f128, TypeSoftenFloat); 1080 } 1081 1082 // Decide how to handle f64. If the target does not have native f64 support, 1083 // expand it to i64 and we will be generating soft float library calls. 1084 if (!isTypeLegal(MVT::f64)) { 1085 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64]; 1086 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64]; 1087 TransformToType[MVT::f64] = MVT::i64; 1088 ValueTypeActions.setTypeAction(MVT::f64, TypeSoftenFloat); 1089 } 1090 1091 // Decide how to handle f32. If the target does not have native support for 1092 // f32, promote it to f64 if it is legal. Otherwise, expand it to i32. 1093 if (!isTypeLegal(MVT::f32)) { 1094 if (isTypeLegal(MVT::f64)) { 1095 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::f64]; 1096 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::f64]; 1097 TransformToType[MVT::f32] = MVT::f64; 1098 ValueTypeActions.setTypeAction(MVT::f32, TypePromoteInteger); 1099 } else { 1100 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32]; 1101 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32]; 1102 TransformToType[MVT::f32] = MVT::i32; 1103 ValueTypeActions.setTypeAction(MVT::f32, TypeSoftenFloat); 1104 } 1105 } 1106 1107 // Loop over all of the vector value types to see which need transformations. 1108 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE; 1109 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) { 1110 MVT VT = (MVT::SimpleValueType) i; 1111 if (isTypeLegal(VT)) 1112 continue; 1113 1114 MVT EltVT = VT.getVectorElementType(); 1115 unsigned NElts = VT.getVectorNumElements(); 1116 bool IsLegalWiderType = false; 1117 LegalizeTypeAction PreferredAction = getPreferredVectorAction(VT); 1118 switch (PreferredAction) { 1119 case TypePromoteInteger: { 1120 // Try to promote the elements of integer vectors. If no legal 1121 // promotion was found, fall through to the widen-vector method. 1122 for (unsigned nVT = i + 1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) { 1123 MVT SVT = (MVT::SimpleValueType) nVT; 1124 // Promote vectors of integers to vectors with the same number 1125 // of elements, with a wider element type. 1126 if (SVT.getVectorElementType().getSizeInBits() > EltVT.getSizeInBits() 1127 && SVT.getVectorNumElements() == NElts && isTypeLegal(SVT) 1128 && SVT.getScalarType().isInteger()) { 1129 TransformToType[i] = SVT; 1130 RegisterTypeForVT[i] = SVT; 1131 NumRegistersForVT[i] = 1; 1132 ValueTypeActions.setTypeAction(VT, TypePromoteInteger); 1133 IsLegalWiderType = true; 1134 break; 1135 } 1136 } 1137 if (IsLegalWiderType) 1138 break; 1139 } 1140 case TypeWidenVector: { 1141 // Try to widen the vector. 1142 for (unsigned nVT = i + 1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) { 1143 MVT SVT = (MVT::SimpleValueType) nVT; 1144 if (SVT.getVectorElementType() == EltVT 1145 && SVT.getVectorNumElements() > NElts && isTypeLegal(SVT)) { 1146 TransformToType[i] = SVT; 1147 RegisterTypeForVT[i] = SVT; 1148 NumRegistersForVT[i] = 1; 1149 ValueTypeActions.setTypeAction(VT, TypeWidenVector); 1150 IsLegalWiderType = true; 1151 break; 1152 } 1153 } 1154 if (IsLegalWiderType) 1155 break; 1156 } 1157 case TypeSplitVector: 1158 case TypeScalarizeVector: { 1159 MVT IntermediateVT; 1160 MVT RegisterVT; 1161 unsigned NumIntermediates; 1162 NumRegistersForVT[i] = getVectorTypeBreakdownMVT(VT, IntermediateVT, 1163 NumIntermediates, RegisterVT, this); 1164 RegisterTypeForVT[i] = RegisterVT; 1165 1166 MVT NVT = VT.getPow2VectorType(); 1167 if (NVT == VT) { 1168 // Type is already a power of 2. The default action is to split. 1169 TransformToType[i] = MVT::Other; 1170 if (PreferredAction == TypeScalarizeVector) 1171 ValueTypeActions.setTypeAction(VT, TypeScalarizeVector); 1172 else 1173 ValueTypeActions.setTypeAction(VT, TypeSplitVector); 1174 } else { 1175 TransformToType[i] = NVT; 1176 ValueTypeActions.setTypeAction(VT, TypeWidenVector); 1177 } 1178 break; 1179 } 1180 default: 1181 llvm_unreachable("Unknown vector legalization action!"); 1182 } 1183 } 1184 1185 // Determine the 'representative' register class for each value type. 1186 // An representative register class is the largest (meaning one which is 1187 // not a sub-register class / subreg register class) legal register class for 1188 // a group of value types. For example, on i386, i8, i16, and i32 1189 // representative would be GR32; while on x86_64 it's GR64. 1190 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) { 1191 const TargetRegisterClass* RRC; 1192 uint8_t Cost; 1193 std::tie(RRC, Cost) = findRepresentativeClass((MVT::SimpleValueType)i); 1194 RepRegClassForVT[i] = RRC; 1195 RepRegClassCostForVT[i] = Cost; 1196 } 1197 } 1198 1199 EVT TargetLoweringBase::getSetCCResultType(LLVMContext &, EVT VT) const { 1200 assert(!VT.isVector() && "No default SetCC type for vectors!"); 1201 return getPointerTy(0).SimpleTy; 1202 } 1203 1204 MVT::SimpleValueType TargetLoweringBase::getCmpLibcallReturnType() const { 1205 return MVT::i32; // return the default value 1206 } 1207 1208 /// getVectorTypeBreakdown - Vector types are broken down into some number of 1209 /// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32 1210 /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack. 1211 /// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86. 1212 /// 1213 /// This method returns the number of registers needed, and the VT for each 1214 /// register. It also returns the VT and quantity of the intermediate values 1215 /// before they are promoted/expanded. 1216 /// 1217 unsigned TargetLoweringBase::getVectorTypeBreakdown(LLVMContext &Context, EVT VT, 1218 EVT &IntermediateVT, 1219 unsigned &NumIntermediates, 1220 MVT &RegisterVT) const { 1221 unsigned NumElts = VT.getVectorNumElements(); 1222 1223 // If there is a wider vector type with the same element type as this one, 1224 // or a promoted vector type that has the same number of elements which 1225 // are wider, then we should convert to that legal vector type. 1226 // This handles things like <2 x float> -> <4 x float> and 1227 // <4 x i1> -> <4 x i32>. 1228 LegalizeTypeAction TA = getTypeAction(Context, VT); 1229 if (NumElts != 1 && (TA == TypeWidenVector || TA == TypePromoteInteger)) { 1230 EVT RegisterEVT = getTypeToTransformTo(Context, VT); 1231 if (isTypeLegal(RegisterEVT)) { 1232 IntermediateVT = RegisterEVT; 1233 RegisterVT = RegisterEVT.getSimpleVT(); 1234 NumIntermediates = 1; 1235 return 1; 1236 } 1237 } 1238 1239 // Figure out the right, legal destination reg to copy into. 1240 EVT EltTy = VT.getVectorElementType(); 1241 1242 unsigned NumVectorRegs = 1; 1243 1244 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we 1245 // could break down into LHS/RHS like LegalizeDAG does. 1246 if (!isPowerOf2_32(NumElts)) { 1247 NumVectorRegs = NumElts; 1248 NumElts = 1; 1249 } 1250 1251 // Divide the input until we get to a supported size. This will always 1252 // end with a scalar if the target doesn't support vectors. 1253 while (NumElts > 1 && !isTypeLegal( 1254 EVT::getVectorVT(Context, EltTy, NumElts))) { 1255 NumElts >>= 1; 1256 NumVectorRegs <<= 1; 1257 } 1258 1259 NumIntermediates = NumVectorRegs; 1260 1261 EVT NewVT = EVT::getVectorVT(Context, EltTy, NumElts); 1262 if (!isTypeLegal(NewVT)) 1263 NewVT = EltTy; 1264 IntermediateVT = NewVT; 1265 1266 MVT DestVT = getRegisterType(Context, NewVT); 1267 RegisterVT = DestVT; 1268 unsigned NewVTSize = NewVT.getSizeInBits(); 1269 1270 // Convert sizes such as i33 to i64. 1271 if (!isPowerOf2_32(NewVTSize)) 1272 NewVTSize = NextPowerOf2(NewVTSize); 1273 1274 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16. 1275 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits()); 1276 1277 // Otherwise, promotion or legal types use the same number of registers as 1278 // the vector decimated to the appropriate level. 1279 return NumVectorRegs; 1280 } 1281 1282 /// Get the EVTs and ArgFlags collections that represent the legalized return 1283 /// type of the given function. This does not require a DAG or a return value, 1284 /// and is suitable for use before any DAGs for the function are constructed. 1285 /// TODO: Move this out of TargetLowering.cpp. 1286 void llvm::GetReturnInfo(Type* ReturnType, AttributeSet attr, 1287 SmallVectorImpl<ISD::OutputArg> &Outs, 1288 const TargetLowering &TLI) { 1289 SmallVector<EVT, 4> ValueVTs; 1290 ComputeValueVTs(TLI, ReturnType, ValueVTs); 1291 unsigned NumValues = ValueVTs.size(); 1292 if (NumValues == 0) return; 1293 1294 for (unsigned j = 0, f = NumValues; j != f; ++j) { 1295 EVT VT = ValueVTs[j]; 1296 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 1297 1298 if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::SExt)) 1299 ExtendKind = ISD::SIGN_EXTEND; 1300 else if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::ZExt)) 1301 ExtendKind = ISD::ZERO_EXTEND; 1302 1303 // FIXME: C calling convention requires the return type to be promoted to 1304 // at least 32-bit. But this is not necessary for non-C calling 1305 // conventions. The frontend should mark functions whose return values 1306 // require promoting with signext or zeroext attributes. 1307 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) { 1308 MVT MinVT = TLI.getRegisterType(ReturnType->getContext(), MVT::i32); 1309 if (VT.bitsLT(MinVT)) 1310 VT = MinVT; 1311 } 1312 1313 unsigned NumParts = TLI.getNumRegisters(ReturnType->getContext(), VT); 1314 MVT PartVT = TLI.getRegisterType(ReturnType->getContext(), VT); 1315 1316 // 'inreg' on function refers to return value 1317 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy(); 1318 if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::InReg)) 1319 Flags.setInReg(); 1320 1321 // Propagate extension type if any 1322 if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::SExt)) 1323 Flags.setSExt(); 1324 else if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::ZExt)) 1325 Flags.setZExt(); 1326 1327 for (unsigned i = 0; i < NumParts; ++i) 1328 Outs.push_back(ISD::OutputArg(Flags, PartVT, VT, /*isFixed=*/true, 0, 0)); 1329 } 1330 } 1331 1332 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 1333 /// function arguments in the caller parameter area. This is the actual 1334 /// alignment, not its logarithm. 1335 unsigned TargetLoweringBase::getByValTypeAlignment(Type *Ty) const { 1336 return DL->getABITypeAlignment(Ty); 1337 } 1338 1339 //===----------------------------------------------------------------------===// 1340 // TargetTransformInfo Helpers 1341 //===----------------------------------------------------------------------===// 1342 1343 int TargetLoweringBase::InstructionOpcodeToISD(unsigned Opcode) const { 1344 enum InstructionOpcodes { 1345 #define HANDLE_INST(NUM, OPCODE, CLASS) OPCODE = NUM, 1346 #define LAST_OTHER_INST(NUM) InstructionOpcodesCount = NUM 1347 #include "llvm/IR/Instruction.def" 1348 }; 1349 switch (static_cast<InstructionOpcodes>(Opcode)) { 1350 case Ret: return 0; 1351 case Br: return 0; 1352 case Switch: return 0; 1353 case IndirectBr: return 0; 1354 case Invoke: return 0; 1355 case Resume: return 0; 1356 case Unreachable: return 0; 1357 case Add: return ISD::ADD; 1358 case FAdd: return ISD::FADD; 1359 case Sub: return ISD::SUB; 1360 case FSub: return ISD::FSUB; 1361 case Mul: return ISD::MUL; 1362 case FMul: return ISD::FMUL; 1363 case UDiv: return ISD::UDIV; 1364 case SDiv: return ISD::SDIV; 1365 case FDiv: return ISD::FDIV; 1366 case URem: return ISD::UREM; 1367 case SRem: return ISD::SREM; 1368 case FRem: return ISD::FREM; 1369 case Shl: return ISD::SHL; 1370 case LShr: return ISD::SRL; 1371 case AShr: return ISD::SRA; 1372 case And: return ISD::AND; 1373 case Or: return ISD::OR; 1374 case Xor: return ISD::XOR; 1375 case Alloca: return 0; 1376 case Load: return ISD::LOAD; 1377 case Store: return ISD::STORE; 1378 case GetElementPtr: return 0; 1379 case Fence: return 0; 1380 case AtomicCmpXchg: return 0; 1381 case AtomicRMW: return 0; 1382 case Trunc: return ISD::TRUNCATE; 1383 case ZExt: return ISD::ZERO_EXTEND; 1384 case SExt: return ISD::SIGN_EXTEND; 1385 case FPToUI: return ISD::FP_TO_UINT; 1386 case FPToSI: return ISD::FP_TO_SINT; 1387 case UIToFP: return ISD::UINT_TO_FP; 1388 case SIToFP: return ISD::SINT_TO_FP; 1389 case FPTrunc: return ISD::FP_ROUND; 1390 case FPExt: return ISD::FP_EXTEND; 1391 case PtrToInt: return ISD::BITCAST; 1392 case IntToPtr: return ISD::BITCAST; 1393 case BitCast: return ISD::BITCAST; 1394 case AddrSpaceCast: return ISD::ADDRSPACECAST; 1395 case ICmp: return ISD::SETCC; 1396 case FCmp: return ISD::SETCC; 1397 case PHI: return 0; 1398 case Call: return 0; 1399 case Select: return ISD::SELECT; 1400 case UserOp1: return 0; 1401 case UserOp2: return 0; 1402 case VAArg: return 0; 1403 case ExtractElement: return ISD::EXTRACT_VECTOR_ELT; 1404 case InsertElement: return ISD::INSERT_VECTOR_ELT; 1405 case ShuffleVector: return ISD::VECTOR_SHUFFLE; 1406 case ExtractValue: return ISD::MERGE_VALUES; 1407 case InsertValue: return ISD::MERGE_VALUES; 1408 case LandingPad: return 0; 1409 } 1410 1411 llvm_unreachable("Unknown instruction type encountered!"); 1412 } 1413 1414 std::pair<unsigned, MVT> 1415 TargetLoweringBase::getTypeLegalizationCost(Type *Ty) const { 1416 LLVMContext &C = Ty->getContext(); 1417 EVT MTy = getValueType(Ty); 1418 1419 unsigned Cost = 1; 1420 // We keep legalizing the type until we find a legal kind. We assume that 1421 // the only operation that costs anything is the split. After splitting 1422 // we need to handle two types. 1423 while (true) { 1424 LegalizeKind LK = getTypeConversion(C, MTy); 1425 1426 if (LK.first == TypeLegal) 1427 return std::make_pair(Cost, MTy.getSimpleVT()); 1428 1429 if (LK.first == TypeSplitVector || LK.first == TypeExpandInteger) 1430 Cost *= 2; 1431 1432 // Keep legalizing the type. 1433 MTy = LK.second; 1434 } 1435 } 1436 1437 //===----------------------------------------------------------------------===// 1438 // Loop Strength Reduction hooks 1439 //===----------------------------------------------------------------------===// 1440 1441 /// isLegalAddressingMode - Return true if the addressing mode represented 1442 /// by AM is legal for this target, for a load/store of the specified type. 1443 bool TargetLoweringBase::isLegalAddressingMode(const AddrMode &AM, 1444 Type *Ty) const { 1445 // The default implementation of this implements a conservative RISCy, r+r and 1446 // r+i addr mode. 1447 1448 // Allows a sign-extended 16-bit immediate field. 1449 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1) 1450 return false; 1451 1452 // No global is ever allowed as a base. 1453 if (AM.BaseGV) 1454 return false; 1455 1456 // Only support r+r, 1457 switch (AM.Scale) { 1458 case 0: // "r+i" or just "i", depending on HasBaseReg. 1459 break; 1460 case 1: 1461 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. 1462 return false; 1463 // Otherwise we have r+r or r+i. 1464 break; 1465 case 2: 1466 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. 1467 return false; 1468 // Allow 2*r as r+r. 1469 break; 1470 default: // Don't allow n * r 1471 return false; 1472 } 1473 1474 return true; 1475 } 1476