1 //===-- TargetLoweringBase.cpp - Implement the TargetLoweringBase class ---===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This implements the TargetLoweringBase class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "llvm/Target/TargetLowering.h" 15 #include "llvm/ADT/BitVector.h" 16 #include "llvm/ADT/STLExtras.h" 17 #include "llvm/ADT/Triple.h" 18 #include "llvm/CodeGen/Analysis.h" 19 #include "llvm/CodeGen/MachineFrameInfo.h" 20 #include "llvm/CodeGen/MachineFunction.h" 21 #include "llvm/CodeGen/MachineJumpTableInfo.h" 22 #include "llvm/IR/DataLayout.h" 23 #include "llvm/IR/DerivedTypes.h" 24 #include "llvm/IR/GlobalVariable.h" 25 #include "llvm/MC/MCAsmInfo.h" 26 #include "llvm/MC/MCExpr.h" 27 #include "llvm/Support/CommandLine.h" 28 #include "llvm/Support/ErrorHandling.h" 29 #include "llvm/Support/MathExtras.h" 30 #include "llvm/Target/TargetLoweringObjectFile.h" 31 #include "llvm/Target/TargetMachine.h" 32 #include "llvm/Target/TargetRegisterInfo.h" 33 #include <cctype> 34 using namespace llvm; 35 36 /// InitLibcallNames - Set default libcall names. 37 /// 38 static void InitLibcallNames(const char **Names, const TargetMachine &TM) { 39 Names[RTLIB::SHL_I16] = "__ashlhi3"; 40 Names[RTLIB::SHL_I32] = "__ashlsi3"; 41 Names[RTLIB::SHL_I64] = "__ashldi3"; 42 Names[RTLIB::SHL_I128] = "__ashlti3"; 43 Names[RTLIB::SRL_I16] = "__lshrhi3"; 44 Names[RTLIB::SRL_I32] = "__lshrsi3"; 45 Names[RTLIB::SRL_I64] = "__lshrdi3"; 46 Names[RTLIB::SRL_I128] = "__lshrti3"; 47 Names[RTLIB::SRA_I16] = "__ashrhi3"; 48 Names[RTLIB::SRA_I32] = "__ashrsi3"; 49 Names[RTLIB::SRA_I64] = "__ashrdi3"; 50 Names[RTLIB::SRA_I128] = "__ashrti3"; 51 Names[RTLIB::MUL_I8] = "__mulqi3"; 52 Names[RTLIB::MUL_I16] = "__mulhi3"; 53 Names[RTLIB::MUL_I32] = "__mulsi3"; 54 Names[RTLIB::MUL_I64] = "__muldi3"; 55 Names[RTLIB::MUL_I128] = "__multi3"; 56 Names[RTLIB::MULO_I32] = "__mulosi4"; 57 Names[RTLIB::MULO_I64] = "__mulodi4"; 58 Names[RTLIB::MULO_I128] = "__muloti4"; 59 Names[RTLIB::SDIV_I8] = "__divqi3"; 60 Names[RTLIB::SDIV_I16] = "__divhi3"; 61 Names[RTLIB::SDIV_I32] = "__divsi3"; 62 Names[RTLIB::SDIV_I64] = "__divdi3"; 63 Names[RTLIB::SDIV_I128] = "__divti3"; 64 Names[RTLIB::UDIV_I8] = "__udivqi3"; 65 Names[RTLIB::UDIV_I16] = "__udivhi3"; 66 Names[RTLIB::UDIV_I32] = "__udivsi3"; 67 Names[RTLIB::UDIV_I64] = "__udivdi3"; 68 Names[RTLIB::UDIV_I128] = "__udivti3"; 69 Names[RTLIB::SREM_I8] = "__modqi3"; 70 Names[RTLIB::SREM_I16] = "__modhi3"; 71 Names[RTLIB::SREM_I32] = "__modsi3"; 72 Names[RTLIB::SREM_I64] = "__moddi3"; 73 Names[RTLIB::SREM_I128] = "__modti3"; 74 Names[RTLIB::UREM_I8] = "__umodqi3"; 75 Names[RTLIB::UREM_I16] = "__umodhi3"; 76 Names[RTLIB::UREM_I32] = "__umodsi3"; 77 Names[RTLIB::UREM_I64] = "__umoddi3"; 78 Names[RTLIB::UREM_I128] = "__umodti3"; 79 80 // These are generally not available. 81 Names[RTLIB::SDIVREM_I8] = 0; 82 Names[RTLIB::SDIVREM_I16] = 0; 83 Names[RTLIB::SDIVREM_I32] = 0; 84 Names[RTLIB::SDIVREM_I64] = 0; 85 Names[RTLIB::SDIVREM_I128] = 0; 86 Names[RTLIB::UDIVREM_I8] = 0; 87 Names[RTLIB::UDIVREM_I16] = 0; 88 Names[RTLIB::UDIVREM_I32] = 0; 89 Names[RTLIB::UDIVREM_I64] = 0; 90 Names[RTLIB::UDIVREM_I128] = 0; 91 92 Names[RTLIB::NEG_I32] = "__negsi2"; 93 Names[RTLIB::NEG_I64] = "__negdi2"; 94 Names[RTLIB::ADD_F32] = "__addsf3"; 95 Names[RTLIB::ADD_F64] = "__adddf3"; 96 Names[RTLIB::ADD_F80] = "__addxf3"; 97 Names[RTLIB::ADD_F128] = "__addtf3"; 98 Names[RTLIB::ADD_PPCF128] = "__gcc_qadd"; 99 Names[RTLIB::SUB_F32] = "__subsf3"; 100 Names[RTLIB::SUB_F64] = "__subdf3"; 101 Names[RTLIB::SUB_F80] = "__subxf3"; 102 Names[RTLIB::SUB_F128] = "__subtf3"; 103 Names[RTLIB::SUB_PPCF128] = "__gcc_qsub"; 104 Names[RTLIB::MUL_F32] = "__mulsf3"; 105 Names[RTLIB::MUL_F64] = "__muldf3"; 106 Names[RTLIB::MUL_F80] = "__mulxf3"; 107 Names[RTLIB::MUL_F128] = "__multf3"; 108 Names[RTLIB::MUL_PPCF128] = "__gcc_qmul"; 109 Names[RTLIB::DIV_F32] = "__divsf3"; 110 Names[RTLIB::DIV_F64] = "__divdf3"; 111 Names[RTLIB::DIV_F80] = "__divxf3"; 112 Names[RTLIB::DIV_F128] = "__divtf3"; 113 Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv"; 114 Names[RTLIB::REM_F32] = "fmodf"; 115 Names[RTLIB::REM_F64] = "fmod"; 116 Names[RTLIB::REM_F80] = "fmodl"; 117 Names[RTLIB::REM_F128] = "fmodl"; 118 Names[RTLIB::REM_PPCF128] = "fmodl"; 119 Names[RTLIB::FMA_F32] = "fmaf"; 120 Names[RTLIB::FMA_F64] = "fma"; 121 Names[RTLIB::FMA_F80] = "fmal"; 122 Names[RTLIB::FMA_F128] = "fmal"; 123 Names[RTLIB::FMA_PPCF128] = "fmal"; 124 Names[RTLIB::POWI_F32] = "__powisf2"; 125 Names[RTLIB::POWI_F64] = "__powidf2"; 126 Names[RTLIB::POWI_F80] = "__powixf2"; 127 Names[RTLIB::POWI_F128] = "__powitf2"; 128 Names[RTLIB::POWI_PPCF128] = "__powitf2"; 129 Names[RTLIB::SQRT_F32] = "sqrtf"; 130 Names[RTLIB::SQRT_F64] = "sqrt"; 131 Names[RTLIB::SQRT_F80] = "sqrtl"; 132 Names[RTLIB::SQRT_F128] = "sqrtl"; 133 Names[RTLIB::SQRT_PPCF128] = "sqrtl"; 134 Names[RTLIB::LOG_F32] = "logf"; 135 Names[RTLIB::LOG_F64] = "log"; 136 Names[RTLIB::LOG_F80] = "logl"; 137 Names[RTLIB::LOG_F128] = "logl"; 138 Names[RTLIB::LOG_PPCF128] = "logl"; 139 Names[RTLIB::LOG2_F32] = "log2f"; 140 Names[RTLIB::LOG2_F64] = "log2"; 141 Names[RTLIB::LOG2_F80] = "log2l"; 142 Names[RTLIB::LOG2_F128] = "log2l"; 143 Names[RTLIB::LOG2_PPCF128] = "log2l"; 144 Names[RTLIB::LOG10_F32] = "log10f"; 145 Names[RTLIB::LOG10_F64] = "log10"; 146 Names[RTLIB::LOG10_F80] = "log10l"; 147 Names[RTLIB::LOG10_F128] = "log10l"; 148 Names[RTLIB::LOG10_PPCF128] = "log10l"; 149 Names[RTLIB::EXP_F32] = "expf"; 150 Names[RTLIB::EXP_F64] = "exp"; 151 Names[RTLIB::EXP_F80] = "expl"; 152 Names[RTLIB::EXP_F128] = "expl"; 153 Names[RTLIB::EXP_PPCF128] = "expl"; 154 Names[RTLIB::EXP2_F32] = "exp2f"; 155 Names[RTLIB::EXP2_F64] = "exp2"; 156 Names[RTLIB::EXP2_F80] = "exp2l"; 157 Names[RTLIB::EXP2_F128] = "exp2l"; 158 Names[RTLIB::EXP2_PPCF128] = "exp2l"; 159 Names[RTLIB::SIN_F32] = "sinf"; 160 Names[RTLIB::SIN_F64] = "sin"; 161 Names[RTLIB::SIN_F80] = "sinl"; 162 Names[RTLIB::SIN_F128] = "sinl"; 163 Names[RTLIB::SIN_PPCF128] = "sinl"; 164 Names[RTLIB::COS_F32] = "cosf"; 165 Names[RTLIB::COS_F64] = "cos"; 166 Names[RTLIB::COS_F80] = "cosl"; 167 Names[RTLIB::COS_F128] = "cosl"; 168 Names[RTLIB::COS_PPCF128] = "cosl"; 169 Names[RTLIB::POW_F32] = "powf"; 170 Names[RTLIB::POW_F64] = "pow"; 171 Names[RTLIB::POW_F80] = "powl"; 172 Names[RTLIB::POW_F128] = "powl"; 173 Names[RTLIB::POW_PPCF128] = "powl"; 174 Names[RTLIB::CEIL_F32] = "ceilf"; 175 Names[RTLIB::CEIL_F64] = "ceil"; 176 Names[RTLIB::CEIL_F80] = "ceill"; 177 Names[RTLIB::CEIL_F128] = "ceill"; 178 Names[RTLIB::CEIL_PPCF128] = "ceill"; 179 Names[RTLIB::TRUNC_F32] = "truncf"; 180 Names[RTLIB::TRUNC_F64] = "trunc"; 181 Names[RTLIB::TRUNC_F80] = "truncl"; 182 Names[RTLIB::TRUNC_F128] = "truncl"; 183 Names[RTLIB::TRUNC_PPCF128] = "truncl"; 184 Names[RTLIB::RINT_F32] = "rintf"; 185 Names[RTLIB::RINT_F64] = "rint"; 186 Names[RTLIB::RINT_F80] = "rintl"; 187 Names[RTLIB::RINT_F128] = "rintl"; 188 Names[RTLIB::RINT_PPCF128] = "rintl"; 189 Names[RTLIB::NEARBYINT_F32] = "nearbyintf"; 190 Names[RTLIB::NEARBYINT_F64] = "nearbyint"; 191 Names[RTLIB::NEARBYINT_F80] = "nearbyintl"; 192 Names[RTLIB::NEARBYINT_F128] = "nearbyintl"; 193 Names[RTLIB::NEARBYINT_PPCF128] = "nearbyintl"; 194 Names[RTLIB::ROUND_F32] = "roundf"; 195 Names[RTLIB::ROUND_F64] = "round"; 196 Names[RTLIB::ROUND_F80] = "roundl"; 197 Names[RTLIB::ROUND_F128] = "roundl"; 198 Names[RTLIB::ROUND_PPCF128] = "roundl"; 199 Names[RTLIB::FLOOR_F32] = "floorf"; 200 Names[RTLIB::FLOOR_F64] = "floor"; 201 Names[RTLIB::FLOOR_F80] = "floorl"; 202 Names[RTLIB::FLOOR_F128] = "floorl"; 203 Names[RTLIB::FLOOR_PPCF128] = "floorl"; 204 Names[RTLIB::COPYSIGN_F32] = "copysignf"; 205 Names[RTLIB::COPYSIGN_F64] = "copysign"; 206 Names[RTLIB::COPYSIGN_F80] = "copysignl"; 207 Names[RTLIB::COPYSIGN_F128] = "copysignl"; 208 Names[RTLIB::COPYSIGN_PPCF128] = "copysignl"; 209 Names[RTLIB::FPEXT_F64_F128] = "__extenddftf2"; 210 Names[RTLIB::FPEXT_F32_F128] = "__extendsftf2"; 211 Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2"; 212 Names[RTLIB::FPEXT_F16_F32] = "__gnu_h2f_ieee"; 213 Names[RTLIB::FPROUND_F32_F16] = "__gnu_f2h_ieee"; 214 Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2"; 215 Names[RTLIB::FPROUND_F80_F32] = "__truncxfsf2"; 216 Names[RTLIB::FPROUND_F128_F32] = "__trunctfsf2"; 217 Names[RTLIB::FPROUND_PPCF128_F32] = "__trunctfsf2"; 218 Names[RTLIB::FPROUND_F80_F64] = "__truncxfdf2"; 219 Names[RTLIB::FPROUND_F128_F64] = "__trunctfdf2"; 220 Names[RTLIB::FPROUND_PPCF128_F64] = "__trunctfdf2"; 221 Names[RTLIB::FPTOSINT_F32_I8] = "__fixsfqi"; 222 Names[RTLIB::FPTOSINT_F32_I16] = "__fixsfhi"; 223 Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi"; 224 Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi"; 225 Names[RTLIB::FPTOSINT_F32_I128] = "__fixsfti"; 226 Names[RTLIB::FPTOSINT_F64_I8] = "__fixdfqi"; 227 Names[RTLIB::FPTOSINT_F64_I16] = "__fixdfhi"; 228 Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi"; 229 Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi"; 230 Names[RTLIB::FPTOSINT_F64_I128] = "__fixdfti"; 231 Names[RTLIB::FPTOSINT_F80_I32] = "__fixxfsi"; 232 Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi"; 233 Names[RTLIB::FPTOSINT_F80_I128] = "__fixxfti"; 234 Names[RTLIB::FPTOSINT_F128_I32] = "__fixtfsi"; 235 Names[RTLIB::FPTOSINT_F128_I64] = "__fixtfdi"; 236 Names[RTLIB::FPTOSINT_F128_I128] = "__fixtfti"; 237 Names[RTLIB::FPTOSINT_PPCF128_I32] = "__fixtfsi"; 238 Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi"; 239 Names[RTLIB::FPTOSINT_PPCF128_I128] = "__fixtfti"; 240 Names[RTLIB::FPTOUINT_F32_I8] = "__fixunssfqi"; 241 Names[RTLIB::FPTOUINT_F32_I16] = "__fixunssfhi"; 242 Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi"; 243 Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi"; 244 Names[RTLIB::FPTOUINT_F32_I128] = "__fixunssfti"; 245 Names[RTLIB::FPTOUINT_F64_I8] = "__fixunsdfqi"; 246 Names[RTLIB::FPTOUINT_F64_I16] = "__fixunsdfhi"; 247 Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi"; 248 Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi"; 249 Names[RTLIB::FPTOUINT_F64_I128] = "__fixunsdfti"; 250 Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi"; 251 Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi"; 252 Names[RTLIB::FPTOUINT_F80_I128] = "__fixunsxfti"; 253 Names[RTLIB::FPTOUINT_F128_I32] = "__fixunstfsi"; 254 Names[RTLIB::FPTOUINT_F128_I64] = "__fixunstfdi"; 255 Names[RTLIB::FPTOUINT_F128_I128] = "__fixunstfti"; 256 Names[RTLIB::FPTOUINT_PPCF128_I32] = "__fixunstfsi"; 257 Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi"; 258 Names[RTLIB::FPTOUINT_PPCF128_I128] = "__fixunstfti"; 259 Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf"; 260 Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf"; 261 Names[RTLIB::SINTTOFP_I32_F80] = "__floatsixf"; 262 Names[RTLIB::SINTTOFP_I32_F128] = "__floatsitf"; 263 Names[RTLIB::SINTTOFP_I32_PPCF128] = "__floatsitf"; 264 Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf"; 265 Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf"; 266 Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf"; 267 Names[RTLIB::SINTTOFP_I64_F128] = "__floatditf"; 268 Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf"; 269 Names[RTLIB::SINTTOFP_I128_F32] = "__floattisf"; 270 Names[RTLIB::SINTTOFP_I128_F64] = "__floattidf"; 271 Names[RTLIB::SINTTOFP_I128_F80] = "__floattixf"; 272 Names[RTLIB::SINTTOFP_I128_F128] = "__floattitf"; 273 Names[RTLIB::SINTTOFP_I128_PPCF128] = "__floattitf"; 274 Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf"; 275 Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf"; 276 Names[RTLIB::UINTTOFP_I32_F80] = "__floatunsixf"; 277 Names[RTLIB::UINTTOFP_I32_F128] = "__floatunsitf"; 278 Names[RTLIB::UINTTOFP_I32_PPCF128] = "__floatunsitf"; 279 Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf"; 280 Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf"; 281 Names[RTLIB::UINTTOFP_I64_F80] = "__floatundixf"; 282 Names[RTLIB::UINTTOFP_I64_F128] = "__floatunditf"; 283 Names[RTLIB::UINTTOFP_I64_PPCF128] = "__floatunditf"; 284 Names[RTLIB::UINTTOFP_I128_F32] = "__floatuntisf"; 285 Names[RTLIB::UINTTOFP_I128_F64] = "__floatuntidf"; 286 Names[RTLIB::UINTTOFP_I128_F80] = "__floatuntixf"; 287 Names[RTLIB::UINTTOFP_I128_F128] = "__floatuntitf"; 288 Names[RTLIB::UINTTOFP_I128_PPCF128] = "__floatuntitf"; 289 Names[RTLIB::OEQ_F32] = "__eqsf2"; 290 Names[RTLIB::OEQ_F64] = "__eqdf2"; 291 Names[RTLIB::OEQ_F128] = "__eqtf2"; 292 Names[RTLIB::UNE_F32] = "__nesf2"; 293 Names[RTLIB::UNE_F64] = "__nedf2"; 294 Names[RTLIB::UNE_F128] = "__netf2"; 295 Names[RTLIB::OGE_F32] = "__gesf2"; 296 Names[RTLIB::OGE_F64] = "__gedf2"; 297 Names[RTLIB::OGE_F128] = "__getf2"; 298 Names[RTLIB::OLT_F32] = "__ltsf2"; 299 Names[RTLIB::OLT_F64] = "__ltdf2"; 300 Names[RTLIB::OLT_F128] = "__lttf2"; 301 Names[RTLIB::OLE_F32] = "__lesf2"; 302 Names[RTLIB::OLE_F64] = "__ledf2"; 303 Names[RTLIB::OLE_F128] = "__letf2"; 304 Names[RTLIB::OGT_F32] = "__gtsf2"; 305 Names[RTLIB::OGT_F64] = "__gtdf2"; 306 Names[RTLIB::OGT_F128] = "__gttf2"; 307 Names[RTLIB::UO_F32] = "__unordsf2"; 308 Names[RTLIB::UO_F64] = "__unorddf2"; 309 Names[RTLIB::UO_F128] = "__unordtf2"; 310 Names[RTLIB::O_F32] = "__unordsf2"; 311 Names[RTLIB::O_F64] = "__unorddf2"; 312 Names[RTLIB::O_F128] = "__unordtf2"; 313 Names[RTLIB::MEMCPY] = "memcpy"; 314 Names[RTLIB::MEMMOVE] = "memmove"; 315 Names[RTLIB::MEMSET] = "memset"; 316 Names[RTLIB::UNWIND_RESUME] = "_Unwind_Resume"; 317 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1] = "__sync_val_compare_and_swap_1"; 318 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2] = "__sync_val_compare_and_swap_2"; 319 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4] = "__sync_val_compare_and_swap_4"; 320 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8] = "__sync_val_compare_and_swap_8"; 321 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_16] = "__sync_val_compare_and_swap_16"; 322 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_1] = "__sync_lock_test_and_set_1"; 323 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_2] = "__sync_lock_test_and_set_2"; 324 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_4] = "__sync_lock_test_and_set_4"; 325 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_8] = "__sync_lock_test_and_set_8"; 326 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_16] = "__sync_lock_test_and_set_16"; 327 Names[RTLIB::SYNC_FETCH_AND_ADD_1] = "__sync_fetch_and_add_1"; 328 Names[RTLIB::SYNC_FETCH_AND_ADD_2] = "__sync_fetch_and_add_2"; 329 Names[RTLIB::SYNC_FETCH_AND_ADD_4] = "__sync_fetch_and_add_4"; 330 Names[RTLIB::SYNC_FETCH_AND_ADD_8] = "__sync_fetch_and_add_8"; 331 Names[RTLIB::SYNC_FETCH_AND_ADD_16] = "__sync_fetch_and_add_16"; 332 Names[RTLIB::SYNC_FETCH_AND_SUB_1] = "__sync_fetch_and_sub_1"; 333 Names[RTLIB::SYNC_FETCH_AND_SUB_2] = "__sync_fetch_and_sub_2"; 334 Names[RTLIB::SYNC_FETCH_AND_SUB_4] = "__sync_fetch_and_sub_4"; 335 Names[RTLIB::SYNC_FETCH_AND_SUB_8] = "__sync_fetch_and_sub_8"; 336 Names[RTLIB::SYNC_FETCH_AND_SUB_16] = "__sync_fetch_and_sub_16"; 337 Names[RTLIB::SYNC_FETCH_AND_AND_1] = "__sync_fetch_and_and_1"; 338 Names[RTLIB::SYNC_FETCH_AND_AND_2] = "__sync_fetch_and_and_2"; 339 Names[RTLIB::SYNC_FETCH_AND_AND_4] = "__sync_fetch_and_and_4"; 340 Names[RTLIB::SYNC_FETCH_AND_AND_8] = "__sync_fetch_and_and_8"; 341 Names[RTLIB::SYNC_FETCH_AND_AND_16] = "__sync_fetch_and_and_16"; 342 Names[RTLIB::SYNC_FETCH_AND_OR_1] = "__sync_fetch_and_or_1"; 343 Names[RTLIB::SYNC_FETCH_AND_OR_2] = "__sync_fetch_and_or_2"; 344 Names[RTLIB::SYNC_FETCH_AND_OR_4] = "__sync_fetch_and_or_4"; 345 Names[RTLIB::SYNC_FETCH_AND_OR_8] = "__sync_fetch_and_or_8"; 346 Names[RTLIB::SYNC_FETCH_AND_OR_16] = "__sync_fetch_and_or_16"; 347 Names[RTLIB::SYNC_FETCH_AND_XOR_1] = "__sync_fetch_and_xor_1"; 348 Names[RTLIB::SYNC_FETCH_AND_XOR_2] = "__sync_fetch_and_xor_2"; 349 Names[RTLIB::SYNC_FETCH_AND_XOR_4] = "__sync_fetch_and_xor_4"; 350 Names[RTLIB::SYNC_FETCH_AND_XOR_8] = "__sync_fetch_and_xor_8"; 351 Names[RTLIB::SYNC_FETCH_AND_XOR_16] = "__sync_fetch_and_xor_16"; 352 Names[RTLIB::SYNC_FETCH_AND_NAND_1] = "__sync_fetch_and_nand_1"; 353 Names[RTLIB::SYNC_FETCH_AND_NAND_2] = "__sync_fetch_and_nand_2"; 354 Names[RTLIB::SYNC_FETCH_AND_NAND_4] = "__sync_fetch_and_nand_4"; 355 Names[RTLIB::SYNC_FETCH_AND_NAND_8] = "__sync_fetch_and_nand_8"; 356 Names[RTLIB::SYNC_FETCH_AND_NAND_16] = "__sync_fetch_and_nand_16"; 357 358 if (Triple(TM.getTargetTriple()).getEnvironment() == Triple::GNU) { 359 Names[RTLIB::SINCOS_F32] = "sincosf"; 360 Names[RTLIB::SINCOS_F64] = "sincos"; 361 Names[RTLIB::SINCOS_F80] = "sincosl"; 362 Names[RTLIB::SINCOS_F128] = "sincosl"; 363 Names[RTLIB::SINCOS_PPCF128] = "sincosl"; 364 } else { 365 // These are generally not available. 366 Names[RTLIB::SINCOS_F32] = 0; 367 Names[RTLIB::SINCOS_F64] = 0; 368 Names[RTLIB::SINCOS_F80] = 0; 369 Names[RTLIB::SINCOS_F128] = 0; 370 Names[RTLIB::SINCOS_PPCF128] = 0; 371 } 372 373 if (Triple(TM.getTargetTriple()).getOS() != Triple::OpenBSD) { 374 Names[RTLIB::STACKPROTECTOR_CHECK_FAIL] = "__stack_chk_fail"; 375 } else { 376 // These are generally not available. 377 Names[RTLIB::STACKPROTECTOR_CHECK_FAIL] = 0; 378 } 379 } 380 381 /// InitLibcallCallingConvs - Set default libcall CallingConvs. 382 /// 383 static void InitLibcallCallingConvs(CallingConv::ID *CCs) { 384 for (int i = 0; i < RTLIB::UNKNOWN_LIBCALL; ++i) { 385 CCs[i] = CallingConv::C; 386 } 387 } 388 389 /// getFPEXT - Return the FPEXT_*_* value for the given types, or 390 /// UNKNOWN_LIBCALL if there is none. 391 RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) { 392 if (OpVT == MVT::f32) { 393 if (RetVT == MVT::f64) 394 return FPEXT_F32_F64; 395 if (RetVT == MVT::f128) 396 return FPEXT_F32_F128; 397 } else if (OpVT == MVT::f64) { 398 if (RetVT == MVT::f128) 399 return FPEXT_F64_F128; 400 } 401 402 return UNKNOWN_LIBCALL; 403 } 404 405 /// getFPROUND - Return the FPROUND_*_* value for the given types, or 406 /// UNKNOWN_LIBCALL if there is none. 407 RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) { 408 if (RetVT == MVT::f32) { 409 if (OpVT == MVT::f64) 410 return FPROUND_F64_F32; 411 if (OpVT == MVT::f80) 412 return FPROUND_F80_F32; 413 if (OpVT == MVT::f128) 414 return FPROUND_F128_F32; 415 if (OpVT == MVT::ppcf128) 416 return FPROUND_PPCF128_F32; 417 } else if (RetVT == MVT::f64) { 418 if (OpVT == MVT::f80) 419 return FPROUND_F80_F64; 420 if (OpVT == MVT::f128) 421 return FPROUND_F128_F64; 422 if (OpVT == MVT::ppcf128) 423 return FPROUND_PPCF128_F64; 424 } 425 426 return UNKNOWN_LIBCALL; 427 } 428 429 /// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or 430 /// UNKNOWN_LIBCALL if there is none. 431 RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT, EVT RetVT) { 432 if (OpVT == MVT::f32) { 433 if (RetVT == MVT::i8) 434 return FPTOSINT_F32_I8; 435 if (RetVT == MVT::i16) 436 return FPTOSINT_F32_I16; 437 if (RetVT == MVT::i32) 438 return FPTOSINT_F32_I32; 439 if (RetVT == MVT::i64) 440 return FPTOSINT_F32_I64; 441 if (RetVT == MVT::i128) 442 return FPTOSINT_F32_I128; 443 } else if (OpVT == MVT::f64) { 444 if (RetVT == MVT::i8) 445 return FPTOSINT_F64_I8; 446 if (RetVT == MVT::i16) 447 return FPTOSINT_F64_I16; 448 if (RetVT == MVT::i32) 449 return FPTOSINT_F64_I32; 450 if (RetVT == MVT::i64) 451 return FPTOSINT_F64_I64; 452 if (RetVT == MVT::i128) 453 return FPTOSINT_F64_I128; 454 } else if (OpVT == MVT::f80) { 455 if (RetVT == MVT::i32) 456 return FPTOSINT_F80_I32; 457 if (RetVT == MVT::i64) 458 return FPTOSINT_F80_I64; 459 if (RetVT == MVT::i128) 460 return FPTOSINT_F80_I128; 461 } else if (OpVT == MVT::f128) { 462 if (RetVT == MVT::i32) 463 return FPTOSINT_F128_I32; 464 if (RetVT == MVT::i64) 465 return FPTOSINT_F128_I64; 466 if (RetVT == MVT::i128) 467 return FPTOSINT_F128_I128; 468 } else if (OpVT == MVT::ppcf128) { 469 if (RetVT == MVT::i32) 470 return FPTOSINT_PPCF128_I32; 471 if (RetVT == MVT::i64) 472 return FPTOSINT_PPCF128_I64; 473 if (RetVT == MVT::i128) 474 return FPTOSINT_PPCF128_I128; 475 } 476 return UNKNOWN_LIBCALL; 477 } 478 479 /// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or 480 /// UNKNOWN_LIBCALL if there is none. 481 RTLIB::Libcall RTLIB::getFPTOUINT(EVT OpVT, EVT RetVT) { 482 if (OpVT == MVT::f32) { 483 if (RetVT == MVT::i8) 484 return FPTOUINT_F32_I8; 485 if (RetVT == MVT::i16) 486 return FPTOUINT_F32_I16; 487 if (RetVT == MVT::i32) 488 return FPTOUINT_F32_I32; 489 if (RetVT == MVT::i64) 490 return FPTOUINT_F32_I64; 491 if (RetVT == MVT::i128) 492 return FPTOUINT_F32_I128; 493 } else if (OpVT == MVT::f64) { 494 if (RetVT == MVT::i8) 495 return FPTOUINT_F64_I8; 496 if (RetVT == MVT::i16) 497 return FPTOUINT_F64_I16; 498 if (RetVT == MVT::i32) 499 return FPTOUINT_F64_I32; 500 if (RetVT == MVT::i64) 501 return FPTOUINT_F64_I64; 502 if (RetVT == MVT::i128) 503 return FPTOUINT_F64_I128; 504 } else if (OpVT == MVT::f80) { 505 if (RetVT == MVT::i32) 506 return FPTOUINT_F80_I32; 507 if (RetVT == MVT::i64) 508 return FPTOUINT_F80_I64; 509 if (RetVT == MVT::i128) 510 return FPTOUINT_F80_I128; 511 } else if (OpVT == MVT::f128) { 512 if (RetVT == MVT::i32) 513 return FPTOUINT_F128_I32; 514 if (RetVT == MVT::i64) 515 return FPTOUINT_F128_I64; 516 if (RetVT == MVT::i128) 517 return FPTOUINT_F128_I128; 518 } else if (OpVT == MVT::ppcf128) { 519 if (RetVT == MVT::i32) 520 return FPTOUINT_PPCF128_I32; 521 if (RetVT == MVT::i64) 522 return FPTOUINT_PPCF128_I64; 523 if (RetVT == MVT::i128) 524 return FPTOUINT_PPCF128_I128; 525 } 526 return UNKNOWN_LIBCALL; 527 } 528 529 /// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or 530 /// UNKNOWN_LIBCALL if there is none. 531 RTLIB::Libcall RTLIB::getSINTTOFP(EVT OpVT, EVT RetVT) { 532 if (OpVT == MVT::i32) { 533 if (RetVT == MVT::f32) 534 return SINTTOFP_I32_F32; 535 if (RetVT == MVT::f64) 536 return SINTTOFP_I32_F64; 537 if (RetVT == MVT::f80) 538 return SINTTOFP_I32_F80; 539 if (RetVT == MVT::f128) 540 return SINTTOFP_I32_F128; 541 if (RetVT == MVT::ppcf128) 542 return SINTTOFP_I32_PPCF128; 543 } else if (OpVT == MVT::i64) { 544 if (RetVT == MVT::f32) 545 return SINTTOFP_I64_F32; 546 if (RetVT == MVT::f64) 547 return SINTTOFP_I64_F64; 548 if (RetVT == MVT::f80) 549 return SINTTOFP_I64_F80; 550 if (RetVT == MVT::f128) 551 return SINTTOFP_I64_F128; 552 if (RetVT == MVT::ppcf128) 553 return SINTTOFP_I64_PPCF128; 554 } else if (OpVT == MVT::i128) { 555 if (RetVT == MVT::f32) 556 return SINTTOFP_I128_F32; 557 if (RetVT == MVT::f64) 558 return SINTTOFP_I128_F64; 559 if (RetVT == MVT::f80) 560 return SINTTOFP_I128_F80; 561 if (RetVT == MVT::f128) 562 return SINTTOFP_I128_F128; 563 if (RetVT == MVT::ppcf128) 564 return SINTTOFP_I128_PPCF128; 565 } 566 return UNKNOWN_LIBCALL; 567 } 568 569 /// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or 570 /// UNKNOWN_LIBCALL if there is none. 571 RTLIB::Libcall RTLIB::getUINTTOFP(EVT OpVT, EVT RetVT) { 572 if (OpVT == MVT::i32) { 573 if (RetVT == MVT::f32) 574 return UINTTOFP_I32_F32; 575 if (RetVT == MVT::f64) 576 return UINTTOFP_I32_F64; 577 if (RetVT == MVT::f80) 578 return UINTTOFP_I32_F80; 579 if (RetVT == MVT::f128) 580 return UINTTOFP_I32_F128; 581 if (RetVT == MVT::ppcf128) 582 return UINTTOFP_I32_PPCF128; 583 } else if (OpVT == MVT::i64) { 584 if (RetVT == MVT::f32) 585 return UINTTOFP_I64_F32; 586 if (RetVT == MVT::f64) 587 return UINTTOFP_I64_F64; 588 if (RetVT == MVT::f80) 589 return UINTTOFP_I64_F80; 590 if (RetVT == MVT::f128) 591 return UINTTOFP_I64_F128; 592 if (RetVT == MVT::ppcf128) 593 return UINTTOFP_I64_PPCF128; 594 } else if (OpVT == MVT::i128) { 595 if (RetVT == MVT::f32) 596 return UINTTOFP_I128_F32; 597 if (RetVT == MVT::f64) 598 return UINTTOFP_I128_F64; 599 if (RetVT == MVT::f80) 600 return UINTTOFP_I128_F80; 601 if (RetVT == MVT::f128) 602 return UINTTOFP_I128_F128; 603 if (RetVT == MVT::ppcf128) 604 return UINTTOFP_I128_PPCF128; 605 } 606 return UNKNOWN_LIBCALL; 607 } 608 609 /// InitCmpLibcallCCs - Set default comparison libcall CC. 610 /// 611 static void InitCmpLibcallCCs(ISD::CondCode *CCs) { 612 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL); 613 CCs[RTLIB::OEQ_F32] = ISD::SETEQ; 614 CCs[RTLIB::OEQ_F64] = ISD::SETEQ; 615 CCs[RTLIB::OEQ_F128] = ISD::SETEQ; 616 CCs[RTLIB::UNE_F32] = ISD::SETNE; 617 CCs[RTLIB::UNE_F64] = ISD::SETNE; 618 CCs[RTLIB::UNE_F128] = ISD::SETNE; 619 CCs[RTLIB::OGE_F32] = ISD::SETGE; 620 CCs[RTLIB::OGE_F64] = ISD::SETGE; 621 CCs[RTLIB::OGE_F128] = ISD::SETGE; 622 CCs[RTLIB::OLT_F32] = ISD::SETLT; 623 CCs[RTLIB::OLT_F64] = ISD::SETLT; 624 CCs[RTLIB::OLT_F128] = ISD::SETLT; 625 CCs[RTLIB::OLE_F32] = ISD::SETLE; 626 CCs[RTLIB::OLE_F64] = ISD::SETLE; 627 CCs[RTLIB::OLE_F128] = ISD::SETLE; 628 CCs[RTLIB::OGT_F32] = ISD::SETGT; 629 CCs[RTLIB::OGT_F64] = ISD::SETGT; 630 CCs[RTLIB::OGT_F128] = ISD::SETGT; 631 CCs[RTLIB::UO_F32] = ISD::SETNE; 632 CCs[RTLIB::UO_F64] = ISD::SETNE; 633 CCs[RTLIB::UO_F128] = ISD::SETNE; 634 CCs[RTLIB::O_F32] = ISD::SETEQ; 635 CCs[RTLIB::O_F64] = ISD::SETEQ; 636 CCs[RTLIB::O_F128] = ISD::SETEQ; 637 } 638 639 /// NOTE: The constructor takes ownership of TLOF. 640 TargetLoweringBase::TargetLoweringBase(const TargetMachine &tm, 641 const TargetLoweringObjectFile *tlof) 642 : TM(tm), TD(TM.getDataLayout()), TLOF(*tlof) { 643 initActions(); 644 645 // Perform these initializations only once. 646 IsLittleEndian = TD->isLittleEndian(); 647 MaxStoresPerMemset = MaxStoresPerMemcpy = MaxStoresPerMemmove = 8; 648 MaxStoresPerMemsetOptSize = MaxStoresPerMemcpyOptSize 649 = MaxStoresPerMemmoveOptSize = 4; 650 UseUnderscoreSetJmp = false; 651 UseUnderscoreLongJmp = false; 652 SelectIsExpensive = false; 653 IntDivIsCheap = false; 654 Pow2DivIsCheap = false; 655 JumpIsExpensive = false; 656 PredictableSelectIsExpensive = false; 657 StackPointerRegisterToSaveRestore = 0; 658 ExceptionPointerRegister = 0; 659 ExceptionSelectorRegister = 0; 660 BooleanContents = UndefinedBooleanContent; 661 BooleanVectorContents = UndefinedBooleanContent; 662 SchedPreferenceInfo = Sched::ILP; 663 JumpBufSize = 0; 664 JumpBufAlignment = 0; 665 MinFunctionAlignment = 0; 666 PrefFunctionAlignment = 0; 667 PrefLoopAlignment = 0; 668 MinStackArgumentAlignment = 1; 669 InsertFencesForAtomic = false; 670 SupportJumpTables = true; 671 MinimumJumpTableEntries = 4; 672 673 InitLibcallNames(LibcallRoutineNames, TM); 674 InitCmpLibcallCCs(CmpLibcallCCs); 675 InitLibcallCallingConvs(LibcallCallingConvs); 676 } 677 678 TargetLoweringBase::~TargetLoweringBase() { 679 delete &TLOF; 680 } 681 682 void TargetLoweringBase::initActions() { 683 // All operations default to being supported. 684 memset(OpActions, 0, sizeof(OpActions)); 685 memset(LoadExtActions, 0, sizeof(LoadExtActions)); 686 memset(TruncStoreActions, 0, sizeof(TruncStoreActions)); 687 memset(IndexedModeActions, 0, sizeof(IndexedModeActions)); 688 memset(CondCodeActions, 0, sizeof(CondCodeActions)); 689 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*)); 690 memset(TargetDAGCombineArray, 0, array_lengthof(TargetDAGCombineArray)); 691 692 // Set default actions for various operations. 693 for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) { 694 // Default all indexed load / store to expand. 695 for (unsigned IM = (unsigned)ISD::PRE_INC; 696 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) { 697 setIndexedLoadAction(IM, (MVT::SimpleValueType)VT, Expand); 698 setIndexedStoreAction(IM, (MVT::SimpleValueType)VT, Expand); 699 } 700 701 // These operations default to expand. 702 setOperationAction(ISD::FGETSIGN, (MVT::SimpleValueType)VT, Expand); 703 setOperationAction(ISD::CONCAT_VECTORS, (MVT::SimpleValueType)VT, Expand); 704 705 // These library functions default to expand. 706 setOperationAction(ISD::FROUND, (MVT::SimpleValueType)VT, Expand); 707 708 // These operations default to expand for vector types. 709 if (VT >= MVT::FIRST_VECTOR_VALUETYPE && 710 VT <= MVT::LAST_VECTOR_VALUETYPE) 711 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand); 712 } 713 714 // Most targets ignore the @llvm.prefetch intrinsic. 715 setOperationAction(ISD::PREFETCH, MVT::Other, Expand); 716 717 // ConstantFP nodes default to expand. Targets can either change this to 718 // Legal, in which case all fp constants are legal, or use isFPImmLegal() 719 // to optimize expansions for certain constants. 720 setOperationAction(ISD::ConstantFP, MVT::f16, Expand); 721 setOperationAction(ISD::ConstantFP, MVT::f32, Expand); 722 setOperationAction(ISD::ConstantFP, MVT::f64, Expand); 723 setOperationAction(ISD::ConstantFP, MVT::f80, Expand); 724 setOperationAction(ISD::ConstantFP, MVT::f128, Expand); 725 726 // These library functions default to expand. 727 setOperationAction(ISD::FLOG , MVT::f16, Expand); 728 setOperationAction(ISD::FLOG2, MVT::f16, Expand); 729 setOperationAction(ISD::FLOG10, MVT::f16, Expand); 730 setOperationAction(ISD::FEXP , MVT::f16, Expand); 731 setOperationAction(ISD::FEXP2, MVT::f16, Expand); 732 setOperationAction(ISD::FFLOOR, MVT::f16, Expand); 733 setOperationAction(ISD::FNEARBYINT, MVT::f16, Expand); 734 setOperationAction(ISD::FCEIL, MVT::f16, Expand); 735 setOperationAction(ISD::FRINT, MVT::f16, Expand); 736 setOperationAction(ISD::FTRUNC, MVT::f16, Expand); 737 setOperationAction(ISD::FLOG , MVT::f32, Expand); 738 setOperationAction(ISD::FLOG2, MVT::f32, Expand); 739 setOperationAction(ISD::FLOG10, MVT::f32, Expand); 740 setOperationAction(ISD::FEXP , MVT::f32, Expand); 741 setOperationAction(ISD::FEXP2, MVT::f32, Expand); 742 setOperationAction(ISD::FFLOOR, MVT::f32, Expand); 743 setOperationAction(ISD::FNEARBYINT, MVT::f32, Expand); 744 setOperationAction(ISD::FCEIL, MVT::f32, Expand); 745 setOperationAction(ISD::FRINT, MVT::f32, Expand); 746 setOperationAction(ISD::FTRUNC, MVT::f32, Expand); 747 setOperationAction(ISD::FLOG , MVT::f64, Expand); 748 setOperationAction(ISD::FLOG2, MVT::f64, Expand); 749 setOperationAction(ISD::FLOG10, MVT::f64, Expand); 750 setOperationAction(ISD::FEXP , MVT::f64, Expand); 751 setOperationAction(ISD::FEXP2, MVT::f64, Expand); 752 setOperationAction(ISD::FFLOOR, MVT::f64, Expand); 753 setOperationAction(ISD::FNEARBYINT, MVT::f64, Expand); 754 setOperationAction(ISD::FCEIL, MVT::f64, Expand); 755 setOperationAction(ISD::FRINT, MVT::f64, Expand); 756 setOperationAction(ISD::FTRUNC, MVT::f64, Expand); 757 setOperationAction(ISD::FLOG , MVT::f128, Expand); 758 setOperationAction(ISD::FLOG2, MVT::f128, Expand); 759 setOperationAction(ISD::FLOG10, MVT::f128, Expand); 760 setOperationAction(ISD::FEXP , MVT::f128, Expand); 761 setOperationAction(ISD::FEXP2, MVT::f128, Expand); 762 setOperationAction(ISD::FFLOOR, MVT::f128, Expand); 763 setOperationAction(ISD::FNEARBYINT, MVT::f128, Expand); 764 setOperationAction(ISD::FCEIL, MVT::f128, Expand); 765 setOperationAction(ISD::FRINT, MVT::f128, Expand); 766 setOperationAction(ISD::FTRUNC, MVT::f128, Expand); 767 768 // Default ISD::TRAP to expand (which turns it into abort). 769 setOperationAction(ISD::TRAP, MVT::Other, Expand); 770 771 // On most systems, DEBUGTRAP and TRAP have no difference. The "Expand" 772 // here is to inform DAG Legalizer to replace DEBUGTRAP with TRAP. 773 // 774 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Expand); 775 } 776 777 MVT TargetLoweringBase::getPointerTy(uint32_t AS) const { 778 return MVT::getIntegerVT(getPointerSizeInBits(AS)); 779 } 780 781 unsigned TargetLoweringBase::getPointerSizeInBits(uint32_t AS) const { 782 return TD->getPointerSizeInBits(AS); 783 } 784 785 unsigned TargetLoweringBase::getPointerTypeSizeInBits(Type *Ty) const { 786 assert(Ty->isPointerTy()); 787 return getPointerSizeInBits(Ty->getPointerAddressSpace()); 788 } 789 790 MVT TargetLoweringBase::getScalarShiftAmountTy(EVT LHSTy) const { 791 return MVT::getIntegerVT(8*TD->getPointerSize(0)); 792 } 793 794 EVT TargetLoweringBase::getShiftAmountTy(EVT LHSTy) const { 795 assert(LHSTy.isInteger() && "Shift amount is not an integer type!"); 796 if (LHSTy.isVector()) 797 return LHSTy; 798 return getScalarShiftAmountTy(LHSTy); 799 } 800 801 /// canOpTrap - Returns true if the operation can trap for the value type. 802 /// VT must be a legal type. 803 bool TargetLoweringBase::canOpTrap(unsigned Op, EVT VT) const { 804 assert(isTypeLegal(VT)); 805 switch (Op) { 806 default: 807 return false; 808 case ISD::FDIV: 809 case ISD::FREM: 810 case ISD::SDIV: 811 case ISD::UDIV: 812 case ISD::SREM: 813 case ISD::UREM: 814 return true; 815 } 816 } 817 818 819 static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT, 820 unsigned &NumIntermediates, 821 MVT &RegisterVT, 822 TargetLoweringBase *TLI) { 823 // Figure out the right, legal destination reg to copy into. 824 unsigned NumElts = VT.getVectorNumElements(); 825 MVT EltTy = VT.getVectorElementType(); 826 827 unsigned NumVectorRegs = 1; 828 829 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we 830 // could break down into LHS/RHS like LegalizeDAG does. 831 if (!isPowerOf2_32(NumElts)) { 832 NumVectorRegs = NumElts; 833 NumElts = 1; 834 } 835 836 // Divide the input until we get to a supported size. This will always 837 // end with a scalar if the target doesn't support vectors. 838 while (NumElts > 1 && !TLI->isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) { 839 NumElts >>= 1; 840 NumVectorRegs <<= 1; 841 } 842 843 NumIntermediates = NumVectorRegs; 844 845 MVT NewVT = MVT::getVectorVT(EltTy, NumElts); 846 if (!TLI->isTypeLegal(NewVT)) 847 NewVT = EltTy; 848 IntermediateVT = NewVT; 849 850 unsigned NewVTSize = NewVT.getSizeInBits(); 851 852 // Convert sizes such as i33 to i64. 853 if (!isPowerOf2_32(NewVTSize)) 854 NewVTSize = NextPowerOf2(NewVTSize); 855 856 MVT DestVT = TLI->getRegisterType(NewVT); 857 RegisterVT = DestVT; 858 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16. 859 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits()); 860 861 // Otherwise, promotion or legal types use the same number of registers as 862 // the vector decimated to the appropriate level. 863 return NumVectorRegs; 864 } 865 866 /// isLegalRC - Return true if the value types that can be represented by the 867 /// specified register class are all legal. 868 bool TargetLoweringBase::isLegalRC(const TargetRegisterClass *RC) const { 869 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end(); 870 I != E; ++I) { 871 if (isTypeLegal(*I)) 872 return true; 873 } 874 return false; 875 } 876 877 /// findRepresentativeClass - Return the largest legal super-reg register class 878 /// of the register class for the specified type and its associated "cost". 879 std::pair<const TargetRegisterClass*, uint8_t> 880 TargetLoweringBase::findRepresentativeClass(MVT VT) const { 881 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo(); 882 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy]; 883 if (!RC) 884 return std::make_pair(RC, 0); 885 886 // Compute the set of all super-register classes. 887 BitVector SuperRegRC(TRI->getNumRegClasses()); 888 for (SuperRegClassIterator RCI(RC, TRI); RCI.isValid(); ++RCI) 889 SuperRegRC.setBitsInMask(RCI.getMask()); 890 891 // Find the first legal register class with the largest spill size. 892 const TargetRegisterClass *BestRC = RC; 893 for (int i = SuperRegRC.find_first(); i >= 0; i = SuperRegRC.find_next(i)) { 894 const TargetRegisterClass *SuperRC = TRI->getRegClass(i); 895 // We want the largest possible spill size. 896 if (SuperRC->getSize() <= BestRC->getSize()) 897 continue; 898 if (!isLegalRC(SuperRC)) 899 continue; 900 BestRC = SuperRC; 901 } 902 return std::make_pair(BestRC, 1); 903 } 904 905 /// computeRegisterProperties - Once all of the register classes are added, 906 /// this allows us to compute derived properties we expose. 907 void TargetLoweringBase::computeRegisterProperties() { 908 assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE && 909 "Too many value types for ValueTypeActions to hold!"); 910 911 // Everything defaults to needing one register. 912 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) { 913 NumRegistersForVT[i] = 1; 914 RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i; 915 } 916 // ...except isVoid, which doesn't need any registers. 917 NumRegistersForVT[MVT::isVoid] = 0; 918 919 // Find the largest integer register class. 920 unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE; 921 for (; RegClassForVT[LargestIntReg] == 0; --LargestIntReg) 922 assert(LargestIntReg != MVT::i1 && "No integer registers defined!"); 923 924 // Every integer value type larger than this largest register takes twice as 925 // many registers to represent as the previous ValueType. 926 for (unsigned ExpandedReg = LargestIntReg + 1; 927 ExpandedReg <= MVT::LAST_INTEGER_VALUETYPE; ++ExpandedReg) { 928 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1]; 929 RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg; 930 TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1); 931 ValueTypeActions.setTypeAction((MVT::SimpleValueType)ExpandedReg, 932 TypeExpandInteger); 933 } 934 935 // Inspect all of the ValueType's smaller than the largest integer 936 // register to see which ones need promotion. 937 unsigned LegalIntReg = LargestIntReg; 938 for (unsigned IntReg = LargestIntReg - 1; 939 IntReg >= (unsigned)MVT::i1; --IntReg) { 940 MVT IVT = (MVT::SimpleValueType)IntReg; 941 if (isTypeLegal(IVT)) { 942 LegalIntReg = IntReg; 943 } else { 944 RegisterTypeForVT[IntReg] = TransformToType[IntReg] = 945 (const MVT::SimpleValueType)LegalIntReg; 946 ValueTypeActions.setTypeAction(IVT, TypePromoteInteger); 947 } 948 } 949 950 // ppcf128 type is really two f64's. 951 if (!isTypeLegal(MVT::ppcf128)) { 952 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64]; 953 RegisterTypeForVT[MVT::ppcf128] = MVT::f64; 954 TransformToType[MVT::ppcf128] = MVT::f64; 955 ValueTypeActions.setTypeAction(MVT::ppcf128, TypeExpandFloat); 956 } 957 958 // Decide how to handle f128. If the target does not have native f128 support, 959 // expand it to i128 and we will be generating soft float library calls. 960 if (!isTypeLegal(MVT::f128)) { 961 NumRegistersForVT[MVT::f128] = NumRegistersForVT[MVT::i128]; 962 RegisterTypeForVT[MVT::f128] = RegisterTypeForVT[MVT::i128]; 963 TransformToType[MVT::f128] = MVT::i128; 964 ValueTypeActions.setTypeAction(MVT::f128, TypeSoftenFloat); 965 } 966 967 // Decide how to handle f64. If the target does not have native f64 support, 968 // expand it to i64 and we will be generating soft float library calls. 969 if (!isTypeLegal(MVT::f64)) { 970 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64]; 971 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64]; 972 TransformToType[MVT::f64] = MVT::i64; 973 ValueTypeActions.setTypeAction(MVT::f64, TypeSoftenFloat); 974 } 975 976 // Decide how to handle f32. If the target does not have native support for 977 // f32, promote it to f64 if it is legal. Otherwise, expand it to i32. 978 if (!isTypeLegal(MVT::f32)) { 979 if (isTypeLegal(MVT::f64)) { 980 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::f64]; 981 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::f64]; 982 TransformToType[MVT::f32] = MVT::f64; 983 ValueTypeActions.setTypeAction(MVT::f32, TypePromoteInteger); 984 } else { 985 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32]; 986 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32]; 987 TransformToType[MVT::f32] = MVT::i32; 988 ValueTypeActions.setTypeAction(MVT::f32, TypeSoftenFloat); 989 } 990 } 991 992 // Loop over all of the vector value types to see which need transformations. 993 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE; 994 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) { 995 MVT VT = (MVT::SimpleValueType)i; 996 if (isTypeLegal(VT)) continue; 997 998 // Determine if there is a legal wider type. If so, we should promote to 999 // that wider vector type. 1000 MVT EltVT = VT.getVectorElementType(); 1001 unsigned NElts = VT.getVectorNumElements(); 1002 if (NElts != 1 && !shouldSplitVectorElementType(EltVT)) { 1003 bool IsLegalWiderType = false; 1004 // First try to promote the elements of integer vectors. If no legal 1005 // promotion was found, fallback to the widen-vector method. 1006 for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) { 1007 MVT SVT = (MVT::SimpleValueType)nVT; 1008 // Promote vectors of integers to vectors with the same number 1009 // of elements, with a wider element type. 1010 if (SVT.getVectorElementType().getSizeInBits() > EltVT.getSizeInBits() 1011 && SVT.getVectorNumElements() == NElts && 1012 isTypeLegal(SVT) && SVT.getScalarType().isInteger()) { 1013 TransformToType[i] = SVT; 1014 RegisterTypeForVT[i] = SVT; 1015 NumRegistersForVT[i] = 1; 1016 ValueTypeActions.setTypeAction(VT, TypePromoteInteger); 1017 IsLegalWiderType = true; 1018 break; 1019 } 1020 } 1021 1022 if (IsLegalWiderType) continue; 1023 1024 // Try to widen the vector. 1025 for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) { 1026 MVT SVT = (MVT::SimpleValueType)nVT; 1027 if (SVT.getVectorElementType() == EltVT && 1028 SVT.getVectorNumElements() > NElts && 1029 isTypeLegal(SVT)) { 1030 TransformToType[i] = SVT; 1031 RegisterTypeForVT[i] = SVT; 1032 NumRegistersForVT[i] = 1; 1033 ValueTypeActions.setTypeAction(VT, TypeWidenVector); 1034 IsLegalWiderType = true; 1035 break; 1036 } 1037 } 1038 if (IsLegalWiderType) continue; 1039 } 1040 1041 MVT IntermediateVT; 1042 MVT RegisterVT; 1043 unsigned NumIntermediates; 1044 NumRegistersForVT[i] = 1045 getVectorTypeBreakdownMVT(VT, IntermediateVT, NumIntermediates, 1046 RegisterVT, this); 1047 RegisterTypeForVT[i] = RegisterVT; 1048 1049 MVT NVT = VT.getPow2VectorType(); 1050 if (NVT == VT) { 1051 // Type is already a power of 2. The default action is to split. 1052 TransformToType[i] = MVT::Other; 1053 unsigned NumElts = VT.getVectorNumElements(); 1054 ValueTypeActions.setTypeAction(VT, 1055 NumElts > 1 ? TypeSplitVector : TypeScalarizeVector); 1056 } else { 1057 TransformToType[i] = NVT; 1058 ValueTypeActions.setTypeAction(VT, TypeWidenVector); 1059 } 1060 } 1061 1062 // Determine the 'representative' register class for each value type. 1063 // An representative register class is the largest (meaning one which is 1064 // not a sub-register class / subreg register class) legal register class for 1065 // a group of value types. For example, on i386, i8, i16, and i32 1066 // representative would be GR32; while on x86_64 it's GR64. 1067 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) { 1068 const TargetRegisterClass* RRC; 1069 uint8_t Cost; 1070 tie(RRC, Cost) = findRepresentativeClass((MVT::SimpleValueType)i); 1071 RepRegClassForVT[i] = RRC; 1072 RepRegClassCostForVT[i] = Cost; 1073 } 1074 } 1075 1076 EVT TargetLoweringBase::getSetCCResultType(LLVMContext &, EVT VT) const { 1077 assert(!VT.isVector() && "No default SetCC type for vectors!"); 1078 return getPointerTy(0).SimpleTy; 1079 } 1080 1081 MVT::SimpleValueType TargetLoweringBase::getCmpLibcallReturnType() const { 1082 return MVT::i32; // return the default value 1083 } 1084 1085 /// getVectorTypeBreakdown - Vector types are broken down into some number of 1086 /// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32 1087 /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack. 1088 /// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86. 1089 /// 1090 /// This method returns the number of registers needed, and the VT for each 1091 /// register. It also returns the VT and quantity of the intermediate values 1092 /// before they are promoted/expanded. 1093 /// 1094 unsigned TargetLoweringBase::getVectorTypeBreakdown(LLVMContext &Context, EVT VT, 1095 EVT &IntermediateVT, 1096 unsigned &NumIntermediates, 1097 MVT &RegisterVT) const { 1098 unsigned NumElts = VT.getVectorNumElements(); 1099 1100 // If there is a wider vector type with the same element type as this one, 1101 // or a promoted vector type that has the same number of elements which 1102 // are wider, then we should convert to that legal vector type. 1103 // This handles things like <2 x float> -> <4 x float> and 1104 // <4 x i1> -> <4 x i32>. 1105 LegalizeTypeAction TA = getTypeAction(Context, VT); 1106 if (NumElts != 1 && (TA == TypeWidenVector || TA == TypePromoteInteger)) { 1107 EVT RegisterEVT = getTypeToTransformTo(Context, VT); 1108 if (isTypeLegal(RegisterEVT)) { 1109 IntermediateVT = RegisterEVT; 1110 RegisterVT = RegisterEVT.getSimpleVT(); 1111 NumIntermediates = 1; 1112 return 1; 1113 } 1114 } 1115 1116 // Figure out the right, legal destination reg to copy into. 1117 EVT EltTy = VT.getVectorElementType(); 1118 1119 unsigned NumVectorRegs = 1; 1120 1121 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we 1122 // could break down into LHS/RHS like LegalizeDAG does. 1123 if (!isPowerOf2_32(NumElts)) { 1124 NumVectorRegs = NumElts; 1125 NumElts = 1; 1126 } 1127 1128 // Divide the input until we get to a supported size. This will always 1129 // end with a scalar if the target doesn't support vectors. 1130 while (NumElts > 1 && !isTypeLegal( 1131 EVT::getVectorVT(Context, EltTy, NumElts))) { 1132 NumElts >>= 1; 1133 NumVectorRegs <<= 1; 1134 } 1135 1136 NumIntermediates = NumVectorRegs; 1137 1138 EVT NewVT = EVT::getVectorVT(Context, EltTy, NumElts); 1139 if (!isTypeLegal(NewVT)) 1140 NewVT = EltTy; 1141 IntermediateVT = NewVT; 1142 1143 MVT DestVT = getRegisterType(Context, NewVT); 1144 RegisterVT = DestVT; 1145 unsigned NewVTSize = NewVT.getSizeInBits(); 1146 1147 // Convert sizes such as i33 to i64. 1148 if (!isPowerOf2_32(NewVTSize)) 1149 NewVTSize = NextPowerOf2(NewVTSize); 1150 1151 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16. 1152 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits()); 1153 1154 // Otherwise, promotion or legal types use the same number of registers as 1155 // the vector decimated to the appropriate level. 1156 return NumVectorRegs; 1157 } 1158 1159 /// Get the EVTs and ArgFlags collections that represent the legalized return 1160 /// type of the given function. This does not require a DAG or a return value, 1161 /// and is suitable for use before any DAGs for the function are constructed. 1162 /// TODO: Move this out of TargetLowering.cpp. 1163 void llvm::GetReturnInfo(Type* ReturnType, AttributeSet attr, 1164 SmallVectorImpl<ISD::OutputArg> &Outs, 1165 const TargetLowering &TLI) { 1166 SmallVector<EVT, 4> ValueVTs; 1167 ComputeValueVTs(TLI, ReturnType, ValueVTs); 1168 unsigned NumValues = ValueVTs.size(); 1169 if (NumValues == 0) return; 1170 1171 for (unsigned j = 0, f = NumValues; j != f; ++j) { 1172 EVT VT = ValueVTs[j]; 1173 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 1174 1175 if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::SExt)) 1176 ExtendKind = ISD::SIGN_EXTEND; 1177 else if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::ZExt)) 1178 ExtendKind = ISD::ZERO_EXTEND; 1179 1180 // FIXME: C calling convention requires the return type to be promoted to 1181 // at least 32-bit. But this is not necessary for non-C calling 1182 // conventions. The frontend should mark functions whose return values 1183 // require promoting with signext or zeroext attributes. 1184 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) { 1185 MVT MinVT = TLI.getRegisterType(ReturnType->getContext(), MVT::i32); 1186 if (VT.bitsLT(MinVT)) 1187 VT = MinVT; 1188 } 1189 1190 unsigned NumParts = TLI.getNumRegisters(ReturnType->getContext(), VT); 1191 MVT PartVT = TLI.getRegisterType(ReturnType->getContext(), VT); 1192 1193 // 'inreg' on function refers to return value 1194 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy(); 1195 if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::InReg)) 1196 Flags.setInReg(); 1197 1198 // Propagate extension type if any 1199 if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::SExt)) 1200 Flags.setSExt(); 1201 else if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::ZExt)) 1202 Flags.setZExt(); 1203 1204 for (unsigned i = 0; i < NumParts; ++i) 1205 Outs.push_back(ISD::OutputArg(Flags, PartVT, /*isFixed=*/true, 0, 0)); 1206 } 1207 } 1208 1209 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 1210 /// function arguments in the caller parameter area. This is the actual 1211 /// alignment, not its logarithm. 1212 unsigned TargetLoweringBase::getByValTypeAlignment(Type *Ty) const { 1213 return TD->getCallFrameTypeAlignment(Ty); 1214 } 1215 1216 //===----------------------------------------------------------------------===// 1217 // TargetTransformInfo Helpers 1218 //===----------------------------------------------------------------------===// 1219 1220 int TargetLoweringBase::InstructionOpcodeToISD(unsigned Opcode) const { 1221 enum InstructionOpcodes { 1222 #define HANDLE_INST(NUM, OPCODE, CLASS) OPCODE = NUM, 1223 #define LAST_OTHER_INST(NUM) InstructionOpcodesCount = NUM 1224 #include "llvm/IR/Instruction.def" 1225 }; 1226 switch (static_cast<InstructionOpcodes>(Opcode)) { 1227 case Ret: return 0; 1228 case Br: return 0; 1229 case Switch: return 0; 1230 case IndirectBr: return 0; 1231 case Invoke: return 0; 1232 case Resume: return 0; 1233 case Unreachable: return 0; 1234 case Add: return ISD::ADD; 1235 case FAdd: return ISD::FADD; 1236 case Sub: return ISD::SUB; 1237 case FSub: return ISD::FSUB; 1238 case Mul: return ISD::MUL; 1239 case FMul: return ISD::FMUL; 1240 case UDiv: return ISD::UDIV; 1241 case SDiv: return ISD::UDIV; 1242 case FDiv: return ISD::FDIV; 1243 case URem: return ISD::UREM; 1244 case SRem: return ISD::SREM; 1245 case FRem: return ISD::FREM; 1246 case Shl: return ISD::SHL; 1247 case LShr: return ISD::SRL; 1248 case AShr: return ISD::SRA; 1249 case And: return ISD::AND; 1250 case Or: return ISD::OR; 1251 case Xor: return ISD::XOR; 1252 case Alloca: return 0; 1253 case Load: return ISD::LOAD; 1254 case Store: return ISD::STORE; 1255 case GetElementPtr: return 0; 1256 case Fence: return 0; 1257 case AtomicCmpXchg: return 0; 1258 case AtomicRMW: return 0; 1259 case Trunc: return ISD::TRUNCATE; 1260 case ZExt: return ISD::ZERO_EXTEND; 1261 case SExt: return ISD::SIGN_EXTEND; 1262 case FPToUI: return ISD::FP_TO_UINT; 1263 case FPToSI: return ISD::FP_TO_SINT; 1264 case UIToFP: return ISD::UINT_TO_FP; 1265 case SIToFP: return ISD::SINT_TO_FP; 1266 case FPTrunc: return ISD::FP_ROUND; 1267 case FPExt: return ISD::FP_EXTEND; 1268 case PtrToInt: return ISD::BITCAST; 1269 case IntToPtr: return ISD::BITCAST; 1270 case BitCast: return ISD::BITCAST; 1271 case ICmp: return ISD::SETCC; 1272 case FCmp: return ISD::SETCC; 1273 case PHI: return 0; 1274 case Call: return 0; 1275 case Select: return ISD::SELECT; 1276 case UserOp1: return 0; 1277 case UserOp2: return 0; 1278 case VAArg: return 0; 1279 case ExtractElement: return ISD::EXTRACT_VECTOR_ELT; 1280 case InsertElement: return ISD::INSERT_VECTOR_ELT; 1281 case ShuffleVector: return ISD::VECTOR_SHUFFLE; 1282 case ExtractValue: return ISD::MERGE_VALUES; 1283 case InsertValue: return ISD::MERGE_VALUES; 1284 case LandingPad: return 0; 1285 } 1286 1287 llvm_unreachable("Unknown instruction type encountered!"); 1288 } 1289 1290 std::pair<unsigned, MVT> 1291 TargetLoweringBase::getTypeLegalizationCost(Type *Ty) const { 1292 LLVMContext &C = Ty->getContext(); 1293 EVT MTy = getValueType(Ty); 1294 1295 unsigned Cost = 1; 1296 // We keep legalizing the type until we find a legal kind. We assume that 1297 // the only operation that costs anything is the split. After splitting 1298 // we need to handle two types. 1299 while (true) { 1300 LegalizeKind LK = getTypeConversion(C, MTy); 1301 1302 if (LK.first == TypeLegal) 1303 return std::make_pair(Cost, MTy.getSimpleVT()); 1304 1305 if (LK.first == TypeSplitVector || LK.first == TypeExpandInteger) 1306 Cost *= 2; 1307 1308 // Keep legalizing the type. 1309 MTy = LK.second; 1310 } 1311 } 1312 1313 //===----------------------------------------------------------------------===// 1314 // Loop Strength Reduction hooks 1315 //===----------------------------------------------------------------------===// 1316 1317 /// isLegalAddressingMode - Return true if the addressing mode represented 1318 /// by AM is legal for this target, for a load/store of the specified type. 1319 bool TargetLoweringBase::isLegalAddressingMode(const AddrMode &AM, 1320 Type *Ty) const { 1321 // The default implementation of this implements a conservative RISCy, r+r and 1322 // r+i addr mode. 1323 1324 // Allows a sign-extended 16-bit immediate field. 1325 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1) 1326 return false; 1327 1328 // No global is ever allowed as a base. 1329 if (AM.BaseGV) 1330 return false; 1331 1332 // Only support r+r, 1333 switch (AM.Scale) { 1334 case 0: // "r+i" or just "i", depending on HasBaseReg. 1335 break; 1336 case 1: 1337 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. 1338 return false; 1339 // Otherwise we have r+r or r+i. 1340 break; 1341 case 2: 1342 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. 1343 return false; 1344 // Allow 2*r as r+r. 1345 break; 1346 } 1347 1348 return true; 1349 } 1350