1 //===-- TargetLoweringBase.cpp - Implement the TargetLoweringBase class ---===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This implements the TargetLoweringBase class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "llvm/Target/TargetLowering.h" 15 #include "llvm/ADT/BitVector.h" 16 #include "llvm/ADT/STLExtras.h" 17 #include "llvm/ADT/Triple.h" 18 #include "llvm/CodeGen/Analysis.h" 19 #include "llvm/CodeGen/MachineFrameInfo.h" 20 #include "llvm/CodeGen/MachineFunction.h" 21 #include "llvm/CodeGen/MachineInstrBuilder.h" 22 #include "llvm/CodeGen/MachineJumpTableInfo.h" 23 #include "llvm/CodeGen/StackMaps.h" 24 #include "llvm/IR/DataLayout.h" 25 #include "llvm/IR/DerivedTypes.h" 26 #include "llvm/IR/GlobalVariable.h" 27 #include "llvm/IR/Mangler.h" 28 #include "llvm/MC/MCAsmInfo.h" 29 #include "llvm/MC/MCContext.h" 30 #include "llvm/MC/MCExpr.h" 31 #include "llvm/Support/CommandLine.h" 32 #include "llvm/Support/ErrorHandling.h" 33 #include "llvm/Support/MathExtras.h" 34 #include "llvm/Target/TargetLoweringObjectFile.h" 35 #include "llvm/Target/TargetMachine.h" 36 #include "llvm/Target/TargetRegisterInfo.h" 37 #include "llvm/Target/TargetSubtargetInfo.h" 38 #include <cctype> 39 using namespace llvm; 40 41 static cl::opt<bool> JumpIsExpensiveOverride( 42 "jump-is-expensive", cl::init(false), 43 cl::desc("Do not create extra branches to split comparison logic."), 44 cl::Hidden); 45 46 /// InitLibcallNames - Set default libcall names. 47 /// 48 static void InitLibcallNames(const char **Names, const Triple &TT) { 49 Names[RTLIB::SHL_I16] = "__ashlhi3"; 50 Names[RTLIB::SHL_I32] = "__ashlsi3"; 51 Names[RTLIB::SHL_I64] = "__ashldi3"; 52 Names[RTLIB::SHL_I128] = "__ashlti3"; 53 Names[RTLIB::SRL_I16] = "__lshrhi3"; 54 Names[RTLIB::SRL_I32] = "__lshrsi3"; 55 Names[RTLIB::SRL_I64] = "__lshrdi3"; 56 Names[RTLIB::SRL_I128] = "__lshrti3"; 57 Names[RTLIB::SRA_I16] = "__ashrhi3"; 58 Names[RTLIB::SRA_I32] = "__ashrsi3"; 59 Names[RTLIB::SRA_I64] = "__ashrdi3"; 60 Names[RTLIB::SRA_I128] = "__ashrti3"; 61 Names[RTLIB::MUL_I8] = "__mulqi3"; 62 Names[RTLIB::MUL_I16] = "__mulhi3"; 63 Names[RTLIB::MUL_I32] = "__mulsi3"; 64 Names[RTLIB::MUL_I64] = "__muldi3"; 65 Names[RTLIB::MUL_I128] = "__multi3"; 66 Names[RTLIB::MULO_I32] = "__mulosi4"; 67 Names[RTLIB::MULO_I64] = "__mulodi4"; 68 Names[RTLIB::MULO_I128] = "__muloti4"; 69 Names[RTLIB::SDIV_I8] = "__divqi3"; 70 Names[RTLIB::SDIV_I16] = "__divhi3"; 71 Names[RTLIB::SDIV_I32] = "__divsi3"; 72 Names[RTLIB::SDIV_I64] = "__divdi3"; 73 Names[RTLIB::SDIV_I128] = "__divti3"; 74 Names[RTLIB::UDIV_I8] = "__udivqi3"; 75 Names[RTLIB::UDIV_I16] = "__udivhi3"; 76 Names[RTLIB::UDIV_I32] = "__udivsi3"; 77 Names[RTLIB::UDIV_I64] = "__udivdi3"; 78 Names[RTLIB::UDIV_I128] = "__udivti3"; 79 Names[RTLIB::SREM_I8] = "__modqi3"; 80 Names[RTLIB::SREM_I16] = "__modhi3"; 81 Names[RTLIB::SREM_I32] = "__modsi3"; 82 Names[RTLIB::SREM_I64] = "__moddi3"; 83 Names[RTLIB::SREM_I128] = "__modti3"; 84 Names[RTLIB::UREM_I8] = "__umodqi3"; 85 Names[RTLIB::UREM_I16] = "__umodhi3"; 86 Names[RTLIB::UREM_I32] = "__umodsi3"; 87 Names[RTLIB::UREM_I64] = "__umoddi3"; 88 Names[RTLIB::UREM_I128] = "__umodti3"; 89 90 // These are generally not available. 91 Names[RTLIB::SDIVREM_I8] = nullptr; 92 Names[RTLIB::SDIVREM_I16] = nullptr; 93 Names[RTLIB::SDIVREM_I32] = nullptr; 94 Names[RTLIB::SDIVREM_I64] = nullptr; 95 Names[RTLIB::SDIVREM_I128] = nullptr; 96 Names[RTLIB::UDIVREM_I8] = nullptr; 97 Names[RTLIB::UDIVREM_I16] = nullptr; 98 Names[RTLIB::UDIVREM_I32] = nullptr; 99 Names[RTLIB::UDIVREM_I64] = nullptr; 100 Names[RTLIB::UDIVREM_I128] = nullptr; 101 102 Names[RTLIB::NEG_I32] = "__negsi2"; 103 Names[RTLIB::NEG_I64] = "__negdi2"; 104 Names[RTLIB::ADD_F32] = "__addsf3"; 105 Names[RTLIB::ADD_F64] = "__adddf3"; 106 Names[RTLIB::ADD_F80] = "__addxf3"; 107 Names[RTLIB::ADD_F128] = "__addtf3"; 108 Names[RTLIB::ADD_PPCF128] = "__gcc_qadd"; 109 Names[RTLIB::SUB_F32] = "__subsf3"; 110 Names[RTLIB::SUB_F64] = "__subdf3"; 111 Names[RTLIB::SUB_F80] = "__subxf3"; 112 Names[RTLIB::SUB_F128] = "__subtf3"; 113 Names[RTLIB::SUB_PPCF128] = "__gcc_qsub"; 114 Names[RTLIB::MUL_F32] = "__mulsf3"; 115 Names[RTLIB::MUL_F64] = "__muldf3"; 116 Names[RTLIB::MUL_F80] = "__mulxf3"; 117 Names[RTLIB::MUL_F128] = "__multf3"; 118 Names[RTLIB::MUL_PPCF128] = "__gcc_qmul"; 119 Names[RTLIB::DIV_F32] = "__divsf3"; 120 Names[RTLIB::DIV_F64] = "__divdf3"; 121 Names[RTLIB::DIV_F80] = "__divxf3"; 122 Names[RTLIB::DIV_F128] = "__divtf3"; 123 Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv"; 124 Names[RTLIB::REM_F32] = "fmodf"; 125 Names[RTLIB::REM_F64] = "fmod"; 126 Names[RTLIB::REM_F80] = "fmodl"; 127 Names[RTLIB::REM_F128] = "fmodl"; 128 Names[RTLIB::REM_PPCF128] = "fmodl"; 129 Names[RTLIB::FMA_F32] = "fmaf"; 130 Names[RTLIB::FMA_F64] = "fma"; 131 Names[RTLIB::FMA_F80] = "fmal"; 132 Names[RTLIB::FMA_F128] = "fmal"; 133 Names[RTLIB::FMA_PPCF128] = "fmal"; 134 Names[RTLIB::POWI_F32] = "__powisf2"; 135 Names[RTLIB::POWI_F64] = "__powidf2"; 136 Names[RTLIB::POWI_F80] = "__powixf2"; 137 Names[RTLIB::POWI_F128] = "__powitf2"; 138 Names[RTLIB::POWI_PPCF128] = "__powitf2"; 139 Names[RTLIB::SQRT_F32] = "sqrtf"; 140 Names[RTLIB::SQRT_F64] = "sqrt"; 141 Names[RTLIB::SQRT_F80] = "sqrtl"; 142 Names[RTLIB::SQRT_F128] = "sqrtl"; 143 Names[RTLIB::SQRT_PPCF128] = "sqrtl"; 144 Names[RTLIB::LOG_F32] = "logf"; 145 Names[RTLIB::LOG_F64] = "log"; 146 Names[RTLIB::LOG_F80] = "logl"; 147 Names[RTLIB::LOG_F128] = "logl"; 148 Names[RTLIB::LOG_PPCF128] = "logl"; 149 Names[RTLIB::LOG2_F32] = "log2f"; 150 Names[RTLIB::LOG2_F64] = "log2"; 151 Names[RTLIB::LOG2_F80] = "log2l"; 152 Names[RTLIB::LOG2_F128] = "log2l"; 153 Names[RTLIB::LOG2_PPCF128] = "log2l"; 154 Names[RTLIB::LOG10_F32] = "log10f"; 155 Names[RTLIB::LOG10_F64] = "log10"; 156 Names[RTLIB::LOG10_F80] = "log10l"; 157 Names[RTLIB::LOG10_F128] = "log10l"; 158 Names[RTLIB::LOG10_PPCF128] = "log10l"; 159 Names[RTLIB::EXP_F32] = "expf"; 160 Names[RTLIB::EXP_F64] = "exp"; 161 Names[RTLIB::EXP_F80] = "expl"; 162 Names[RTLIB::EXP_F128] = "expl"; 163 Names[RTLIB::EXP_PPCF128] = "expl"; 164 Names[RTLIB::EXP2_F32] = "exp2f"; 165 Names[RTLIB::EXP2_F64] = "exp2"; 166 Names[RTLIB::EXP2_F80] = "exp2l"; 167 Names[RTLIB::EXP2_F128] = "exp2l"; 168 Names[RTLIB::EXP2_PPCF128] = "exp2l"; 169 Names[RTLIB::SIN_F32] = "sinf"; 170 Names[RTLIB::SIN_F64] = "sin"; 171 Names[RTLIB::SIN_F80] = "sinl"; 172 Names[RTLIB::SIN_F128] = "sinl"; 173 Names[RTLIB::SIN_PPCF128] = "sinl"; 174 Names[RTLIB::COS_F32] = "cosf"; 175 Names[RTLIB::COS_F64] = "cos"; 176 Names[RTLIB::COS_F80] = "cosl"; 177 Names[RTLIB::COS_F128] = "cosl"; 178 Names[RTLIB::COS_PPCF128] = "cosl"; 179 Names[RTLIB::POW_F32] = "powf"; 180 Names[RTLIB::POW_F64] = "pow"; 181 Names[RTLIB::POW_F80] = "powl"; 182 Names[RTLIB::POW_F128] = "powl"; 183 Names[RTLIB::POW_PPCF128] = "powl"; 184 Names[RTLIB::CEIL_F32] = "ceilf"; 185 Names[RTLIB::CEIL_F64] = "ceil"; 186 Names[RTLIB::CEIL_F80] = "ceill"; 187 Names[RTLIB::CEIL_F128] = "ceill"; 188 Names[RTLIB::CEIL_PPCF128] = "ceill"; 189 Names[RTLIB::TRUNC_F32] = "truncf"; 190 Names[RTLIB::TRUNC_F64] = "trunc"; 191 Names[RTLIB::TRUNC_F80] = "truncl"; 192 Names[RTLIB::TRUNC_F128] = "truncl"; 193 Names[RTLIB::TRUNC_PPCF128] = "truncl"; 194 Names[RTLIB::RINT_F32] = "rintf"; 195 Names[RTLIB::RINT_F64] = "rint"; 196 Names[RTLIB::RINT_F80] = "rintl"; 197 Names[RTLIB::RINT_F128] = "rintl"; 198 Names[RTLIB::RINT_PPCF128] = "rintl"; 199 Names[RTLIB::NEARBYINT_F32] = "nearbyintf"; 200 Names[RTLIB::NEARBYINT_F64] = "nearbyint"; 201 Names[RTLIB::NEARBYINT_F80] = "nearbyintl"; 202 Names[RTLIB::NEARBYINT_F128] = "nearbyintl"; 203 Names[RTLIB::NEARBYINT_PPCF128] = "nearbyintl"; 204 Names[RTLIB::ROUND_F32] = "roundf"; 205 Names[RTLIB::ROUND_F64] = "round"; 206 Names[RTLIB::ROUND_F80] = "roundl"; 207 Names[RTLIB::ROUND_F128] = "roundl"; 208 Names[RTLIB::ROUND_PPCF128] = "roundl"; 209 Names[RTLIB::FLOOR_F32] = "floorf"; 210 Names[RTLIB::FLOOR_F64] = "floor"; 211 Names[RTLIB::FLOOR_F80] = "floorl"; 212 Names[RTLIB::FLOOR_F128] = "floorl"; 213 Names[RTLIB::FLOOR_PPCF128] = "floorl"; 214 Names[RTLIB::FMIN_F32] = "fminf"; 215 Names[RTLIB::FMIN_F64] = "fmin"; 216 Names[RTLIB::FMIN_F80] = "fminl"; 217 Names[RTLIB::FMIN_F128] = "fminl"; 218 Names[RTLIB::FMIN_PPCF128] = "fminl"; 219 Names[RTLIB::FMAX_F32] = "fmaxf"; 220 Names[RTLIB::FMAX_F64] = "fmax"; 221 Names[RTLIB::FMAX_F80] = "fmaxl"; 222 Names[RTLIB::FMAX_F128] = "fmaxl"; 223 Names[RTLIB::FMAX_PPCF128] = "fmaxl"; 224 Names[RTLIB::ROUND_F32] = "roundf"; 225 Names[RTLIB::ROUND_F64] = "round"; 226 Names[RTLIB::ROUND_F80] = "roundl"; 227 Names[RTLIB::ROUND_F128] = "roundl"; 228 Names[RTLIB::ROUND_PPCF128] = "roundl"; 229 Names[RTLIB::COPYSIGN_F32] = "copysignf"; 230 Names[RTLIB::COPYSIGN_F64] = "copysign"; 231 Names[RTLIB::COPYSIGN_F80] = "copysignl"; 232 Names[RTLIB::COPYSIGN_F128] = "copysignl"; 233 Names[RTLIB::COPYSIGN_PPCF128] = "copysignl"; 234 Names[RTLIB::FPEXT_F64_F128] = "__extenddftf2"; 235 Names[RTLIB::FPEXT_F32_F128] = "__extendsftf2"; 236 Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2"; 237 Names[RTLIB::FPEXT_F16_F32] = "__gnu_h2f_ieee"; 238 Names[RTLIB::FPROUND_F32_F16] = "__gnu_f2h_ieee"; 239 Names[RTLIB::FPROUND_F64_F16] = "__truncdfhf2"; 240 Names[RTLIB::FPROUND_F80_F16] = "__truncxfhf2"; 241 Names[RTLIB::FPROUND_F128_F16] = "__trunctfhf2"; 242 Names[RTLIB::FPROUND_PPCF128_F16] = "__trunctfhf2"; 243 Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2"; 244 Names[RTLIB::FPROUND_F80_F32] = "__truncxfsf2"; 245 Names[RTLIB::FPROUND_F128_F32] = "__trunctfsf2"; 246 Names[RTLIB::FPROUND_PPCF128_F32] = "__trunctfsf2"; 247 Names[RTLIB::FPROUND_F80_F64] = "__truncxfdf2"; 248 Names[RTLIB::FPROUND_F128_F64] = "__trunctfdf2"; 249 Names[RTLIB::FPROUND_PPCF128_F64] = "__trunctfdf2"; 250 Names[RTLIB::FPTOSINT_F32_I8] = "__fixsfqi"; 251 Names[RTLIB::FPTOSINT_F32_I16] = "__fixsfhi"; 252 Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi"; 253 Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi"; 254 Names[RTLIB::FPTOSINT_F32_I128] = "__fixsfti"; 255 Names[RTLIB::FPTOSINT_F64_I8] = "__fixdfqi"; 256 Names[RTLIB::FPTOSINT_F64_I16] = "__fixdfhi"; 257 Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi"; 258 Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi"; 259 Names[RTLIB::FPTOSINT_F64_I128] = "__fixdfti"; 260 Names[RTLIB::FPTOSINT_F80_I32] = "__fixxfsi"; 261 Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi"; 262 Names[RTLIB::FPTOSINT_F80_I128] = "__fixxfti"; 263 Names[RTLIB::FPTOSINT_F128_I32] = "__fixtfsi"; 264 Names[RTLIB::FPTOSINT_F128_I64] = "__fixtfdi"; 265 Names[RTLIB::FPTOSINT_F128_I128] = "__fixtfti"; 266 Names[RTLIB::FPTOSINT_PPCF128_I32] = "__fixtfsi"; 267 Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi"; 268 Names[RTLIB::FPTOSINT_PPCF128_I128] = "__fixtfti"; 269 Names[RTLIB::FPTOUINT_F32_I8] = "__fixunssfqi"; 270 Names[RTLIB::FPTOUINT_F32_I16] = "__fixunssfhi"; 271 Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi"; 272 Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi"; 273 Names[RTLIB::FPTOUINT_F32_I128] = "__fixunssfti"; 274 Names[RTLIB::FPTOUINT_F64_I8] = "__fixunsdfqi"; 275 Names[RTLIB::FPTOUINT_F64_I16] = "__fixunsdfhi"; 276 Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi"; 277 Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi"; 278 Names[RTLIB::FPTOUINT_F64_I128] = "__fixunsdfti"; 279 Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi"; 280 Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi"; 281 Names[RTLIB::FPTOUINT_F80_I128] = "__fixunsxfti"; 282 Names[RTLIB::FPTOUINT_F128_I32] = "__fixunstfsi"; 283 Names[RTLIB::FPTOUINT_F128_I64] = "__fixunstfdi"; 284 Names[RTLIB::FPTOUINT_F128_I128] = "__fixunstfti"; 285 Names[RTLIB::FPTOUINT_PPCF128_I32] = "__fixunstfsi"; 286 Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi"; 287 Names[RTLIB::FPTOUINT_PPCF128_I128] = "__fixunstfti"; 288 Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf"; 289 Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf"; 290 Names[RTLIB::SINTTOFP_I32_F80] = "__floatsixf"; 291 Names[RTLIB::SINTTOFP_I32_F128] = "__floatsitf"; 292 Names[RTLIB::SINTTOFP_I32_PPCF128] = "__floatsitf"; 293 Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf"; 294 Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf"; 295 Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf"; 296 Names[RTLIB::SINTTOFP_I64_F128] = "__floatditf"; 297 Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf"; 298 Names[RTLIB::SINTTOFP_I128_F32] = "__floattisf"; 299 Names[RTLIB::SINTTOFP_I128_F64] = "__floattidf"; 300 Names[RTLIB::SINTTOFP_I128_F80] = "__floattixf"; 301 Names[RTLIB::SINTTOFP_I128_F128] = "__floattitf"; 302 Names[RTLIB::SINTTOFP_I128_PPCF128] = "__floattitf"; 303 Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf"; 304 Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf"; 305 Names[RTLIB::UINTTOFP_I32_F80] = "__floatunsixf"; 306 Names[RTLIB::UINTTOFP_I32_F128] = "__floatunsitf"; 307 Names[RTLIB::UINTTOFP_I32_PPCF128] = "__floatunsitf"; 308 Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf"; 309 Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf"; 310 Names[RTLIB::UINTTOFP_I64_F80] = "__floatundixf"; 311 Names[RTLIB::UINTTOFP_I64_F128] = "__floatunditf"; 312 Names[RTLIB::UINTTOFP_I64_PPCF128] = "__floatunditf"; 313 Names[RTLIB::UINTTOFP_I128_F32] = "__floatuntisf"; 314 Names[RTLIB::UINTTOFP_I128_F64] = "__floatuntidf"; 315 Names[RTLIB::UINTTOFP_I128_F80] = "__floatuntixf"; 316 Names[RTLIB::UINTTOFP_I128_F128] = "__floatuntitf"; 317 Names[RTLIB::UINTTOFP_I128_PPCF128] = "__floatuntitf"; 318 Names[RTLIB::OEQ_F32] = "__eqsf2"; 319 Names[RTLIB::OEQ_F64] = "__eqdf2"; 320 Names[RTLIB::OEQ_F128] = "__eqtf2"; 321 Names[RTLIB::UNE_F32] = "__nesf2"; 322 Names[RTLIB::UNE_F64] = "__nedf2"; 323 Names[RTLIB::UNE_F128] = "__netf2"; 324 Names[RTLIB::OGE_F32] = "__gesf2"; 325 Names[RTLIB::OGE_F64] = "__gedf2"; 326 Names[RTLIB::OGE_F128] = "__getf2"; 327 Names[RTLIB::OLT_F32] = "__ltsf2"; 328 Names[RTLIB::OLT_F64] = "__ltdf2"; 329 Names[RTLIB::OLT_F128] = "__lttf2"; 330 Names[RTLIB::OLE_F32] = "__lesf2"; 331 Names[RTLIB::OLE_F64] = "__ledf2"; 332 Names[RTLIB::OLE_F128] = "__letf2"; 333 Names[RTLIB::OGT_F32] = "__gtsf2"; 334 Names[RTLIB::OGT_F64] = "__gtdf2"; 335 Names[RTLIB::OGT_F128] = "__gttf2"; 336 Names[RTLIB::UO_F32] = "__unordsf2"; 337 Names[RTLIB::UO_F64] = "__unorddf2"; 338 Names[RTLIB::UO_F128] = "__unordtf2"; 339 Names[RTLIB::O_F32] = "__unordsf2"; 340 Names[RTLIB::O_F64] = "__unorddf2"; 341 Names[RTLIB::O_F128] = "__unordtf2"; 342 Names[RTLIB::MEMCPY] = "memcpy"; 343 Names[RTLIB::MEMMOVE] = "memmove"; 344 Names[RTLIB::MEMSET] = "memset"; 345 Names[RTLIB::UNWIND_RESUME] = "_Unwind_Resume"; 346 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1] = "__sync_val_compare_and_swap_1"; 347 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2] = "__sync_val_compare_and_swap_2"; 348 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4] = "__sync_val_compare_and_swap_4"; 349 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8] = "__sync_val_compare_and_swap_8"; 350 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_16] = "__sync_val_compare_and_swap_16"; 351 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_1] = "__sync_lock_test_and_set_1"; 352 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_2] = "__sync_lock_test_and_set_2"; 353 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_4] = "__sync_lock_test_and_set_4"; 354 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_8] = "__sync_lock_test_and_set_8"; 355 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_16] = "__sync_lock_test_and_set_16"; 356 Names[RTLIB::SYNC_FETCH_AND_ADD_1] = "__sync_fetch_and_add_1"; 357 Names[RTLIB::SYNC_FETCH_AND_ADD_2] = "__sync_fetch_and_add_2"; 358 Names[RTLIB::SYNC_FETCH_AND_ADD_4] = "__sync_fetch_and_add_4"; 359 Names[RTLIB::SYNC_FETCH_AND_ADD_8] = "__sync_fetch_and_add_8"; 360 Names[RTLIB::SYNC_FETCH_AND_ADD_16] = "__sync_fetch_and_add_16"; 361 Names[RTLIB::SYNC_FETCH_AND_SUB_1] = "__sync_fetch_and_sub_1"; 362 Names[RTLIB::SYNC_FETCH_AND_SUB_2] = "__sync_fetch_and_sub_2"; 363 Names[RTLIB::SYNC_FETCH_AND_SUB_4] = "__sync_fetch_and_sub_4"; 364 Names[RTLIB::SYNC_FETCH_AND_SUB_8] = "__sync_fetch_and_sub_8"; 365 Names[RTLIB::SYNC_FETCH_AND_SUB_16] = "__sync_fetch_and_sub_16"; 366 Names[RTLIB::SYNC_FETCH_AND_AND_1] = "__sync_fetch_and_and_1"; 367 Names[RTLIB::SYNC_FETCH_AND_AND_2] = "__sync_fetch_and_and_2"; 368 Names[RTLIB::SYNC_FETCH_AND_AND_4] = "__sync_fetch_and_and_4"; 369 Names[RTLIB::SYNC_FETCH_AND_AND_8] = "__sync_fetch_and_and_8"; 370 Names[RTLIB::SYNC_FETCH_AND_AND_16] = "__sync_fetch_and_and_16"; 371 Names[RTLIB::SYNC_FETCH_AND_OR_1] = "__sync_fetch_and_or_1"; 372 Names[RTLIB::SYNC_FETCH_AND_OR_2] = "__sync_fetch_and_or_2"; 373 Names[RTLIB::SYNC_FETCH_AND_OR_4] = "__sync_fetch_and_or_4"; 374 Names[RTLIB::SYNC_FETCH_AND_OR_8] = "__sync_fetch_and_or_8"; 375 Names[RTLIB::SYNC_FETCH_AND_OR_16] = "__sync_fetch_and_or_16"; 376 Names[RTLIB::SYNC_FETCH_AND_XOR_1] = "__sync_fetch_and_xor_1"; 377 Names[RTLIB::SYNC_FETCH_AND_XOR_2] = "__sync_fetch_and_xor_2"; 378 Names[RTLIB::SYNC_FETCH_AND_XOR_4] = "__sync_fetch_and_xor_4"; 379 Names[RTLIB::SYNC_FETCH_AND_XOR_8] = "__sync_fetch_and_xor_8"; 380 Names[RTLIB::SYNC_FETCH_AND_XOR_16] = "__sync_fetch_and_xor_16"; 381 Names[RTLIB::SYNC_FETCH_AND_NAND_1] = "__sync_fetch_and_nand_1"; 382 Names[RTLIB::SYNC_FETCH_AND_NAND_2] = "__sync_fetch_and_nand_2"; 383 Names[RTLIB::SYNC_FETCH_AND_NAND_4] = "__sync_fetch_and_nand_4"; 384 Names[RTLIB::SYNC_FETCH_AND_NAND_8] = "__sync_fetch_and_nand_8"; 385 Names[RTLIB::SYNC_FETCH_AND_NAND_16] = "__sync_fetch_and_nand_16"; 386 Names[RTLIB::SYNC_FETCH_AND_MAX_1] = "__sync_fetch_and_max_1"; 387 Names[RTLIB::SYNC_FETCH_AND_MAX_2] = "__sync_fetch_and_max_2"; 388 Names[RTLIB::SYNC_FETCH_AND_MAX_4] = "__sync_fetch_and_max_4"; 389 Names[RTLIB::SYNC_FETCH_AND_MAX_8] = "__sync_fetch_and_max_8"; 390 Names[RTLIB::SYNC_FETCH_AND_MAX_16] = "__sync_fetch_and_max_16"; 391 Names[RTLIB::SYNC_FETCH_AND_UMAX_1] = "__sync_fetch_and_umax_1"; 392 Names[RTLIB::SYNC_FETCH_AND_UMAX_2] = "__sync_fetch_and_umax_2"; 393 Names[RTLIB::SYNC_FETCH_AND_UMAX_4] = "__sync_fetch_and_umax_4"; 394 Names[RTLIB::SYNC_FETCH_AND_UMAX_8] = "__sync_fetch_and_umax_8"; 395 Names[RTLIB::SYNC_FETCH_AND_UMAX_16] = "__sync_fetch_and_umax_16"; 396 Names[RTLIB::SYNC_FETCH_AND_MIN_1] = "__sync_fetch_and_min_1"; 397 Names[RTLIB::SYNC_FETCH_AND_MIN_2] = "__sync_fetch_and_min_2"; 398 Names[RTLIB::SYNC_FETCH_AND_MIN_4] = "__sync_fetch_and_min_4"; 399 Names[RTLIB::SYNC_FETCH_AND_MIN_8] = "__sync_fetch_and_min_8"; 400 Names[RTLIB::SYNC_FETCH_AND_MIN_16] = "__sync_fetch_and_min_16"; 401 Names[RTLIB::SYNC_FETCH_AND_UMIN_1] = "__sync_fetch_and_umin_1"; 402 Names[RTLIB::SYNC_FETCH_AND_UMIN_2] = "__sync_fetch_and_umin_2"; 403 Names[RTLIB::SYNC_FETCH_AND_UMIN_4] = "__sync_fetch_and_umin_4"; 404 Names[RTLIB::SYNC_FETCH_AND_UMIN_8] = "__sync_fetch_and_umin_8"; 405 Names[RTLIB::SYNC_FETCH_AND_UMIN_16] = "__sync_fetch_and_umin_16"; 406 407 if (TT.getEnvironment() == Triple::GNU) { 408 Names[RTLIB::SINCOS_F32] = "sincosf"; 409 Names[RTLIB::SINCOS_F64] = "sincos"; 410 Names[RTLIB::SINCOS_F80] = "sincosl"; 411 Names[RTLIB::SINCOS_F128] = "sincosl"; 412 Names[RTLIB::SINCOS_PPCF128] = "sincosl"; 413 } else { 414 // These are generally not available. 415 Names[RTLIB::SINCOS_F32] = nullptr; 416 Names[RTLIB::SINCOS_F64] = nullptr; 417 Names[RTLIB::SINCOS_F80] = nullptr; 418 Names[RTLIB::SINCOS_F128] = nullptr; 419 Names[RTLIB::SINCOS_PPCF128] = nullptr; 420 } 421 422 if (!TT.isOSOpenBSD()) { 423 Names[RTLIB::STACKPROTECTOR_CHECK_FAIL] = "__stack_chk_fail"; 424 } else { 425 // These are generally not available. 426 Names[RTLIB::STACKPROTECTOR_CHECK_FAIL] = nullptr; 427 } 428 429 // For f16/f32 conversions, Darwin uses the standard naming scheme, instead 430 // of the gnueabi-style __gnu_*_ieee. 431 // FIXME: What about other targets? 432 if (TT.isOSDarwin()) { 433 Names[RTLIB::FPEXT_F16_F32] = "__extendhfsf2"; 434 Names[RTLIB::FPROUND_F32_F16] = "__truncsfhf2"; 435 } 436 } 437 438 /// InitLibcallCallingConvs - Set default libcall CallingConvs. 439 /// 440 static void InitLibcallCallingConvs(CallingConv::ID *CCs) { 441 for (int i = 0; i < RTLIB::UNKNOWN_LIBCALL; ++i) { 442 CCs[i] = CallingConv::C; 443 } 444 } 445 446 /// getFPEXT - Return the FPEXT_*_* value for the given types, or 447 /// UNKNOWN_LIBCALL if there is none. 448 RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) { 449 if (OpVT == MVT::f16) { 450 if (RetVT == MVT::f32) 451 return FPEXT_F16_F32; 452 } else if (OpVT == MVT::f32) { 453 if (RetVT == MVT::f64) 454 return FPEXT_F32_F64; 455 if (RetVT == MVT::f128) 456 return FPEXT_F32_F128; 457 } else if (OpVT == MVT::f64) { 458 if (RetVT == MVT::f128) 459 return FPEXT_F64_F128; 460 } 461 462 return UNKNOWN_LIBCALL; 463 } 464 465 /// getFPROUND - Return the FPROUND_*_* value for the given types, or 466 /// UNKNOWN_LIBCALL if there is none. 467 RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) { 468 if (RetVT == MVT::f16) { 469 if (OpVT == MVT::f32) 470 return FPROUND_F32_F16; 471 if (OpVT == MVT::f64) 472 return FPROUND_F64_F16; 473 if (OpVT == MVT::f80) 474 return FPROUND_F80_F16; 475 if (OpVT == MVT::f128) 476 return FPROUND_F128_F16; 477 if (OpVT == MVT::ppcf128) 478 return FPROUND_PPCF128_F16; 479 } else if (RetVT == MVT::f32) { 480 if (OpVT == MVT::f64) 481 return FPROUND_F64_F32; 482 if (OpVT == MVT::f80) 483 return FPROUND_F80_F32; 484 if (OpVT == MVT::f128) 485 return FPROUND_F128_F32; 486 if (OpVT == MVT::ppcf128) 487 return FPROUND_PPCF128_F32; 488 } else if (RetVT == MVT::f64) { 489 if (OpVT == MVT::f80) 490 return FPROUND_F80_F64; 491 if (OpVT == MVT::f128) 492 return FPROUND_F128_F64; 493 if (OpVT == MVT::ppcf128) 494 return FPROUND_PPCF128_F64; 495 } 496 497 return UNKNOWN_LIBCALL; 498 } 499 500 /// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or 501 /// UNKNOWN_LIBCALL if there is none. 502 RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT, EVT RetVT) { 503 if (OpVT == MVT::f32) { 504 if (RetVT == MVT::i8) 505 return FPTOSINT_F32_I8; 506 if (RetVT == MVT::i16) 507 return FPTOSINT_F32_I16; 508 if (RetVT == MVT::i32) 509 return FPTOSINT_F32_I32; 510 if (RetVT == MVT::i64) 511 return FPTOSINT_F32_I64; 512 if (RetVT == MVT::i128) 513 return FPTOSINT_F32_I128; 514 } else if (OpVT == MVT::f64) { 515 if (RetVT == MVT::i8) 516 return FPTOSINT_F64_I8; 517 if (RetVT == MVT::i16) 518 return FPTOSINT_F64_I16; 519 if (RetVT == MVT::i32) 520 return FPTOSINT_F64_I32; 521 if (RetVT == MVT::i64) 522 return FPTOSINT_F64_I64; 523 if (RetVT == MVT::i128) 524 return FPTOSINT_F64_I128; 525 } else if (OpVT == MVT::f80) { 526 if (RetVT == MVT::i32) 527 return FPTOSINT_F80_I32; 528 if (RetVT == MVT::i64) 529 return FPTOSINT_F80_I64; 530 if (RetVT == MVT::i128) 531 return FPTOSINT_F80_I128; 532 } else if (OpVT == MVT::f128) { 533 if (RetVT == MVT::i32) 534 return FPTOSINT_F128_I32; 535 if (RetVT == MVT::i64) 536 return FPTOSINT_F128_I64; 537 if (RetVT == MVT::i128) 538 return FPTOSINT_F128_I128; 539 } else if (OpVT == MVT::ppcf128) { 540 if (RetVT == MVT::i32) 541 return FPTOSINT_PPCF128_I32; 542 if (RetVT == MVT::i64) 543 return FPTOSINT_PPCF128_I64; 544 if (RetVT == MVT::i128) 545 return FPTOSINT_PPCF128_I128; 546 } 547 return UNKNOWN_LIBCALL; 548 } 549 550 /// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or 551 /// UNKNOWN_LIBCALL if there is none. 552 RTLIB::Libcall RTLIB::getFPTOUINT(EVT OpVT, EVT RetVT) { 553 if (OpVT == MVT::f32) { 554 if (RetVT == MVT::i8) 555 return FPTOUINT_F32_I8; 556 if (RetVT == MVT::i16) 557 return FPTOUINT_F32_I16; 558 if (RetVT == MVT::i32) 559 return FPTOUINT_F32_I32; 560 if (RetVT == MVT::i64) 561 return FPTOUINT_F32_I64; 562 if (RetVT == MVT::i128) 563 return FPTOUINT_F32_I128; 564 } else if (OpVT == MVT::f64) { 565 if (RetVT == MVT::i8) 566 return FPTOUINT_F64_I8; 567 if (RetVT == MVT::i16) 568 return FPTOUINT_F64_I16; 569 if (RetVT == MVT::i32) 570 return FPTOUINT_F64_I32; 571 if (RetVT == MVT::i64) 572 return FPTOUINT_F64_I64; 573 if (RetVT == MVT::i128) 574 return FPTOUINT_F64_I128; 575 } else if (OpVT == MVT::f80) { 576 if (RetVT == MVT::i32) 577 return FPTOUINT_F80_I32; 578 if (RetVT == MVT::i64) 579 return FPTOUINT_F80_I64; 580 if (RetVT == MVT::i128) 581 return FPTOUINT_F80_I128; 582 } else if (OpVT == MVT::f128) { 583 if (RetVT == MVT::i32) 584 return FPTOUINT_F128_I32; 585 if (RetVT == MVT::i64) 586 return FPTOUINT_F128_I64; 587 if (RetVT == MVT::i128) 588 return FPTOUINT_F128_I128; 589 } else if (OpVT == MVT::ppcf128) { 590 if (RetVT == MVT::i32) 591 return FPTOUINT_PPCF128_I32; 592 if (RetVT == MVT::i64) 593 return FPTOUINT_PPCF128_I64; 594 if (RetVT == MVT::i128) 595 return FPTOUINT_PPCF128_I128; 596 } 597 return UNKNOWN_LIBCALL; 598 } 599 600 /// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or 601 /// UNKNOWN_LIBCALL if there is none. 602 RTLIB::Libcall RTLIB::getSINTTOFP(EVT OpVT, EVT RetVT) { 603 if (OpVT == MVT::i32) { 604 if (RetVT == MVT::f32) 605 return SINTTOFP_I32_F32; 606 if (RetVT == MVT::f64) 607 return SINTTOFP_I32_F64; 608 if (RetVT == MVT::f80) 609 return SINTTOFP_I32_F80; 610 if (RetVT == MVT::f128) 611 return SINTTOFP_I32_F128; 612 if (RetVT == MVT::ppcf128) 613 return SINTTOFP_I32_PPCF128; 614 } else if (OpVT == MVT::i64) { 615 if (RetVT == MVT::f32) 616 return SINTTOFP_I64_F32; 617 if (RetVT == MVT::f64) 618 return SINTTOFP_I64_F64; 619 if (RetVT == MVT::f80) 620 return SINTTOFP_I64_F80; 621 if (RetVT == MVT::f128) 622 return SINTTOFP_I64_F128; 623 if (RetVT == MVT::ppcf128) 624 return SINTTOFP_I64_PPCF128; 625 } else if (OpVT == MVT::i128) { 626 if (RetVT == MVT::f32) 627 return SINTTOFP_I128_F32; 628 if (RetVT == MVT::f64) 629 return SINTTOFP_I128_F64; 630 if (RetVT == MVT::f80) 631 return SINTTOFP_I128_F80; 632 if (RetVT == MVT::f128) 633 return SINTTOFP_I128_F128; 634 if (RetVT == MVT::ppcf128) 635 return SINTTOFP_I128_PPCF128; 636 } 637 return UNKNOWN_LIBCALL; 638 } 639 640 /// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or 641 /// UNKNOWN_LIBCALL if there is none. 642 RTLIB::Libcall RTLIB::getUINTTOFP(EVT OpVT, EVT RetVT) { 643 if (OpVT == MVT::i32) { 644 if (RetVT == MVT::f32) 645 return UINTTOFP_I32_F32; 646 if (RetVT == MVT::f64) 647 return UINTTOFP_I32_F64; 648 if (RetVT == MVT::f80) 649 return UINTTOFP_I32_F80; 650 if (RetVT == MVT::f128) 651 return UINTTOFP_I32_F128; 652 if (RetVT == MVT::ppcf128) 653 return UINTTOFP_I32_PPCF128; 654 } else if (OpVT == MVT::i64) { 655 if (RetVT == MVT::f32) 656 return UINTTOFP_I64_F32; 657 if (RetVT == MVT::f64) 658 return UINTTOFP_I64_F64; 659 if (RetVT == MVT::f80) 660 return UINTTOFP_I64_F80; 661 if (RetVT == MVT::f128) 662 return UINTTOFP_I64_F128; 663 if (RetVT == MVT::ppcf128) 664 return UINTTOFP_I64_PPCF128; 665 } else if (OpVT == MVT::i128) { 666 if (RetVT == MVT::f32) 667 return UINTTOFP_I128_F32; 668 if (RetVT == MVT::f64) 669 return UINTTOFP_I128_F64; 670 if (RetVT == MVT::f80) 671 return UINTTOFP_I128_F80; 672 if (RetVT == MVT::f128) 673 return UINTTOFP_I128_F128; 674 if (RetVT == MVT::ppcf128) 675 return UINTTOFP_I128_PPCF128; 676 } 677 return UNKNOWN_LIBCALL; 678 } 679 680 RTLIB::Libcall RTLIB::getATOMIC(unsigned Opc, MVT VT) { 681 #define OP_TO_LIBCALL(Name, Enum) \ 682 case Name: \ 683 switch (VT.SimpleTy) { \ 684 default: \ 685 return UNKNOWN_LIBCALL; \ 686 case MVT::i8: \ 687 return Enum##_1; \ 688 case MVT::i16: \ 689 return Enum##_2; \ 690 case MVT::i32: \ 691 return Enum##_4; \ 692 case MVT::i64: \ 693 return Enum##_8; \ 694 case MVT::i128: \ 695 return Enum##_16; \ 696 } 697 698 switch (Opc) { 699 OP_TO_LIBCALL(ISD::ATOMIC_SWAP, SYNC_LOCK_TEST_AND_SET) 700 OP_TO_LIBCALL(ISD::ATOMIC_CMP_SWAP, SYNC_VAL_COMPARE_AND_SWAP) 701 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_ADD, SYNC_FETCH_AND_ADD) 702 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_SUB, SYNC_FETCH_AND_SUB) 703 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_AND, SYNC_FETCH_AND_AND) 704 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_OR, SYNC_FETCH_AND_OR) 705 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_XOR, SYNC_FETCH_AND_XOR) 706 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_NAND, SYNC_FETCH_AND_NAND) 707 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_MAX, SYNC_FETCH_AND_MAX) 708 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_UMAX, SYNC_FETCH_AND_UMAX) 709 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_MIN, SYNC_FETCH_AND_MIN) 710 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_UMIN, SYNC_FETCH_AND_UMIN) 711 } 712 713 #undef OP_TO_LIBCALL 714 715 return UNKNOWN_LIBCALL; 716 } 717 718 /// InitCmpLibcallCCs - Set default comparison libcall CC. 719 /// 720 static void InitCmpLibcallCCs(ISD::CondCode *CCs) { 721 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL); 722 CCs[RTLIB::OEQ_F32] = ISD::SETEQ; 723 CCs[RTLIB::OEQ_F64] = ISD::SETEQ; 724 CCs[RTLIB::OEQ_F128] = ISD::SETEQ; 725 CCs[RTLIB::UNE_F32] = ISD::SETNE; 726 CCs[RTLIB::UNE_F64] = ISD::SETNE; 727 CCs[RTLIB::UNE_F128] = ISD::SETNE; 728 CCs[RTLIB::OGE_F32] = ISD::SETGE; 729 CCs[RTLIB::OGE_F64] = ISD::SETGE; 730 CCs[RTLIB::OGE_F128] = ISD::SETGE; 731 CCs[RTLIB::OLT_F32] = ISD::SETLT; 732 CCs[RTLIB::OLT_F64] = ISD::SETLT; 733 CCs[RTLIB::OLT_F128] = ISD::SETLT; 734 CCs[RTLIB::OLE_F32] = ISD::SETLE; 735 CCs[RTLIB::OLE_F64] = ISD::SETLE; 736 CCs[RTLIB::OLE_F128] = ISD::SETLE; 737 CCs[RTLIB::OGT_F32] = ISD::SETGT; 738 CCs[RTLIB::OGT_F64] = ISD::SETGT; 739 CCs[RTLIB::OGT_F128] = ISD::SETGT; 740 CCs[RTLIB::UO_F32] = ISD::SETNE; 741 CCs[RTLIB::UO_F64] = ISD::SETNE; 742 CCs[RTLIB::UO_F128] = ISD::SETNE; 743 CCs[RTLIB::O_F32] = ISD::SETEQ; 744 CCs[RTLIB::O_F64] = ISD::SETEQ; 745 CCs[RTLIB::O_F128] = ISD::SETEQ; 746 } 747 748 /// NOTE: The TargetMachine owns TLOF. 749 TargetLoweringBase::TargetLoweringBase(const TargetMachine &tm) : TM(tm) { 750 initActions(); 751 752 // Perform these initializations only once. 753 MaxStoresPerMemset = MaxStoresPerMemcpy = MaxStoresPerMemmove = 8; 754 MaxStoresPerMemsetOptSize = MaxStoresPerMemcpyOptSize 755 = MaxStoresPerMemmoveOptSize = 4; 756 UseUnderscoreSetJmp = false; 757 UseUnderscoreLongJmp = false; 758 SelectIsExpensive = false; 759 HasMultipleConditionRegisters = false; 760 HasExtractBitsInsn = false; 761 FsqrtIsCheap = false; 762 JumpIsExpensive = JumpIsExpensiveOverride; 763 PredictableSelectIsExpensive = false; 764 MaskAndBranchFoldingIsLegal = false; 765 EnableExtLdPromotion = false; 766 HasFloatingPointExceptions = true; 767 StackPointerRegisterToSaveRestore = 0; 768 BooleanContents = UndefinedBooleanContent; 769 BooleanFloatContents = UndefinedBooleanContent; 770 BooleanVectorContents = UndefinedBooleanContent; 771 SchedPreferenceInfo = Sched::ILP; 772 JumpBufSize = 0; 773 JumpBufAlignment = 0; 774 MinFunctionAlignment = 0; 775 PrefFunctionAlignment = 0; 776 PrefLoopAlignment = 0; 777 GatherAllAliasesMaxDepth = 6; 778 MinStackArgumentAlignment = 1; 779 InsertFencesForAtomic = false; 780 MinimumJumpTableEntries = 4; 781 782 InitLibcallNames(LibcallRoutineNames, TM.getTargetTriple()); 783 InitCmpLibcallCCs(CmpLibcallCCs); 784 InitLibcallCallingConvs(LibcallCallingConvs); 785 } 786 787 void TargetLoweringBase::initActions() { 788 // All operations default to being supported. 789 memset(OpActions, 0, sizeof(OpActions)); 790 memset(LoadExtActions, 0, sizeof(LoadExtActions)); 791 memset(TruncStoreActions, 0, sizeof(TruncStoreActions)); 792 memset(IndexedModeActions, 0, sizeof(IndexedModeActions)); 793 memset(CondCodeActions, 0, sizeof(CondCodeActions)); 794 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*)); 795 memset(TargetDAGCombineArray, 0, array_lengthof(TargetDAGCombineArray)); 796 797 // Set default actions for various operations. 798 for (MVT VT : MVT::all_valuetypes()) { 799 // Default all indexed load / store to expand. 800 for (unsigned IM = (unsigned)ISD::PRE_INC; 801 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) { 802 setIndexedLoadAction(IM, VT, Expand); 803 setIndexedStoreAction(IM, VT, Expand); 804 } 805 806 // Most backends expect to see the node which just returns the value loaded. 807 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Expand); 808 809 // These operations default to expand. 810 setOperationAction(ISD::FGETSIGN, VT, Expand); 811 setOperationAction(ISD::CONCAT_VECTORS, VT, Expand); 812 setOperationAction(ISD::FMINNUM, VT, Expand); 813 setOperationAction(ISD::FMAXNUM, VT, Expand); 814 setOperationAction(ISD::FMINNAN, VT, Expand); 815 setOperationAction(ISD::FMAXNAN, VT, Expand); 816 setOperationAction(ISD::FMAD, VT, Expand); 817 setOperationAction(ISD::SMIN, VT, Expand); 818 setOperationAction(ISD::SMAX, VT, Expand); 819 setOperationAction(ISD::UMIN, VT, Expand); 820 setOperationAction(ISD::UMAX, VT, Expand); 821 822 // Overflow operations default to expand 823 setOperationAction(ISD::SADDO, VT, Expand); 824 setOperationAction(ISD::SSUBO, VT, Expand); 825 setOperationAction(ISD::UADDO, VT, Expand); 826 setOperationAction(ISD::USUBO, VT, Expand); 827 setOperationAction(ISD::SMULO, VT, Expand); 828 setOperationAction(ISD::UMULO, VT, Expand); 829 setOperationAction(ISD::UABSDIFF, VT, Expand); 830 setOperationAction(ISD::SABSDIFF, VT, Expand); 831 setOperationAction(ISD::BITREVERSE, VT, Expand); 832 833 // These library functions default to expand. 834 setOperationAction(ISD::FROUND, VT, Expand); 835 836 // These operations default to expand for vector types. 837 if (VT.isVector()) { 838 setOperationAction(ISD::FCOPYSIGN, VT, Expand); 839 setOperationAction(ISD::ANY_EXTEND_VECTOR_INREG, VT, Expand); 840 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, VT, Expand); 841 setOperationAction(ISD::ZERO_EXTEND_VECTOR_INREG, VT, Expand); 842 } 843 844 // For most targets @llvm.get.dynamic.area.offest just returns 0. 845 setOperationAction(ISD::GET_DYNAMIC_AREA_OFFSET, VT, Expand); 846 } 847 848 // Most targets ignore the @llvm.prefetch intrinsic. 849 setOperationAction(ISD::PREFETCH, MVT::Other, Expand); 850 851 // Most targets also ignore the @llvm.readcyclecounter intrinsic. 852 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Expand); 853 854 // ConstantFP nodes default to expand. Targets can either change this to 855 // Legal, in which case all fp constants are legal, or use isFPImmLegal() 856 // to optimize expansions for certain constants. 857 setOperationAction(ISD::ConstantFP, MVT::f16, Expand); 858 setOperationAction(ISD::ConstantFP, MVT::f32, Expand); 859 setOperationAction(ISD::ConstantFP, MVT::f64, Expand); 860 setOperationAction(ISD::ConstantFP, MVT::f80, Expand); 861 setOperationAction(ISD::ConstantFP, MVT::f128, Expand); 862 863 // These library functions default to expand. 864 for (MVT VT : {MVT::f32, MVT::f64, MVT::f128}) { 865 setOperationAction(ISD::FLOG , VT, Expand); 866 setOperationAction(ISD::FLOG2, VT, Expand); 867 setOperationAction(ISD::FLOG10, VT, Expand); 868 setOperationAction(ISD::FEXP , VT, Expand); 869 setOperationAction(ISD::FEXP2, VT, Expand); 870 setOperationAction(ISD::FFLOOR, VT, Expand); 871 setOperationAction(ISD::FMINNUM, VT, Expand); 872 setOperationAction(ISD::FMAXNUM, VT, Expand); 873 setOperationAction(ISD::FNEARBYINT, VT, Expand); 874 setOperationAction(ISD::FCEIL, VT, Expand); 875 setOperationAction(ISD::FRINT, VT, Expand); 876 setOperationAction(ISD::FTRUNC, VT, Expand); 877 setOperationAction(ISD::FROUND, VT, Expand); 878 } 879 880 // Default ISD::TRAP to expand (which turns it into abort). 881 setOperationAction(ISD::TRAP, MVT::Other, Expand); 882 883 // On most systems, DEBUGTRAP and TRAP have no difference. The "Expand" 884 // here is to inform DAG Legalizer to replace DEBUGTRAP with TRAP. 885 // 886 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Expand); 887 } 888 889 MVT TargetLoweringBase::getScalarShiftAmountTy(const DataLayout &DL, 890 EVT) const { 891 return MVT::getIntegerVT(8 * DL.getPointerSize(0)); 892 } 893 894 EVT TargetLoweringBase::getShiftAmountTy(EVT LHSTy, 895 const DataLayout &DL) const { 896 assert(LHSTy.isInteger() && "Shift amount is not an integer type!"); 897 if (LHSTy.isVector()) 898 return LHSTy; 899 return getScalarShiftAmountTy(DL, LHSTy); 900 } 901 902 /// canOpTrap - Returns true if the operation can trap for the value type. 903 /// VT must be a legal type. 904 bool TargetLoweringBase::canOpTrap(unsigned Op, EVT VT) const { 905 assert(isTypeLegal(VT)); 906 switch (Op) { 907 default: 908 return false; 909 case ISD::FDIV: 910 case ISD::FREM: 911 case ISD::SDIV: 912 case ISD::UDIV: 913 case ISD::SREM: 914 case ISD::UREM: 915 return true; 916 } 917 } 918 919 void TargetLoweringBase::setJumpIsExpensive(bool isExpensive) { 920 // If the command-line option was specified, ignore this request. 921 if (!JumpIsExpensiveOverride.getNumOccurrences()) 922 JumpIsExpensive = isExpensive; 923 } 924 925 TargetLoweringBase::LegalizeKind 926 TargetLoweringBase::getTypeConversion(LLVMContext &Context, EVT VT) const { 927 // If this is a simple type, use the ComputeRegisterProp mechanism. 928 if (VT.isSimple()) { 929 MVT SVT = VT.getSimpleVT(); 930 assert((unsigned)SVT.SimpleTy < array_lengthof(TransformToType)); 931 MVT NVT = TransformToType[SVT.SimpleTy]; 932 LegalizeTypeAction LA = ValueTypeActions.getTypeAction(SVT); 933 934 assert((LA == TypeLegal || LA == TypeSoftenFloat || 935 ValueTypeActions.getTypeAction(NVT) != TypePromoteInteger) && 936 "Promote may not follow Expand or Promote"); 937 938 if (LA == TypeSplitVector) 939 return LegalizeKind(LA, 940 EVT::getVectorVT(Context, SVT.getVectorElementType(), 941 SVT.getVectorNumElements() / 2)); 942 if (LA == TypeScalarizeVector) 943 return LegalizeKind(LA, SVT.getVectorElementType()); 944 return LegalizeKind(LA, NVT); 945 } 946 947 // Handle Extended Scalar Types. 948 if (!VT.isVector()) { 949 assert(VT.isInteger() && "Float types must be simple"); 950 unsigned BitSize = VT.getSizeInBits(); 951 // First promote to a power-of-two size, then expand if necessary. 952 if (BitSize < 8 || !isPowerOf2_32(BitSize)) { 953 EVT NVT = VT.getRoundIntegerType(Context); 954 assert(NVT != VT && "Unable to round integer VT"); 955 LegalizeKind NextStep = getTypeConversion(Context, NVT); 956 // Avoid multi-step promotion. 957 if (NextStep.first == TypePromoteInteger) 958 return NextStep; 959 // Return rounded integer type. 960 return LegalizeKind(TypePromoteInteger, NVT); 961 } 962 963 return LegalizeKind(TypeExpandInteger, 964 EVT::getIntegerVT(Context, VT.getSizeInBits() / 2)); 965 } 966 967 // Handle vector types. 968 unsigned NumElts = VT.getVectorNumElements(); 969 EVT EltVT = VT.getVectorElementType(); 970 971 // Vectors with only one element are always scalarized. 972 if (NumElts == 1) 973 return LegalizeKind(TypeScalarizeVector, EltVT); 974 975 // Try to widen vector elements until the element type is a power of two and 976 // promote it to a legal type later on, for example: 977 // <3 x i8> -> <4 x i8> -> <4 x i32> 978 if (EltVT.isInteger()) { 979 // Vectors with a number of elements that is not a power of two are always 980 // widened, for example <3 x i8> -> <4 x i8>. 981 if (!VT.isPow2VectorType()) { 982 NumElts = (unsigned)NextPowerOf2(NumElts); 983 EVT NVT = EVT::getVectorVT(Context, EltVT, NumElts); 984 return LegalizeKind(TypeWidenVector, NVT); 985 } 986 987 // Examine the element type. 988 LegalizeKind LK = getTypeConversion(Context, EltVT); 989 990 // If type is to be expanded, split the vector. 991 // <4 x i140> -> <2 x i140> 992 if (LK.first == TypeExpandInteger) 993 return LegalizeKind(TypeSplitVector, 994 EVT::getVectorVT(Context, EltVT, NumElts / 2)); 995 996 // Promote the integer element types until a legal vector type is found 997 // or until the element integer type is too big. If a legal type was not 998 // found, fallback to the usual mechanism of widening/splitting the 999 // vector. 1000 EVT OldEltVT = EltVT; 1001 while (1) { 1002 // Increase the bitwidth of the element to the next pow-of-two 1003 // (which is greater than 8 bits). 1004 EltVT = EVT::getIntegerVT(Context, 1 + EltVT.getSizeInBits()) 1005 .getRoundIntegerType(Context); 1006 1007 // Stop trying when getting a non-simple element type. 1008 // Note that vector elements may be greater than legal vector element 1009 // types. Example: X86 XMM registers hold 64bit element on 32bit 1010 // systems. 1011 if (!EltVT.isSimple()) 1012 break; 1013 1014 // Build a new vector type and check if it is legal. 1015 MVT NVT = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts); 1016 // Found a legal promoted vector type. 1017 if (NVT != MVT() && ValueTypeActions.getTypeAction(NVT) == TypeLegal) 1018 return LegalizeKind(TypePromoteInteger, 1019 EVT::getVectorVT(Context, EltVT, NumElts)); 1020 } 1021 1022 // Reset the type to the unexpanded type if we did not find a legal vector 1023 // type with a promoted vector element type. 1024 EltVT = OldEltVT; 1025 } 1026 1027 // Try to widen the vector until a legal type is found. 1028 // If there is no wider legal type, split the vector. 1029 while (1) { 1030 // Round up to the next power of 2. 1031 NumElts = (unsigned)NextPowerOf2(NumElts); 1032 1033 // If there is no simple vector type with this many elements then there 1034 // cannot be a larger legal vector type. Note that this assumes that 1035 // there are no skipped intermediate vector types in the simple types. 1036 if (!EltVT.isSimple()) 1037 break; 1038 MVT LargerVector = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts); 1039 if (LargerVector == MVT()) 1040 break; 1041 1042 // If this type is legal then widen the vector. 1043 if (ValueTypeActions.getTypeAction(LargerVector) == TypeLegal) 1044 return LegalizeKind(TypeWidenVector, LargerVector); 1045 } 1046 1047 // Widen odd vectors to next power of two. 1048 if (!VT.isPow2VectorType()) { 1049 EVT NVT = VT.getPow2VectorType(Context); 1050 return LegalizeKind(TypeWidenVector, NVT); 1051 } 1052 1053 // Vectors with illegal element types are expanded. 1054 EVT NVT = EVT::getVectorVT(Context, EltVT, VT.getVectorNumElements() / 2); 1055 return LegalizeKind(TypeSplitVector, NVT); 1056 } 1057 1058 static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT, 1059 unsigned &NumIntermediates, 1060 MVT &RegisterVT, 1061 TargetLoweringBase *TLI) { 1062 // Figure out the right, legal destination reg to copy into. 1063 unsigned NumElts = VT.getVectorNumElements(); 1064 MVT EltTy = VT.getVectorElementType(); 1065 1066 unsigned NumVectorRegs = 1; 1067 1068 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we 1069 // could break down into LHS/RHS like LegalizeDAG does. 1070 if (!isPowerOf2_32(NumElts)) { 1071 NumVectorRegs = NumElts; 1072 NumElts = 1; 1073 } 1074 1075 // Divide the input until we get to a supported size. This will always 1076 // end with a scalar if the target doesn't support vectors. 1077 while (NumElts > 1 && !TLI->isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) { 1078 NumElts >>= 1; 1079 NumVectorRegs <<= 1; 1080 } 1081 1082 NumIntermediates = NumVectorRegs; 1083 1084 MVT NewVT = MVT::getVectorVT(EltTy, NumElts); 1085 if (!TLI->isTypeLegal(NewVT)) 1086 NewVT = EltTy; 1087 IntermediateVT = NewVT; 1088 1089 unsigned NewVTSize = NewVT.getSizeInBits(); 1090 1091 // Convert sizes such as i33 to i64. 1092 if (!isPowerOf2_32(NewVTSize)) 1093 NewVTSize = NextPowerOf2(NewVTSize); 1094 1095 MVT DestVT = TLI->getRegisterType(NewVT); 1096 RegisterVT = DestVT; 1097 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16. 1098 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits()); 1099 1100 // Otherwise, promotion or legal types use the same number of registers as 1101 // the vector decimated to the appropriate level. 1102 return NumVectorRegs; 1103 } 1104 1105 /// isLegalRC - Return true if the value types that can be represented by the 1106 /// specified register class are all legal. 1107 bool TargetLoweringBase::isLegalRC(const TargetRegisterClass *RC) const { 1108 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end(); 1109 I != E; ++I) { 1110 if (isTypeLegal(*I)) 1111 return true; 1112 } 1113 return false; 1114 } 1115 1116 /// Replace/modify any TargetFrameIndex operands with a targte-dependent 1117 /// sequence of memory operands that is recognized by PrologEpilogInserter. 1118 MachineBasicBlock* 1119 TargetLoweringBase::emitPatchPoint(MachineInstr *MI, 1120 MachineBasicBlock *MBB) const { 1121 MachineFunction &MF = *MI->getParent()->getParent(); 1122 1123 // MI changes inside this loop as we grow operands. 1124 for(unsigned OperIdx = 0; OperIdx != MI->getNumOperands(); ++OperIdx) { 1125 MachineOperand &MO = MI->getOperand(OperIdx); 1126 if (!MO.isFI()) 1127 continue; 1128 1129 // foldMemoryOperand builds a new MI after replacing a single FI operand 1130 // with the canonical set of five x86 addressing-mode operands. 1131 int FI = MO.getIndex(); 1132 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), MI->getDesc()); 1133 1134 // Copy operands before the frame-index. 1135 for (unsigned i = 0; i < OperIdx; ++i) 1136 MIB.addOperand(MI->getOperand(i)); 1137 // Add frame index operands: direct-mem-ref tag, #FI, offset. 1138 MIB.addImm(StackMaps::DirectMemRefOp); 1139 MIB.addOperand(MI->getOperand(OperIdx)); 1140 MIB.addImm(0); 1141 // Copy the operands after the frame index. 1142 for (unsigned i = OperIdx + 1; i != MI->getNumOperands(); ++i) 1143 MIB.addOperand(MI->getOperand(i)); 1144 1145 // Inherit previous memory operands. 1146 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end()); 1147 assert(MIB->mayLoad() && "Folded a stackmap use to a non-load!"); 1148 1149 // Add a new memory operand for this FI. 1150 const MachineFrameInfo &MFI = *MF.getFrameInfo(); 1151 assert(MFI.getObjectOffset(FI) != -1); 1152 1153 unsigned Flags = MachineMemOperand::MOLoad; 1154 if (MI->getOpcode() == TargetOpcode::STATEPOINT) { 1155 Flags |= MachineMemOperand::MOStore; 1156 Flags |= MachineMemOperand::MOVolatile; 1157 } 1158 MachineMemOperand *MMO = MF.getMachineMemOperand( 1159 MachinePointerInfo::getFixedStack(MF, FI), Flags, 1160 MF.getDataLayout().getPointerSize(), MFI.getObjectAlignment(FI)); 1161 MIB->addMemOperand(MF, MMO); 1162 1163 // Replace the instruction and update the operand index. 1164 MBB->insert(MachineBasicBlock::iterator(MI), MIB); 1165 OperIdx += (MIB->getNumOperands() - MI->getNumOperands()) - 1; 1166 MI->eraseFromParent(); 1167 MI = MIB; 1168 } 1169 return MBB; 1170 } 1171 1172 /// findRepresentativeClass - Return the largest legal super-reg register class 1173 /// of the register class for the specified type and its associated "cost". 1174 // This function is in TargetLowering because it uses RegClassForVT which would 1175 // need to be moved to TargetRegisterInfo and would necessitate moving 1176 // isTypeLegal over as well - a massive change that would just require 1177 // TargetLowering having a TargetRegisterInfo class member that it would use. 1178 std::pair<const TargetRegisterClass *, uint8_t> 1179 TargetLoweringBase::findRepresentativeClass(const TargetRegisterInfo *TRI, 1180 MVT VT) const { 1181 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy]; 1182 if (!RC) 1183 return std::make_pair(RC, 0); 1184 1185 // Compute the set of all super-register classes. 1186 BitVector SuperRegRC(TRI->getNumRegClasses()); 1187 for (SuperRegClassIterator RCI(RC, TRI); RCI.isValid(); ++RCI) 1188 SuperRegRC.setBitsInMask(RCI.getMask()); 1189 1190 // Find the first legal register class with the largest spill size. 1191 const TargetRegisterClass *BestRC = RC; 1192 for (int i = SuperRegRC.find_first(); i >= 0; i = SuperRegRC.find_next(i)) { 1193 const TargetRegisterClass *SuperRC = TRI->getRegClass(i); 1194 // We want the largest possible spill size. 1195 if (SuperRC->getSize() <= BestRC->getSize()) 1196 continue; 1197 if (!isLegalRC(SuperRC)) 1198 continue; 1199 BestRC = SuperRC; 1200 } 1201 return std::make_pair(BestRC, 1); 1202 } 1203 1204 /// computeRegisterProperties - Once all of the register classes are added, 1205 /// this allows us to compute derived properties we expose. 1206 void TargetLoweringBase::computeRegisterProperties( 1207 const TargetRegisterInfo *TRI) { 1208 static_assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE, 1209 "Too many value types for ValueTypeActions to hold!"); 1210 1211 // Everything defaults to needing one register. 1212 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) { 1213 NumRegistersForVT[i] = 1; 1214 RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i; 1215 } 1216 // ...except isVoid, which doesn't need any registers. 1217 NumRegistersForVT[MVT::isVoid] = 0; 1218 1219 // Find the largest integer register class. 1220 unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE; 1221 for (; RegClassForVT[LargestIntReg] == nullptr; --LargestIntReg) 1222 assert(LargestIntReg != MVT::i1 && "No integer registers defined!"); 1223 1224 // Every integer value type larger than this largest register takes twice as 1225 // many registers to represent as the previous ValueType. 1226 for (unsigned ExpandedReg = LargestIntReg + 1; 1227 ExpandedReg <= MVT::LAST_INTEGER_VALUETYPE; ++ExpandedReg) { 1228 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1]; 1229 RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg; 1230 TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1); 1231 ValueTypeActions.setTypeAction((MVT::SimpleValueType)ExpandedReg, 1232 TypeExpandInteger); 1233 } 1234 1235 // Inspect all of the ValueType's smaller than the largest integer 1236 // register to see which ones need promotion. 1237 unsigned LegalIntReg = LargestIntReg; 1238 for (unsigned IntReg = LargestIntReg - 1; 1239 IntReg >= (unsigned)MVT::i1; --IntReg) { 1240 MVT IVT = (MVT::SimpleValueType)IntReg; 1241 if (isTypeLegal(IVT)) { 1242 LegalIntReg = IntReg; 1243 } else { 1244 RegisterTypeForVT[IntReg] = TransformToType[IntReg] = 1245 (const MVT::SimpleValueType)LegalIntReg; 1246 ValueTypeActions.setTypeAction(IVT, TypePromoteInteger); 1247 } 1248 } 1249 1250 // ppcf128 type is really two f64's. 1251 if (!isTypeLegal(MVT::ppcf128)) { 1252 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64]; 1253 RegisterTypeForVT[MVT::ppcf128] = MVT::f64; 1254 TransformToType[MVT::ppcf128] = MVT::f64; 1255 ValueTypeActions.setTypeAction(MVT::ppcf128, TypeExpandFloat); 1256 } 1257 1258 // Decide how to handle f128. If the target does not have native f128 support, 1259 // expand it to i128 and we will be generating soft float library calls. 1260 if (!isTypeLegal(MVT::f128)) { 1261 NumRegistersForVT[MVT::f128] = NumRegistersForVT[MVT::i128]; 1262 RegisterTypeForVT[MVT::f128] = RegisterTypeForVT[MVT::i128]; 1263 TransformToType[MVT::f128] = MVT::i128; 1264 ValueTypeActions.setTypeAction(MVT::f128, TypeSoftenFloat); 1265 } 1266 1267 // Decide how to handle f64. If the target does not have native f64 support, 1268 // expand it to i64 and we will be generating soft float library calls. 1269 if (!isTypeLegal(MVT::f64)) { 1270 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64]; 1271 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64]; 1272 TransformToType[MVT::f64] = MVT::i64; 1273 ValueTypeActions.setTypeAction(MVT::f64, TypeSoftenFloat); 1274 } 1275 1276 // Decide how to handle f32. If the target does not have native f32 support, 1277 // expand it to i32 and we will be generating soft float library calls. 1278 if (!isTypeLegal(MVT::f32)) { 1279 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32]; 1280 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32]; 1281 TransformToType[MVT::f32] = MVT::i32; 1282 ValueTypeActions.setTypeAction(MVT::f32, TypeSoftenFloat); 1283 } 1284 1285 // Decide how to handle f16. If the target does not have native f16 support, 1286 // promote it to f32, because there are no f16 library calls (except for 1287 // conversions). 1288 if (!isTypeLegal(MVT::f16)) { 1289 NumRegistersForVT[MVT::f16] = NumRegistersForVT[MVT::f32]; 1290 RegisterTypeForVT[MVT::f16] = RegisterTypeForVT[MVT::f32]; 1291 TransformToType[MVT::f16] = MVT::f32; 1292 ValueTypeActions.setTypeAction(MVT::f16, TypePromoteFloat); 1293 } 1294 1295 // Loop over all of the vector value types to see which need transformations. 1296 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE; 1297 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) { 1298 MVT VT = (MVT::SimpleValueType) i; 1299 if (isTypeLegal(VT)) 1300 continue; 1301 1302 MVT EltVT = VT.getVectorElementType(); 1303 unsigned NElts = VT.getVectorNumElements(); 1304 bool IsLegalWiderType = false; 1305 LegalizeTypeAction PreferredAction = getPreferredVectorAction(VT); 1306 switch (PreferredAction) { 1307 case TypePromoteInteger: { 1308 // Try to promote the elements of integer vectors. If no legal 1309 // promotion was found, fall through to the widen-vector method. 1310 for (unsigned nVT = i + 1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) { 1311 MVT SVT = (MVT::SimpleValueType) nVT; 1312 // Promote vectors of integers to vectors with the same number 1313 // of elements, with a wider element type. 1314 if (SVT.getVectorElementType().getSizeInBits() > EltVT.getSizeInBits() 1315 && SVT.getVectorNumElements() == NElts && isTypeLegal(SVT) 1316 && SVT.getScalarType().isInteger()) { 1317 TransformToType[i] = SVT; 1318 RegisterTypeForVT[i] = SVT; 1319 NumRegistersForVT[i] = 1; 1320 ValueTypeActions.setTypeAction(VT, TypePromoteInteger); 1321 IsLegalWiderType = true; 1322 break; 1323 } 1324 } 1325 if (IsLegalWiderType) 1326 break; 1327 } 1328 case TypeWidenVector: { 1329 // Try to widen the vector. 1330 for (unsigned nVT = i + 1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) { 1331 MVT SVT = (MVT::SimpleValueType) nVT; 1332 if (SVT.getVectorElementType() == EltVT 1333 && SVT.getVectorNumElements() > NElts && isTypeLegal(SVT)) { 1334 TransformToType[i] = SVT; 1335 RegisterTypeForVT[i] = SVT; 1336 NumRegistersForVT[i] = 1; 1337 ValueTypeActions.setTypeAction(VT, TypeWidenVector); 1338 IsLegalWiderType = true; 1339 break; 1340 } 1341 } 1342 if (IsLegalWiderType) 1343 break; 1344 } 1345 case TypeSplitVector: 1346 case TypeScalarizeVector: { 1347 MVT IntermediateVT; 1348 MVT RegisterVT; 1349 unsigned NumIntermediates; 1350 NumRegistersForVT[i] = getVectorTypeBreakdownMVT(VT, IntermediateVT, 1351 NumIntermediates, RegisterVT, this); 1352 RegisterTypeForVT[i] = RegisterVT; 1353 1354 MVT NVT = VT.getPow2VectorType(); 1355 if (NVT == VT) { 1356 // Type is already a power of 2. The default action is to split. 1357 TransformToType[i] = MVT::Other; 1358 if (PreferredAction == TypeScalarizeVector) 1359 ValueTypeActions.setTypeAction(VT, TypeScalarizeVector); 1360 else if (PreferredAction == TypeSplitVector) 1361 ValueTypeActions.setTypeAction(VT, TypeSplitVector); 1362 else 1363 // Set type action according to the number of elements. 1364 ValueTypeActions.setTypeAction(VT, NElts == 1 ? TypeScalarizeVector 1365 : TypeSplitVector); 1366 } else { 1367 TransformToType[i] = NVT; 1368 ValueTypeActions.setTypeAction(VT, TypeWidenVector); 1369 } 1370 break; 1371 } 1372 default: 1373 llvm_unreachable("Unknown vector legalization action!"); 1374 } 1375 } 1376 1377 // Determine the 'representative' register class for each value type. 1378 // An representative register class is the largest (meaning one which is 1379 // not a sub-register class / subreg register class) legal register class for 1380 // a group of value types. For example, on i386, i8, i16, and i32 1381 // representative would be GR32; while on x86_64 it's GR64. 1382 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) { 1383 const TargetRegisterClass* RRC; 1384 uint8_t Cost; 1385 std::tie(RRC, Cost) = findRepresentativeClass(TRI, (MVT::SimpleValueType)i); 1386 RepRegClassForVT[i] = RRC; 1387 RepRegClassCostForVT[i] = Cost; 1388 } 1389 } 1390 1391 EVT TargetLoweringBase::getSetCCResultType(const DataLayout &DL, LLVMContext &, 1392 EVT VT) const { 1393 assert(!VT.isVector() && "No default SetCC type for vectors!"); 1394 return getPointerTy(DL).SimpleTy; 1395 } 1396 1397 MVT::SimpleValueType TargetLoweringBase::getCmpLibcallReturnType() const { 1398 return MVT::i32; // return the default value 1399 } 1400 1401 /// getVectorTypeBreakdown - Vector types are broken down into some number of 1402 /// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32 1403 /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack. 1404 /// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86. 1405 /// 1406 /// This method returns the number of registers needed, and the VT for each 1407 /// register. It also returns the VT and quantity of the intermediate values 1408 /// before they are promoted/expanded. 1409 /// 1410 unsigned TargetLoweringBase::getVectorTypeBreakdown(LLVMContext &Context, EVT VT, 1411 EVT &IntermediateVT, 1412 unsigned &NumIntermediates, 1413 MVT &RegisterVT) const { 1414 unsigned NumElts = VT.getVectorNumElements(); 1415 1416 // If there is a wider vector type with the same element type as this one, 1417 // or a promoted vector type that has the same number of elements which 1418 // are wider, then we should convert to that legal vector type. 1419 // This handles things like <2 x float> -> <4 x float> and 1420 // <4 x i1> -> <4 x i32>. 1421 LegalizeTypeAction TA = getTypeAction(Context, VT); 1422 if (NumElts != 1 && (TA == TypeWidenVector || TA == TypePromoteInteger)) { 1423 EVT RegisterEVT = getTypeToTransformTo(Context, VT); 1424 if (isTypeLegal(RegisterEVT)) { 1425 IntermediateVT = RegisterEVT; 1426 RegisterVT = RegisterEVT.getSimpleVT(); 1427 NumIntermediates = 1; 1428 return 1; 1429 } 1430 } 1431 1432 // Figure out the right, legal destination reg to copy into. 1433 EVT EltTy = VT.getVectorElementType(); 1434 1435 unsigned NumVectorRegs = 1; 1436 1437 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we 1438 // could break down into LHS/RHS like LegalizeDAG does. 1439 if (!isPowerOf2_32(NumElts)) { 1440 NumVectorRegs = NumElts; 1441 NumElts = 1; 1442 } 1443 1444 // Divide the input until we get to a supported size. This will always 1445 // end with a scalar if the target doesn't support vectors. 1446 while (NumElts > 1 && !isTypeLegal( 1447 EVT::getVectorVT(Context, EltTy, NumElts))) { 1448 NumElts >>= 1; 1449 NumVectorRegs <<= 1; 1450 } 1451 1452 NumIntermediates = NumVectorRegs; 1453 1454 EVT NewVT = EVT::getVectorVT(Context, EltTy, NumElts); 1455 if (!isTypeLegal(NewVT)) 1456 NewVT = EltTy; 1457 IntermediateVT = NewVT; 1458 1459 MVT DestVT = getRegisterType(Context, NewVT); 1460 RegisterVT = DestVT; 1461 unsigned NewVTSize = NewVT.getSizeInBits(); 1462 1463 // Convert sizes such as i33 to i64. 1464 if (!isPowerOf2_32(NewVTSize)) 1465 NewVTSize = NextPowerOf2(NewVTSize); 1466 1467 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16. 1468 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits()); 1469 1470 // Otherwise, promotion or legal types use the same number of registers as 1471 // the vector decimated to the appropriate level. 1472 return NumVectorRegs; 1473 } 1474 1475 /// Get the EVTs and ArgFlags collections that represent the legalized return 1476 /// type of the given function. This does not require a DAG or a return value, 1477 /// and is suitable for use before any DAGs for the function are constructed. 1478 /// TODO: Move this out of TargetLowering.cpp. 1479 void llvm::GetReturnInfo(Type *ReturnType, AttributeSet attr, 1480 SmallVectorImpl<ISD::OutputArg> &Outs, 1481 const TargetLowering &TLI, const DataLayout &DL) { 1482 SmallVector<EVT, 4> ValueVTs; 1483 ComputeValueVTs(TLI, DL, ReturnType, ValueVTs); 1484 unsigned NumValues = ValueVTs.size(); 1485 if (NumValues == 0) return; 1486 1487 for (unsigned j = 0, f = NumValues; j != f; ++j) { 1488 EVT VT = ValueVTs[j]; 1489 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 1490 1491 if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::SExt)) 1492 ExtendKind = ISD::SIGN_EXTEND; 1493 else if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::ZExt)) 1494 ExtendKind = ISD::ZERO_EXTEND; 1495 1496 // FIXME: C calling convention requires the return type to be promoted to 1497 // at least 32-bit. But this is not necessary for non-C calling 1498 // conventions. The frontend should mark functions whose return values 1499 // require promoting with signext or zeroext attributes. 1500 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) { 1501 MVT MinVT = TLI.getRegisterType(ReturnType->getContext(), MVT::i32); 1502 if (VT.bitsLT(MinVT)) 1503 VT = MinVT; 1504 } 1505 1506 unsigned NumParts = TLI.getNumRegisters(ReturnType->getContext(), VT); 1507 MVT PartVT = TLI.getRegisterType(ReturnType->getContext(), VT); 1508 1509 // 'inreg' on function refers to return value 1510 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy(); 1511 if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::InReg)) 1512 Flags.setInReg(); 1513 1514 // Propagate extension type if any 1515 if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::SExt)) 1516 Flags.setSExt(); 1517 else if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::ZExt)) 1518 Flags.setZExt(); 1519 1520 for (unsigned i = 0; i < NumParts; ++i) 1521 Outs.push_back(ISD::OutputArg(Flags, PartVT, VT, /*isFixed=*/true, 0, 0)); 1522 } 1523 } 1524 1525 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 1526 /// function arguments in the caller parameter area. This is the actual 1527 /// alignment, not its logarithm. 1528 unsigned TargetLoweringBase::getByValTypeAlignment(Type *Ty, 1529 const DataLayout &DL) const { 1530 return DL.getABITypeAlignment(Ty); 1531 } 1532 1533 bool TargetLoweringBase::allowsMemoryAccess(LLVMContext &Context, 1534 const DataLayout &DL, EVT VT, 1535 unsigned AddrSpace, 1536 unsigned Alignment, 1537 bool *Fast) const { 1538 // Check if the specified alignment is sufficient based on the data layout. 1539 // TODO: While using the data layout works in practice, a better solution 1540 // would be to implement this check directly (make this a virtual function). 1541 // For example, the ABI alignment may change based on software platform while 1542 // this function should only be affected by hardware implementation. 1543 Type *Ty = VT.getTypeForEVT(Context); 1544 if (Alignment >= DL.getABITypeAlignment(Ty)) { 1545 // Assume that an access that meets the ABI-specified alignment is fast. 1546 if (Fast != nullptr) 1547 *Fast = true; 1548 return true; 1549 } 1550 1551 // This is a misaligned access. 1552 return allowsMisalignedMemoryAccesses(VT, AddrSpace, Alignment, Fast); 1553 } 1554 1555 1556 //===----------------------------------------------------------------------===// 1557 // TargetTransformInfo Helpers 1558 //===----------------------------------------------------------------------===// 1559 1560 int TargetLoweringBase::InstructionOpcodeToISD(unsigned Opcode) const { 1561 enum InstructionOpcodes { 1562 #define HANDLE_INST(NUM, OPCODE, CLASS) OPCODE = NUM, 1563 #define LAST_OTHER_INST(NUM) InstructionOpcodesCount = NUM 1564 #include "llvm/IR/Instruction.def" 1565 }; 1566 switch (static_cast<InstructionOpcodes>(Opcode)) { 1567 case Ret: return 0; 1568 case Br: return 0; 1569 case Switch: return 0; 1570 case IndirectBr: return 0; 1571 case Invoke: return 0; 1572 case Resume: return 0; 1573 case Unreachable: return 0; 1574 case CleanupEndPad: return 0; 1575 case CleanupRet: return 0; 1576 case CatchEndPad: return 0; 1577 case CatchRet: return 0; 1578 case CatchPad: return 0; 1579 case TerminatePad: return 0; 1580 case CleanupPad: return 0; 1581 case Add: return ISD::ADD; 1582 case FAdd: return ISD::FADD; 1583 case Sub: return ISD::SUB; 1584 case FSub: return ISD::FSUB; 1585 case Mul: return ISD::MUL; 1586 case FMul: return ISD::FMUL; 1587 case UDiv: return ISD::UDIV; 1588 case SDiv: return ISD::SDIV; 1589 case FDiv: return ISD::FDIV; 1590 case URem: return ISD::UREM; 1591 case SRem: return ISD::SREM; 1592 case FRem: return ISD::FREM; 1593 case Shl: return ISD::SHL; 1594 case LShr: return ISD::SRL; 1595 case AShr: return ISD::SRA; 1596 case And: return ISD::AND; 1597 case Or: return ISD::OR; 1598 case Xor: return ISD::XOR; 1599 case Alloca: return 0; 1600 case Load: return ISD::LOAD; 1601 case Store: return ISD::STORE; 1602 case GetElementPtr: return 0; 1603 case Fence: return 0; 1604 case AtomicCmpXchg: return 0; 1605 case AtomicRMW: return 0; 1606 case Trunc: return ISD::TRUNCATE; 1607 case ZExt: return ISD::ZERO_EXTEND; 1608 case SExt: return ISD::SIGN_EXTEND; 1609 case FPToUI: return ISD::FP_TO_UINT; 1610 case FPToSI: return ISD::FP_TO_SINT; 1611 case UIToFP: return ISD::UINT_TO_FP; 1612 case SIToFP: return ISD::SINT_TO_FP; 1613 case FPTrunc: return ISD::FP_ROUND; 1614 case FPExt: return ISD::FP_EXTEND; 1615 case PtrToInt: return ISD::BITCAST; 1616 case IntToPtr: return ISD::BITCAST; 1617 case BitCast: return ISD::BITCAST; 1618 case AddrSpaceCast: return ISD::ADDRSPACECAST; 1619 case ICmp: return ISD::SETCC; 1620 case FCmp: return ISD::SETCC; 1621 case PHI: return 0; 1622 case Call: return 0; 1623 case Select: return ISD::SELECT; 1624 case UserOp1: return 0; 1625 case UserOp2: return 0; 1626 case VAArg: return 0; 1627 case ExtractElement: return ISD::EXTRACT_VECTOR_ELT; 1628 case InsertElement: return ISD::INSERT_VECTOR_ELT; 1629 case ShuffleVector: return ISD::VECTOR_SHUFFLE; 1630 case ExtractValue: return ISD::MERGE_VALUES; 1631 case InsertValue: return ISD::MERGE_VALUES; 1632 case LandingPad: return 0; 1633 } 1634 1635 llvm_unreachable("Unknown instruction type encountered!"); 1636 } 1637 1638 std::pair<int, MVT> 1639 TargetLoweringBase::getTypeLegalizationCost(const DataLayout &DL, 1640 Type *Ty) const { 1641 LLVMContext &C = Ty->getContext(); 1642 EVT MTy = getValueType(DL, Ty); 1643 1644 int Cost = 1; 1645 // We keep legalizing the type until we find a legal kind. We assume that 1646 // the only operation that costs anything is the split. After splitting 1647 // we need to handle two types. 1648 while (true) { 1649 LegalizeKind LK = getTypeConversion(C, MTy); 1650 1651 if (LK.first == TypeLegal) 1652 return std::make_pair(Cost, MTy.getSimpleVT()); 1653 1654 if (LK.first == TypeSplitVector || LK.first == TypeExpandInteger) 1655 Cost *= 2; 1656 1657 // Do not loop with f128 type. 1658 if (MTy == LK.second) 1659 return std::make_pair(Cost, MTy.getSimpleVT()); 1660 1661 // Keep legalizing the type. 1662 MTy = LK.second; 1663 } 1664 } 1665 1666 Value *TargetLoweringBase::getSafeStackPointerLocation(IRBuilder<> &IRB) const { 1667 if (!TM.getTargetTriple().isAndroid()) 1668 return nullptr; 1669 1670 // Android provides a libc function to retrieve the address of the current 1671 // thread's unsafe stack pointer. 1672 Module *M = IRB.GetInsertBlock()->getParent()->getParent(); 1673 Type *StackPtrTy = Type::getInt8PtrTy(M->getContext()); 1674 Value *Fn = M->getOrInsertFunction("__safestack_pointer_address", 1675 StackPtrTy->getPointerTo(0), nullptr); 1676 return IRB.CreateCall(Fn); 1677 } 1678 1679 //===----------------------------------------------------------------------===// 1680 // Loop Strength Reduction hooks 1681 //===----------------------------------------------------------------------===// 1682 1683 /// isLegalAddressingMode - Return true if the addressing mode represented 1684 /// by AM is legal for this target, for a load/store of the specified type. 1685 bool TargetLoweringBase::isLegalAddressingMode(const DataLayout &DL, 1686 const AddrMode &AM, Type *Ty, 1687 unsigned AS) const { 1688 // The default implementation of this implements a conservative RISCy, r+r and 1689 // r+i addr mode. 1690 1691 // Allows a sign-extended 16-bit immediate field. 1692 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1) 1693 return false; 1694 1695 // No global is ever allowed as a base. 1696 if (AM.BaseGV) 1697 return false; 1698 1699 // Only support r+r, 1700 switch (AM.Scale) { 1701 case 0: // "r+i" or just "i", depending on HasBaseReg. 1702 break; 1703 case 1: 1704 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. 1705 return false; 1706 // Otherwise we have r+r or r+i. 1707 break; 1708 case 2: 1709 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. 1710 return false; 1711 // Allow 2*r as r+r. 1712 break; 1713 default: // Don't allow n * r 1714 return false; 1715 } 1716 1717 return true; 1718 } 1719