1 //===- TargetLoweringBase.cpp - Implement the TargetLoweringBase class ----===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This implements the TargetLoweringBase class. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "llvm/ADT/BitVector.h" 14 #include "llvm/ADT/STLExtras.h" 15 #include "llvm/ADT/SmallVector.h" 16 #include "llvm/ADT/StringExtras.h" 17 #include "llvm/ADT/StringRef.h" 18 #include "llvm/ADT/Triple.h" 19 #include "llvm/ADT/Twine.h" 20 #include "llvm/Analysis/Loads.h" 21 #include "llvm/Analysis/TargetTransformInfo.h" 22 #include "llvm/CodeGen/Analysis.h" 23 #include "llvm/CodeGen/ISDOpcodes.h" 24 #include "llvm/CodeGen/MachineBasicBlock.h" 25 #include "llvm/CodeGen/MachineFrameInfo.h" 26 #include "llvm/CodeGen/MachineFunction.h" 27 #include "llvm/CodeGen/MachineInstr.h" 28 #include "llvm/CodeGen/MachineInstrBuilder.h" 29 #include "llvm/CodeGen/MachineMemOperand.h" 30 #include "llvm/CodeGen/MachineOperand.h" 31 #include "llvm/CodeGen/MachineRegisterInfo.h" 32 #include "llvm/CodeGen/RuntimeLibcalls.h" 33 #include "llvm/CodeGen/StackMaps.h" 34 #include "llvm/CodeGen/TargetLowering.h" 35 #include "llvm/CodeGen/TargetOpcodes.h" 36 #include "llvm/CodeGen/TargetRegisterInfo.h" 37 #include "llvm/CodeGen/ValueTypes.h" 38 #include "llvm/IR/Attributes.h" 39 #include "llvm/IR/CallingConv.h" 40 #include "llvm/IR/DataLayout.h" 41 #include "llvm/IR/DerivedTypes.h" 42 #include "llvm/IR/Function.h" 43 #include "llvm/IR/GlobalValue.h" 44 #include "llvm/IR/GlobalVariable.h" 45 #include "llvm/IR/IRBuilder.h" 46 #include "llvm/IR/Module.h" 47 #include "llvm/IR/Type.h" 48 #include "llvm/Support/BranchProbability.h" 49 #include "llvm/Support/Casting.h" 50 #include "llvm/Support/CommandLine.h" 51 #include "llvm/Support/Compiler.h" 52 #include "llvm/Support/ErrorHandling.h" 53 #include "llvm/Support/MachineValueType.h" 54 #include "llvm/Support/MathExtras.h" 55 #include "llvm/Target/TargetMachine.h" 56 #include "llvm/Transforms/Utils/SizeOpts.h" 57 #include <algorithm> 58 #include <cassert> 59 #include <cstddef> 60 #include <cstdint> 61 #include <cstring> 62 #include <iterator> 63 #include <string> 64 #include <tuple> 65 #include <utility> 66 67 using namespace llvm; 68 69 static cl::opt<bool> JumpIsExpensiveOverride( 70 "jump-is-expensive", cl::init(false), 71 cl::desc("Do not create extra branches to split comparison logic."), 72 cl::Hidden); 73 74 static cl::opt<unsigned> MinimumJumpTableEntries 75 ("min-jump-table-entries", cl::init(4), cl::Hidden, 76 cl::desc("Set minimum number of entries to use a jump table.")); 77 78 static cl::opt<unsigned> MaximumJumpTableSize 79 ("max-jump-table-size", cl::init(UINT_MAX), cl::Hidden, 80 cl::desc("Set maximum size of jump tables.")); 81 82 /// Minimum jump table density for normal functions. 83 static cl::opt<unsigned> 84 JumpTableDensity("jump-table-density", cl::init(10), cl::Hidden, 85 cl::desc("Minimum density for building a jump table in " 86 "a normal function")); 87 88 /// Minimum jump table density for -Os or -Oz functions. 89 static cl::opt<unsigned> OptsizeJumpTableDensity( 90 "optsize-jump-table-density", cl::init(40), cl::Hidden, 91 cl::desc("Minimum density for building a jump table in " 92 "an optsize function")); 93 94 // FIXME: This option is only to test if the strict fp operation processed 95 // correctly by preventing mutating strict fp operation to normal fp operation 96 // during development. When the backend supports strict float operation, this 97 // option will be meaningless. 98 static cl::opt<bool> DisableStrictNodeMutation("disable-strictnode-mutation", 99 cl::desc("Don't mutate strict-float node to a legalize node"), 100 cl::init(false), cl::Hidden); 101 102 static bool darwinHasSinCos(const Triple &TT) { 103 assert(TT.isOSDarwin() && "should be called with darwin triple"); 104 // Don't bother with 32 bit x86. 105 if (TT.getArch() == Triple::x86) 106 return false; 107 // Macos < 10.9 has no sincos_stret. 108 if (TT.isMacOSX()) 109 return !TT.isMacOSXVersionLT(10, 9) && TT.isArch64Bit(); 110 // iOS < 7.0 has no sincos_stret. 111 if (TT.isiOS()) 112 return !TT.isOSVersionLT(7, 0); 113 // Any other darwin such as WatchOS/TvOS is new enough. 114 return true; 115 } 116 117 // Although this default value is arbitrary, it is not random. It is assumed 118 // that a condition that evaluates the same way by a higher percentage than this 119 // is best represented as control flow. Therefore, the default value N should be 120 // set such that the win from N% correct executions is greater than the loss 121 // from (100 - N)% mispredicted executions for the majority of intended targets. 122 static cl::opt<int> MinPercentageForPredictableBranch( 123 "min-predictable-branch", cl::init(99), 124 cl::desc("Minimum percentage (0-100) that a condition must be either true " 125 "or false to assume that the condition is predictable"), 126 cl::Hidden); 127 128 void TargetLoweringBase::InitLibcalls(const Triple &TT) { 129 #define HANDLE_LIBCALL(code, name) \ 130 setLibcallName(RTLIB::code, name); 131 #include "llvm/IR/RuntimeLibcalls.def" 132 #undef HANDLE_LIBCALL 133 // Initialize calling conventions to their default. 134 for (int LC = 0; LC < RTLIB::UNKNOWN_LIBCALL; ++LC) 135 setLibcallCallingConv((RTLIB::Libcall)LC, CallingConv::C); 136 137 // For IEEE quad-precision libcall names, PPC uses "kf" instead of "tf". 138 if (TT.getArch() == Triple::ppc || TT.isPPC64()) { 139 setLibcallName(RTLIB::ADD_F128, "__addkf3"); 140 setLibcallName(RTLIB::SUB_F128, "__subkf3"); 141 setLibcallName(RTLIB::MUL_F128, "__mulkf3"); 142 setLibcallName(RTLIB::DIV_F128, "__divkf3"); 143 setLibcallName(RTLIB::FPEXT_F32_F128, "__extendsfkf2"); 144 setLibcallName(RTLIB::FPEXT_F64_F128, "__extenddfkf2"); 145 setLibcallName(RTLIB::FPROUND_F128_F32, "__trunckfsf2"); 146 setLibcallName(RTLIB::FPROUND_F128_F64, "__trunckfdf2"); 147 setLibcallName(RTLIB::FPTOSINT_F128_I32, "__fixkfsi"); 148 setLibcallName(RTLIB::FPTOSINT_F128_I64, "__fixkfdi"); 149 setLibcallName(RTLIB::FPTOUINT_F128_I32, "__fixunskfsi"); 150 setLibcallName(RTLIB::FPTOUINT_F128_I64, "__fixunskfdi"); 151 setLibcallName(RTLIB::SINTTOFP_I32_F128, "__floatsikf"); 152 setLibcallName(RTLIB::SINTTOFP_I64_F128, "__floatdikf"); 153 setLibcallName(RTLIB::UINTTOFP_I32_F128, "__floatunsikf"); 154 setLibcallName(RTLIB::UINTTOFP_I64_F128, "__floatundikf"); 155 setLibcallName(RTLIB::OEQ_F128, "__eqkf2"); 156 setLibcallName(RTLIB::UNE_F128, "__nekf2"); 157 setLibcallName(RTLIB::OGE_F128, "__gekf2"); 158 setLibcallName(RTLIB::OLT_F128, "__ltkf2"); 159 setLibcallName(RTLIB::OLE_F128, "__lekf2"); 160 setLibcallName(RTLIB::OGT_F128, "__gtkf2"); 161 setLibcallName(RTLIB::UO_F128, "__unordkf2"); 162 } 163 164 // A few names are different on particular architectures or environments. 165 if (TT.isOSDarwin()) { 166 // For f16/f32 conversions, Darwin uses the standard naming scheme, instead 167 // of the gnueabi-style __gnu_*_ieee. 168 // FIXME: What about other targets? 169 setLibcallName(RTLIB::FPEXT_F16_F32, "__extendhfsf2"); 170 setLibcallName(RTLIB::FPROUND_F32_F16, "__truncsfhf2"); 171 172 // Some darwins have an optimized __bzero/bzero function. 173 switch (TT.getArch()) { 174 case Triple::x86: 175 case Triple::x86_64: 176 if (TT.isMacOSX() && !TT.isMacOSXVersionLT(10, 6)) 177 setLibcallName(RTLIB::BZERO, "__bzero"); 178 break; 179 case Triple::aarch64: 180 case Triple::aarch64_32: 181 setLibcallName(RTLIB::BZERO, "bzero"); 182 break; 183 default: 184 break; 185 } 186 187 if (darwinHasSinCos(TT)) { 188 setLibcallName(RTLIB::SINCOS_STRET_F32, "__sincosf_stret"); 189 setLibcallName(RTLIB::SINCOS_STRET_F64, "__sincos_stret"); 190 if (TT.isWatchABI()) { 191 setLibcallCallingConv(RTLIB::SINCOS_STRET_F32, 192 CallingConv::ARM_AAPCS_VFP); 193 setLibcallCallingConv(RTLIB::SINCOS_STRET_F64, 194 CallingConv::ARM_AAPCS_VFP); 195 } 196 } 197 } else { 198 setLibcallName(RTLIB::FPEXT_F16_F32, "__gnu_h2f_ieee"); 199 setLibcallName(RTLIB::FPROUND_F32_F16, "__gnu_f2h_ieee"); 200 } 201 202 if (TT.isGNUEnvironment() || TT.isOSFuchsia() || 203 (TT.isAndroid() && !TT.isAndroidVersionLT(9))) { 204 setLibcallName(RTLIB::SINCOS_F32, "sincosf"); 205 setLibcallName(RTLIB::SINCOS_F64, "sincos"); 206 setLibcallName(RTLIB::SINCOS_F80, "sincosl"); 207 setLibcallName(RTLIB::SINCOS_F128, "sincosl"); 208 setLibcallName(RTLIB::SINCOS_PPCF128, "sincosl"); 209 } 210 211 if (TT.isPS4CPU()) { 212 setLibcallName(RTLIB::SINCOS_F32, "sincosf"); 213 setLibcallName(RTLIB::SINCOS_F64, "sincos"); 214 } 215 216 if (TT.isOSOpenBSD()) { 217 setLibcallName(RTLIB::STACKPROTECTOR_CHECK_FAIL, nullptr); 218 } 219 } 220 221 /// getFPEXT - Return the FPEXT_*_* value for the given types, or 222 /// UNKNOWN_LIBCALL if there is none. 223 RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) { 224 if (OpVT == MVT::f16) { 225 if (RetVT == MVT::f32) 226 return FPEXT_F16_F32; 227 } else if (OpVT == MVT::f32) { 228 if (RetVT == MVT::f64) 229 return FPEXT_F32_F64; 230 if (RetVT == MVT::f128) 231 return FPEXT_F32_F128; 232 if (RetVT == MVT::ppcf128) 233 return FPEXT_F32_PPCF128; 234 } else if (OpVT == MVT::f64) { 235 if (RetVT == MVT::f128) 236 return FPEXT_F64_F128; 237 else if (RetVT == MVT::ppcf128) 238 return FPEXT_F64_PPCF128; 239 } else if (OpVT == MVT::f80) { 240 if (RetVT == MVT::f128) 241 return FPEXT_F80_F128; 242 } 243 244 return UNKNOWN_LIBCALL; 245 } 246 247 /// getFPROUND - Return the FPROUND_*_* value for the given types, or 248 /// UNKNOWN_LIBCALL if there is none. 249 RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) { 250 if (RetVT == MVT::f16) { 251 if (OpVT == MVT::f32) 252 return FPROUND_F32_F16; 253 if (OpVT == MVT::f64) 254 return FPROUND_F64_F16; 255 if (OpVT == MVT::f80) 256 return FPROUND_F80_F16; 257 if (OpVT == MVT::f128) 258 return FPROUND_F128_F16; 259 if (OpVT == MVT::ppcf128) 260 return FPROUND_PPCF128_F16; 261 } else if (RetVT == MVT::f32) { 262 if (OpVT == MVT::f64) 263 return FPROUND_F64_F32; 264 if (OpVT == MVT::f80) 265 return FPROUND_F80_F32; 266 if (OpVT == MVT::f128) 267 return FPROUND_F128_F32; 268 if (OpVT == MVT::ppcf128) 269 return FPROUND_PPCF128_F32; 270 } else if (RetVT == MVT::f64) { 271 if (OpVT == MVT::f80) 272 return FPROUND_F80_F64; 273 if (OpVT == MVT::f128) 274 return FPROUND_F128_F64; 275 if (OpVT == MVT::ppcf128) 276 return FPROUND_PPCF128_F64; 277 } else if (RetVT == MVT::f80) { 278 if (OpVT == MVT::f128) 279 return FPROUND_F128_F80; 280 } 281 282 return UNKNOWN_LIBCALL; 283 } 284 285 /// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or 286 /// UNKNOWN_LIBCALL if there is none. 287 RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT, EVT RetVT) { 288 if (OpVT == MVT::f32) { 289 if (RetVT == MVT::i32) 290 return FPTOSINT_F32_I32; 291 if (RetVT == MVT::i64) 292 return FPTOSINT_F32_I64; 293 if (RetVT == MVT::i128) 294 return FPTOSINT_F32_I128; 295 } else if (OpVT == MVT::f64) { 296 if (RetVT == MVT::i32) 297 return FPTOSINT_F64_I32; 298 if (RetVT == MVT::i64) 299 return FPTOSINT_F64_I64; 300 if (RetVT == MVT::i128) 301 return FPTOSINT_F64_I128; 302 } else if (OpVT == MVT::f80) { 303 if (RetVT == MVT::i32) 304 return FPTOSINT_F80_I32; 305 if (RetVT == MVT::i64) 306 return FPTOSINT_F80_I64; 307 if (RetVT == MVT::i128) 308 return FPTOSINT_F80_I128; 309 } else if (OpVT == MVT::f128) { 310 if (RetVT == MVT::i32) 311 return FPTOSINT_F128_I32; 312 if (RetVT == MVT::i64) 313 return FPTOSINT_F128_I64; 314 if (RetVT == MVT::i128) 315 return FPTOSINT_F128_I128; 316 } else if (OpVT == MVT::ppcf128) { 317 if (RetVT == MVT::i32) 318 return FPTOSINT_PPCF128_I32; 319 if (RetVT == MVT::i64) 320 return FPTOSINT_PPCF128_I64; 321 if (RetVT == MVT::i128) 322 return FPTOSINT_PPCF128_I128; 323 } 324 return UNKNOWN_LIBCALL; 325 } 326 327 /// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or 328 /// UNKNOWN_LIBCALL if there is none. 329 RTLIB::Libcall RTLIB::getFPTOUINT(EVT OpVT, EVT RetVT) { 330 if (OpVT == MVT::f32) { 331 if (RetVT == MVT::i32) 332 return FPTOUINT_F32_I32; 333 if (RetVT == MVT::i64) 334 return FPTOUINT_F32_I64; 335 if (RetVT == MVT::i128) 336 return FPTOUINT_F32_I128; 337 } else if (OpVT == MVT::f64) { 338 if (RetVT == MVT::i32) 339 return FPTOUINT_F64_I32; 340 if (RetVT == MVT::i64) 341 return FPTOUINT_F64_I64; 342 if (RetVT == MVT::i128) 343 return FPTOUINT_F64_I128; 344 } else if (OpVT == MVT::f80) { 345 if (RetVT == MVT::i32) 346 return FPTOUINT_F80_I32; 347 if (RetVT == MVT::i64) 348 return FPTOUINT_F80_I64; 349 if (RetVT == MVT::i128) 350 return FPTOUINT_F80_I128; 351 } else if (OpVT == MVT::f128) { 352 if (RetVT == MVT::i32) 353 return FPTOUINT_F128_I32; 354 if (RetVT == MVT::i64) 355 return FPTOUINT_F128_I64; 356 if (RetVT == MVT::i128) 357 return FPTOUINT_F128_I128; 358 } else if (OpVT == MVT::ppcf128) { 359 if (RetVT == MVT::i32) 360 return FPTOUINT_PPCF128_I32; 361 if (RetVT == MVT::i64) 362 return FPTOUINT_PPCF128_I64; 363 if (RetVT == MVT::i128) 364 return FPTOUINT_PPCF128_I128; 365 } 366 return UNKNOWN_LIBCALL; 367 } 368 369 /// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or 370 /// UNKNOWN_LIBCALL if there is none. 371 RTLIB::Libcall RTLIB::getSINTTOFP(EVT OpVT, EVT RetVT) { 372 if (OpVT == MVT::i32) { 373 if (RetVT == MVT::f32) 374 return SINTTOFP_I32_F32; 375 if (RetVT == MVT::f64) 376 return SINTTOFP_I32_F64; 377 if (RetVT == MVT::f80) 378 return SINTTOFP_I32_F80; 379 if (RetVT == MVT::f128) 380 return SINTTOFP_I32_F128; 381 if (RetVT == MVT::ppcf128) 382 return SINTTOFP_I32_PPCF128; 383 } else if (OpVT == MVT::i64) { 384 if (RetVT == MVT::f32) 385 return SINTTOFP_I64_F32; 386 if (RetVT == MVT::f64) 387 return SINTTOFP_I64_F64; 388 if (RetVT == MVT::f80) 389 return SINTTOFP_I64_F80; 390 if (RetVT == MVT::f128) 391 return SINTTOFP_I64_F128; 392 if (RetVT == MVT::ppcf128) 393 return SINTTOFP_I64_PPCF128; 394 } else if (OpVT == MVT::i128) { 395 if (RetVT == MVT::f32) 396 return SINTTOFP_I128_F32; 397 if (RetVT == MVT::f64) 398 return SINTTOFP_I128_F64; 399 if (RetVT == MVT::f80) 400 return SINTTOFP_I128_F80; 401 if (RetVT == MVT::f128) 402 return SINTTOFP_I128_F128; 403 if (RetVT == MVT::ppcf128) 404 return SINTTOFP_I128_PPCF128; 405 } 406 return UNKNOWN_LIBCALL; 407 } 408 409 /// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or 410 /// UNKNOWN_LIBCALL if there is none. 411 RTLIB::Libcall RTLIB::getUINTTOFP(EVT OpVT, EVT RetVT) { 412 if (OpVT == MVT::i32) { 413 if (RetVT == MVT::f32) 414 return UINTTOFP_I32_F32; 415 if (RetVT == MVT::f64) 416 return UINTTOFP_I32_F64; 417 if (RetVT == MVT::f80) 418 return UINTTOFP_I32_F80; 419 if (RetVT == MVT::f128) 420 return UINTTOFP_I32_F128; 421 if (RetVT == MVT::ppcf128) 422 return UINTTOFP_I32_PPCF128; 423 } else if (OpVT == MVT::i64) { 424 if (RetVT == MVT::f32) 425 return UINTTOFP_I64_F32; 426 if (RetVT == MVT::f64) 427 return UINTTOFP_I64_F64; 428 if (RetVT == MVT::f80) 429 return UINTTOFP_I64_F80; 430 if (RetVT == MVT::f128) 431 return UINTTOFP_I64_F128; 432 if (RetVT == MVT::ppcf128) 433 return UINTTOFP_I64_PPCF128; 434 } else if (OpVT == MVT::i128) { 435 if (RetVT == MVT::f32) 436 return UINTTOFP_I128_F32; 437 if (RetVT == MVT::f64) 438 return UINTTOFP_I128_F64; 439 if (RetVT == MVT::f80) 440 return UINTTOFP_I128_F80; 441 if (RetVT == MVT::f128) 442 return UINTTOFP_I128_F128; 443 if (RetVT == MVT::ppcf128) 444 return UINTTOFP_I128_PPCF128; 445 } 446 return UNKNOWN_LIBCALL; 447 } 448 449 RTLIB::Libcall RTLIB::getSYNC(unsigned Opc, MVT VT) { 450 #define OP_TO_LIBCALL(Name, Enum) \ 451 case Name: \ 452 switch (VT.SimpleTy) { \ 453 default: \ 454 return UNKNOWN_LIBCALL; \ 455 case MVT::i8: \ 456 return Enum##_1; \ 457 case MVT::i16: \ 458 return Enum##_2; \ 459 case MVT::i32: \ 460 return Enum##_4; \ 461 case MVT::i64: \ 462 return Enum##_8; \ 463 case MVT::i128: \ 464 return Enum##_16; \ 465 } 466 467 switch (Opc) { 468 OP_TO_LIBCALL(ISD::ATOMIC_SWAP, SYNC_LOCK_TEST_AND_SET) 469 OP_TO_LIBCALL(ISD::ATOMIC_CMP_SWAP, SYNC_VAL_COMPARE_AND_SWAP) 470 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_ADD, SYNC_FETCH_AND_ADD) 471 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_SUB, SYNC_FETCH_AND_SUB) 472 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_AND, SYNC_FETCH_AND_AND) 473 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_OR, SYNC_FETCH_AND_OR) 474 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_XOR, SYNC_FETCH_AND_XOR) 475 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_NAND, SYNC_FETCH_AND_NAND) 476 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_MAX, SYNC_FETCH_AND_MAX) 477 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_UMAX, SYNC_FETCH_AND_UMAX) 478 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_MIN, SYNC_FETCH_AND_MIN) 479 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_UMIN, SYNC_FETCH_AND_UMIN) 480 } 481 482 #undef OP_TO_LIBCALL 483 484 return UNKNOWN_LIBCALL; 485 } 486 487 RTLIB::Libcall RTLIB::getMEMCPY_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize) { 488 switch (ElementSize) { 489 case 1: 490 return MEMCPY_ELEMENT_UNORDERED_ATOMIC_1; 491 case 2: 492 return MEMCPY_ELEMENT_UNORDERED_ATOMIC_2; 493 case 4: 494 return MEMCPY_ELEMENT_UNORDERED_ATOMIC_4; 495 case 8: 496 return MEMCPY_ELEMENT_UNORDERED_ATOMIC_8; 497 case 16: 498 return MEMCPY_ELEMENT_UNORDERED_ATOMIC_16; 499 default: 500 return UNKNOWN_LIBCALL; 501 } 502 } 503 504 RTLIB::Libcall RTLIB::getMEMMOVE_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize) { 505 switch (ElementSize) { 506 case 1: 507 return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_1; 508 case 2: 509 return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_2; 510 case 4: 511 return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_4; 512 case 8: 513 return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_8; 514 case 16: 515 return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_16; 516 default: 517 return UNKNOWN_LIBCALL; 518 } 519 } 520 521 RTLIB::Libcall RTLIB::getMEMSET_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize) { 522 switch (ElementSize) { 523 case 1: 524 return MEMSET_ELEMENT_UNORDERED_ATOMIC_1; 525 case 2: 526 return MEMSET_ELEMENT_UNORDERED_ATOMIC_2; 527 case 4: 528 return MEMSET_ELEMENT_UNORDERED_ATOMIC_4; 529 case 8: 530 return MEMSET_ELEMENT_UNORDERED_ATOMIC_8; 531 case 16: 532 return MEMSET_ELEMENT_UNORDERED_ATOMIC_16; 533 default: 534 return UNKNOWN_LIBCALL; 535 } 536 } 537 538 /// InitCmpLibcallCCs - Set default comparison libcall CC. 539 static void InitCmpLibcallCCs(ISD::CondCode *CCs) { 540 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL); 541 CCs[RTLIB::OEQ_F32] = ISD::SETEQ; 542 CCs[RTLIB::OEQ_F64] = ISD::SETEQ; 543 CCs[RTLIB::OEQ_F128] = ISD::SETEQ; 544 CCs[RTLIB::OEQ_PPCF128] = ISD::SETEQ; 545 CCs[RTLIB::UNE_F32] = ISD::SETNE; 546 CCs[RTLIB::UNE_F64] = ISD::SETNE; 547 CCs[RTLIB::UNE_F128] = ISD::SETNE; 548 CCs[RTLIB::UNE_PPCF128] = ISD::SETNE; 549 CCs[RTLIB::OGE_F32] = ISD::SETGE; 550 CCs[RTLIB::OGE_F64] = ISD::SETGE; 551 CCs[RTLIB::OGE_F128] = ISD::SETGE; 552 CCs[RTLIB::OGE_PPCF128] = ISD::SETGE; 553 CCs[RTLIB::OLT_F32] = ISD::SETLT; 554 CCs[RTLIB::OLT_F64] = ISD::SETLT; 555 CCs[RTLIB::OLT_F128] = ISD::SETLT; 556 CCs[RTLIB::OLT_PPCF128] = ISD::SETLT; 557 CCs[RTLIB::OLE_F32] = ISD::SETLE; 558 CCs[RTLIB::OLE_F64] = ISD::SETLE; 559 CCs[RTLIB::OLE_F128] = ISD::SETLE; 560 CCs[RTLIB::OLE_PPCF128] = ISD::SETLE; 561 CCs[RTLIB::OGT_F32] = ISD::SETGT; 562 CCs[RTLIB::OGT_F64] = ISD::SETGT; 563 CCs[RTLIB::OGT_F128] = ISD::SETGT; 564 CCs[RTLIB::OGT_PPCF128] = ISD::SETGT; 565 CCs[RTLIB::UO_F32] = ISD::SETNE; 566 CCs[RTLIB::UO_F64] = ISD::SETNE; 567 CCs[RTLIB::UO_F128] = ISD::SETNE; 568 CCs[RTLIB::UO_PPCF128] = ISD::SETNE; 569 } 570 571 /// NOTE: The TargetMachine owns TLOF. 572 TargetLoweringBase::TargetLoweringBase(const TargetMachine &tm) : TM(tm) { 573 initActions(); 574 575 // Perform these initializations only once. 576 MaxStoresPerMemset = MaxStoresPerMemcpy = MaxStoresPerMemmove = 577 MaxLoadsPerMemcmp = 8; 578 MaxGluedStoresPerMemcpy = 0; 579 MaxStoresPerMemsetOptSize = MaxStoresPerMemcpyOptSize = 580 MaxStoresPerMemmoveOptSize = MaxLoadsPerMemcmpOptSize = 4; 581 HasMultipleConditionRegisters = false; 582 HasExtractBitsInsn = false; 583 JumpIsExpensive = JumpIsExpensiveOverride; 584 PredictableSelectIsExpensive = false; 585 EnableExtLdPromotion = false; 586 StackPointerRegisterToSaveRestore = 0; 587 BooleanContents = UndefinedBooleanContent; 588 BooleanFloatContents = UndefinedBooleanContent; 589 BooleanVectorContents = UndefinedBooleanContent; 590 SchedPreferenceInfo = Sched::ILP; 591 GatherAllAliasesMaxDepth = 18; 592 IsStrictFPEnabled = DisableStrictNodeMutation; 593 // TODO: the default will be switched to 0 in the next commit, along 594 // with the Target-specific changes necessary. 595 MaxAtomicSizeInBitsSupported = 1024; 596 597 MinCmpXchgSizeInBits = 0; 598 SupportsUnalignedAtomics = false; 599 600 std::fill(std::begin(LibcallRoutineNames), std::end(LibcallRoutineNames), nullptr); 601 602 InitLibcalls(TM.getTargetTriple()); 603 InitCmpLibcallCCs(CmpLibcallCCs); 604 } 605 606 void TargetLoweringBase::initActions() { 607 // All operations default to being supported. 608 memset(OpActions, 0, sizeof(OpActions)); 609 memset(LoadExtActions, 0, sizeof(LoadExtActions)); 610 memset(TruncStoreActions, 0, sizeof(TruncStoreActions)); 611 memset(IndexedModeActions, 0, sizeof(IndexedModeActions)); 612 memset(CondCodeActions, 0, sizeof(CondCodeActions)); 613 std::fill(std::begin(RegClassForVT), std::end(RegClassForVT), nullptr); 614 std::fill(std::begin(TargetDAGCombineArray), 615 std::end(TargetDAGCombineArray), 0); 616 617 for (MVT VT : MVT::fp_valuetypes()) { 618 MVT IntVT = MVT::getIntegerVT(VT.getSizeInBits().getFixedSize()); 619 if (IntVT.isValid()) { 620 setOperationAction(ISD::ATOMIC_SWAP, VT, Promote); 621 AddPromotedToType(ISD::ATOMIC_SWAP, VT, IntVT); 622 } 623 } 624 625 // Set default actions for various operations. 626 for (MVT VT : MVT::all_valuetypes()) { 627 // Default all indexed load / store to expand. 628 for (unsigned IM = (unsigned)ISD::PRE_INC; 629 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) { 630 setIndexedLoadAction(IM, VT, Expand); 631 setIndexedStoreAction(IM, VT, Expand); 632 setIndexedMaskedLoadAction(IM, VT, Expand); 633 setIndexedMaskedStoreAction(IM, VT, Expand); 634 } 635 636 // Most backends expect to see the node which just returns the value loaded. 637 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Expand); 638 639 // These operations default to expand. 640 setOperationAction(ISD::FGETSIGN, VT, Expand); 641 setOperationAction(ISD::CONCAT_VECTORS, VT, Expand); 642 setOperationAction(ISD::FMINNUM, VT, Expand); 643 setOperationAction(ISD::FMAXNUM, VT, Expand); 644 setOperationAction(ISD::FMINNUM_IEEE, VT, Expand); 645 setOperationAction(ISD::FMAXNUM_IEEE, VT, Expand); 646 setOperationAction(ISD::FMINIMUM, VT, Expand); 647 setOperationAction(ISD::FMAXIMUM, VT, Expand); 648 setOperationAction(ISD::FMAD, VT, Expand); 649 setOperationAction(ISD::SMIN, VT, Expand); 650 setOperationAction(ISD::SMAX, VT, Expand); 651 setOperationAction(ISD::UMIN, VT, Expand); 652 setOperationAction(ISD::UMAX, VT, Expand); 653 setOperationAction(ISD::ABS, VT, Expand); 654 setOperationAction(ISD::FSHL, VT, Expand); 655 setOperationAction(ISD::FSHR, VT, Expand); 656 setOperationAction(ISD::SADDSAT, VT, Expand); 657 setOperationAction(ISD::UADDSAT, VT, Expand); 658 setOperationAction(ISD::SSUBSAT, VT, Expand); 659 setOperationAction(ISD::USUBSAT, VT, Expand); 660 setOperationAction(ISD::SMULFIX, VT, Expand); 661 setOperationAction(ISD::SMULFIXSAT, VT, Expand); 662 setOperationAction(ISD::UMULFIX, VT, Expand); 663 setOperationAction(ISD::UMULFIXSAT, VT, Expand); 664 setOperationAction(ISD::SDIVFIX, VT, Expand); 665 setOperationAction(ISD::SDIVFIXSAT, VT, Expand); 666 setOperationAction(ISD::UDIVFIX, VT, Expand); 667 setOperationAction(ISD::UDIVFIXSAT, VT, Expand); 668 669 // Overflow operations default to expand 670 setOperationAction(ISD::SADDO, VT, Expand); 671 setOperationAction(ISD::SSUBO, VT, Expand); 672 setOperationAction(ISD::UADDO, VT, Expand); 673 setOperationAction(ISD::USUBO, VT, Expand); 674 setOperationAction(ISD::SMULO, VT, Expand); 675 setOperationAction(ISD::UMULO, VT, Expand); 676 677 // ADDCARRY operations default to expand 678 setOperationAction(ISD::ADDCARRY, VT, Expand); 679 setOperationAction(ISD::SUBCARRY, VT, Expand); 680 setOperationAction(ISD::SETCCCARRY, VT, Expand); 681 682 // ADDC/ADDE/SUBC/SUBE default to expand. 683 setOperationAction(ISD::ADDC, VT, Expand); 684 setOperationAction(ISD::ADDE, VT, Expand); 685 setOperationAction(ISD::SUBC, VT, Expand); 686 setOperationAction(ISD::SUBE, VT, Expand); 687 688 // These default to Expand so they will be expanded to CTLZ/CTTZ by default. 689 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand); 690 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand); 691 692 setOperationAction(ISD::BITREVERSE, VT, Expand); 693 694 // These library functions default to expand. 695 setOperationAction(ISD::FROUND, VT, Expand); 696 setOperationAction(ISD::FROUNDEVEN, VT, Expand); 697 setOperationAction(ISD::FPOWI, VT, Expand); 698 699 // These operations default to expand for vector types. 700 if (VT.isVector()) { 701 setOperationAction(ISD::FCOPYSIGN, VT, Expand); 702 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand); 703 setOperationAction(ISD::ANY_EXTEND_VECTOR_INREG, VT, Expand); 704 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, VT, Expand); 705 setOperationAction(ISD::ZERO_EXTEND_VECTOR_INREG, VT, Expand); 706 setOperationAction(ISD::SPLAT_VECTOR, VT, Expand); 707 } 708 709 // Constrained floating-point operations default to expand. 710 #define DAG_INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC, DAGN) \ 711 setOperationAction(ISD::STRICT_##DAGN, VT, Expand); 712 #include "llvm/IR/ConstrainedOps.def" 713 714 // For most targets @llvm.get.dynamic.area.offset just returns 0. 715 setOperationAction(ISD::GET_DYNAMIC_AREA_OFFSET, VT, Expand); 716 717 // Vector reduction default to expand. 718 setOperationAction(ISD::VECREDUCE_FADD, VT, Expand); 719 setOperationAction(ISD::VECREDUCE_FMUL, VT, Expand); 720 setOperationAction(ISD::VECREDUCE_ADD, VT, Expand); 721 setOperationAction(ISD::VECREDUCE_MUL, VT, Expand); 722 setOperationAction(ISD::VECREDUCE_AND, VT, Expand); 723 setOperationAction(ISD::VECREDUCE_OR, VT, Expand); 724 setOperationAction(ISD::VECREDUCE_XOR, VT, Expand); 725 setOperationAction(ISD::VECREDUCE_SMAX, VT, Expand); 726 setOperationAction(ISD::VECREDUCE_SMIN, VT, Expand); 727 setOperationAction(ISD::VECREDUCE_UMAX, VT, Expand); 728 setOperationAction(ISD::VECREDUCE_UMIN, VT, Expand); 729 setOperationAction(ISD::VECREDUCE_FMAX, VT, Expand); 730 setOperationAction(ISD::VECREDUCE_FMIN, VT, Expand); 731 } 732 733 // Most targets ignore the @llvm.prefetch intrinsic. 734 setOperationAction(ISD::PREFETCH, MVT::Other, Expand); 735 736 // Most targets also ignore the @llvm.readcyclecounter intrinsic. 737 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Expand); 738 739 // ConstantFP nodes default to expand. Targets can either change this to 740 // Legal, in which case all fp constants are legal, or use isFPImmLegal() 741 // to optimize expansions for certain constants. 742 setOperationAction(ISD::ConstantFP, MVT::f16, Expand); 743 setOperationAction(ISD::ConstantFP, MVT::f32, Expand); 744 setOperationAction(ISD::ConstantFP, MVT::f64, Expand); 745 setOperationAction(ISD::ConstantFP, MVT::f80, Expand); 746 setOperationAction(ISD::ConstantFP, MVT::f128, Expand); 747 748 // These library functions default to expand. 749 for (MVT VT : {MVT::f32, MVT::f64, MVT::f128}) { 750 setOperationAction(ISD::FCBRT, VT, Expand); 751 setOperationAction(ISD::FLOG , VT, Expand); 752 setOperationAction(ISD::FLOG2, VT, Expand); 753 setOperationAction(ISD::FLOG10, VT, Expand); 754 setOperationAction(ISD::FEXP , VT, Expand); 755 setOperationAction(ISD::FEXP2, VT, Expand); 756 setOperationAction(ISD::FFLOOR, VT, Expand); 757 setOperationAction(ISD::FNEARBYINT, VT, Expand); 758 setOperationAction(ISD::FCEIL, VT, Expand); 759 setOperationAction(ISD::FRINT, VT, Expand); 760 setOperationAction(ISD::FTRUNC, VT, Expand); 761 setOperationAction(ISD::FROUND, VT, Expand); 762 setOperationAction(ISD::FROUNDEVEN, VT, Expand); 763 setOperationAction(ISD::LROUND, VT, Expand); 764 setOperationAction(ISD::LLROUND, VT, Expand); 765 setOperationAction(ISD::LRINT, VT, Expand); 766 setOperationAction(ISD::LLRINT, VT, Expand); 767 } 768 769 // Default ISD::TRAP to expand (which turns it into abort). 770 setOperationAction(ISD::TRAP, MVT::Other, Expand); 771 772 // On most systems, DEBUGTRAP and TRAP have no difference. The "Expand" 773 // here is to inform DAG Legalizer to replace DEBUGTRAP with TRAP. 774 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Expand); 775 } 776 777 MVT TargetLoweringBase::getScalarShiftAmountTy(const DataLayout &DL, 778 EVT) const { 779 return MVT::getIntegerVT(DL.getPointerSizeInBits(0)); 780 } 781 782 EVT TargetLoweringBase::getShiftAmountTy(EVT LHSTy, const DataLayout &DL, 783 bool LegalTypes) const { 784 assert(LHSTy.isInteger() && "Shift amount is not an integer type!"); 785 if (LHSTy.isVector()) 786 return LHSTy; 787 return LegalTypes ? getScalarShiftAmountTy(DL, LHSTy) 788 : getPointerTy(DL); 789 } 790 791 bool TargetLoweringBase::canOpTrap(unsigned Op, EVT VT) const { 792 assert(isTypeLegal(VT)); 793 switch (Op) { 794 default: 795 return false; 796 case ISD::SDIV: 797 case ISD::UDIV: 798 case ISD::SREM: 799 case ISD::UREM: 800 return true; 801 } 802 } 803 804 bool TargetLoweringBase::isFreeAddrSpaceCast(unsigned SrcAS, 805 unsigned DestAS) const { 806 return TM.isNoopAddrSpaceCast(SrcAS, DestAS); 807 } 808 809 void TargetLoweringBase::setJumpIsExpensive(bool isExpensive) { 810 // If the command-line option was specified, ignore this request. 811 if (!JumpIsExpensiveOverride.getNumOccurrences()) 812 JumpIsExpensive = isExpensive; 813 } 814 815 TargetLoweringBase::LegalizeKind 816 TargetLoweringBase::getTypeConversion(LLVMContext &Context, EVT VT) const { 817 // If this is a simple type, use the ComputeRegisterProp mechanism. 818 if (VT.isSimple()) { 819 MVT SVT = VT.getSimpleVT(); 820 assert((unsigned)SVT.SimpleTy < array_lengthof(TransformToType)); 821 MVT NVT = TransformToType[SVT.SimpleTy]; 822 LegalizeTypeAction LA = ValueTypeActions.getTypeAction(SVT); 823 824 assert((LA == TypeLegal || LA == TypeSoftenFloat || 825 LA == TypeSoftPromoteHalf || 826 (NVT.isVector() || 827 ValueTypeActions.getTypeAction(NVT) != TypePromoteInteger)) && 828 "Promote may not follow Expand or Promote"); 829 830 if (LA == TypeSplitVector) 831 return LegalizeKind(LA, 832 EVT::getVectorVT(Context, SVT.getVectorElementType(), 833 SVT.getVectorElementCount() / 2)); 834 if (LA == TypeScalarizeVector) 835 return LegalizeKind(LA, SVT.getVectorElementType()); 836 return LegalizeKind(LA, NVT); 837 } 838 839 // Handle Extended Scalar Types. 840 if (!VT.isVector()) { 841 assert(VT.isInteger() && "Float types must be simple"); 842 unsigned BitSize = VT.getSizeInBits(); 843 // First promote to a power-of-two size, then expand if necessary. 844 if (BitSize < 8 || !isPowerOf2_32(BitSize)) { 845 EVT NVT = VT.getRoundIntegerType(Context); 846 assert(NVT != VT && "Unable to round integer VT"); 847 LegalizeKind NextStep = getTypeConversion(Context, NVT); 848 // Avoid multi-step promotion. 849 if (NextStep.first == TypePromoteInteger) 850 return NextStep; 851 // Return rounded integer type. 852 return LegalizeKind(TypePromoteInteger, NVT); 853 } 854 855 return LegalizeKind(TypeExpandInteger, 856 EVT::getIntegerVT(Context, VT.getSizeInBits() / 2)); 857 } 858 859 // Handle vector types. 860 ElementCount NumElts = VT.getVectorElementCount(); 861 EVT EltVT = VT.getVectorElementType(); 862 863 // Vectors with only one element are always scalarized. 864 if (NumElts == 1) 865 return LegalizeKind(TypeScalarizeVector, EltVT); 866 867 if (VT.getVectorElementCount() == ElementCount(1, true)) 868 report_fatal_error("Cannot legalize this vector"); 869 870 // Try to widen vector elements until the element type is a power of two and 871 // promote it to a legal type later on, for example: 872 // <3 x i8> -> <4 x i8> -> <4 x i32> 873 if (EltVT.isInteger()) { 874 // Vectors with a number of elements that is not a power of two are always 875 // widened, for example <3 x i8> -> <4 x i8>. 876 if (!VT.isPow2VectorType()) { 877 NumElts = NumElts.NextPowerOf2(); 878 EVT NVT = EVT::getVectorVT(Context, EltVT, NumElts); 879 return LegalizeKind(TypeWidenVector, NVT); 880 } 881 882 // Examine the element type. 883 LegalizeKind LK = getTypeConversion(Context, EltVT); 884 885 // If type is to be expanded, split the vector. 886 // <4 x i140> -> <2 x i140> 887 if (LK.first == TypeExpandInteger) 888 return LegalizeKind(TypeSplitVector, 889 EVT::getVectorVT(Context, EltVT, NumElts / 2)); 890 891 // Promote the integer element types until a legal vector type is found 892 // or until the element integer type is too big. If a legal type was not 893 // found, fallback to the usual mechanism of widening/splitting the 894 // vector. 895 EVT OldEltVT = EltVT; 896 while (true) { 897 // Increase the bitwidth of the element to the next pow-of-two 898 // (which is greater than 8 bits). 899 EltVT = EVT::getIntegerVT(Context, 1 + EltVT.getSizeInBits()) 900 .getRoundIntegerType(Context); 901 902 // Stop trying when getting a non-simple element type. 903 // Note that vector elements may be greater than legal vector element 904 // types. Example: X86 XMM registers hold 64bit element on 32bit 905 // systems. 906 if (!EltVT.isSimple()) 907 break; 908 909 // Build a new vector type and check if it is legal. 910 MVT NVT = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts); 911 // Found a legal promoted vector type. 912 if (NVT != MVT() && ValueTypeActions.getTypeAction(NVT) == TypeLegal) 913 return LegalizeKind(TypePromoteInteger, 914 EVT::getVectorVT(Context, EltVT, NumElts)); 915 } 916 917 // Reset the type to the unexpanded type if we did not find a legal vector 918 // type with a promoted vector element type. 919 EltVT = OldEltVT; 920 } 921 922 // Try to widen the vector until a legal type is found. 923 // If there is no wider legal type, split the vector. 924 while (true) { 925 // Round up to the next power of 2. 926 NumElts = NumElts.NextPowerOf2(); 927 928 // If there is no simple vector type with this many elements then there 929 // cannot be a larger legal vector type. Note that this assumes that 930 // there are no skipped intermediate vector types in the simple types. 931 if (!EltVT.isSimple()) 932 break; 933 MVT LargerVector = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts); 934 if (LargerVector == MVT()) 935 break; 936 937 // If this type is legal then widen the vector. 938 if (ValueTypeActions.getTypeAction(LargerVector) == TypeLegal) 939 return LegalizeKind(TypeWidenVector, LargerVector); 940 } 941 942 // Widen odd vectors to next power of two. 943 if (!VT.isPow2VectorType()) { 944 EVT NVT = VT.getPow2VectorType(Context); 945 return LegalizeKind(TypeWidenVector, NVT); 946 } 947 948 // Vectors with illegal element types are expanded. 949 EVT NVT = EVT::getVectorVT(Context, EltVT, VT.getVectorElementCount() / 2); 950 return LegalizeKind(TypeSplitVector, NVT); 951 } 952 953 static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT, 954 unsigned &NumIntermediates, 955 MVT &RegisterVT, 956 TargetLoweringBase *TLI) { 957 // Figure out the right, legal destination reg to copy into. 958 ElementCount EC = VT.getVectorElementCount(); 959 MVT EltTy = VT.getVectorElementType(); 960 961 unsigned NumVectorRegs = 1; 962 963 // Scalable vectors cannot be scalarized, so splitting or widening is 964 // required. 965 if (VT.isScalableVector() && !isPowerOf2_32(EC.Min)) 966 llvm_unreachable( 967 "Splitting or widening of non-power-of-2 MVTs is not implemented."); 968 969 // FIXME: We don't support non-power-of-2-sized vectors for now. 970 // Ideally we could break down into LHS/RHS like LegalizeDAG does. 971 if (!isPowerOf2_32(EC.Min)) { 972 // Split EC to unit size (scalable property is preserved). 973 NumVectorRegs = EC.Min; 974 EC = EC / NumVectorRegs; 975 } 976 977 // Divide the input until we get to a supported size. This will 978 // always end up with an EC that represent a scalar or a scalable 979 // scalar. 980 while (EC.Min > 1 && !TLI->isTypeLegal(MVT::getVectorVT(EltTy, EC))) { 981 EC.Min >>= 1; 982 NumVectorRegs <<= 1; 983 } 984 985 NumIntermediates = NumVectorRegs; 986 987 MVT NewVT = MVT::getVectorVT(EltTy, EC); 988 if (!TLI->isTypeLegal(NewVT)) 989 NewVT = EltTy; 990 IntermediateVT = NewVT; 991 992 unsigned LaneSizeInBits = NewVT.getScalarSizeInBits().getFixedSize(); 993 994 // Convert sizes such as i33 to i64. 995 if (!isPowerOf2_32(LaneSizeInBits)) 996 LaneSizeInBits = NextPowerOf2(LaneSizeInBits); 997 998 MVT DestVT = TLI->getRegisterType(NewVT); 999 RegisterVT = DestVT; 1000 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16. 1001 return NumVectorRegs * 1002 (LaneSizeInBits / DestVT.getScalarSizeInBits().getFixedSize()); 1003 1004 // Otherwise, promotion or legal types use the same number of registers as 1005 // the vector decimated to the appropriate level. 1006 return NumVectorRegs; 1007 } 1008 1009 /// isLegalRC - Return true if the value types that can be represented by the 1010 /// specified register class are all legal. 1011 bool TargetLoweringBase::isLegalRC(const TargetRegisterInfo &TRI, 1012 const TargetRegisterClass &RC) const { 1013 for (auto I = TRI.legalclasstypes_begin(RC); *I != MVT::Other; ++I) 1014 if (isTypeLegal(*I)) 1015 return true; 1016 return false; 1017 } 1018 1019 /// Replace/modify any TargetFrameIndex operands with a targte-dependent 1020 /// sequence of memory operands that is recognized by PrologEpilogInserter. 1021 MachineBasicBlock * 1022 TargetLoweringBase::emitPatchPoint(MachineInstr &InitialMI, 1023 MachineBasicBlock *MBB) const { 1024 MachineInstr *MI = &InitialMI; 1025 MachineFunction &MF = *MI->getMF(); 1026 MachineFrameInfo &MFI = MF.getFrameInfo(); 1027 1028 // We're handling multiple types of operands here: 1029 // PATCHPOINT MetaArgs - live-in, read only, direct 1030 // STATEPOINT Deopt Spill - live-through, read only, indirect 1031 // STATEPOINT Deopt Alloca - live-through, read only, direct 1032 // (We're currently conservative and mark the deopt slots read/write in 1033 // practice.) 1034 // STATEPOINT GC Spill - live-through, read/write, indirect 1035 // STATEPOINT GC Alloca - live-through, read/write, direct 1036 // The live-in vs live-through is handled already (the live through ones are 1037 // all stack slots), but we need to handle the different type of stackmap 1038 // operands and memory effects here. 1039 1040 if (!llvm::any_of(MI->operands(), 1041 [](MachineOperand &Operand) { return Operand.isFI(); })) 1042 return MBB; 1043 1044 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), MI->getDesc()); 1045 1046 // Inherit previous memory operands. 1047 MIB.cloneMemRefs(*MI); 1048 1049 for (unsigned i = 0; i < MI->getNumOperands(); ++i) { 1050 MachineOperand &MO = MI->getOperand(i); 1051 if (!MO.isFI()) { 1052 // Index of Def operand this Use it tied to. 1053 // Since Defs are coming before Uses, if Use is tied, then 1054 // index of Def must be smaller that index of that Use. 1055 // Also, Defs preserve their position in new MI. 1056 unsigned TiedTo = i; 1057 if (MO.isReg() && MO.isTied()) 1058 TiedTo = MI->findTiedOperandIdx(i); 1059 MIB.add(MO); 1060 if (TiedTo < i) 1061 MIB->tieOperands(TiedTo, MIB->getNumOperands() - 1); 1062 continue; 1063 } 1064 1065 // foldMemoryOperand builds a new MI after replacing a single FI operand 1066 // with the canonical set of five x86 addressing-mode operands. 1067 int FI = MO.getIndex(); 1068 1069 // Add frame index operands recognized by stackmaps.cpp 1070 if (MFI.isStatepointSpillSlotObjectIndex(FI)) { 1071 // indirect-mem-ref tag, size, #FI, offset. 1072 // Used for spills inserted by StatepointLowering. This codepath is not 1073 // used for patchpoints/stackmaps at all, for these spilling is done via 1074 // foldMemoryOperand callback only. 1075 assert(MI->getOpcode() == TargetOpcode::STATEPOINT && "sanity"); 1076 MIB.addImm(StackMaps::IndirectMemRefOp); 1077 MIB.addImm(MFI.getObjectSize(FI)); 1078 MIB.add(MO); 1079 MIB.addImm(0); 1080 } else { 1081 // direct-mem-ref tag, #FI, offset. 1082 // Used by patchpoint, and direct alloca arguments to statepoints 1083 MIB.addImm(StackMaps::DirectMemRefOp); 1084 MIB.add(MO); 1085 MIB.addImm(0); 1086 } 1087 1088 assert(MIB->mayLoad() && "Folded a stackmap use to a non-load!"); 1089 1090 // Add a new memory operand for this FI. 1091 assert(MFI.getObjectOffset(FI) != -1); 1092 1093 // Note: STATEPOINT MMOs are added during SelectionDAG. STACKMAP, and 1094 // PATCHPOINT should be updated to do the same. (TODO) 1095 if (MI->getOpcode() != TargetOpcode::STATEPOINT) { 1096 auto Flags = MachineMemOperand::MOLoad; 1097 MachineMemOperand *MMO = MF.getMachineMemOperand( 1098 MachinePointerInfo::getFixedStack(MF, FI), Flags, 1099 MF.getDataLayout().getPointerSize(), MFI.getObjectAlign(FI)); 1100 MIB->addMemOperand(MF, MMO); 1101 } 1102 } 1103 MBB->insert(MachineBasicBlock::iterator(MI), MIB); 1104 MI->eraseFromParent(); 1105 return MBB; 1106 } 1107 1108 MachineBasicBlock * 1109 TargetLoweringBase::emitXRayCustomEvent(MachineInstr &MI, 1110 MachineBasicBlock *MBB) const { 1111 assert(MI.getOpcode() == TargetOpcode::PATCHABLE_EVENT_CALL && 1112 "Called emitXRayCustomEvent on the wrong MI!"); 1113 auto &MF = *MI.getMF(); 1114 auto MIB = BuildMI(MF, MI.getDebugLoc(), MI.getDesc()); 1115 for (unsigned OpIdx = 0; OpIdx != MI.getNumOperands(); ++OpIdx) 1116 MIB.add(MI.getOperand(OpIdx)); 1117 1118 MBB->insert(MachineBasicBlock::iterator(MI), MIB); 1119 MI.eraseFromParent(); 1120 return MBB; 1121 } 1122 1123 MachineBasicBlock * 1124 TargetLoweringBase::emitXRayTypedEvent(MachineInstr &MI, 1125 MachineBasicBlock *MBB) const { 1126 assert(MI.getOpcode() == TargetOpcode::PATCHABLE_TYPED_EVENT_CALL && 1127 "Called emitXRayTypedEvent on the wrong MI!"); 1128 auto &MF = *MI.getMF(); 1129 auto MIB = BuildMI(MF, MI.getDebugLoc(), MI.getDesc()); 1130 for (unsigned OpIdx = 0; OpIdx != MI.getNumOperands(); ++OpIdx) 1131 MIB.add(MI.getOperand(OpIdx)); 1132 1133 MBB->insert(MachineBasicBlock::iterator(MI), MIB); 1134 MI.eraseFromParent(); 1135 return MBB; 1136 } 1137 1138 /// findRepresentativeClass - Return the largest legal super-reg register class 1139 /// of the register class for the specified type and its associated "cost". 1140 // This function is in TargetLowering because it uses RegClassForVT which would 1141 // need to be moved to TargetRegisterInfo and would necessitate moving 1142 // isTypeLegal over as well - a massive change that would just require 1143 // TargetLowering having a TargetRegisterInfo class member that it would use. 1144 std::pair<const TargetRegisterClass *, uint8_t> 1145 TargetLoweringBase::findRepresentativeClass(const TargetRegisterInfo *TRI, 1146 MVT VT) const { 1147 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy]; 1148 if (!RC) 1149 return std::make_pair(RC, 0); 1150 1151 // Compute the set of all super-register classes. 1152 BitVector SuperRegRC(TRI->getNumRegClasses()); 1153 for (SuperRegClassIterator RCI(RC, TRI); RCI.isValid(); ++RCI) 1154 SuperRegRC.setBitsInMask(RCI.getMask()); 1155 1156 // Find the first legal register class with the largest spill size. 1157 const TargetRegisterClass *BestRC = RC; 1158 for (unsigned i : SuperRegRC.set_bits()) { 1159 const TargetRegisterClass *SuperRC = TRI->getRegClass(i); 1160 // We want the largest possible spill size. 1161 if (TRI->getSpillSize(*SuperRC) <= TRI->getSpillSize(*BestRC)) 1162 continue; 1163 if (!isLegalRC(*TRI, *SuperRC)) 1164 continue; 1165 BestRC = SuperRC; 1166 } 1167 return std::make_pair(BestRC, 1); 1168 } 1169 1170 /// computeRegisterProperties - Once all of the register classes are added, 1171 /// this allows us to compute derived properties we expose. 1172 void TargetLoweringBase::computeRegisterProperties( 1173 const TargetRegisterInfo *TRI) { 1174 static_assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE, 1175 "Too many value types for ValueTypeActions to hold!"); 1176 1177 // Everything defaults to needing one register. 1178 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) { 1179 NumRegistersForVT[i] = 1; 1180 RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i; 1181 } 1182 // ...except isVoid, which doesn't need any registers. 1183 NumRegistersForVT[MVT::isVoid] = 0; 1184 1185 // Find the largest integer register class. 1186 unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE; 1187 for (; RegClassForVT[LargestIntReg] == nullptr; --LargestIntReg) 1188 assert(LargestIntReg != MVT::i1 && "No integer registers defined!"); 1189 1190 // Every integer value type larger than this largest register takes twice as 1191 // many registers to represent as the previous ValueType. 1192 for (unsigned ExpandedReg = LargestIntReg + 1; 1193 ExpandedReg <= MVT::LAST_INTEGER_VALUETYPE; ++ExpandedReg) { 1194 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1]; 1195 RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg; 1196 TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1); 1197 ValueTypeActions.setTypeAction((MVT::SimpleValueType)ExpandedReg, 1198 TypeExpandInteger); 1199 } 1200 1201 // Inspect all of the ValueType's smaller than the largest integer 1202 // register to see which ones need promotion. 1203 unsigned LegalIntReg = LargestIntReg; 1204 for (unsigned IntReg = LargestIntReg - 1; 1205 IntReg >= (unsigned)MVT::i1; --IntReg) { 1206 MVT IVT = (MVT::SimpleValueType)IntReg; 1207 if (isTypeLegal(IVT)) { 1208 LegalIntReg = IntReg; 1209 } else { 1210 RegisterTypeForVT[IntReg] = TransformToType[IntReg] = 1211 (MVT::SimpleValueType)LegalIntReg; 1212 ValueTypeActions.setTypeAction(IVT, TypePromoteInteger); 1213 } 1214 } 1215 1216 // ppcf128 type is really two f64's. 1217 if (!isTypeLegal(MVT::ppcf128)) { 1218 if (isTypeLegal(MVT::f64)) { 1219 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64]; 1220 RegisterTypeForVT[MVT::ppcf128] = MVT::f64; 1221 TransformToType[MVT::ppcf128] = MVT::f64; 1222 ValueTypeActions.setTypeAction(MVT::ppcf128, TypeExpandFloat); 1223 } else { 1224 NumRegistersForVT[MVT::ppcf128] = NumRegistersForVT[MVT::i128]; 1225 RegisterTypeForVT[MVT::ppcf128] = RegisterTypeForVT[MVT::i128]; 1226 TransformToType[MVT::ppcf128] = MVT::i128; 1227 ValueTypeActions.setTypeAction(MVT::ppcf128, TypeSoftenFloat); 1228 } 1229 } 1230 1231 // Decide how to handle f128. If the target does not have native f128 support, 1232 // expand it to i128 and we will be generating soft float library calls. 1233 if (!isTypeLegal(MVT::f128)) { 1234 NumRegistersForVT[MVT::f128] = NumRegistersForVT[MVT::i128]; 1235 RegisterTypeForVT[MVT::f128] = RegisterTypeForVT[MVT::i128]; 1236 TransformToType[MVT::f128] = MVT::i128; 1237 ValueTypeActions.setTypeAction(MVT::f128, TypeSoftenFloat); 1238 } 1239 1240 // Decide how to handle f64. If the target does not have native f64 support, 1241 // expand it to i64 and we will be generating soft float library calls. 1242 if (!isTypeLegal(MVT::f64)) { 1243 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64]; 1244 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64]; 1245 TransformToType[MVT::f64] = MVT::i64; 1246 ValueTypeActions.setTypeAction(MVT::f64, TypeSoftenFloat); 1247 } 1248 1249 // Decide how to handle f32. If the target does not have native f32 support, 1250 // expand it to i32 and we will be generating soft float library calls. 1251 if (!isTypeLegal(MVT::f32)) { 1252 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32]; 1253 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32]; 1254 TransformToType[MVT::f32] = MVT::i32; 1255 ValueTypeActions.setTypeAction(MVT::f32, TypeSoftenFloat); 1256 } 1257 1258 // Decide how to handle f16. If the target does not have native f16 support, 1259 // promote it to f32, because there are no f16 library calls (except for 1260 // conversions). 1261 if (!isTypeLegal(MVT::f16)) { 1262 // Allow targets to control how we legalize half. 1263 if (softPromoteHalfType()) { 1264 NumRegistersForVT[MVT::f16] = NumRegistersForVT[MVT::i16]; 1265 RegisterTypeForVT[MVT::f16] = RegisterTypeForVT[MVT::i16]; 1266 TransformToType[MVT::f16] = MVT::f32; 1267 ValueTypeActions.setTypeAction(MVT::f16, TypeSoftPromoteHalf); 1268 } else { 1269 NumRegistersForVT[MVT::f16] = NumRegistersForVT[MVT::f32]; 1270 RegisterTypeForVT[MVT::f16] = RegisterTypeForVT[MVT::f32]; 1271 TransformToType[MVT::f16] = MVT::f32; 1272 ValueTypeActions.setTypeAction(MVT::f16, TypePromoteFloat); 1273 } 1274 } 1275 1276 // Loop over all of the vector value types to see which need transformations. 1277 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE; 1278 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) { 1279 MVT VT = (MVT::SimpleValueType) i; 1280 if (isTypeLegal(VT)) 1281 continue; 1282 1283 MVT EltVT = VT.getVectorElementType(); 1284 ElementCount EC = VT.getVectorElementCount(); 1285 bool IsLegalWiderType = false; 1286 bool IsScalable = VT.isScalableVector(); 1287 LegalizeTypeAction PreferredAction = getPreferredVectorAction(VT); 1288 switch (PreferredAction) { 1289 case TypePromoteInteger: { 1290 MVT::SimpleValueType EndVT = IsScalable ? 1291 MVT::LAST_INTEGER_SCALABLE_VECTOR_VALUETYPE : 1292 MVT::LAST_INTEGER_FIXEDLEN_VECTOR_VALUETYPE; 1293 // Try to promote the elements of integer vectors. If no legal 1294 // promotion was found, fall through to the widen-vector method. 1295 for (unsigned nVT = i + 1; 1296 (MVT::SimpleValueType)nVT <= EndVT; ++nVT) { 1297 MVT SVT = (MVT::SimpleValueType) nVT; 1298 // Promote vectors of integers to vectors with the same number 1299 // of elements, with a wider element type. 1300 if (SVT.getScalarSizeInBits() > EltVT.getSizeInBits() && 1301 SVT.getVectorElementCount() == EC && isTypeLegal(SVT)) { 1302 TransformToType[i] = SVT; 1303 RegisterTypeForVT[i] = SVT; 1304 NumRegistersForVT[i] = 1; 1305 ValueTypeActions.setTypeAction(VT, TypePromoteInteger); 1306 IsLegalWiderType = true; 1307 break; 1308 } 1309 } 1310 if (IsLegalWiderType) 1311 break; 1312 LLVM_FALLTHROUGH; 1313 } 1314 1315 case TypeWidenVector: 1316 if (isPowerOf2_32(EC.Min)) { 1317 // Try to widen the vector. 1318 for (unsigned nVT = i + 1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) { 1319 MVT SVT = (MVT::SimpleValueType) nVT; 1320 if (SVT.getVectorElementType() == EltVT && 1321 SVT.isScalableVector() == IsScalable && 1322 SVT.getVectorElementCount().Min > EC.Min && isTypeLegal(SVT)) { 1323 TransformToType[i] = SVT; 1324 RegisterTypeForVT[i] = SVT; 1325 NumRegistersForVT[i] = 1; 1326 ValueTypeActions.setTypeAction(VT, TypeWidenVector); 1327 IsLegalWiderType = true; 1328 break; 1329 } 1330 } 1331 if (IsLegalWiderType) 1332 break; 1333 } else { 1334 // Only widen to the next power of 2 to keep consistency with EVT. 1335 MVT NVT = VT.getPow2VectorType(); 1336 if (isTypeLegal(NVT)) { 1337 TransformToType[i] = NVT; 1338 ValueTypeActions.setTypeAction(VT, TypeWidenVector); 1339 RegisterTypeForVT[i] = NVT; 1340 NumRegistersForVT[i] = 1; 1341 break; 1342 } 1343 } 1344 LLVM_FALLTHROUGH; 1345 1346 case TypeSplitVector: 1347 case TypeScalarizeVector: { 1348 MVT IntermediateVT; 1349 MVT RegisterVT; 1350 unsigned NumIntermediates; 1351 unsigned NumRegisters = getVectorTypeBreakdownMVT(VT, IntermediateVT, 1352 NumIntermediates, RegisterVT, this); 1353 NumRegistersForVT[i] = NumRegisters; 1354 assert(NumRegistersForVT[i] == NumRegisters && 1355 "NumRegistersForVT size cannot represent NumRegisters!"); 1356 RegisterTypeForVT[i] = RegisterVT; 1357 1358 MVT NVT = VT.getPow2VectorType(); 1359 if (NVT == VT) { 1360 // Type is already a power of 2. The default action is to split. 1361 TransformToType[i] = MVT::Other; 1362 if (PreferredAction == TypeScalarizeVector) 1363 ValueTypeActions.setTypeAction(VT, TypeScalarizeVector); 1364 else if (PreferredAction == TypeSplitVector) 1365 ValueTypeActions.setTypeAction(VT, TypeSplitVector); 1366 else if (EC.Min > 1) 1367 ValueTypeActions.setTypeAction(VT, TypeSplitVector); 1368 else 1369 ValueTypeActions.setTypeAction(VT, EC.Scalable 1370 ? TypeScalarizeScalableVector 1371 : TypeScalarizeVector); 1372 } else { 1373 TransformToType[i] = NVT; 1374 ValueTypeActions.setTypeAction(VT, TypeWidenVector); 1375 } 1376 break; 1377 } 1378 default: 1379 llvm_unreachable("Unknown vector legalization action!"); 1380 } 1381 } 1382 1383 // Determine the 'representative' register class for each value type. 1384 // An representative register class is the largest (meaning one which is 1385 // not a sub-register class / subreg register class) legal register class for 1386 // a group of value types. For example, on i386, i8, i16, and i32 1387 // representative would be GR32; while on x86_64 it's GR64. 1388 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) { 1389 const TargetRegisterClass* RRC; 1390 uint8_t Cost; 1391 std::tie(RRC, Cost) = findRepresentativeClass(TRI, (MVT::SimpleValueType)i); 1392 RepRegClassForVT[i] = RRC; 1393 RepRegClassCostForVT[i] = Cost; 1394 } 1395 } 1396 1397 EVT TargetLoweringBase::getSetCCResultType(const DataLayout &DL, LLVMContext &, 1398 EVT VT) const { 1399 assert(!VT.isVector() && "No default SetCC type for vectors!"); 1400 return getPointerTy(DL).SimpleTy; 1401 } 1402 1403 MVT::SimpleValueType TargetLoweringBase::getCmpLibcallReturnType() const { 1404 return MVT::i32; // return the default value 1405 } 1406 1407 /// getVectorTypeBreakdown - Vector types are broken down into some number of 1408 /// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32 1409 /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack. 1410 /// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86. 1411 /// 1412 /// This method returns the number of registers needed, and the VT for each 1413 /// register. It also returns the VT and quantity of the intermediate values 1414 /// before they are promoted/expanded. 1415 unsigned TargetLoweringBase::getVectorTypeBreakdown(LLVMContext &Context, EVT VT, 1416 EVT &IntermediateVT, 1417 unsigned &NumIntermediates, 1418 MVT &RegisterVT) const { 1419 ElementCount EltCnt = VT.getVectorElementCount(); 1420 1421 // If there is a wider vector type with the same element type as this one, 1422 // or a promoted vector type that has the same number of elements which 1423 // are wider, then we should convert to that legal vector type. 1424 // This handles things like <2 x float> -> <4 x float> and 1425 // <4 x i1> -> <4 x i32>. 1426 LegalizeTypeAction TA = getTypeAction(Context, VT); 1427 if (EltCnt.Min != 1 && (TA == TypeWidenVector || TA == TypePromoteInteger)) { 1428 EVT RegisterEVT = getTypeToTransformTo(Context, VT); 1429 if (isTypeLegal(RegisterEVT)) { 1430 IntermediateVT = RegisterEVT; 1431 RegisterVT = RegisterEVT.getSimpleVT(); 1432 NumIntermediates = 1; 1433 return 1; 1434 } 1435 } 1436 1437 // Figure out the right, legal destination reg to copy into. 1438 EVT EltTy = VT.getVectorElementType(); 1439 1440 unsigned NumVectorRegs = 1; 1441 1442 // Scalable vectors cannot be scalarized, so handle the legalisation of the 1443 // types like done elsewhere in SelectionDAG. 1444 if (VT.isScalableVector() && !isPowerOf2_32(EltCnt.Min)) { 1445 LegalizeKind LK; 1446 EVT PartVT = VT; 1447 do { 1448 // Iterate until we've found a legal (part) type to hold VT. 1449 LK = getTypeConversion(Context, PartVT); 1450 PartVT = LK.second; 1451 } while (LK.first != TypeLegal); 1452 1453 NumIntermediates = 1454 VT.getVectorElementCount().Min / PartVT.getVectorElementCount().Min; 1455 1456 // FIXME: This code needs to be extended to handle more complex vector 1457 // breakdowns, like nxv7i64 -> nxv8i64 -> 4 x nxv2i64. Currently the only 1458 // supported cases are vectors that are broken down into equal parts 1459 // such as nxv6i64 -> 3 x nxv2i64. 1460 assert(NumIntermediates * PartVT.getVectorElementCount().Min == 1461 VT.getVectorElementCount().Min && 1462 "Expected an integer multiple of PartVT"); 1463 IntermediateVT = PartVT; 1464 RegisterVT = getRegisterType(Context, IntermediateVT); 1465 return NumIntermediates; 1466 } 1467 1468 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally 1469 // we could break down into LHS/RHS like LegalizeDAG does. 1470 if (!isPowerOf2_32(EltCnt.Min)) { 1471 NumVectorRegs = EltCnt.Min; 1472 EltCnt.Min = 1; 1473 } 1474 1475 // Divide the input until we get to a supported size. This will always 1476 // end with a scalar if the target doesn't support vectors. 1477 while (EltCnt.Min > 1 && 1478 !isTypeLegal(EVT::getVectorVT(Context, EltTy, EltCnt))) { 1479 EltCnt.Min >>= 1; 1480 NumVectorRegs <<= 1; 1481 } 1482 1483 NumIntermediates = NumVectorRegs; 1484 1485 EVT NewVT = EVT::getVectorVT(Context, EltTy, EltCnt); 1486 if (!isTypeLegal(NewVT)) 1487 NewVT = EltTy; 1488 IntermediateVT = NewVT; 1489 1490 MVT DestVT = getRegisterType(Context, NewVT); 1491 RegisterVT = DestVT; 1492 1493 if (EVT(DestVT).bitsLT(NewVT)) { // Value is expanded, e.g. i64 -> i16. 1494 TypeSize NewVTSize = NewVT.getSizeInBits(); 1495 // Convert sizes such as i33 to i64. 1496 if (!isPowerOf2_32(NewVTSize.getKnownMinSize())) 1497 NewVTSize = NewVTSize.NextPowerOf2(); 1498 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits()); 1499 } 1500 1501 // Otherwise, promotion or legal types use the same number of registers as 1502 // the vector decimated to the appropriate level. 1503 return NumVectorRegs; 1504 } 1505 1506 bool TargetLoweringBase::isSuitableForJumpTable(const SwitchInst *SI, 1507 uint64_t NumCases, 1508 uint64_t Range, 1509 ProfileSummaryInfo *PSI, 1510 BlockFrequencyInfo *BFI) const { 1511 // FIXME: This function check the maximum table size and density, but the 1512 // minimum size is not checked. It would be nice if the minimum size is 1513 // also combined within this function. Currently, the minimum size check is 1514 // performed in findJumpTable() in SelectionDAGBuiler and 1515 // getEstimatedNumberOfCaseClusters() in BasicTTIImpl. 1516 const bool OptForSize = 1517 SI->getParent()->getParent()->hasOptSize() || 1518 llvm::shouldOptimizeForSize(SI->getParent(), PSI, BFI); 1519 const unsigned MinDensity = getMinimumJumpTableDensity(OptForSize); 1520 const unsigned MaxJumpTableSize = getMaximumJumpTableSize(); 1521 1522 // Check whether the number of cases is small enough and 1523 // the range is dense enough for a jump table. 1524 return (OptForSize || Range <= MaxJumpTableSize) && 1525 (NumCases * 100 >= Range * MinDensity); 1526 } 1527 1528 /// Get the EVTs and ArgFlags collections that represent the legalized return 1529 /// type of the given function. This does not require a DAG or a return value, 1530 /// and is suitable for use before any DAGs for the function are constructed. 1531 /// TODO: Move this out of TargetLowering.cpp. 1532 void llvm::GetReturnInfo(CallingConv::ID CC, Type *ReturnType, 1533 AttributeList attr, 1534 SmallVectorImpl<ISD::OutputArg> &Outs, 1535 const TargetLowering &TLI, const DataLayout &DL) { 1536 SmallVector<EVT, 4> ValueVTs; 1537 ComputeValueVTs(TLI, DL, ReturnType, ValueVTs); 1538 unsigned NumValues = ValueVTs.size(); 1539 if (NumValues == 0) return; 1540 1541 for (unsigned j = 0, f = NumValues; j != f; ++j) { 1542 EVT VT = ValueVTs[j]; 1543 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 1544 1545 if (attr.hasAttribute(AttributeList::ReturnIndex, Attribute::SExt)) 1546 ExtendKind = ISD::SIGN_EXTEND; 1547 else if (attr.hasAttribute(AttributeList::ReturnIndex, Attribute::ZExt)) 1548 ExtendKind = ISD::ZERO_EXTEND; 1549 1550 // FIXME: C calling convention requires the return type to be promoted to 1551 // at least 32-bit. But this is not necessary for non-C calling 1552 // conventions. The frontend should mark functions whose return values 1553 // require promoting with signext or zeroext attributes. 1554 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) { 1555 MVT MinVT = TLI.getRegisterType(ReturnType->getContext(), MVT::i32); 1556 if (VT.bitsLT(MinVT)) 1557 VT = MinVT; 1558 } 1559 1560 unsigned NumParts = 1561 TLI.getNumRegistersForCallingConv(ReturnType->getContext(), CC, VT); 1562 MVT PartVT = 1563 TLI.getRegisterTypeForCallingConv(ReturnType->getContext(), CC, VT); 1564 1565 // 'inreg' on function refers to return value 1566 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy(); 1567 if (attr.hasAttribute(AttributeList::ReturnIndex, Attribute::InReg)) 1568 Flags.setInReg(); 1569 1570 // Propagate extension type if any 1571 if (attr.hasAttribute(AttributeList::ReturnIndex, Attribute::SExt)) 1572 Flags.setSExt(); 1573 else if (attr.hasAttribute(AttributeList::ReturnIndex, Attribute::ZExt)) 1574 Flags.setZExt(); 1575 1576 for (unsigned i = 0; i < NumParts; ++i) 1577 Outs.push_back(ISD::OutputArg(Flags, PartVT, VT, /*isfixed=*/true, 0, 0)); 1578 } 1579 } 1580 1581 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 1582 /// function arguments in the caller parameter area. This is the actual 1583 /// alignment, not its logarithm. 1584 unsigned TargetLoweringBase::getByValTypeAlignment(Type *Ty, 1585 const DataLayout &DL) const { 1586 return DL.getABITypeAlign(Ty).value(); 1587 } 1588 1589 bool TargetLoweringBase::allowsMemoryAccessForAlignment( 1590 LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace, 1591 Align Alignment, MachineMemOperand::Flags Flags, bool *Fast) const { 1592 // Check if the specified alignment is sufficient based on the data layout. 1593 // TODO: While using the data layout works in practice, a better solution 1594 // would be to implement this check directly (make this a virtual function). 1595 // For example, the ABI alignment may change based on software platform while 1596 // this function should only be affected by hardware implementation. 1597 Type *Ty = VT.getTypeForEVT(Context); 1598 if (Alignment >= DL.getABITypeAlign(Ty)) { 1599 // Assume that an access that meets the ABI-specified alignment is fast. 1600 if (Fast != nullptr) 1601 *Fast = true; 1602 return true; 1603 } 1604 1605 // This is a misaligned access. 1606 return allowsMisalignedMemoryAccesses(VT, AddrSpace, Alignment.value(), Flags, 1607 Fast); 1608 } 1609 1610 bool TargetLoweringBase::allowsMemoryAccessForAlignment( 1611 LLVMContext &Context, const DataLayout &DL, EVT VT, 1612 const MachineMemOperand &MMO, bool *Fast) const { 1613 return allowsMemoryAccessForAlignment(Context, DL, VT, MMO.getAddrSpace(), 1614 MMO.getAlign(), MMO.getFlags(), Fast); 1615 } 1616 1617 bool TargetLoweringBase::allowsMemoryAccess(LLVMContext &Context, 1618 const DataLayout &DL, EVT VT, 1619 unsigned AddrSpace, Align Alignment, 1620 MachineMemOperand::Flags Flags, 1621 bool *Fast) const { 1622 return allowsMemoryAccessForAlignment(Context, DL, VT, AddrSpace, Alignment, 1623 Flags, Fast); 1624 } 1625 1626 bool TargetLoweringBase::allowsMemoryAccess(LLVMContext &Context, 1627 const DataLayout &DL, EVT VT, 1628 const MachineMemOperand &MMO, 1629 bool *Fast) const { 1630 return allowsMemoryAccess(Context, DL, VT, MMO.getAddrSpace(), MMO.getAlign(), 1631 MMO.getFlags(), Fast); 1632 } 1633 1634 BranchProbability TargetLoweringBase::getPredictableBranchThreshold() const { 1635 return BranchProbability(MinPercentageForPredictableBranch, 100); 1636 } 1637 1638 //===----------------------------------------------------------------------===// 1639 // TargetTransformInfo Helpers 1640 //===----------------------------------------------------------------------===// 1641 1642 int TargetLoweringBase::InstructionOpcodeToISD(unsigned Opcode) const { 1643 enum InstructionOpcodes { 1644 #define HANDLE_INST(NUM, OPCODE, CLASS) OPCODE = NUM, 1645 #define LAST_OTHER_INST(NUM) InstructionOpcodesCount = NUM 1646 #include "llvm/IR/Instruction.def" 1647 }; 1648 switch (static_cast<InstructionOpcodes>(Opcode)) { 1649 case Ret: return 0; 1650 case Br: return 0; 1651 case Switch: return 0; 1652 case IndirectBr: return 0; 1653 case Invoke: return 0; 1654 case CallBr: return 0; 1655 case Resume: return 0; 1656 case Unreachable: return 0; 1657 case CleanupRet: return 0; 1658 case CatchRet: return 0; 1659 case CatchPad: return 0; 1660 case CatchSwitch: return 0; 1661 case CleanupPad: return 0; 1662 case FNeg: return ISD::FNEG; 1663 case Add: return ISD::ADD; 1664 case FAdd: return ISD::FADD; 1665 case Sub: return ISD::SUB; 1666 case FSub: return ISD::FSUB; 1667 case Mul: return ISD::MUL; 1668 case FMul: return ISD::FMUL; 1669 case UDiv: return ISD::UDIV; 1670 case SDiv: return ISD::SDIV; 1671 case FDiv: return ISD::FDIV; 1672 case URem: return ISD::UREM; 1673 case SRem: return ISD::SREM; 1674 case FRem: return ISD::FREM; 1675 case Shl: return ISD::SHL; 1676 case LShr: return ISD::SRL; 1677 case AShr: return ISD::SRA; 1678 case And: return ISD::AND; 1679 case Or: return ISD::OR; 1680 case Xor: return ISD::XOR; 1681 case Alloca: return 0; 1682 case Load: return ISD::LOAD; 1683 case Store: return ISD::STORE; 1684 case GetElementPtr: return 0; 1685 case Fence: return 0; 1686 case AtomicCmpXchg: return 0; 1687 case AtomicRMW: return 0; 1688 case Trunc: return ISD::TRUNCATE; 1689 case ZExt: return ISD::ZERO_EXTEND; 1690 case SExt: return ISD::SIGN_EXTEND; 1691 case FPToUI: return ISD::FP_TO_UINT; 1692 case FPToSI: return ISD::FP_TO_SINT; 1693 case UIToFP: return ISD::UINT_TO_FP; 1694 case SIToFP: return ISD::SINT_TO_FP; 1695 case FPTrunc: return ISD::FP_ROUND; 1696 case FPExt: return ISD::FP_EXTEND; 1697 case PtrToInt: return ISD::BITCAST; 1698 case IntToPtr: return ISD::BITCAST; 1699 case BitCast: return ISD::BITCAST; 1700 case AddrSpaceCast: return ISD::ADDRSPACECAST; 1701 case ICmp: return ISD::SETCC; 1702 case FCmp: return ISD::SETCC; 1703 case PHI: return 0; 1704 case Call: return 0; 1705 case Select: return ISD::SELECT; 1706 case UserOp1: return 0; 1707 case UserOp2: return 0; 1708 case VAArg: return 0; 1709 case ExtractElement: return ISD::EXTRACT_VECTOR_ELT; 1710 case InsertElement: return ISD::INSERT_VECTOR_ELT; 1711 case ShuffleVector: return ISD::VECTOR_SHUFFLE; 1712 case ExtractValue: return ISD::MERGE_VALUES; 1713 case InsertValue: return ISD::MERGE_VALUES; 1714 case LandingPad: return 0; 1715 case Freeze: return ISD::FREEZE; 1716 } 1717 1718 llvm_unreachable("Unknown instruction type encountered!"); 1719 } 1720 1721 std::pair<int, MVT> 1722 TargetLoweringBase::getTypeLegalizationCost(const DataLayout &DL, 1723 Type *Ty) const { 1724 LLVMContext &C = Ty->getContext(); 1725 EVT MTy = getValueType(DL, Ty); 1726 1727 int Cost = 1; 1728 // We keep legalizing the type until we find a legal kind. We assume that 1729 // the only operation that costs anything is the split. After splitting 1730 // we need to handle two types. 1731 while (true) { 1732 LegalizeKind LK = getTypeConversion(C, MTy); 1733 1734 if (LK.first == TypeLegal) 1735 return std::make_pair(Cost, MTy.getSimpleVT()); 1736 1737 if (LK.first == TypeSplitVector || LK.first == TypeExpandInteger) 1738 Cost *= 2; 1739 1740 // Do not loop with f128 type. 1741 if (MTy == LK.second) 1742 return std::make_pair(Cost, MTy.getSimpleVT()); 1743 1744 // Keep legalizing the type. 1745 MTy = LK.second; 1746 } 1747 } 1748 1749 Value *TargetLoweringBase::getDefaultSafeStackPointerLocation(IRBuilder<> &IRB, 1750 bool UseTLS) const { 1751 // compiler-rt provides a variable with a magic name. Targets that do not 1752 // link with compiler-rt may also provide such a variable. 1753 Module *M = IRB.GetInsertBlock()->getParent()->getParent(); 1754 const char *UnsafeStackPtrVar = "__safestack_unsafe_stack_ptr"; 1755 auto UnsafeStackPtr = 1756 dyn_cast_or_null<GlobalVariable>(M->getNamedValue(UnsafeStackPtrVar)); 1757 1758 Type *StackPtrTy = Type::getInt8PtrTy(M->getContext()); 1759 1760 if (!UnsafeStackPtr) { 1761 auto TLSModel = UseTLS ? 1762 GlobalValue::InitialExecTLSModel : 1763 GlobalValue::NotThreadLocal; 1764 // The global variable is not defined yet, define it ourselves. 1765 // We use the initial-exec TLS model because we do not support the 1766 // variable living anywhere other than in the main executable. 1767 UnsafeStackPtr = new GlobalVariable( 1768 *M, StackPtrTy, false, GlobalValue::ExternalLinkage, nullptr, 1769 UnsafeStackPtrVar, nullptr, TLSModel); 1770 } else { 1771 // The variable exists, check its type and attributes. 1772 if (UnsafeStackPtr->getValueType() != StackPtrTy) 1773 report_fatal_error(Twine(UnsafeStackPtrVar) + " must have void* type"); 1774 if (UseTLS != UnsafeStackPtr->isThreadLocal()) 1775 report_fatal_error(Twine(UnsafeStackPtrVar) + " must " + 1776 (UseTLS ? "" : "not ") + "be thread-local"); 1777 } 1778 return UnsafeStackPtr; 1779 } 1780 1781 Value *TargetLoweringBase::getSafeStackPointerLocation(IRBuilder<> &IRB) const { 1782 if (!TM.getTargetTriple().isAndroid()) 1783 return getDefaultSafeStackPointerLocation(IRB, true); 1784 1785 // Android provides a libc function to retrieve the address of the current 1786 // thread's unsafe stack pointer. 1787 Module *M = IRB.GetInsertBlock()->getParent()->getParent(); 1788 Type *StackPtrTy = Type::getInt8PtrTy(M->getContext()); 1789 FunctionCallee Fn = M->getOrInsertFunction("__safestack_pointer_address", 1790 StackPtrTy->getPointerTo(0)); 1791 return IRB.CreateCall(Fn); 1792 } 1793 1794 //===----------------------------------------------------------------------===// 1795 // Loop Strength Reduction hooks 1796 //===----------------------------------------------------------------------===// 1797 1798 /// isLegalAddressingMode - Return true if the addressing mode represented 1799 /// by AM is legal for this target, for a load/store of the specified type. 1800 bool TargetLoweringBase::isLegalAddressingMode(const DataLayout &DL, 1801 const AddrMode &AM, Type *Ty, 1802 unsigned AS, Instruction *I) const { 1803 // The default implementation of this implements a conservative RISCy, r+r and 1804 // r+i addr mode. 1805 1806 // Allows a sign-extended 16-bit immediate field. 1807 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1) 1808 return false; 1809 1810 // No global is ever allowed as a base. 1811 if (AM.BaseGV) 1812 return false; 1813 1814 // Only support r+r, 1815 switch (AM.Scale) { 1816 case 0: // "r+i" or just "i", depending on HasBaseReg. 1817 break; 1818 case 1: 1819 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. 1820 return false; 1821 // Otherwise we have r+r or r+i. 1822 break; 1823 case 2: 1824 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. 1825 return false; 1826 // Allow 2*r as r+r. 1827 break; 1828 default: // Don't allow n * r 1829 return false; 1830 } 1831 1832 return true; 1833 } 1834 1835 //===----------------------------------------------------------------------===// 1836 // Stack Protector 1837 //===----------------------------------------------------------------------===// 1838 1839 // For OpenBSD return its special guard variable. Otherwise return nullptr, 1840 // so that SelectionDAG handle SSP. 1841 Value *TargetLoweringBase::getIRStackGuard(IRBuilder<> &IRB) const { 1842 if (getTargetMachine().getTargetTriple().isOSOpenBSD()) { 1843 Module &M = *IRB.GetInsertBlock()->getParent()->getParent(); 1844 PointerType *PtrTy = Type::getInt8PtrTy(M.getContext()); 1845 return M.getOrInsertGlobal("__guard_local", PtrTy); 1846 } 1847 return nullptr; 1848 } 1849 1850 // Currently only support "standard" __stack_chk_guard. 1851 // TODO: add LOAD_STACK_GUARD support. 1852 void TargetLoweringBase::insertSSPDeclarations(Module &M) const { 1853 if (!M.getNamedValue("__stack_chk_guard")) 1854 new GlobalVariable(M, Type::getInt8PtrTy(M.getContext()), false, 1855 GlobalVariable::ExternalLinkage, 1856 nullptr, "__stack_chk_guard"); 1857 } 1858 1859 // Currently only support "standard" __stack_chk_guard. 1860 // TODO: add LOAD_STACK_GUARD support. 1861 Value *TargetLoweringBase::getSDagStackGuard(const Module &M) const { 1862 return M.getNamedValue("__stack_chk_guard"); 1863 } 1864 1865 Function *TargetLoweringBase::getSSPStackGuardCheck(const Module &M) const { 1866 return nullptr; 1867 } 1868 1869 unsigned TargetLoweringBase::getMinimumJumpTableEntries() const { 1870 return MinimumJumpTableEntries; 1871 } 1872 1873 void TargetLoweringBase::setMinimumJumpTableEntries(unsigned Val) { 1874 MinimumJumpTableEntries = Val; 1875 } 1876 1877 unsigned TargetLoweringBase::getMinimumJumpTableDensity(bool OptForSize) const { 1878 return OptForSize ? OptsizeJumpTableDensity : JumpTableDensity; 1879 } 1880 1881 unsigned TargetLoweringBase::getMaximumJumpTableSize() const { 1882 return MaximumJumpTableSize; 1883 } 1884 1885 void TargetLoweringBase::setMaximumJumpTableSize(unsigned Val) { 1886 MaximumJumpTableSize = Val; 1887 } 1888 1889 bool TargetLoweringBase::isJumpTableRelative() const { 1890 return getTargetMachine().isPositionIndependent(); 1891 } 1892 1893 //===----------------------------------------------------------------------===// 1894 // Reciprocal Estimates 1895 //===----------------------------------------------------------------------===// 1896 1897 /// Get the reciprocal estimate attribute string for a function that will 1898 /// override the target defaults. 1899 static StringRef getRecipEstimateForFunc(MachineFunction &MF) { 1900 const Function &F = MF.getFunction(); 1901 return F.getFnAttribute("reciprocal-estimates").getValueAsString(); 1902 } 1903 1904 /// Construct a string for the given reciprocal operation of the given type. 1905 /// This string should match the corresponding option to the front-end's 1906 /// "-mrecip" flag assuming those strings have been passed through in an 1907 /// attribute string. For example, "vec-divf" for a division of a vXf32. 1908 static std::string getReciprocalOpName(bool IsSqrt, EVT VT) { 1909 std::string Name = VT.isVector() ? "vec-" : ""; 1910 1911 Name += IsSqrt ? "sqrt" : "div"; 1912 1913 // TODO: Handle "half" or other float types? 1914 if (VT.getScalarType() == MVT::f64) { 1915 Name += "d"; 1916 } else { 1917 assert(VT.getScalarType() == MVT::f32 && 1918 "Unexpected FP type for reciprocal estimate"); 1919 Name += "f"; 1920 } 1921 1922 return Name; 1923 } 1924 1925 /// Return the character position and value (a single numeric character) of a 1926 /// customized refinement operation in the input string if it exists. Return 1927 /// false if there is no customized refinement step count. 1928 static bool parseRefinementStep(StringRef In, size_t &Position, 1929 uint8_t &Value) { 1930 const char RefStepToken = ':'; 1931 Position = In.find(RefStepToken); 1932 if (Position == StringRef::npos) 1933 return false; 1934 1935 StringRef RefStepString = In.substr(Position + 1); 1936 // Allow exactly one numeric character for the additional refinement 1937 // step parameter. 1938 if (RefStepString.size() == 1) { 1939 char RefStepChar = RefStepString[0]; 1940 if (RefStepChar >= '0' && RefStepChar <= '9') { 1941 Value = RefStepChar - '0'; 1942 return true; 1943 } 1944 } 1945 report_fatal_error("Invalid refinement step for -recip."); 1946 } 1947 1948 /// For the input attribute string, return one of the ReciprocalEstimate enum 1949 /// status values (enabled, disabled, or not specified) for this operation on 1950 /// the specified data type. 1951 static int getOpEnabled(bool IsSqrt, EVT VT, StringRef Override) { 1952 if (Override.empty()) 1953 return TargetLoweringBase::ReciprocalEstimate::Unspecified; 1954 1955 SmallVector<StringRef, 4> OverrideVector; 1956 Override.split(OverrideVector, ','); 1957 unsigned NumArgs = OverrideVector.size(); 1958 1959 // Check if "all", "none", or "default" was specified. 1960 if (NumArgs == 1) { 1961 // Look for an optional setting of the number of refinement steps needed 1962 // for this type of reciprocal operation. 1963 size_t RefPos; 1964 uint8_t RefSteps; 1965 if (parseRefinementStep(Override, RefPos, RefSteps)) { 1966 // Split the string for further processing. 1967 Override = Override.substr(0, RefPos); 1968 } 1969 1970 // All reciprocal types are enabled. 1971 if (Override == "all") 1972 return TargetLoweringBase::ReciprocalEstimate::Enabled; 1973 1974 // All reciprocal types are disabled. 1975 if (Override == "none") 1976 return TargetLoweringBase::ReciprocalEstimate::Disabled; 1977 1978 // Target defaults for enablement are used. 1979 if (Override == "default") 1980 return TargetLoweringBase::ReciprocalEstimate::Unspecified; 1981 } 1982 1983 // The attribute string may omit the size suffix ('f'/'d'). 1984 std::string VTName = getReciprocalOpName(IsSqrt, VT); 1985 std::string VTNameNoSize = VTName; 1986 VTNameNoSize.pop_back(); 1987 static const char DisabledPrefix = '!'; 1988 1989 for (StringRef RecipType : OverrideVector) { 1990 size_t RefPos; 1991 uint8_t RefSteps; 1992 if (parseRefinementStep(RecipType, RefPos, RefSteps)) 1993 RecipType = RecipType.substr(0, RefPos); 1994 1995 // Ignore the disablement token for string matching. 1996 bool IsDisabled = RecipType[0] == DisabledPrefix; 1997 if (IsDisabled) 1998 RecipType = RecipType.substr(1); 1999 2000 if (RecipType.equals(VTName) || RecipType.equals(VTNameNoSize)) 2001 return IsDisabled ? TargetLoweringBase::ReciprocalEstimate::Disabled 2002 : TargetLoweringBase::ReciprocalEstimate::Enabled; 2003 } 2004 2005 return TargetLoweringBase::ReciprocalEstimate::Unspecified; 2006 } 2007 2008 /// For the input attribute string, return the customized refinement step count 2009 /// for this operation on the specified data type. If the step count does not 2010 /// exist, return the ReciprocalEstimate enum value for unspecified. 2011 static int getOpRefinementSteps(bool IsSqrt, EVT VT, StringRef Override) { 2012 if (Override.empty()) 2013 return TargetLoweringBase::ReciprocalEstimate::Unspecified; 2014 2015 SmallVector<StringRef, 4> OverrideVector; 2016 Override.split(OverrideVector, ','); 2017 unsigned NumArgs = OverrideVector.size(); 2018 2019 // Check if "all", "default", or "none" was specified. 2020 if (NumArgs == 1) { 2021 // Look for an optional setting of the number of refinement steps needed 2022 // for this type of reciprocal operation. 2023 size_t RefPos; 2024 uint8_t RefSteps; 2025 if (!parseRefinementStep(Override, RefPos, RefSteps)) 2026 return TargetLoweringBase::ReciprocalEstimate::Unspecified; 2027 2028 // Split the string for further processing. 2029 Override = Override.substr(0, RefPos); 2030 assert(Override != "none" && 2031 "Disabled reciprocals, but specifed refinement steps?"); 2032 2033 // If this is a general override, return the specified number of steps. 2034 if (Override == "all" || Override == "default") 2035 return RefSteps; 2036 } 2037 2038 // The attribute string may omit the size suffix ('f'/'d'). 2039 std::string VTName = getReciprocalOpName(IsSqrt, VT); 2040 std::string VTNameNoSize = VTName; 2041 VTNameNoSize.pop_back(); 2042 2043 for (StringRef RecipType : OverrideVector) { 2044 size_t RefPos; 2045 uint8_t RefSteps; 2046 if (!parseRefinementStep(RecipType, RefPos, RefSteps)) 2047 continue; 2048 2049 RecipType = RecipType.substr(0, RefPos); 2050 if (RecipType.equals(VTName) || RecipType.equals(VTNameNoSize)) 2051 return RefSteps; 2052 } 2053 2054 return TargetLoweringBase::ReciprocalEstimate::Unspecified; 2055 } 2056 2057 int TargetLoweringBase::getRecipEstimateSqrtEnabled(EVT VT, 2058 MachineFunction &MF) const { 2059 return getOpEnabled(true, VT, getRecipEstimateForFunc(MF)); 2060 } 2061 2062 int TargetLoweringBase::getRecipEstimateDivEnabled(EVT VT, 2063 MachineFunction &MF) const { 2064 return getOpEnabled(false, VT, getRecipEstimateForFunc(MF)); 2065 } 2066 2067 int TargetLoweringBase::getSqrtRefinementSteps(EVT VT, 2068 MachineFunction &MF) const { 2069 return getOpRefinementSteps(true, VT, getRecipEstimateForFunc(MF)); 2070 } 2071 2072 int TargetLoweringBase::getDivRefinementSteps(EVT VT, 2073 MachineFunction &MF) const { 2074 return getOpRefinementSteps(false, VT, getRecipEstimateForFunc(MF)); 2075 } 2076 2077 void TargetLoweringBase::finalizeLowering(MachineFunction &MF) const { 2078 MF.getRegInfo().freezeReservedRegs(MF); 2079 } 2080 2081 MachineMemOperand::Flags 2082 TargetLoweringBase::getLoadMemOperandFlags(const LoadInst &LI, 2083 const DataLayout &DL) const { 2084 MachineMemOperand::Flags Flags = MachineMemOperand::MOLoad; 2085 if (LI.isVolatile()) 2086 Flags |= MachineMemOperand::MOVolatile; 2087 2088 if (LI.hasMetadata(LLVMContext::MD_nontemporal)) 2089 Flags |= MachineMemOperand::MONonTemporal; 2090 2091 if (LI.hasMetadata(LLVMContext::MD_invariant_load)) 2092 Flags |= MachineMemOperand::MOInvariant; 2093 2094 if (isDereferenceablePointer(LI.getPointerOperand(), LI.getType(), DL)) 2095 Flags |= MachineMemOperand::MODereferenceable; 2096 2097 Flags |= getTargetMMOFlags(LI); 2098 return Flags; 2099 } 2100 2101 MachineMemOperand::Flags 2102 TargetLoweringBase::getStoreMemOperandFlags(const StoreInst &SI, 2103 const DataLayout &DL) const { 2104 MachineMemOperand::Flags Flags = MachineMemOperand::MOStore; 2105 2106 if (SI.isVolatile()) 2107 Flags |= MachineMemOperand::MOVolatile; 2108 2109 if (SI.hasMetadata(LLVMContext::MD_nontemporal)) 2110 Flags |= MachineMemOperand::MONonTemporal; 2111 2112 // FIXME: Not preserving dereferenceable 2113 Flags |= getTargetMMOFlags(SI); 2114 return Flags; 2115 } 2116 2117 MachineMemOperand::Flags 2118 TargetLoweringBase::getAtomicMemOperandFlags(const Instruction &AI, 2119 const DataLayout &DL) const { 2120 auto Flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore; 2121 2122 if (const AtomicRMWInst *RMW = dyn_cast<AtomicRMWInst>(&AI)) { 2123 if (RMW->isVolatile()) 2124 Flags |= MachineMemOperand::MOVolatile; 2125 } else if (const AtomicCmpXchgInst *CmpX = dyn_cast<AtomicCmpXchgInst>(&AI)) { 2126 if (CmpX->isVolatile()) 2127 Flags |= MachineMemOperand::MOVolatile; 2128 } else 2129 llvm_unreachable("not an atomic instruction"); 2130 2131 // FIXME: Not preserving dereferenceable 2132 Flags |= getTargetMMOFlags(AI); 2133 return Flags; 2134 } 2135 2136 //===----------------------------------------------------------------------===// 2137 // GlobalISel Hooks 2138 //===----------------------------------------------------------------------===// 2139 2140 bool TargetLoweringBase::shouldLocalize(const MachineInstr &MI, 2141 const TargetTransformInfo *TTI) const { 2142 auto &MF = *MI.getMF(); 2143 auto &MRI = MF.getRegInfo(); 2144 // Assuming a spill and reload of a value has a cost of 1 instruction each, 2145 // this helper function computes the maximum number of uses we should consider 2146 // for remat. E.g. on arm64 global addresses take 2 insts to materialize. We 2147 // break even in terms of code size when the original MI has 2 users vs 2148 // choosing to potentially spill. Any more than 2 users we we have a net code 2149 // size increase. This doesn't take into account register pressure though. 2150 auto maxUses = [](unsigned RematCost) { 2151 // A cost of 1 means remats are basically free. 2152 if (RematCost == 1) 2153 return UINT_MAX; 2154 if (RematCost == 2) 2155 return 2U; 2156 2157 // Remat is too expensive, only sink if there's one user. 2158 if (RematCost > 2) 2159 return 1U; 2160 llvm_unreachable("Unexpected remat cost"); 2161 }; 2162 2163 // Helper to walk through uses and terminate if we've reached a limit. Saves 2164 // us spending time traversing uses if all we want to know is if it's >= min. 2165 auto isUsesAtMost = [&](unsigned Reg, unsigned MaxUses) { 2166 unsigned NumUses = 0; 2167 auto UI = MRI.use_instr_nodbg_begin(Reg), UE = MRI.use_instr_nodbg_end(); 2168 for (; UI != UE && NumUses < MaxUses; ++UI) { 2169 NumUses++; 2170 } 2171 // If we haven't reached the end yet then there are more than MaxUses users. 2172 return UI == UE; 2173 }; 2174 2175 switch (MI.getOpcode()) { 2176 default: 2177 return false; 2178 // Constants-like instructions should be close to their users. 2179 // We don't want long live-ranges for them. 2180 case TargetOpcode::G_CONSTANT: 2181 case TargetOpcode::G_FCONSTANT: 2182 case TargetOpcode::G_FRAME_INDEX: 2183 case TargetOpcode::G_INTTOPTR: 2184 return true; 2185 case TargetOpcode::G_GLOBAL_VALUE: { 2186 unsigned RematCost = TTI->getGISelRematGlobalCost(); 2187 Register Reg = MI.getOperand(0).getReg(); 2188 unsigned MaxUses = maxUses(RematCost); 2189 if (MaxUses == UINT_MAX) 2190 return true; // Remats are "free" so always localize. 2191 bool B = isUsesAtMost(Reg, MaxUses); 2192 return B; 2193 } 2194 } 2195 } 2196