1 //===- TargetLoweringBase.cpp - Implement the TargetLoweringBase class ----===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This implements the TargetLoweringBase class. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "llvm/ADT/BitVector.h" 14 #include "llvm/ADT/STLExtras.h" 15 #include "llvm/ADT/SmallVector.h" 16 #include "llvm/ADT/StringExtras.h" 17 #include "llvm/ADT/StringRef.h" 18 #include "llvm/ADT/Triple.h" 19 #include "llvm/ADT/Twine.h" 20 #include "llvm/CodeGen/Analysis.h" 21 #include "llvm/CodeGen/ISDOpcodes.h" 22 #include "llvm/CodeGen/MachineBasicBlock.h" 23 #include "llvm/CodeGen/MachineFrameInfo.h" 24 #include "llvm/CodeGen/MachineFunction.h" 25 #include "llvm/CodeGen/MachineInstr.h" 26 #include "llvm/CodeGen/MachineInstrBuilder.h" 27 #include "llvm/CodeGen/MachineMemOperand.h" 28 #include "llvm/CodeGen/MachineOperand.h" 29 #include "llvm/CodeGen/MachineRegisterInfo.h" 30 #include "llvm/CodeGen/RuntimeLibcalls.h" 31 #include "llvm/CodeGen/StackMaps.h" 32 #include "llvm/CodeGen/TargetLowering.h" 33 #include "llvm/CodeGen/TargetOpcodes.h" 34 #include "llvm/CodeGen/TargetRegisterInfo.h" 35 #include "llvm/CodeGen/ValueTypes.h" 36 #include "llvm/IR/Attributes.h" 37 #include "llvm/IR/CallingConv.h" 38 #include "llvm/IR/DataLayout.h" 39 #include "llvm/IR/DerivedTypes.h" 40 #include "llvm/IR/Function.h" 41 #include "llvm/IR/GlobalValue.h" 42 #include "llvm/IR/GlobalVariable.h" 43 #include "llvm/IR/IRBuilder.h" 44 #include "llvm/IR/Module.h" 45 #include "llvm/IR/Type.h" 46 #include "llvm/Support/BranchProbability.h" 47 #include "llvm/Support/Casting.h" 48 #include "llvm/Support/CommandLine.h" 49 #include "llvm/Support/Compiler.h" 50 #include "llvm/Support/ErrorHandling.h" 51 #include "llvm/Support/MachineValueType.h" 52 #include "llvm/Support/MathExtras.h" 53 #include "llvm/Target/TargetMachine.h" 54 #include <algorithm> 55 #include <cassert> 56 #include <cstddef> 57 #include <cstdint> 58 #include <cstring> 59 #include <iterator> 60 #include <string> 61 #include <tuple> 62 #include <utility> 63 64 using namespace llvm; 65 66 static cl::opt<bool> JumpIsExpensiveOverride( 67 "jump-is-expensive", cl::init(false), 68 cl::desc("Do not create extra branches to split comparison logic."), 69 cl::Hidden); 70 71 static cl::opt<unsigned> MinimumJumpTableEntries 72 ("min-jump-table-entries", cl::init(4), cl::Hidden, 73 cl::desc("Set minimum number of entries to use a jump table.")); 74 75 static cl::opt<unsigned> MaximumJumpTableSize 76 ("max-jump-table-size", cl::init(UINT_MAX), cl::Hidden, 77 cl::desc("Set maximum size of jump tables.")); 78 79 /// Minimum jump table density for normal functions. 80 static cl::opt<unsigned> 81 JumpTableDensity("jump-table-density", cl::init(10), cl::Hidden, 82 cl::desc("Minimum density for building a jump table in " 83 "a normal function")); 84 85 /// Minimum jump table density for -Os or -Oz functions. 86 static cl::opt<unsigned> OptsizeJumpTableDensity( 87 "optsize-jump-table-density", cl::init(40), cl::Hidden, 88 cl::desc("Minimum density for building a jump table in " 89 "an optsize function")); 90 91 static bool darwinHasSinCos(const Triple &TT) { 92 assert(TT.isOSDarwin() && "should be called with darwin triple"); 93 // Don't bother with 32 bit x86. 94 if (TT.getArch() == Triple::x86) 95 return false; 96 // Macos < 10.9 has no sincos_stret. 97 if (TT.isMacOSX()) 98 return !TT.isMacOSXVersionLT(10, 9) && TT.isArch64Bit(); 99 // iOS < 7.0 has no sincos_stret. 100 if (TT.isiOS()) 101 return !TT.isOSVersionLT(7, 0); 102 // Any other darwin such as WatchOS/TvOS is new enough. 103 return true; 104 } 105 106 // Although this default value is arbitrary, it is not random. It is assumed 107 // that a condition that evaluates the same way by a higher percentage than this 108 // is best represented as control flow. Therefore, the default value N should be 109 // set such that the win from N% correct executions is greater than the loss 110 // from (100 - N)% mispredicted executions for the majority of intended targets. 111 static cl::opt<int> MinPercentageForPredictableBranch( 112 "min-predictable-branch", cl::init(99), 113 cl::desc("Minimum percentage (0-100) that a condition must be either true " 114 "or false to assume that the condition is predictable"), 115 cl::Hidden); 116 117 void TargetLoweringBase::InitLibcalls(const Triple &TT) { 118 #define HANDLE_LIBCALL(code, name) \ 119 setLibcallName(RTLIB::code, name); 120 #include "llvm/IR/RuntimeLibcalls.def" 121 #undef HANDLE_LIBCALL 122 // Initialize calling conventions to their default. 123 for (int LC = 0; LC < RTLIB::UNKNOWN_LIBCALL; ++LC) 124 setLibcallCallingConv((RTLIB::Libcall)LC, CallingConv::C); 125 126 // A few names are different on particular architectures or environments. 127 if (TT.isOSDarwin()) { 128 // For f16/f32 conversions, Darwin uses the standard naming scheme, instead 129 // of the gnueabi-style __gnu_*_ieee. 130 // FIXME: What about other targets? 131 setLibcallName(RTLIB::FPEXT_F16_F32, "__extendhfsf2"); 132 setLibcallName(RTLIB::FPROUND_F32_F16, "__truncsfhf2"); 133 134 // Some darwins have an optimized __bzero/bzero function. 135 switch (TT.getArch()) { 136 case Triple::x86: 137 case Triple::x86_64: 138 if (TT.isMacOSX() && !TT.isMacOSXVersionLT(10, 6)) 139 setLibcallName(RTLIB::BZERO, "__bzero"); 140 break; 141 case Triple::aarch64: 142 setLibcallName(RTLIB::BZERO, "bzero"); 143 break; 144 default: 145 break; 146 } 147 148 if (darwinHasSinCos(TT)) { 149 setLibcallName(RTLIB::SINCOS_STRET_F32, "__sincosf_stret"); 150 setLibcallName(RTLIB::SINCOS_STRET_F64, "__sincos_stret"); 151 if (TT.isWatchABI()) { 152 setLibcallCallingConv(RTLIB::SINCOS_STRET_F32, 153 CallingConv::ARM_AAPCS_VFP); 154 setLibcallCallingConv(RTLIB::SINCOS_STRET_F64, 155 CallingConv::ARM_AAPCS_VFP); 156 } 157 } 158 } else { 159 setLibcallName(RTLIB::FPEXT_F16_F32, "__gnu_h2f_ieee"); 160 setLibcallName(RTLIB::FPROUND_F32_F16, "__gnu_f2h_ieee"); 161 } 162 163 if (TT.isGNUEnvironment() || TT.isOSFuchsia() || 164 (TT.isAndroid() && !TT.isAndroidVersionLT(9))) { 165 setLibcallName(RTLIB::SINCOS_F32, "sincosf"); 166 setLibcallName(RTLIB::SINCOS_F64, "sincos"); 167 setLibcallName(RTLIB::SINCOS_F80, "sincosl"); 168 setLibcallName(RTLIB::SINCOS_F128, "sincosl"); 169 setLibcallName(RTLIB::SINCOS_PPCF128, "sincosl"); 170 } 171 172 if (TT.isOSOpenBSD()) { 173 setLibcallName(RTLIB::STACKPROTECTOR_CHECK_FAIL, nullptr); 174 } 175 } 176 177 /// getFPEXT - Return the FPEXT_*_* value for the given types, or 178 /// UNKNOWN_LIBCALL if there is none. 179 RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) { 180 if (OpVT == MVT::f16) { 181 if (RetVT == MVT::f32) 182 return FPEXT_F16_F32; 183 } else if (OpVT == MVT::f32) { 184 if (RetVT == MVT::f64) 185 return FPEXT_F32_F64; 186 if (RetVT == MVT::f128) 187 return FPEXT_F32_F128; 188 if (RetVT == MVT::ppcf128) 189 return FPEXT_F32_PPCF128; 190 } else if (OpVT == MVT::f64) { 191 if (RetVT == MVT::f128) 192 return FPEXT_F64_F128; 193 else if (RetVT == MVT::ppcf128) 194 return FPEXT_F64_PPCF128; 195 } else if (OpVT == MVT::f80) { 196 if (RetVT == MVT::f128) 197 return FPEXT_F80_F128; 198 } 199 200 return UNKNOWN_LIBCALL; 201 } 202 203 /// getFPROUND - Return the FPROUND_*_* value for the given types, or 204 /// UNKNOWN_LIBCALL if there is none. 205 RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) { 206 if (RetVT == MVT::f16) { 207 if (OpVT == MVT::f32) 208 return FPROUND_F32_F16; 209 if (OpVT == MVT::f64) 210 return FPROUND_F64_F16; 211 if (OpVT == MVT::f80) 212 return FPROUND_F80_F16; 213 if (OpVT == MVT::f128) 214 return FPROUND_F128_F16; 215 if (OpVT == MVT::ppcf128) 216 return FPROUND_PPCF128_F16; 217 } else if (RetVT == MVT::f32) { 218 if (OpVT == MVT::f64) 219 return FPROUND_F64_F32; 220 if (OpVT == MVT::f80) 221 return FPROUND_F80_F32; 222 if (OpVT == MVT::f128) 223 return FPROUND_F128_F32; 224 if (OpVT == MVT::ppcf128) 225 return FPROUND_PPCF128_F32; 226 } else if (RetVT == MVT::f64) { 227 if (OpVT == MVT::f80) 228 return FPROUND_F80_F64; 229 if (OpVT == MVT::f128) 230 return FPROUND_F128_F64; 231 if (OpVT == MVT::ppcf128) 232 return FPROUND_PPCF128_F64; 233 } else if (RetVT == MVT::f80) { 234 if (OpVT == MVT::f128) 235 return FPROUND_F128_F80; 236 } 237 238 return UNKNOWN_LIBCALL; 239 } 240 241 /// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or 242 /// UNKNOWN_LIBCALL if there is none. 243 RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT, EVT RetVT) { 244 if (OpVT == MVT::f32) { 245 if (RetVT == MVT::i32) 246 return FPTOSINT_F32_I32; 247 if (RetVT == MVT::i64) 248 return FPTOSINT_F32_I64; 249 if (RetVT == MVT::i128) 250 return FPTOSINT_F32_I128; 251 } else if (OpVT == MVT::f64) { 252 if (RetVT == MVT::i32) 253 return FPTOSINT_F64_I32; 254 if (RetVT == MVT::i64) 255 return FPTOSINT_F64_I64; 256 if (RetVT == MVT::i128) 257 return FPTOSINT_F64_I128; 258 } else if (OpVT == MVT::f80) { 259 if (RetVT == MVT::i32) 260 return FPTOSINT_F80_I32; 261 if (RetVT == MVT::i64) 262 return FPTOSINT_F80_I64; 263 if (RetVT == MVT::i128) 264 return FPTOSINT_F80_I128; 265 } else if (OpVT == MVT::f128) { 266 if (RetVT == MVT::i32) 267 return FPTOSINT_F128_I32; 268 if (RetVT == MVT::i64) 269 return FPTOSINT_F128_I64; 270 if (RetVT == MVT::i128) 271 return FPTOSINT_F128_I128; 272 } else if (OpVT == MVT::ppcf128) { 273 if (RetVT == MVT::i32) 274 return FPTOSINT_PPCF128_I32; 275 if (RetVT == MVT::i64) 276 return FPTOSINT_PPCF128_I64; 277 if (RetVT == MVT::i128) 278 return FPTOSINT_PPCF128_I128; 279 } 280 return UNKNOWN_LIBCALL; 281 } 282 283 /// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or 284 /// UNKNOWN_LIBCALL if there is none. 285 RTLIB::Libcall RTLIB::getFPTOUINT(EVT OpVT, EVT RetVT) { 286 if (OpVT == MVT::f32) { 287 if (RetVT == MVT::i32) 288 return FPTOUINT_F32_I32; 289 if (RetVT == MVT::i64) 290 return FPTOUINT_F32_I64; 291 if (RetVT == MVT::i128) 292 return FPTOUINT_F32_I128; 293 } else if (OpVT == MVT::f64) { 294 if (RetVT == MVT::i32) 295 return FPTOUINT_F64_I32; 296 if (RetVT == MVT::i64) 297 return FPTOUINT_F64_I64; 298 if (RetVT == MVT::i128) 299 return FPTOUINT_F64_I128; 300 } else if (OpVT == MVT::f80) { 301 if (RetVT == MVT::i32) 302 return FPTOUINT_F80_I32; 303 if (RetVT == MVT::i64) 304 return FPTOUINT_F80_I64; 305 if (RetVT == MVT::i128) 306 return FPTOUINT_F80_I128; 307 } else if (OpVT == MVT::f128) { 308 if (RetVT == MVT::i32) 309 return FPTOUINT_F128_I32; 310 if (RetVT == MVT::i64) 311 return FPTOUINT_F128_I64; 312 if (RetVT == MVT::i128) 313 return FPTOUINT_F128_I128; 314 } else if (OpVT == MVT::ppcf128) { 315 if (RetVT == MVT::i32) 316 return FPTOUINT_PPCF128_I32; 317 if (RetVT == MVT::i64) 318 return FPTOUINT_PPCF128_I64; 319 if (RetVT == MVT::i128) 320 return FPTOUINT_PPCF128_I128; 321 } 322 return UNKNOWN_LIBCALL; 323 } 324 325 /// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or 326 /// UNKNOWN_LIBCALL if there is none. 327 RTLIB::Libcall RTLIB::getSINTTOFP(EVT OpVT, EVT RetVT) { 328 if (OpVT == MVT::i32) { 329 if (RetVT == MVT::f32) 330 return SINTTOFP_I32_F32; 331 if (RetVT == MVT::f64) 332 return SINTTOFP_I32_F64; 333 if (RetVT == MVT::f80) 334 return SINTTOFP_I32_F80; 335 if (RetVT == MVT::f128) 336 return SINTTOFP_I32_F128; 337 if (RetVT == MVT::ppcf128) 338 return SINTTOFP_I32_PPCF128; 339 } else if (OpVT == MVT::i64) { 340 if (RetVT == MVT::f32) 341 return SINTTOFP_I64_F32; 342 if (RetVT == MVT::f64) 343 return SINTTOFP_I64_F64; 344 if (RetVT == MVT::f80) 345 return SINTTOFP_I64_F80; 346 if (RetVT == MVT::f128) 347 return SINTTOFP_I64_F128; 348 if (RetVT == MVT::ppcf128) 349 return SINTTOFP_I64_PPCF128; 350 } else if (OpVT == MVT::i128) { 351 if (RetVT == MVT::f32) 352 return SINTTOFP_I128_F32; 353 if (RetVT == MVT::f64) 354 return SINTTOFP_I128_F64; 355 if (RetVT == MVT::f80) 356 return SINTTOFP_I128_F80; 357 if (RetVT == MVT::f128) 358 return SINTTOFP_I128_F128; 359 if (RetVT == MVT::ppcf128) 360 return SINTTOFP_I128_PPCF128; 361 } 362 return UNKNOWN_LIBCALL; 363 } 364 365 /// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or 366 /// UNKNOWN_LIBCALL if there is none. 367 RTLIB::Libcall RTLIB::getUINTTOFP(EVT OpVT, EVT RetVT) { 368 if (OpVT == MVT::i32) { 369 if (RetVT == MVT::f32) 370 return UINTTOFP_I32_F32; 371 if (RetVT == MVT::f64) 372 return UINTTOFP_I32_F64; 373 if (RetVT == MVT::f80) 374 return UINTTOFP_I32_F80; 375 if (RetVT == MVT::f128) 376 return UINTTOFP_I32_F128; 377 if (RetVT == MVT::ppcf128) 378 return UINTTOFP_I32_PPCF128; 379 } else if (OpVT == MVT::i64) { 380 if (RetVT == MVT::f32) 381 return UINTTOFP_I64_F32; 382 if (RetVT == MVT::f64) 383 return UINTTOFP_I64_F64; 384 if (RetVT == MVT::f80) 385 return UINTTOFP_I64_F80; 386 if (RetVT == MVT::f128) 387 return UINTTOFP_I64_F128; 388 if (RetVT == MVT::ppcf128) 389 return UINTTOFP_I64_PPCF128; 390 } else if (OpVT == MVT::i128) { 391 if (RetVT == MVT::f32) 392 return UINTTOFP_I128_F32; 393 if (RetVT == MVT::f64) 394 return UINTTOFP_I128_F64; 395 if (RetVT == MVT::f80) 396 return UINTTOFP_I128_F80; 397 if (RetVT == MVT::f128) 398 return UINTTOFP_I128_F128; 399 if (RetVT == MVT::ppcf128) 400 return UINTTOFP_I128_PPCF128; 401 } 402 return UNKNOWN_LIBCALL; 403 } 404 405 RTLIB::Libcall RTLIB::getSYNC(unsigned Opc, MVT VT) { 406 #define OP_TO_LIBCALL(Name, Enum) \ 407 case Name: \ 408 switch (VT.SimpleTy) { \ 409 default: \ 410 return UNKNOWN_LIBCALL; \ 411 case MVT::i8: \ 412 return Enum##_1; \ 413 case MVT::i16: \ 414 return Enum##_2; \ 415 case MVT::i32: \ 416 return Enum##_4; \ 417 case MVT::i64: \ 418 return Enum##_8; \ 419 case MVT::i128: \ 420 return Enum##_16; \ 421 } 422 423 switch (Opc) { 424 OP_TO_LIBCALL(ISD::ATOMIC_SWAP, SYNC_LOCK_TEST_AND_SET) 425 OP_TO_LIBCALL(ISD::ATOMIC_CMP_SWAP, SYNC_VAL_COMPARE_AND_SWAP) 426 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_ADD, SYNC_FETCH_AND_ADD) 427 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_SUB, SYNC_FETCH_AND_SUB) 428 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_AND, SYNC_FETCH_AND_AND) 429 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_OR, SYNC_FETCH_AND_OR) 430 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_XOR, SYNC_FETCH_AND_XOR) 431 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_NAND, SYNC_FETCH_AND_NAND) 432 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_MAX, SYNC_FETCH_AND_MAX) 433 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_UMAX, SYNC_FETCH_AND_UMAX) 434 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_MIN, SYNC_FETCH_AND_MIN) 435 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_UMIN, SYNC_FETCH_AND_UMIN) 436 } 437 438 #undef OP_TO_LIBCALL 439 440 return UNKNOWN_LIBCALL; 441 } 442 443 RTLIB::Libcall RTLIB::getMEMCPY_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize) { 444 switch (ElementSize) { 445 case 1: 446 return MEMCPY_ELEMENT_UNORDERED_ATOMIC_1; 447 case 2: 448 return MEMCPY_ELEMENT_UNORDERED_ATOMIC_2; 449 case 4: 450 return MEMCPY_ELEMENT_UNORDERED_ATOMIC_4; 451 case 8: 452 return MEMCPY_ELEMENT_UNORDERED_ATOMIC_8; 453 case 16: 454 return MEMCPY_ELEMENT_UNORDERED_ATOMIC_16; 455 default: 456 return UNKNOWN_LIBCALL; 457 } 458 } 459 460 RTLIB::Libcall RTLIB::getMEMMOVE_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize) { 461 switch (ElementSize) { 462 case 1: 463 return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_1; 464 case 2: 465 return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_2; 466 case 4: 467 return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_4; 468 case 8: 469 return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_8; 470 case 16: 471 return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_16; 472 default: 473 return UNKNOWN_LIBCALL; 474 } 475 } 476 477 RTLIB::Libcall RTLIB::getMEMSET_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize) { 478 switch (ElementSize) { 479 case 1: 480 return MEMSET_ELEMENT_UNORDERED_ATOMIC_1; 481 case 2: 482 return MEMSET_ELEMENT_UNORDERED_ATOMIC_2; 483 case 4: 484 return MEMSET_ELEMENT_UNORDERED_ATOMIC_4; 485 case 8: 486 return MEMSET_ELEMENT_UNORDERED_ATOMIC_8; 487 case 16: 488 return MEMSET_ELEMENT_UNORDERED_ATOMIC_16; 489 default: 490 return UNKNOWN_LIBCALL; 491 } 492 } 493 494 /// InitCmpLibcallCCs - Set default comparison libcall CC. 495 static void InitCmpLibcallCCs(ISD::CondCode *CCs) { 496 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL); 497 CCs[RTLIB::OEQ_F32] = ISD::SETEQ; 498 CCs[RTLIB::OEQ_F64] = ISD::SETEQ; 499 CCs[RTLIB::OEQ_F128] = ISD::SETEQ; 500 CCs[RTLIB::OEQ_PPCF128] = ISD::SETEQ; 501 CCs[RTLIB::UNE_F32] = ISD::SETNE; 502 CCs[RTLIB::UNE_F64] = ISD::SETNE; 503 CCs[RTLIB::UNE_F128] = ISD::SETNE; 504 CCs[RTLIB::UNE_PPCF128] = ISD::SETNE; 505 CCs[RTLIB::OGE_F32] = ISD::SETGE; 506 CCs[RTLIB::OGE_F64] = ISD::SETGE; 507 CCs[RTLIB::OGE_F128] = ISD::SETGE; 508 CCs[RTLIB::OGE_PPCF128] = ISD::SETGE; 509 CCs[RTLIB::OLT_F32] = ISD::SETLT; 510 CCs[RTLIB::OLT_F64] = ISD::SETLT; 511 CCs[RTLIB::OLT_F128] = ISD::SETLT; 512 CCs[RTLIB::OLT_PPCF128] = ISD::SETLT; 513 CCs[RTLIB::OLE_F32] = ISD::SETLE; 514 CCs[RTLIB::OLE_F64] = ISD::SETLE; 515 CCs[RTLIB::OLE_F128] = ISD::SETLE; 516 CCs[RTLIB::OLE_PPCF128] = ISD::SETLE; 517 CCs[RTLIB::OGT_F32] = ISD::SETGT; 518 CCs[RTLIB::OGT_F64] = ISD::SETGT; 519 CCs[RTLIB::OGT_F128] = ISD::SETGT; 520 CCs[RTLIB::OGT_PPCF128] = ISD::SETGT; 521 CCs[RTLIB::UO_F32] = ISD::SETNE; 522 CCs[RTLIB::UO_F64] = ISD::SETNE; 523 CCs[RTLIB::UO_F128] = ISD::SETNE; 524 CCs[RTLIB::UO_PPCF128] = ISD::SETNE; 525 CCs[RTLIB::O_F32] = ISD::SETEQ; 526 CCs[RTLIB::O_F64] = ISD::SETEQ; 527 CCs[RTLIB::O_F128] = ISD::SETEQ; 528 CCs[RTLIB::O_PPCF128] = ISD::SETEQ; 529 } 530 531 /// NOTE: The TargetMachine owns TLOF. 532 TargetLoweringBase::TargetLoweringBase(const TargetMachine &tm) : TM(tm) { 533 initActions(); 534 535 // Perform these initializations only once. 536 MaxStoresPerMemset = MaxStoresPerMemcpy = MaxStoresPerMemmove = 537 MaxLoadsPerMemcmp = 8; 538 MaxGluedStoresPerMemcpy = 0; 539 MaxStoresPerMemsetOptSize = MaxStoresPerMemcpyOptSize = 540 MaxStoresPerMemmoveOptSize = MaxLoadsPerMemcmpOptSize = 4; 541 UseUnderscoreSetJmp = false; 542 UseUnderscoreLongJmp = false; 543 HasMultipleConditionRegisters = false; 544 HasExtractBitsInsn = false; 545 JumpIsExpensive = JumpIsExpensiveOverride; 546 PredictableSelectIsExpensive = false; 547 EnableExtLdPromotion = false; 548 StackPointerRegisterToSaveRestore = 0; 549 BooleanContents = UndefinedBooleanContent; 550 BooleanFloatContents = UndefinedBooleanContent; 551 BooleanVectorContents = UndefinedBooleanContent; 552 SchedPreferenceInfo = Sched::ILP; 553 JumpBufSize = 0; 554 JumpBufAlignment = 0; 555 MinFunctionAlignment = 0; 556 PrefFunctionAlignment = 0; 557 PrefLoopAlignment = 0; 558 GatherAllAliasesMaxDepth = 18; 559 MinStackArgumentAlignment = 1; 560 // TODO: the default will be switched to 0 in the next commit, along 561 // with the Target-specific changes necessary. 562 MaxAtomicSizeInBitsSupported = 1024; 563 564 MinCmpXchgSizeInBits = 0; 565 SupportsUnalignedAtomics = false; 566 567 std::fill(std::begin(LibcallRoutineNames), std::end(LibcallRoutineNames), nullptr); 568 569 InitLibcalls(TM.getTargetTriple()); 570 InitCmpLibcallCCs(CmpLibcallCCs); 571 } 572 573 void TargetLoweringBase::initActions() { 574 // All operations default to being supported. 575 memset(OpActions, 0, sizeof(OpActions)); 576 memset(LoadExtActions, 0, sizeof(LoadExtActions)); 577 memset(TruncStoreActions, 0, sizeof(TruncStoreActions)); 578 memset(IndexedModeActions, 0, sizeof(IndexedModeActions)); 579 memset(CondCodeActions, 0, sizeof(CondCodeActions)); 580 std::fill(std::begin(RegClassForVT), std::end(RegClassForVT), nullptr); 581 std::fill(std::begin(TargetDAGCombineArray), 582 std::end(TargetDAGCombineArray), 0); 583 584 for (MVT VT : MVT::fp_valuetypes()) { 585 MVT IntVT = MVT::getIntegerVT(VT.getSizeInBits()); 586 if (IntVT.isValid()) { 587 setOperationAction(ISD::ATOMIC_SWAP, VT, Promote); 588 AddPromotedToType(ISD::ATOMIC_SWAP, VT, IntVT); 589 } 590 } 591 592 // Set default actions for various operations. 593 for (MVT VT : MVT::all_valuetypes()) { 594 // Default all indexed load / store to expand. 595 for (unsigned IM = (unsigned)ISD::PRE_INC; 596 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) { 597 setIndexedLoadAction(IM, VT, Expand); 598 setIndexedStoreAction(IM, VT, Expand); 599 } 600 601 // Most backends expect to see the node which just returns the value loaded. 602 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Expand); 603 604 // These operations default to expand. 605 setOperationAction(ISD::FGETSIGN, VT, Expand); 606 setOperationAction(ISD::CONCAT_VECTORS, VT, Expand); 607 setOperationAction(ISD::FMINNUM, VT, Expand); 608 setOperationAction(ISD::FMAXNUM, VT, Expand); 609 setOperationAction(ISD::FMINNUM_IEEE, VT, Expand); 610 setOperationAction(ISD::FMAXNUM_IEEE, VT, Expand); 611 setOperationAction(ISD::FMINIMUM, VT, Expand); 612 setOperationAction(ISD::FMAXIMUM, VT, Expand); 613 setOperationAction(ISD::FMAD, VT, Expand); 614 setOperationAction(ISD::SMIN, VT, Expand); 615 setOperationAction(ISD::SMAX, VT, Expand); 616 setOperationAction(ISD::UMIN, VT, Expand); 617 setOperationAction(ISD::UMAX, VT, Expand); 618 setOperationAction(ISD::ABS, VT, Expand); 619 setOperationAction(ISD::FSHL, VT, Expand); 620 setOperationAction(ISD::FSHR, VT, Expand); 621 setOperationAction(ISD::SADDSAT, VT, Expand); 622 setOperationAction(ISD::UADDSAT, VT, Expand); 623 setOperationAction(ISD::SSUBSAT, VT, Expand); 624 setOperationAction(ISD::USUBSAT, VT, Expand); 625 setOperationAction(ISD::SMULFIX, VT, Expand); 626 setOperationAction(ISD::SMULFIXSAT, VT, Expand); 627 setOperationAction(ISD::UMULFIX, VT, Expand); 628 629 // Overflow operations default to expand 630 setOperationAction(ISD::SADDO, VT, Expand); 631 setOperationAction(ISD::SSUBO, VT, Expand); 632 setOperationAction(ISD::UADDO, VT, Expand); 633 setOperationAction(ISD::USUBO, VT, Expand); 634 setOperationAction(ISD::SMULO, VT, Expand); 635 setOperationAction(ISD::UMULO, VT, Expand); 636 637 // ADDCARRY operations default to expand 638 setOperationAction(ISD::ADDCARRY, VT, Expand); 639 setOperationAction(ISD::SUBCARRY, VT, Expand); 640 setOperationAction(ISD::SETCCCARRY, VT, Expand); 641 642 // ADDC/ADDE/SUBC/SUBE default to expand. 643 setOperationAction(ISD::ADDC, VT, Expand); 644 setOperationAction(ISD::ADDE, VT, Expand); 645 setOperationAction(ISD::SUBC, VT, Expand); 646 setOperationAction(ISD::SUBE, VT, Expand); 647 648 // These default to Expand so they will be expanded to CTLZ/CTTZ by default. 649 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand); 650 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand); 651 652 setOperationAction(ISD::BITREVERSE, VT, Expand); 653 654 // These library functions default to expand. 655 setOperationAction(ISD::FROUND, VT, Expand); 656 setOperationAction(ISD::FPOWI, VT, Expand); 657 658 // These operations default to expand for vector types. 659 if (VT.isVector()) { 660 setOperationAction(ISD::FCOPYSIGN, VT, Expand); 661 setOperationAction(ISD::ANY_EXTEND_VECTOR_INREG, VT, Expand); 662 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, VT, Expand); 663 setOperationAction(ISD::ZERO_EXTEND_VECTOR_INREG, VT, Expand); 664 } 665 666 // Constrained floating-point operations default to expand. 667 setOperationAction(ISD::STRICT_FADD, VT, Expand); 668 setOperationAction(ISD::STRICT_FSUB, VT, Expand); 669 setOperationAction(ISD::STRICT_FMUL, VT, Expand); 670 setOperationAction(ISD::STRICT_FDIV, VT, Expand); 671 setOperationAction(ISD::STRICT_FREM, VT, Expand); 672 setOperationAction(ISD::STRICT_FMA, VT, Expand); 673 setOperationAction(ISD::STRICT_FSQRT, VT, Expand); 674 setOperationAction(ISD::STRICT_FPOW, VT, Expand); 675 setOperationAction(ISD::STRICT_FPOWI, VT, Expand); 676 setOperationAction(ISD::STRICT_FSIN, VT, Expand); 677 setOperationAction(ISD::STRICT_FCOS, VT, Expand); 678 setOperationAction(ISD::STRICT_FEXP, VT, Expand); 679 setOperationAction(ISD::STRICT_FEXP2, VT, Expand); 680 setOperationAction(ISD::STRICT_FLOG, VT, Expand); 681 setOperationAction(ISD::STRICT_FLOG10, VT, Expand); 682 setOperationAction(ISD::STRICT_FLOG2, VT, Expand); 683 setOperationAction(ISD::STRICT_FRINT, VT, Expand); 684 setOperationAction(ISD::STRICT_FNEARBYINT, VT, Expand); 685 setOperationAction(ISD::STRICT_FCEIL, VT, Expand); 686 setOperationAction(ISD::STRICT_FFLOOR, VT, Expand); 687 setOperationAction(ISD::STRICT_FROUND, VT, Expand); 688 setOperationAction(ISD::STRICT_FTRUNC, VT, Expand); 689 setOperationAction(ISD::STRICT_FMAXNUM, VT, Expand); 690 setOperationAction(ISD::STRICT_FMINNUM, VT, Expand); 691 setOperationAction(ISD::STRICT_FP_ROUND, VT, Expand); 692 setOperationAction(ISD::STRICT_FP_EXTEND, VT, Expand); 693 694 // For most targets @llvm.get.dynamic.area.offset just returns 0. 695 setOperationAction(ISD::GET_DYNAMIC_AREA_OFFSET, VT, Expand); 696 697 // Vector reduction default to expand. 698 setOperationAction(ISD::VECREDUCE_FADD, VT, Expand); 699 setOperationAction(ISD::VECREDUCE_FMUL, VT, Expand); 700 setOperationAction(ISD::VECREDUCE_ADD, VT, Expand); 701 setOperationAction(ISD::VECREDUCE_MUL, VT, Expand); 702 setOperationAction(ISD::VECREDUCE_AND, VT, Expand); 703 setOperationAction(ISD::VECREDUCE_OR, VT, Expand); 704 setOperationAction(ISD::VECREDUCE_XOR, VT, Expand); 705 setOperationAction(ISD::VECREDUCE_SMAX, VT, Expand); 706 setOperationAction(ISD::VECREDUCE_SMIN, VT, Expand); 707 setOperationAction(ISD::VECREDUCE_UMAX, VT, Expand); 708 setOperationAction(ISD::VECREDUCE_UMIN, VT, Expand); 709 setOperationAction(ISD::VECREDUCE_FMAX, VT, Expand); 710 setOperationAction(ISD::VECREDUCE_FMIN, VT, Expand); 711 } 712 713 // Most targets ignore the @llvm.prefetch intrinsic. 714 setOperationAction(ISD::PREFETCH, MVT::Other, Expand); 715 716 // Most targets also ignore the @llvm.readcyclecounter intrinsic. 717 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Expand); 718 719 // ConstantFP nodes default to expand. Targets can either change this to 720 // Legal, in which case all fp constants are legal, or use isFPImmLegal() 721 // to optimize expansions for certain constants. 722 setOperationAction(ISD::ConstantFP, MVT::f16, Expand); 723 setOperationAction(ISD::ConstantFP, MVT::f32, Expand); 724 setOperationAction(ISD::ConstantFP, MVT::f64, Expand); 725 setOperationAction(ISD::ConstantFP, MVT::f80, Expand); 726 setOperationAction(ISD::ConstantFP, MVT::f128, Expand); 727 728 // These library functions default to expand. 729 for (MVT VT : {MVT::f32, MVT::f64, MVT::f128}) { 730 setOperationAction(ISD::FCBRT, VT, Expand); 731 setOperationAction(ISD::FLOG , VT, Expand); 732 setOperationAction(ISD::FLOG2, VT, Expand); 733 setOperationAction(ISD::FLOG10, VT, Expand); 734 setOperationAction(ISD::FEXP , VT, Expand); 735 setOperationAction(ISD::FEXP2, VT, Expand); 736 setOperationAction(ISD::FFLOOR, VT, Expand); 737 setOperationAction(ISD::FNEARBYINT, VT, Expand); 738 setOperationAction(ISD::FCEIL, VT, Expand); 739 setOperationAction(ISD::FRINT, VT, Expand); 740 setOperationAction(ISD::FTRUNC, VT, Expand); 741 setOperationAction(ISD::FROUND, VT, Expand); 742 setOperationAction(ISD::LROUND, VT, Expand); 743 setOperationAction(ISD::LLROUND, VT, Expand); 744 setOperationAction(ISD::LRINT, VT, Expand); 745 setOperationAction(ISD::LLRINT, VT, Expand); 746 } 747 748 // Default ISD::TRAP to expand (which turns it into abort). 749 setOperationAction(ISD::TRAP, MVT::Other, Expand); 750 751 // On most systems, DEBUGTRAP and TRAP have no difference. The "Expand" 752 // here is to inform DAG Legalizer to replace DEBUGTRAP with TRAP. 753 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Expand); 754 } 755 756 MVT TargetLoweringBase::getScalarShiftAmountTy(const DataLayout &DL, 757 EVT) const { 758 return MVT::getIntegerVT(DL.getPointerSizeInBits(0)); 759 } 760 761 EVT TargetLoweringBase::getShiftAmountTy(EVT LHSTy, const DataLayout &DL, 762 bool LegalTypes) const { 763 assert(LHSTy.isInteger() && "Shift amount is not an integer type!"); 764 if (LHSTy.isVector()) 765 return LHSTy; 766 return LegalTypes ? getScalarShiftAmountTy(DL, LHSTy) 767 : getPointerTy(DL); 768 } 769 770 bool TargetLoweringBase::canOpTrap(unsigned Op, EVT VT) const { 771 assert(isTypeLegal(VT)); 772 switch (Op) { 773 default: 774 return false; 775 case ISD::SDIV: 776 case ISD::UDIV: 777 case ISD::SREM: 778 case ISD::UREM: 779 return true; 780 } 781 } 782 783 void TargetLoweringBase::setJumpIsExpensive(bool isExpensive) { 784 // If the command-line option was specified, ignore this request. 785 if (!JumpIsExpensiveOverride.getNumOccurrences()) 786 JumpIsExpensive = isExpensive; 787 } 788 789 TargetLoweringBase::LegalizeKind 790 TargetLoweringBase::getTypeConversion(LLVMContext &Context, EVT VT) const { 791 // If this is a simple type, use the ComputeRegisterProp mechanism. 792 if (VT.isSimple()) { 793 MVT SVT = VT.getSimpleVT(); 794 assert((unsigned)SVT.SimpleTy < array_lengthof(TransformToType)); 795 MVT NVT = TransformToType[SVT.SimpleTy]; 796 LegalizeTypeAction LA = ValueTypeActions.getTypeAction(SVT); 797 798 assert((LA == TypeLegal || LA == TypeSoftenFloat || 799 ValueTypeActions.getTypeAction(NVT) != TypePromoteInteger) && 800 "Promote may not follow Expand or Promote"); 801 802 if (LA == TypeSplitVector) 803 return LegalizeKind(LA, 804 EVT::getVectorVT(Context, SVT.getVectorElementType(), 805 SVT.getVectorNumElements() / 2)); 806 if (LA == TypeScalarizeVector) 807 return LegalizeKind(LA, SVT.getVectorElementType()); 808 return LegalizeKind(LA, NVT); 809 } 810 811 // Handle Extended Scalar Types. 812 if (!VT.isVector()) { 813 assert(VT.isInteger() && "Float types must be simple"); 814 unsigned BitSize = VT.getSizeInBits(); 815 // First promote to a power-of-two size, then expand if necessary. 816 if (BitSize < 8 || !isPowerOf2_32(BitSize)) { 817 EVT NVT = VT.getRoundIntegerType(Context); 818 assert(NVT != VT && "Unable to round integer VT"); 819 LegalizeKind NextStep = getTypeConversion(Context, NVT); 820 // Avoid multi-step promotion. 821 if (NextStep.first == TypePromoteInteger) 822 return NextStep; 823 // Return rounded integer type. 824 return LegalizeKind(TypePromoteInteger, NVT); 825 } 826 827 return LegalizeKind(TypeExpandInteger, 828 EVT::getIntegerVT(Context, VT.getSizeInBits() / 2)); 829 } 830 831 // Handle vector types. 832 unsigned NumElts = VT.getVectorNumElements(); 833 EVT EltVT = VT.getVectorElementType(); 834 835 // Vectors with only one element are always scalarized. 836 if (NumElts == 1) 837 return LegalizeKind(TypeScalarizeVector, EltVT); 838 839 // Try to widen vector elements until the element type is a power of two and 840 // promote it to a legal type later on, for example: 841 // <3 x i8> -> <4 x i8> -> <4 x i32> 842 if (EltVT.isInteger()) { 843 // Vectors with a number of elements that is not a power of two are always 844 // widened, for example <3 x i8> -> <4 x i8>. 845 if (!VT.isPow2VectorType()) { 846 NumElts = (unsigned)NextPowerOf2(NumElts); 847 EVT NVT = EVT::getVectorVT(Context, EltVT, NumElts); 848 return LegalizeKind(TypeWidenVector, NVT); 849 } 850 851 // Examine the element type. 852 LegalizeKind LK = getTypeConversion(Context, EltVT); 853 854 // If type is to be expanded, split the vector. 855 // <4 x i140> -> <2 x i140> 856 if (LK.first == TypeExpandInteger) 857 return LegalizeKind(TypeSplitVector, 858 EVT::getVectorVT(Context, EltVT, NumElts / 2)); 859 860 // Promote the integer element types until a legal vector type is found 861 // or until the element integer type is too big. If a legal type was not 862 // found, fallback to the usual mechanism of widening/splitting the 863 // vector. 864 EVT OldEltVT = EltVT; 865 while (true) { 866 // Increase the bitwidth of the element to the next pow-of-two 867 // (which is greater than 8 bits). 868 EltVT = EVT::getIntegerVT(Context, 1 + EltVT.getSizeInBits()) 869 .getRoundIntegerType(Context); 870 871 // Stop trying when getting a non-simple element type. 872 // Note that vector elements may be greater than legal vector element 873 // types. Example: X86 XMM registers hold 64bit element on 32bit 874 // systems. 875 if (!EltVT.isSimple()) 876 break; 877 878 // Build a new vector type and check if it is legal. 879 MVT NVT = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts); 880 // Found a legal promoted vector type. 881 if (NVT != MVT() && ValueTypeActions.getTypeAction(NVT) == TypeLegal) 882 return LegalizeKind(TypePromoteInteger, 883 EVT::getVectorVT(Context, EltVT, NumElts)); 884 } 885 886 // Reset the type to the unexpanded type if we did not find a legal vector 887 // type with a promoted vector element type. 888 EltVT = OldEltVT; 889 } 890 891 // Try to widen the vector until a legal type is found. 892 // If there is no wider legal type, split the vector. 893 while (true) { 894 // Round up to the next power of 2. 895 NumElts = (unsigned)NextPowerOf2(NumElts); 896 897 // If there is no simple vector type with this many elements then there 898 // cannot be a larger legal vector type. Note that this assumes that 899 // there are no skipped intermediate vector types in the simple types. 900 if (!EltVT.isSimple()) 901 break; 902 MVT LargerVector = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts); 903 if (LargerVector == MVT()) 904 break; 905 906 // If this type is legal then widen the vector. 907 if (ValueTypeActions.getTypeAction(LargerVector) == TypeLegal) 908 return LegalizeKind(TypeWidenVector, LargerVector); 909 } 910 911 // Widen odd vectors to next power of two. 912 if (!VT.isPow2VectorType()) { 913 EVT NVT = VT.getPow2VectorType(Context); 914 return LegalizeKind(TypeWidenVector, NVT); 915 } 916 917 // Vectors with illegal element types are expanded. 918 EVT NVT = EVT::getVectorVT(Context, EltVT, VT.getVectorNumElements() / 2); 919 return LegalizeKind(TypeSplitVector, NVT); 920 } 921 922 static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT, 923 unsigned &NumIntermediates, 924 MVT &RegisterVT, 925 TargetLoweringBase *TLI) { 926 // Figure out the right, legal destination reg to copy into. 927 unsigned NumElts = VT.getVectorNumElements(); 928 MVT EltTy = VT.getVectorElementType(); 929 930 unsigned NumVectorRegs = 1; 931 932 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we 933 // could break down into LHS/RHS like LegalizeDAG does. 934 if (!isPowerOf2_32(NumElts)) { 935 NumVectorRegs = NumElts; 936 NumElts = 1; 937 } 938 939 // Divide the input until we get to a supported size. This will always 940 // end with a scalar if the target doesn't support vectors. 941 while (NumElts > 1 && !TLI->isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) { 942 NumElts >>= 1; 943 NumVectorRegs <<= 1; 944 } 945 946 NumIntermediates = NumVectorRegs; 947 948 MVT NewVT = MVT::getVectorVT(EltTy, NumElts); 949 if (!TLI->isTypeLegal(NewVT)) 950 NewVT = EltTy; 951 IntermediateVT = NewVT; 952 953 unsigned NewVTSize = NewVT.getSizeInBits(); 954 955 // Convert sizes such as i33 to i64. 956 if (!isPowerOf2_32(NewVTSize)) 957 NewVTSize = NextPowerOf2(NewVTSize); 958 959 MVT DestVT = TLI->getRegisterType(NewVT); 960 RegisterVT = DestVT; 961 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16. 962 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits()); 963 964 // Otherwise, promotion or legal types use the same number of registers as 965 // the vector decimated to the appropriate level. 966 return NumVectorRegs; 967 } 968 969 /// isLegalRC - Return true if the value types that can be represented by the 970 /// specified register class are all legal. 971 bool TargetLoweringBase::isLegalRC(const TargetRegisterInfo &TRI, 972 const TargetRegisterClass &RC) const { 973 for (auto I = TRI.legalclasstypes_begin(RC); *I != MVT::Other; ++I) 974 if (isTypeLegal(*I)) 975 return true; 976 return false; 977 } 978 979 /// Replace/modify any TargetFrameIndex operands with a targte-dependent 980 /// sequence of memory operands that is recognized by PrologEpilogInserter. 981 MachineBasicBlock * 982 TargetLoweringBase::emitPatchPoint(MachineInstr &InitialMI, 983 MachineBasicBlock *MBB) const { 984 MachineInstr *MI = &InitialMI; 985 MachineFunction &MF = *MI->getMF(); 986 MachineFrameInfo &MFI = MF.getFrameInfo(); 987 988 // We're handling multiple types of operands here: 989 // PATCHPOINT MetaArgs - live-in, read only, direct 990 // STATEPOINT Deopt Spill - live-through, read only, indirect 991 // STATEPOINT Deopt Alloca - live-through, read only, direct 992 // (We're currently conservative and mark the deopt slots read/write in 993 // practice.) 994 // STATEPOINT GC Spill - live-through, read/write, indirect 995 // STATEPOINT GC Alloca - live-through, read/write, direct 996 // The live-in vs live-through is handled already (the live through ones are 997 // all stack slots), but we need to handle the different type of stackmap 998 // operands and memory effects here. 999 1000 // MI changes inside this loop as we grow operands. 1001 for(unsigned OperIdx = 0; OperIdx != MI->getNumOperands(); ++OperIdx) { 1002 MachineOperand &MO = MI->getOperand(OperIdx); 1003 if (!MO.isFI()) 1004 continue; 1005 1006 // foldMemoryOperand builds a new MI after replacing a single FI operand 1007 // with the canonical set of five x86 addressing-mode operands. 1008 int FI = MO.getIndex(); 1009 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), MI->getDesc()); 1010 1011 // Copy operands before the frame-index. 1012 for (unsigned i = 0; i < OperIdx; ++i) 1013 MIB.add(MI->getOperand(i)); 1014 // Add frame index operands recognized by stackmaps.cpp 1015 if (MFI.isStatepointSpillSlotObjectIndex(FI)) { 1016 // indirect-mem-ref tag, size, #FI, offset. 1017 // Used for spills inserted by StatepointLowering. This codepath is not 1018 // used for patchpoints/stackmaps at all, for these spilling is done via 1019 // foldMemoryOperand callback only. 1020 assert(MI->getOpcode() == TargetOpcode::STATEPOINT && "sanity"); 1021 MIB.addImm(StackMaps::IndirectMemRefOp); 1022 MIB.addImm(MFI.getObjectSize(FI)); 1023 MIB.add(MI->getOperand(OperIdx)); 1024 MIB.addImm(0); 1025 } else { 1026 // direct-mem-ref tag, #FI, offset. 1027 // Used by patchpoint, and direct alloca arguments to statepoints 1028 MIB.addImm(StackMaps::DirectMemRefOp); 1029 MIB.add(MI->getOperand(OperIdx)); 1030 MIB.addImm(0); 1031 } 1032 // Copy the operands after the frame index. 1033 for (unsigned i = OperIdx + 1; i != MI->getNumOperands(); ++i) 1034 MIB.add(MI->getOperand(i)); 1035 1036 // Inherit previous memory operands. 1037 MIB.cloneMemRefs(*MI); 1038 assert(MIB->mayLoad() && "Folded a stackmap use to a non-load!"); 1039 1040 // Add a new memory operand for this FI. 1041 assert(MFI.getObjectOffset(FI) != -1); 1042 1043 // Note: STATEPOINT MMOs are added during SelectionDAG. STACKMAP, and 1044 // PATCHPOINT should be updated to do the same. (TODO) 1045 if (MI->getOpcode() != TargetOpcode::STATEPOINT) { 1046 auto Flags = MachineMemOperand::MOLoad; 1047 MachineMemOperand *MMO = MF.getMachineMemOperand( 1048 MachinePointerInfo::getFixedStack(MF, FI), Flags, 1049 MF.getDataLayout().getPointerSize(), MFI.getObjectAlignment(FI)); 1050 MIB->addMemOperand(MF, MMO); 1051 } 1052 1053 // Replace the instruction and update the operand index. 1054 MBB->insert(MachineBasicBlock::iterator(MI), MIB); 1055 OperIdx += (MIB->getNumOperands() - MI->getNumOperands()) - 1; 1056 MI->eraseFromParent(); 1057 MI = MIB; 1058 } 1059 return MBB; 1060 } 1061 1062 MachineBasicBlock * 1063 TargetLoweringBase::emitXRayCustomEvent(MachineInstr &MI, 1064 MachineBasicBlock *MBB) const { 1065 assert(MI.getOpcode() == TargetOpcode::PATCHABLE_EVENT_CALL && 1066 "Called emitXRayCustomEvent on the wrong MI!"); 1067 auto &MF = *MI.getMF(); 1068 auto MIB = BuildMI(MF, MI.getDebugLoc(), MI.getDesc()); 1069 for (unsigned OpIdx = 0; OpIdx != MI.getNumOperands(); ++OpIdx) 1070 MIB.add(MI.getOperand(OpIdx)); 1071 1072 MBB->insert(MachineBasicBlock::iterator(MI), MIB); 1073 MI.eraseFromParent(); 1074 return MBB; 1075 } 1076 1077 MachineBasicBlock * 1078 TargetLoweringBase::emitXRayTypedEvent(MachineInstr &MI, 1079 MachineBasicBlock *MBB) const { 1080 assert(MI.getOpcode() == TargetOpcode::PATCHABLE_TYPED_EVENT_CALL && 1081 "Called emitXRayTypedEvent on the wrong MI!"); 1082 auto &MF = *MI.getMF(); 1083 auto MIB = BuildMI(MF, MI.getDebugLoc(), MI.getDesc()); 1084 for (unsigned OpIdx = 0; OpIdx != MI.getNumOperands(); ++OpIdx) 1085 MIB.add(MI.getOperand(OpIdx)); 1086 1087 MBB->insert(MachineBasicBlock::iterator(MI), MIB); 1088 MI.eraseFromParent(); 1089 return MBB; 1090 } 1091 1092 /// findRepresentativeClass - Return the largest legal super-reg register class 1093 /// of the register class for the specified type and its associated "cost". 1094 // This function is in TargetLowering because it uses RegClassForVT which would 1095 // need to be moved to TargetRegisterInfo and would necessitate moving 1096 // isTypeLegal over as well - a massive change that would just require 1097 // TargetLowering having a TargetRegisterInfo class member that it would use. 1098 std::pair<const TargetRegisterClass *, uint8_t> 1099 TargetLoweringBase::findRepresentativeClass(const TargetRegisterInfo *TRI, 1100 MVT VT) const { 1101 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy]; 1102 if (!RC) 1103 return std::make_pair(RC, 0); 1104 1105 // Compute the set of all super-register classes. 1106 BitVector SuperRegRC(TRI->getNumRegClasses()); 1107 for (SuperRegClassIterator RCI(RC, TRI); RCI.isValid(); ++RCI) 1108 SuperRegRC.setBitsInMask(RCI.getMask()); 1109 1110 // Find the first legal register class with the largest spill size. 1111 const TargetRegisterClass *BestRC = RC; 1112 for (unsigned i : SuperRegRC.set_bits()) { 1113 const TargetRegisterClass *SuperRC = TRI->getRegClass(i); 1114 // We want the largest possible spill size. 1115 if (TRI->getSpillSize(*SuperRC) <= TRI->getSpillSize(*BestRC)) 1116 continue; 1117 if (!isLegalRC(*TRI, *SuperRC)) 1118 continue; 1119 BestRC = SuperRC; 1120 } 1121 return std::make_pair(BestRC, 1); 1122 } 1123 1124 /// computeRegisterProperties - Once all of the register classes are added, 1125 /// this allows us to compute derived properties we expose. 1126 void TargetLoweringBase::computeRegisterProperties( 1127 const TargetRegisterInfo *TRI) { 1128 static_assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE, 1129 "Too many value types for ValueTypeActions to hold!"); 1130 1131 // Everything defaults to needing one register. 1132 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) { 1133 NumRegistersForVT[i] = 1; 1134 RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i; 1135 } 1136 // ...except isVoid, which doesn't need any registers. 1137 NumRegistersForVT[MVT::isVoid] = 0; 1138 1139 // Find the largest integer register class. 1140 unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE; 1141 for (; RegClassForVT[LargestIntReg] == nullptr; --LargestIntReg) 1142 assert(LargestIntReg != MVT::i1 && "No integer registers defined!"); 1143 1144 // Every integer value type larger than this largest register takes twice as 1145 // many registers to represent as the previous ValueType. 1146 for (unsigned ExpandedReg = LargestIntReg + 1; 1147 ExpandedReg <= MVT::LAST_INTEGER_VALUETYPE; ++ExpandedReg) { 1148 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1]; 1149 RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg; 1150 TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1); 1151 ValueTypeActions.setTypeAction((MVT::SimpleValueType)ExpandedReg, 1152 TypeExpandInteger); 1153 } 1154 1155 // Inspect all of the ValueType's smaller than the largest integer 1156 // register to see which ones need promotion. 1157 unsigned LegalIntReg = LargestIntReg; 1158 for (unsigned IntReg = LargestIntReg - 1; 1159 IntReg >= (unsigned)MVT::i1; --IntReg) { 1160 MVT IVT = (MVT::SimpleValueType)IntReg; 1161 if (isTypeLegal(IVT)) { 1162 LegalIntReg = IntReg; 1163 } else { 1164 RegisterTypeForVT[IntReg] = TransformToType[IntReg] = 1165 (MVT::SimpleValueType)LegalIntReg; 1166 ValueTypeActions.setTypeAction(IVT, TypePromoteInteger); 1167 } 1168 } 1169 1170 // ppcf128 type is really two f64's. 1171 if (!isTypeLegal(MVT::ppcf128)) { 1172 if (isTypeLegal(MVT::f64)) { 1173 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64]; 1174 RegisterTypeForVT[MVT::ppcf128] = MVT::f64; 1175 TransformToType[MVT::ppcf128] = MVT::f64; 1176 ValueTypeActions.setTypeAction(MVT::ppcf128, TypeExpandFloat); 1177 } else { 1178 NumRegistersForVT[MVT::ppcf128] = NumRegistersForVT[MVT::i128]; 1179 RegisterTypeForVT[MVT::ppcf128] = RegisterTypeForVT[MVT::i128]; 1180 TransformToType[MVT::ppcf128] = MVT::i128; 1181 ValueTypeActions.setTypeAction(MVT::ppcf128, TypeSoftenFloat); 1182 } 1183 } 1184 1185 // Decide how to handle f128. If the target does not have native f128 support, 1186 // expand it to i128 and we will be generating soft float library calls. 1187 if (!isTypeLegal(MVT::f128)) { 1188 NumRegistersForVT[MVT::f128] = NumRegistersForVT[MVT::i128]; 1189 RegisterTypeForVT[MVT::f128] = RegisterTypeForVT[MVT::i128]; 1190 TransformToType[MVT::f128] = MVT::i128; 1191 ValueTypeActions.setTypeAction(MVT::f128, TypeSoftenFloat); 1192 } 1193 1194 // Decide how to handle f64. If the target does not have native f64 support, 1195 // expand it to i64 and we will be generating soft float library calls. 1196 if (!isTypeLegal(MVT::f64)) { 1197 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64]; 1198 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64]; 1199 TransformToType[MVT::f64] = MVT::i64; 1200 ValueTypeActions.setTypeAction(MVT::f64, TypeSoftenFloat); 1201 } 1202 1203 // Decide how to handle f32. If the target does not have native f32 support, 1204 // expand it to i32 and we will be generating soft float library calls. 1205 if (!isTypeLegal(MVT::f32)) { 1206 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32]; 1207 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32]; 1208 TransformToType[MVT::f32] = MVT::i32; 1209 ValueTypeActions.setTypeAction(MVT::f32, TypeSoftenFloat); 1210 } 1211 1212 // Decide how to handle f16. If the target does not have native f16 support, 1213 // promote it to f32, because there are no f16 library calls (except for 1214 // conversions). 1215 if (!isTypeLegal(MVT::f16)) { 1216 NumRegistersForVT[MVT::f16] = NumRegistersForVT[MVT::f32]; 1217 RegisterTypeForVT[MVT::f16] = RegisterTypeForVT[MVT::f32]; 1218 TransformToType[MVT::f16] = MVT::f32; 1219 ValueTypeActions.setTypeAction(MVT::f16, TypePromoteFloat); 1220 } 1221 1222 // Loop over all of the vector value types to see which need transformations. 1223 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE; 1224 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) { 1225 MVT VT = (MVT::SimpleValueType) i; 1226 if (isTypeLegal(VT)) 1227 continue; 1228 1229 MVT EltVT = VT.getVectorElementType(); 1230 unsigned NElts = VT.getVectorNumElements(); 1231 bool IsLegalWiderType = false; 1232 LegalizeTypeAction PreferredAction = getPreferredVectorAction(VT); 1233 switch (PreferredAction) { 1234 case TypePromoteInteger: 1235 // Try to promote the elements of integer vectors. If no legal 1236 // promotion was found, fall through to the widen-vector method. 1237 for (unsigned nVT = i + 1; nVT <= MVT::LAST_INTEGER_VECTOR_VALUETYPE; ++nVT) { 1238 MVT SVT = (MVT::SimpleValueType) nVT; 1239 // Promote vectors of integers to vectors with the same number 1240 // of elements, with a wider element type. 1241 if (SVT.getScalarSizeInBits() > EltVT.getSizeInBits() && 1242 SVT.getVectorNumElements() == NElts && isTypeLegal(SVT)) { 1243 TransformToType[i] = SVT; 1244 RegisterTypeForVT[i] = SVT; 1245 NumRegistersForVT[i] = 1; 1246 ValueTypeActions.setTypeAction(VT, TypePromoteInteger); 1247 IsLegalWiderType = true; 1248 break; 1249 } 1250 } 1251 if (IsLegalWiderType) 1252 break; 1253 LLVM_FALLTHROUGH; 1254 1255 case TypeWidenVector: 1256 // Try to widen the vector. 1257 for (unsigned nVT = i + 1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) { 1258 MVT SVT = (MVT::SimpleValueType) nVT; 1259 if (SVT.getVectorElementType() == EltVT 1260 && SVT.getVectorNumElements() > NElts && isTypeLegal(SVT)) { 1261 TransformToType[i] = SVT; 1262 RegisterTypeForVT[i] = SVT; 1263 NumRegistersForVT[i] = 1; 1264 ValueTypeActions.setTypeAction(VT, TypeWidenVector); 1265 IsLegalWiderType = true; 1266 break; 1267 } 1268 } 1269 if (IsLegalWiderType) 1270 break; 1271 LLVM_FALLTHROUGH; 1272 1273 case TypeSplitVector: 1274 case TypeScalarizeVector: { 1275 MVT IntermediateVT; 1276 MVT RegisterVT; 1277 unsigned NumIntermediates; 1278 NumRegistersForVT[i] = getVectorTypeBreakdownMVT(VT, IntermediateVT, 1279 NumIntermediates, RegisterVT, this); 1280 RegisterTypeForVT[i] = RegisterVT; 1281 1282 MVT NVT = VT.getPow2VectorType(); 1283 if (NVT == VT) { 1284 // Type is already a power of 2. The default action is to split. 1285 TransformToType[i] = MVT::Other; 1286 if (PreferredAction == TypeScalarizeVector) 1287 ValueTypeActions.setTypeAction(VT, TypeScalarizeVector); 1288 else if (PreferredAction == TypeSplitVector) 1289 ValueTypeActions.setTypeAction(VT, TypeSplitVector); 1290 else 1291 // Set type action according to the number of elements. 1292 ValueTypeActions.setTypeAction(VT, NElts == 1 ? TypeScalarizeVector 1293 : TypeSplitVector); 1294 } else { 1295 TransformToType[i] = NVT; 1296 ValueTypeActions.setTypeAction(VT, TypeWidenVector); 1297 } 1298 break; 1299 } 1300 default: 1301 llvm_unreachable("Unknown vector legalization action!"); 1302 } 1303 } 1304 1305 // Determine the 'representative' register class for each value type. 1306 // An representative register class is the largest (meaning one which is 1307 // not a sub-register class / subreg register class) legal register class for 1308 // a group of value types. For example, on i386, i8, i16, and i32 1309 // representative would be GR32; while on x86_64 it's GR64. 1310 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) { 1311 const TargetRegisterClass* RRC; 1312 uint8_t Cost; 1313 std::tie(RRC, Cost) = findRepresentativeClass(TRI, (MVT::SimpleValueType)i); 1314 RepRegClassForVT[i] = RRC; 1315 RepRegClassCostForVT[i] = Cost; 1316 } 1317 } 1318 1319 EVT TargetLoweringBase::getSetCCResultType(const DataLayout &DL, LLVMContext &, 1320 EVT VT) const { 1321 assert(!VT.isVector() && "No default SetCC type for vectors!"); 1322 return getPointerTy(DL).SimpleTy; 1323 } 1324 1325 MVT::SimpleValueType TargetLoweringBase::getCmpLibcallReturnType() const { 1326 return MVT::i32; // return the default value 1327 } 1328 1329 /// getVectorTypeBreakdown - Vector types are broken down into some number of 1330 /// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32 1331 /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack. 1332 /// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86. 1333 /// 1334 /// This method returns the number of registers needed, and the VT for each 1335 /// register. It also returns the VT and quantity of the intermediate values 1336 /// before they are promoted/expanded. 1337 unsigned TargetLoweringBase::getVectorTypeBreakdown(LLVMContext &Context, EVT VT, 1338 EVT &IntermediateVT, 1339 unsigned &NumIntermediates, 1340 MVT &RegisterVT) const { 1341 unsigned NumElts = VT.getVectorNumElements(); 1342 1343 // If there is a wider vector type with the same element type as this one, 1344 // or a promoted vector type that has the same number of elements which 1345 // are wider, then we should convert to that legal vector type. 1346 // This handles things like <2 x float> -> <4 x float> and 1347 // <4 x i1> -> <4 x i32>. 1348 LegalizeTypeAction TA = getTypeAction(Context, VT); 1349 if (NumElts != 1 && (TA == TypeWidenVector || TA == TypePromoteInteger)) { 1350 EVT RegisterEVT = getTypeToTransformTo(Context, VT); 1351 if (isTypeLegal(RegisterEVT)) { 1352 IntermediateVT = RegisterEVT; 1353 RegisterVT = RegisterEVT.getSimpleVT(); 1354 NumIntermediates = 1; 1355 return 1; 1356 } 1357 } 1358 1359 // Figure out the right, legal destination reg to copy into. 1360 EVT EltTy = VT.getVectorElementType(); 1361 1362 unsigned NumVectorRegs = 1; 1363 1364 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we 1365 // could break down into LHS/RHS like LegalizeDAG does. 1366 if (!isPowerOf2_32(NumElts)) { 1367 NumVectorRegs = NumElts; 1368 NumElts = 1; 1369 } 1370 1371 // Divide the input until we get to a supported size. This will always 1372 // end with a scalar if the target doesn't support vectors. 1373 while (NumElts > 1 && !isTypeLegal( 1374 EVT::getVectorVT(Context, EltTy, NumElts))) { 1375 NumElts >>= 1; 1376 NumVectorRegs <<= 1; 1377 } 1378 1379 NumIntermediates = NumVectorRegs; 1380 1381 EVT NewVT = EVT::getVectorVT(Context, EltTy, NumElts); 1382 if (!isTypeLegal(NewVT)) 1383 NewVT = EltTy; 1384 IntermediateVT = NewVT; 1385 1386 MVT DestVT = getRegisterType(Context, NewVT); 1387 RegisterVT = DestVT; 1388 unsigned NewVTSize = NewVT.getSizeInBits(); 1389 1390 // Convert sizes such as i33 to i64. 1391 if (!isPowerOf2_32(NewVTSize)) 1392 NewVTSize = NextPowerOf2(NewVTSize); 1393 1394 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16. 1395 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits()); 1396 1397 // Otherwise, promotion or legal types use the same number of registers as 1398 // the vector decimated to the appropriate level. 1399 return NumVectorRegs; 1400 } 1401 1402 /// Get the EVTs and ArgFlags collections that represent the legalized return 1403 /// type of the given function. This does not require a DAG or a return value, 1404 /// and is suitable for use before any DAGs for the function are constructed. 1405 /// TODO: Move this out of TargetLowering.cpp. 1406 void llvm::GetReturnInfo(CallingConv::ID CC, Type *ReturnType, 1407 AttributeList attr, 1408 SmallVectorImpl<ISD::OutputArg> &Outs, 1409 const TargetLowering &TLI, const DataLayout &DL) { 1410 SmallVector<EVT, 4> ValueVTs; 1411 ComputeValueVTs(TLI, DL, ReturnType, ValueVTs); 1412 unsigned NumValues = ValueVTs.size(); 1413 if (NumValues == 0) return; 1414 1415 for (unsigned j = 0, f = NumValues; j != f; ++j) { 1416 EVT VT = ValueVTs[j]; 1417 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 1418 1419 if (attr.hasAttribute(AttributeList::ReturnIndex, Attribute::SExt)) 1420 ExtendKind = ISD::SIGN_EXTEND; 1421 else if (attr.hasAttribute(AttributeList::ReturnIndex, Attribute::ZExt)) 1422 ExtendKind = ISD::ZERO_EXTEND; 1423 1424 // FIXME: C calling convention requires the return type to be promoted to 1425 // at least 32-bit. But this is not necessary for non-C calling 1426 // conventions. The frontend should mark functions whose return values 1427 // require promoting with signext or zeroext attributes. 1428 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) { 1429 MVT MinVT = TLI.getRegisterType(ReturnType->getContext(), MVT::i32); 1430 if (VT.bitsLT(MinVT)) 1431 VT = MinVT; 1432 } 1433 1434 unsigned NumParts = 1435 TLI.getNumRegistersForCallingConv(ReturnType->getContext(), CC, VT); 1436 MVT PartVT = 1437 TLI.getRegisterTypeForCallingConv(ReturnType->getContext(), CC, VT); 1438 1439 // 'inreg' on function refers to return value 1440 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy(); 1441 if (attr.hasAttribute(AttributeList::ReturnIndex, Attribute::InReg)) 1442 Flags.setInReg(); 1443 1444 // Propagate extension type if any 1445 if (attr.hasAttribute(AttributeList::ReturnIndex, Attribute::SExt)) 1446 Flags.setSExt(); 1447 else if (attr.hasAttribute(AttributeList::ReturnIndex, Attribute::ZExt)) 1448 Flags.setZExt(); 1449 1450 for (unsigned i = 0; i < NumParts; ++i) 1451 Outs.push_back(ISD::OutputArg(Flags, PartVT, VT, /*isFixed=*/true, 0, 0)); 1452 } 1453 } 1454 1455 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 1456 /// function arguments in the caller parameter area. This is the actual 1457 /// alignment, not its logarithm. 1458 unsigned TargetLoweringBase::getByValTypeAlignment(Type *Ty, 1459 const DataLayout &DL) const { 1460 return DL.getABITypeAlignment(Ty); 1461 } 1462 1463 bool TargetLoweringBase::allowsMemoryAccess(LLVMContext &Context, 1464 const DataLayout &DL, EVT VT, 1465 unsigned AddrSpace, 1466 unsigned Alignment, 1467 MachineMemOperand::Flags Flags, 1468 bool *Fast) const { 1469 // Check if the specified alignment is sufficient based on the data layout. 1470 // TODO: While using the data layout works in practice, a better solution 1471 // would be to implement this check directly (make this a virtual function). 1472 // For example, the ABI alignment may change based on software platform while 1473 // this function should only be affected by hardware implementation. 1474 Type *Ty = VT.getTypeForEVT(Context); 1475 if (Alignment >= DL.getABITypeAlignment(Ty)) { 1476 // Assume that an access that meets the ABI-specified alignment is fast. 1477 if (Fast != nullptr) 1478 *Fast = true; 1479 return true; 1480 } 1481 1482 // This is a misaligned access. 1483 return allowsMisalignedMemoryAccesses(VT, AddrSpace, Alignment, Flags, Fast); 1484 } 1485 1486 bool TargetLoweringBase::allowsMemoryAccess(LLVMContext &Context, 1487 const DataLayout &DL, EVT VT, 1488 const MachineMemOperand &MMO, 1489 bool *Fast) const { 1490 return allowsMemoryAccess(Context, DL, VT, MMO.getAddrSpace(), 1491 MMO.getAlignment(), MMO.getFlags(), Fast); 1492 } 1493 1494 BranchProbability TargetLoweringBase::getPredictableBranchThreshold() const { 1495 return BranchProbability(MinPercentageForPredictableBranch, 100); 1496 } 1497 1498 //===----------------------------------------------------------------------===// 1499 // TargetTransformInfo Helpers 1500 //===----------------------------------------------------------------------===// 1501 1502 int TargetLoweringBase::InstructionOpcodeToISD(unsigned Opcode) const { 1503 enum InstructionOpcodes { 1504 #define HANDLE_INST(NUM, OPCODE, CLASS) OPCODE = NUM, 1505 #define LAST_OTHER_INST(NUM) InstructionOpcodesCount = NUM 1506 #include "llvm/IR/Instruction.def" 1507 }; 1508 switch (static_cast<InstructionOpcodes>(Opcode)) { 1509 case Ret: return 0; 1510 case Br: return 0; 1511 case Switch: return 0; 1512 case IndirectBr: return 0; 1513 case Invoke: return 0; 1514 case CallBr: return 0; 1515 case Resume: return 0; 1516 case Unreachable: return 0; 1517 case CleanupRet: return 0; 1518 case CatchRet: return 0; 1519 case CatchPad: return 0; 1520 case CatchSwitch: return 0; 1521 case CleanupPad: return 0; 1522 case FNeg: return ISD::FNEG; 1523 case Add: return ISD::ADD; 1524 case FAdd: return ISD::FADD; 1525 case Sub: return ISD::SUB; 1526 case FSub: return ISD::FSUB; 1527 case Mul: return ISD::MUL; 1528 case FMul: return ISD::FMUL; 1529 case UDiv: return ISD::UDIV; 1530 case SDiv: return ISD::SDIV; 1531 case FDiv: return ISD::FDIV; 1532 case URem: return ISD::UREM; 1533 case SRem: return ISD::SREM; 1534 case FRem: return ISD::FREM; 1535 case Shl: return ISD::SHL; 1536 case LShr: return ISD::SRL; 1537 case AShr: return ISD::SRA; 1538 case And: return ISD::AND; 1539 case Or: return ISD::OR; 1540 case Xor: return ISD::XOR; 1541 case Alloca: return 0; 1542 case Load: return ISD::LOAD; 1543 case Store: return ISD::STORE; 1544 case GetElementPtr: return 0; 1545 case Fence: return 0; 1546 case AtomicCmpXchg: return 0; 1547 case AtomicRMW: return 0; 1548 case Trunc: return ISD::TRUNCATE; 1549 case ZExt: return ISD::ZERO_EXTEND; 1550 case SExt: return ISD::SIGN_EXTEND; 1551 case FPToUI: return ISD::FP_TO_UINT; 1552 case FPToSI: return ISD::FP_TO_SINT; 1553 case UIToFP: return ISD::UINT_TO_FP; 1554 case SIToFP: return ISD::SINT_TO_FP; 1555 case FPTrunc: return ISD::FP_ROUND; 1556 case FPExt: return ISD::FP_EXTEND; 1557 case PtrToInt: return ISD::BITCAST; 1558 case IntToPtr: return ISD::BITCAST; 1559 case BitCast: return ISD::BITCAST; 1560 case AddrSpaceCast: return ISD::ADDRSPACECAST; 1561 case ICmp: return ISD::SETCC; 1562 case FCmp: return ISD::SETCC; 1563 case PHI: return 0; 1564 case Call: return 0; 1565 case Select: return ISD::SELECT; 1566 case UserOp1: return 0; 1567 case UserOp2: return 0; 1568 case VAArg: return 0; 1569 case ExtractElement: return ISD::EXTRACT_VECTOR_ELT; 1570 case InsertElement: return ISD::INSERT_VECTOR_ELT; 1571 case ShuffleVector: return ISD::VECTOR_SHUFFLE; 1572 case ExtractValue: return ISD::MERGE_VALUES; 1573 case InsertValue: return ISD::MERGE_VALUES; 1574 case LandingPad: return 0; 1575 } 1576 1577 llvm_unreachable("Unknown instruction type encountered!"); 1578 } 1579 1580 std::pair<int, MVT> 1581 TargetLoweringBase::getTypeLegalizationCost(const DataLayout &DL, 1582 Type *Ty) const { 1583 LLVMContext &C = Ty->getContext(); 1584 EVT MTy = getValueType(DL, Ty); 1585 1586 int Cost = 1; 1587 // We keep legalizing the type until we find a legal kind. We assume that 1588 // the only operation that costs anything is the split. After splitting 1589 // we need to handle two types. 1590 while (true) { 1591 LegalizeKind LK = getTypeConversion(C, MTy); 1592 1593 if (LK.first == TypeLegal) 1594 return std::make_pair(Cost, MTy.getSimpleVT()); 1595 1596 if (LK.first == TypeSplitVector || LK.first == TypeExpandInteger) 1597 Cost *= 2; 1598 1599 // Do not loop with f128 type. 1600 if (MTy == LK.second) 1601 return std::make_pair(Cost, MTy.getSimpleVT()); 1602 1603 // Keep legalizing the type. 1604 MTy = LK.second; 1605 } 1606 } 1607 1608 Value *TargetLoweringBase::getDefaultSafeStackPointerLocation(IRBuilder<> &IRB, 1609 bool UseTLS) const { 1610 // compiler-rt provides a variable with a magic name. Targets that do not 1611 // link with compiler-rt may also provide such a variable. 1612 Module *M = IRB.GetInsertBlock()->getParent()->getParent(); 1613 const char *UnsafeStackPtrVar = "__safestack_unsafe_stack_ptr"; 1614 auto UnsafeStackPtr = 1615 dyn_cast_or_null<GlobalVariable>(M->getNamedValue(UnsafeStackPtrVar)); 1616 1617 Type *StackPtrTy = Type::getInt8PtrTy(M->getContext()); 1618 1619 if (!UnsafeStackPtr) { 1620 auto TLSModel = UseTLS ? 1621 GlobalValue::InitialExecTLSModel : 1622 GlobalValue::NotThreadLocal; 1623 // The global variable is not defined yet, define it ourselves. 1624 // We use the initial-exec TLS model because we do not support the 1625 // variable living anywhere other than in the main executable. 1626 UnsafeStackPtr = new GlobalVariable( 1627 *M, StackPtrTy, false, GlobalValue::ExternalLinkage, nullptr, 1628 UnsafeStackPtrVar, nullptr, TLSModel); 1629 } else { 1630 // The variable exists, check its type and attributes. 1631 if (UnsafeStackPtr->getValueType() != StackPtrTy) 1632 report_fatal_error(Twine(UnsafeStackPtrVar) + " must have void* type"); 1633 if (UseTLS != UnsafeStackPtr->isThreadLocal()) 1634 report_fatal_error(Twine(UnsafeStackPtrVar) + " must " + 1635 (UseTLS ? "" : "not ") + "be thread-local"); 1636 } 1637 return UnsafeStackPtr; 1638 } 1639 1640 Value *TargetLoweringBase::getSafeStackPointerLocation(IRBuilder<> &IRB) const { 1641 if (!TM.getTargetTriple().isAndroid()) 1642 return getDefaultSafeStackPointerLocation(IRB, true); 1643 1644 // Android provides a libc function to retrieve the address of the current 1645 // thread's unsafe stack pointer. 1646 Module *M = IRB.GetInsertBlock()->getParent()->getParent(); 1647 Type *StackPtrTy = Type::getInt8PtrTy(M->getContext()); 1648 FunctionCallee Fn = M->getOrInsertFunction("__safestack_pointer_address", 1649 StackPtrTy->getPointerTo(0)); 1650 return IRB.CreateCall(Fn); 1651 } 1652 1653 //===----------------------------------------------------------------------===// 1654 // Loop Strength Reduction hooks 1655 //===----------------------------------------------------------------------===// 1656 1657 /// isLegalAddressingMode - Return true if the addressing mode represented 1658 /// by AM is legal for this target, for a load/store of the specified type. 1659 bool TargetLoweringBase::isLegalAddressingMode(const DataLayout &DL, 1660 const AddrMode &AM, Type *Ty, 1661 unsigned AS, Instruction *I) const { 1662 // The default implementation of this implements a conservative RISCy, r+r and 1663 // r+i addr mode. 1664 1665 // Allows a sign-extended 16-bit immediate field. 1666 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1) 1667 return false; 1668 1669 // No global is ever allowed as a base. 1670 if (AM.BaseGV) 1671 return false; 1672 1673 // Only support r+r, 1674 switch (AM.Scale) { 1675 case 0: // "r+i" or just "i", depending on HasBaseReg. 1676 break; 1677 case 1: 1678 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. 1679 return false; 1680 // Otherwise we have r+r or r+i. 1681 break; 1682 case 2: 1683 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. 1684 return false; 1685 // Allow 2*r as r+r. 1686 break; 1687 default: // Don't allow n * r 1688 return false; 1689 } 1690 1691 return true; 1692 } 1693 1694 //===----------------------------------------------------------------------===// 1695 // Stack Protector 1696 //===----------------------------------------------------------------------===// 1697 1698 // For OpenBSD return its special guard variable. Otherwise return nullptr, 1699 // so that SelectionDAG handle SSP. 1700 Value *TargetLoweringBase::getIRStackGuard(IRBuilder<> &IRB) const { 1701 if (getTargetMachine().getTargetTriple().isOSOpenBSD()) { 1702 Module &M = *IRB.GetInsertBlock()->getParent()->getParent(); 1703 PointerType *PtrTy = Type::getInt8PtrTy(M.getContext()); 1704 return M.getOrInsertGlobal("__guard_local", PtrTy); 1705 } 1706 return nullptr; 1707 } 1708 1709 // Currently only support "standard" __stack_chk_guard. 1710 // TODO: add LOAD_STACK_GUARD support. 1711 void TargetLoweringBase::insertSSPDeclarations(Module &M) const { 1712 if (!M.getNamedValue("__stack_chk_guard")) 1713 new GlobalVariable(M, Type::getInt8PtrTy(M.getContext()), false, 1714 GlobalVariable::ExternalLinkage, 1715 nullptr, "__stack_chk_guard"); 1716 } 1717 1718 // Currently only support "standard" __stack_chk_guard. 1719 // TODO: add LOAD_STACK_GUARD support. 1720 Value *TargetLoweringBase::getSDagStackGuard(const Module &M) const { 1721 return M.getNamedValue("__stack_chk_guard"); 1722 } 1723 1724 Function *TargetLoweringBase::getSSPStackGuardCheck(const Module &M) const { 1725 return nullptr; 1726 } 1727 1728 unsigned TargetLoweringBase::getMinimumJumpTableEntries() const { 1729 return MinimumJumpTableEntries; 1730 } 1731 1732 void TargetLoweringBase::setMinimumJumpTableEntries(unsigned Val) { 1733 MinimumJumpTableEntries = Val; 1734 } 1735 1736 unsigned TargetLoweringBase::getMinimumJumpTableDensity(bool OptForSize) const { 1737 return OptForSize ? OptsizeJumpTableDensity : JumpTableDensity; 1738 } 1739 1740 unsigned TargetLoweringBase::getMaximumJumpTableSize() const { 1741 return MaximumJumpTableSize; 1742 } 1743 1744 void TargetLoweringBase::setMaximumJumpTableSize(unsigned Val) { 1745 MaximumJumpTableSize = Val; 1746 } 1747 1748 //===----------------------------------------------------------------------===// 1749 // Reciprocal Estimates 1750 //===----------------------------------------------------------------------===// 1751 1752 /// Get the reciprocal estimate attribute string for a function that will 1753 /// override the target defaults. 1754 static StringRef getRecipEstimateForFunc(MachineFunction &MF) { 1755 const Function &F = MF.getFunction(); 1756 return F.getFnAttribute("reciprocal-estimates").getValueAsString(); 1757 } 1758 1759 /// Construct a string for the given reciprocal operation of the given type. 1760 /// This string should match the corresponding option to the front-end's 1761 /// "-mrecip" flag assuming those strings have been passed through in an 1762 /// attribute string. For example, "vec-divf" for a division of a vXf32. 1763 static std::string getReciprocalOpName(bool IsSqrt, EVT VT) { 1764 std::string Name = VT.isVector() ? "vec-" : ""; 1765 1766 Name += IsSqrt ? "sqrt" : "div"; 1767 1768 // TODO: Handle "half" or other float types? 1769 if (VT.getScalarType() == MVT::f64) { 1770 Name += "d"; 1771 } else { 1772 assert(VT.getScalarType() == MVT::f32 && 1773 "Unexpected FP type for reciprocal estimate"); 1774 Name += "f"; 1775 } 1776 1777 return Name; 1778 } 1779 1780 /// Return the character position and value (a single numeric character) of a 1781 /// customized refinement operation in the input string if it exists. Return 1782 /// false if there is no customized refinement step count. 1783 static bool parseRefinementStep(StringRef In, size_t &Position, 1784 uint8_t &Value) { 1785 const char RefStepToken = ':'; 1786 Position = In.find(RefStepToken); 1787 if (Position == StringRef::npos) 1788 return false; 1789 1790 StringRef RefStepString = In.substr(Position + 1); 1791 // Allow exactly one numeric character for the additional refinement 1792 // step parameter. 1793 if (RefStepString.size() == 1) { 1794 char RefStepChar = RefStepString[0]; 1795 if (RefStepChar >= '0' && RefStepChar <= '9') { 1796 Value = RefStepChar - '0'; 1797 return true; 1798 } 1799 } 1800 report_fatal_error("Invalid refinement step for -recip."); 1801 } 1802 1803 /// For the input attribute string, return one of the ReciprocalEstimate enum 1804 /// status values (enabled, disabled, or not specified) for this operation on 1805 /// the specified data type. 1806 static int getOpEnabled(bool IsSqrt, EVT VT, StringRef Override) { 1807 if (Override.empty()) 1808 return TargetLoweringBase::ReciprocalEstimate::Unspecified; 1809 1810 SmallVector<StringRef, 4> OverrideVector; 1811 Override.split(OverrideVector, ','); 1812 unsigned NumArgs = OverrideVector.size(); 1813 1814 // Check if "all", "none", or "default" was specified. 1815 if (NumArgs == 1) { 1816 // Look for an optional setting of the number of refinement steps needed 1817 // for this type of reciprocal operation. 1818 size_t RefPos; 1819 uint8_t RefSteps; 1820 if (parseRefinementStep(Override, RefPos, RefSteps)) { 1821 // Split the string for further processing. 1822 Override = Override.substr(0, RefPos); 1823 } 1824 1825 // All reciprocal types are enabled. 1826 if (Override == "all") 1827 return TargetLoweringBase::ReciprocalEstimate::Enabled; 1828 1829 // All reciprocal types are disabled. 1830 if (Override == "none") 1831 return TargetLoweringBase::ReciprocalEstimate::Disabled; 1832 1833 // Target defaults for enablement are used. 1834 if (Override == "default") 1835 return TargetLoweringBase::ReciprocalEstimate::Unspecified; 1836 } 1837 1838 // The attribute string may omit the size suffix ('f'/'d'). 1839 std::string VTName = getReciprocalOpName(IsSqrt, VT); 1840 std::string VTNameNoSize = VTName; 1841 VTNameNoSize.pop_back(); 1842 static const char DisabledPrefix = '!'; 1843 1844 for (StringRef RecipType : OverrideVector) { 1845 size_t RefPos; 1846 uint8_t RefSteps; 1847 if (parseRefinementStep(RecipType, RefPos, RefSteps)) 1848 RecipType = RecipType.substr(0, RefPos); 1849 1850 // Ignore the disablement token for string matching. 1851 bool IsDisabled = RecipType[0] == DisabledPrefix; 1852 if (IsDisabled) 1853 RecipType = RecipType.substr(1); 1854 1855 if (RecipType.equals(VTName) || RecipType.equals(VTNameNoSize)) 1856 return IsDisabled ? TargetLoweringBase::ReciprocalEstimate::Disabled 1857 : TargetLoweringBase::ReciprocalEstimate::Enabled; 1858 } 1859 1860 return TargetLoweringBase::ReciprocalEstimate::Unspecified; 1861 } 1862 1863 /// For the input attribute string, return the customized refinement step count 1864 /// for this operation on the specified data type. If the step count does not 1865 /// exist, return the ReciprocalEstimate enum value for unspecified. 1866 static int getOpRefinementSteps(bool IsSqrt, EVT VT, StringRef Override) { 1867 if (Override.empty()) 1868 return TargetLoweringBase::ReciprocalEstimate::Unspecified; 1869 1870 SmallVector<StringRef, 4> OverrideVector; 1871 Override.split(OverrideVector, ','); 1872 unsigned NumArgs = OverrideVector.size(); 1873 1874 // Check if "all", "default", or "none" was specified. 1875 if (NumArgs == 1) { 1876 // Look for an optional setting of the number of refinement steps needed 1877 // for this type of reciprocal operation. 1878 size_t RefPos; 1879 uint8_t RefSteps; 1880 if (!parseRefinementStep(Override, RefPos, RefSteps)) 1881 return TargetLoweringBase::ReciprocalEstimate::Unspecified; 1882 1883 // Split the string for further processing. 1884 Override = Override.substr(0, RefPos); 1885 assert(Override != "none" && 1886 "Disabled reciprocals, but specifed refinement steps?"); 1887 1888 // If this is a general override, return the specified number of steps. 1889 if (Override == "all" || Override == "default") 1890 return RefSteps; 1891 } 1892 1893 // The attribute string may omit the size suffix ('f'/'d'). 1894 std::string VTName = getReciprocalOpName(IsSqrt, VT); 1895 std::string VTNameNoSize = VTName; 1896 VTNameNoSize.pop_back(); 1897 1898 for (StringRef RecipType : OverrideVector) { 1899 size_t RefPos; 1900 uint8_t RefSteps; 1901 if (!parseRefinementStep(RecipType, RefPos, RefSteps)) 1902 continue; 1903 1904 RecipType = RecipType.substr(0, RefPos); 1905 if (RecipType.equals(VTName) || RecipType.equals(VTNameNoSize)) 1906 return RefSteps; 1907 } 1908 1909 return TargetLoweringBase::ReciprocalEstimate::Unspecified; 1910 } 1911 1912 int TargetLoweringBase::getRecipEstimateSqrtEnabled(EVT VT, 1913 MachineFunction &MF) const { 1914 return getOpEnabled(true, VT, getRecipEstimateForFunc(MF)); 1915 } 1916 1917 int TargetLoweringBase::getRecipEstimateDivEnabled(EVT VT, 1918 MachineFunction &MF) const { 1919 return getOpEnabled(false, VT, getRecipEstimateForFunc(MF)); 1920 } 1921 1922 int TargetLoweringBase::getSqrtRefinementSteps(EVT VT, 1923 MachineFunction &MF) const { 1924 return getOpRefinementSteps(true, VT, getRecipEstimateForFunc(MF)); 1925 } 1926 1927 int TargetLoweringBase::getDivRefinementSteps(EVT VT, 1928 MachineFunction &MF) const { 1929 return getOpRefinementSteps(false, VT, getRecipEstimateForFunc(MF)); 1930 } 1931 1932 void TargetLoweringBase::finalizeLowering(MachineFunction &MF) const { 1933 MF.getRegInfo().freezeReservedRegs(MF); 1934 } 1935