1 //===-- TargetLoweringBase.cpp - Implement the TargetLoweringBase class ---===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This implements the TargetLoweringBase class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "llvm/Target/TargetLowering.h" 15 #include "llvm/ADT/BitVector.h" 16 #include "llvm/ADT/STLExtras.h" 17 #include "llvm/ADT/Triple.h" 18 #include "llvm/CodeGen/Analysis.h" 19 #include "llvm/CodeGen/MachineFrameInfo.h" 20 #include "llvm/CodeGen/MachineFunction.h" 21 #include "llvm/CodeGen/MachineInstrBuilder.h" 22 #include "llvm/CodeGen/MachineJumpTableInfo.h" 23 #include "llvm/CodeGen/StackMaps.h" 24 #include "llvm/IR/DataLayout.h" 25 #include "llvm/IR/DerivedTypes.h" 26 #include "llvm/IR/GlobalVariable.h" 27 #include "llvm/MC/MCAsmInfo.h" 28 #include "llvm/MC/MCExpr.h" 29 #include "llvm/Support/CommandLine.h" 30 #include "llvm/Support/ErrorHandling.h" 31 #include "llvm/Support/MathExtras.h" 32 #include "llvm/Target/TargetLoweringObjectFile.h" 33 #include "llvm/Target/TargetMachine.h" 34 #include "llvm/Target/TargetRegisterInfo.h" 35 #include <cctype> 36 using namespace llvm; 37 38 /// InitLibcallNames - Set default libcall names. 39 /// 40 static void InitLibcallNames(const char **Names, const TargetMachine &TM) { 41 Names[RTLIB::SHL_I16] = "__ashlhi3"; 42 Names[RTLIB::SHL_I32] = "__ashlsi3"; 43 Names[RTLIB::SHL_I64] = "__ashldi3"; 44 Names[RTLIB::SHL_I128] = "__ashlti3"; 45 Names[RTLIB::SRL_I16] = "__lshrhi3"; 46 Names[RTLIB::SRL_I32] = "__lshrsi3"; 47 Names[RTLIB::SRL_I64] = "__lshrdi3"; 48 Names[RTLIB::SRL_I128] = "__lshrti3"; 49 Names[RTLIB::SRA_I16] = "__ashrhi3"; 50 Names[RTLIB::SRA_I32] = "__ashrsi3"; 51 Names[RTLIB::SRA_I64] = "__ashrdi3"; 52 Names[RTLIB::SRA_I128] = "__ashrti3"; 53 Names[RTLIB::MUL_I8] = "__mulqi3"; 54 Names[RTLIB::MUL_I16] = "__mulhi3"; 55 Names[RTLIB::MUL_I32] = "__mulsi3"; 56 Names[RTLIB::MUL_I64] = "__muldi3"; 57 Names[RTLIB::MUL_I128] = "__multi3"; 58 Names[RTLIB::MULO_I32] = "__mulosi4"; 59 Names[RTLIB::MULO_I64] = "__mulodi4"; 60 Names[RTLIB::MULO_I128] = "__muloti4"; 61 Names[RTLIB::SDIV_I8] = "__divqi3"; 62 Names[RTLIB::SDIV_I16] = "__divhi3"; 63 Names[RTLIB::SDIV_I32] = "__divsi3"; 64 Names[RTLIB::SDIV_I64] = "__divdi3"; 65 Names[RTLIB::SDIV_I128] = "__divti3"; 66 Names[RTLIB::UDIV_I8] = "__udivqi3"; 67 Names[RTLIB::UDIV_I16] = "__udivhi3"; 68 Names[RTLIB::UDIV_I32] = "__udivsi3"; 69 Names[RTLIB::UDIV_I64] = "__udivdi3"; 70 Names[RTLIB::UDIV_I128] = "__udivti3"; 71 Names[RTLIB::SREM_I8] = "__modqi3"; 72 Names[RTLIB::SREM_I16] = "__modhi3"; 73 Names[RTLIB::SREM_I32] = "__modsi3"; 74 Names[RTLIB::SREM_I64] = "__moddi3"; 75 Names[RTLIB::SREM_I128] = "__modti3"; 76 Names[RTLIB::UREM_I8] = "__umodqi3"; 77 Names[RTLIB::UREM_I16] = "__umodhi3"; 78 Names[RTLIB::UREM_I32] = "__umodsi3"; 79 Names[RTLIB::UREM_I64] = "__umoddi3"; 80 Names[RTLIB::UREM_I128] = "__umodti3"; 81 82 // These are generally not available. 83 Names[RTLIB::SDIVREM_I8] = 0; 84 Names[RTLIB::SDIVREM_I16] = 0; 85 Names[RTLIB::SDIVREM_I32] = 0; 86 Names[RTLIB::SDIVREM_I64] = 0; 87 Names[RTLIB::SDIVREM_I128] = 0; 88 Names[RTLIB::UDIVREM_I8] = 0; 89 Names[RTLIB::UDIVREM_I16] = 0; 90 Names[RTLIB::UDIVREM_I32] = 0; 91 Names[RTLIB::UDIVREM_I64] = 0; 92 Names[RTLIB::UDIVREM_I128] = 0; 93 94 Names[RTLIB::NEG_I32] = "__negsi2"; 95 Names[RTLIB::NEG_I64] = "__negdi2"; 96 Names[RTLIB::ADD_F32] = "__addsf3"; 97 Names[RTLIB::ADD_F64] = "__adddf3"; 98 Names[RTLIB::ADD_F80] = "__addxf3"; 99 Names[RTLIB::ADD_F128] = "__addtf3"; 100 Names[RTLIB::ADD_PPCF128] = "__gcc_qadd"; 101 Names[RTLIB::SUB_F32] = "__subsf3"; 102 Names[RTLIB::SUB_F64] = "__subdf3"; 103 Names[RTLIB::SUB_F80] = "__subxf3"; 104 Names[RTLIB::SUB_F128] = "__subtf3"; 105 Names[RTLIB::SUB_PPCF128] = "__gcc_qsub"; 106 Names[RTLIB::MUL_F32] = "__mulsf3"; 107 Names[RTLIB::MUL_F64] = "__muldf3"; 108 Names[RTLIB::MUL_F80] = "__mulxf3"; 109 Names[RTLIB::MUL_F128] = "__multf3"; 110 Names[RTLIB::MUL_PPCF128] = "__gcc_qmul"; 111 Names[RTLIB::DIV_F32] = "__divsf3"; 112 Names[RTLIB::DIV_F64] = "__divdf3"; 113 Names[RTLIB::DIV_F80] = "__divxf3"; 114 Names[RTLIB::DIV_F128] = "__divtf3"; 115 Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv"; 116 Names[RTLIB::REM_F32] = "fmodf"; 117 Names[RTLIB::REM_F64] = "fmod"; 118 Names[RTLIB::REM_F80] = "fmodl"; 119 Names[RTLIB::REM_F128] = "fmodl"; 120 Names[RTLIB::REM_PPCF128] = "fmodl"; 121 Names[RTLIB::FMA_F32] = "fmaf"; 122 Names[RTLIB::FMA_F64] = "fma"; 123 Names[RTLIB::FMA_F80] = "fmal"; 124 Names[RTLIB::FMA_F128] = "fmal"; 125 Names[RTLIB::FMA_PPCF128] = "fmal"; 126 Names[RTLIB::POWI_F32] = "__powisf2"; 127 Names[RTLIB::POWI_F64] = "__powidf2"; 128 Names[RTLIB::POWI_F80] = "__powixf2"; 129 Names[RTLIB::POWI_F128] = "__powitf2"; 130 Names[RTLIB::POWI_PPCF128] = "__powitf2"; 131 Names[RTLIB::SQRT_F32] = "sqrtf"; 132 Names[RTLIB::SQRT_F64] = "sqrt"; 133 Names[RTLIB::SQRT_F80] = "sqrtl"; 134 Names[RTLIB::SQRT_F128] = "sqrtl"; 135 Names[RTLIB::SQRT_PPCF128] = "sqrtl"; 136 Names[RTLIB::LOG_F32] = "logf"; 137 Names[RTLIB::LOG_F64] = "log"; 138 Names[RTLIB::LOG_F80] = "logl"; 139 Names[RTLIB::LOG_F128] = "logl"; 140 Names[RTLIB::LOG_PPCF128] = "logl"; 141 Names[RTLIB::LOG2_F32] = "log2f"; 142 Names[RTLIB::LOG2_F64] = "log2"; 143 Names[RTLIB::LOG2_F80] = "log2l"; 144 Names[RTLIB::LOG2_F128] = "log2l"; 145 Names[RTLIB::LOG2_PPCF128] = "log2l"; 146 Names[RTLIB::LOG10_F32] = "log10f"; 147 Names[RTLIB::LOG10_F64] = "log10"; 148 Names[RTLIB::LOG10_F80] = "log10l"; 149 Names[RTLIB::LOG10_F128] = "log10l"; 150 Names[RTLIB::LOG10_PPCF128] = "log10l"; 151 Names[RTLIB::EXP_F32] = "expf"; 152 Names[RTLIB::EXP_F64] = "exp"; 153 Names[RTLIB::EXP_F80] = "expl"; 154 Names[RTLIB::EXP_F128] = "expl"; 155 Names[RTLIB::EXP_PPCF128] = "expl"; 156 Names[RTLIB::EXP2_F32] = "exp2f"; 157 Names[RTLIB::EXP2_F64] = "exp2"; 158 Names[RTLIB::EXP2_F80] = "exp2l"; 159 Names[RTLIB::EXP2_F128] = "exp2l"; 160 Names[RTLIB::EXP2_PPCF128] = "exp2l"; 161 Names[RTLIB::SIN_F32] = "sinf"; 162 Names[RTLIB::SIN_F64] = "sin"; 163 Names[RTLIB::SIN_F80] = "sinl"; 164 Names[RTLIB::SIN_F128] = "sinl"; 165 Names[RTLIB::SIN_PPCF128] = "sinl"; 166 Names[RTLIB::COS_F32] = "cosf"; 167 Names[RTLIB::COS_F64] = "cos"; 168 Names[RTLIB::COS_F80] = "cosl"; 169 Names[RTLIB::COS_F128] = "cosl"; 170 Names[RTLIB::COS_PPCF128] = "cosl"; 171 Names[RTLIB::POW_F32] = "powf"; 172 Names[RTLIB::POW_F64] = "pow"; 173 Names[RTLIB::POW_F80] = "powl"; 174 Names[RTLIB::POW_F128] = "powl"; 175 Names[RTLIB::POW_PPCF128] = "powl"; 176 Names[RTLIB::CEIL_F32] = "ceilf"; 177 Names[RTLIB::CEIL_F64] = "ceil"; 178 Names[RTLIB::CEIL_F80] = "ceill"; 179 Names[RTLIB::CEIL_F128] = "ceill"; 180 Names[RTLIB::CEIL_PPCF128] = "ceill"; 181 Names[RTLIB::TRUNC_F32] = "truncf"; 182 Names[RTLIB::TRUNC_F64] = "trunc"; 183 Names[RTLIB::TRUNC_F80] = "truncl"; 184 Names[RTLIB::TRUNC_F128] = "truncl"; 185 Names[RTLIB::TRUNC_PPCF128] = "truncl"; 186 Names[RTLIB::RINT_F32] = "rintf"; 187 Names[RTLIB::RINT_F64] = "rint"; 188 Names[RTLIB::RINT_F80] = "rintl"; 189 Names[RTLIB::RINT_F128] = "rintl"; 190 Names[RTLIB::RINT_PPCF128] = "rintl"; 191 Names[RTLIB::NEARBYINT_F32] = "nearbyintf"; 192 Names[RTLIB::NEARBYINT_F64] = "nearbyint"; 193 Names[RTLIB::NEARBYINT_F80] = "nearbyintl"; 194 Names[RTLIB::NEARBYINT_F128] = "nearbyintl"; 195 Names[RTLIB::NEARBYINT_PPCF128] = "nearbyintl"; 196 Names[RTLIB::ROUND_F32] = "roundf"; 197 Names[RTLIB::ROUND_F64] = "round"; 198 Names[RTLIB::ROUND_F80] = "roundl"; 199 Names[RTLIB::ROUND_F128] = "roundl"; 200 Names[RTLIB::ROUND_PPCF128] = "roundl"; 201 Names[RTLIB::FLOOR_F32] = "floorf"; 202 Names[RTLIB::FLOOR_F64] = "floor"; 203 Names[RTLIB::FLOOR_F80] = "floorl"; 204 Names[RTLIB::FLOOR_F128] = "floorl"; 205 Names[RTLIB::FLOOR_PPCF128] = "floorl"; 206 Names[RTLIB::COPYSIGN_F32] = "copysignf"; 207 Names[RTLIB::COPYSIGN_F64] = "copysign"; 208 Names[RTLIB::COPYSIGN_F80] = "copysignl"; 209 Names[RTLIB::COPYSIGN_F128] = "copysignl"; 210 Names[RTLIB::COPYSIGN_PPCF128] = "copysignl"; 211 Names[RTLIB::FPEXT_F64_F128] = "__extenddftf2"; 212 Names[RTLIB::FPEXT_F32_F128] = "__extendsftf2"; 213 Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2"; 214 Names[RTLIB::FPEXT_F16_F32] = "__gnu_h2f_ieee"; 215 Names[RTLIB::FPROUND_F32_F16] = "__gnu_f2h_ieee"; 216 Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2"; 217 Names[RTLIB::FPROUND_F80_F32] = "__truncxfsf2"; 218 Names[RTLIB::FPROUND_F128_F32] = "__trunctfsf2"; 219 Names[RTLIB::FPROUND_PPCF128_F32] = "__trunctfsf2"; 220 Names[RTLIB::FPROUND_F80_F64] = "__truncxfdf2"; 221 Names[RTLIB::FPROUND_F128_F64] = "__trunctfdf2"; 222 Names[RTLIB::FPROUND_PPCF128_F64] = "__trunctfdf2"; 223 Names[RTLIB::FPTOSINT_F32_I8] = "__fixsfqi"; 224 Names[RTLIB::FPTOSINT_F32_I16] = "__fixsfhi"; 225 Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi"; 226 Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi"; 227 Names[RTLIB::FPTOSINT_F32_I128] = "__fixsfti"; 228 Names[RTLIB::FPTOSINT_F64_I8] = "__fixdfqi"; 229 Names[RTLIB::FPTOSINT_F64_I16] = "__fixdfhi"; 230 Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi"; 231 Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi"; 232 Names[RTLIB::FPTOSINT_F64_I128] = "__fixdfti"; 233 Names[RTLIB::FPTOSINT_F80_I32] = "__fixxfsi"; 234 Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi"; 235 Names[RTLIB::FPTOSINT_F80_I128] = "__fixxfti"; 236 Names[RTLIB::FPTOSINT_F128_I32] = "__fixtfsi"; 237 Names[RTLIB::FPTOSINT_F128_I64] = "__fixtfdi"; 238 Names[RTLIB::FPTOSINT_F128_I128] = "__fixtfti"; 239 Names[RTLIB::FPTOSINT_PPCF128_I32] = "__fixtfsi"; 240 Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi"; 241 Names[RTLIB::FPTOSINT_PPCF128_I128] = "__fixtfti"; 242 Names[RTLIB::FPTOUINT_F32_I8] = "__fixunssfqi"; 243 Names[RTLIB::FPTOUINT_F32_I16] = "__fixunssfhi"; 244 Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi"; 245 Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi"; 246 Names[RTLIB::FPTOUINT_F32_I128] = "__fixunssfti"; 247 Names[RTLIB::FPTOUINT_F64_I8] = "__fixunsdfqi"; 248 Names[RTLIB::FPTOUINT_F64_I16] = "__fixunsdfhi"; 249 Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi"; 250 Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi"; 251 Names[RTLIB::FPTOUINT_F64_I128] = "__fixunsdfti"; 252 Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi"; 253 Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi"; 254 Names[RTLIB::FPTOUINT_F80_I128] = "__fixunsxfti"; 255 Names[RTLIB::FPTOUINT_F128_I32] = "__fixunstfsi"; 256 Names[RTLIB::FPTOUINT_F128_I64] = "__fixunstfdi"; 257 Names[RTLIB::FPTOUINT_F128_I128] = "__fixunstfti"; 258 Names[RTLIB::FPTOUINT_PPCF128_I32] = "__fixunstfsi"; 259 Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi"; 260 Names[RTLIB::FPTOUINT_PPCF128_I128] = "__fixunstfti"; 261 Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf"; 262 Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf"; 263 Names[RTLIB::SINTTOFP_I32_F80] = "__floatsixf"; 264 Names[RTLIB::SINTTOFP_I32_F128] = "__floatsitf"; 265 Names[RTLIB::SINTTOFP_I32_PPCF128] = "__floatsitf"; 266 Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf"; 267 Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf"; 268 Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf"; 269 Names[RTLIB::SINTTOFP_I64_F128] = "__floatditf"; 270 Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf"; 271 Names[RTLIB::SINTTOFP_I128_F32] = "__floattisf"; 272 Names[RTLIB::SINTTOFP_I128_F64] = "__floattidf"; 273 Names[RTLIB::SINTTOFP_I128_F80] = "__floattixf"; 274 Names[RTLIB::SINTTOFP_I128_F128] = "__floattitf"; 275 Names[RTLIB::SINTTOFP_I128_PPCF128] = "__floattitf"; 276 Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf"; 277 Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf"; 278 Names[RTLIB::UINTTOFP_I32_F80] = "__floatunsixf"; 279 Names[RTLIB::UINTTOFP_I32_F128] = "__floatunsitf"; 280 Names[RTLIB::UINTTOFP_I32_PPCF128] = "__floatunsitf"; 281 Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf"; 282 Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf"; 283 Names[RTLIB::UINTTOFP_I64_F80] = "__floatundixf"; 284 Names[RTLIB::UINTTOFP_I64_F128] = "__floatunditf"; 285 Names[RTLIB::UINTTOFP_I64_PPCF128] = "__floatunditf"; 286 Names[RTLIB::UINTTOFP_I128_F32] = "__floatuntisf"; 287 Names[RTLIB::UINTTOFP_I128_F64] = "__floatuntidf"; 288 Names[RTLIB::UINTTOFP_I128_F80] = "__floatuntixf"; 289 Names[RTLIB::UINTTOFP_I128_F128] = "__floatuntitf"; 290 Names[RTLIB::UINTTOFP_I128_PPCF128] = "__floatuntitf"; 291 Names[RTLIB::OEQ_F32] = "__eqsf2"; 292 Names[RTLIB::OEQ_F64] = "__eqdf2"; 293 Names[RTLIB::OEQ_F128] = "__eqtf2"; 294 Names[RTLIB::UNE_F32] = "__nesf2"; 295 Names[RTLIB::UNE_F64] = "__nedf2"; 296 Names[RTLIB::UNE_F128] = "__netf2"; 297 Names[RTLIB::OGE_F32] = "__gesf2"; 298 Names[RTLIB::OGE_F64] = "__gedf2"; 299 Names[RTLIB::OGE_F128] = "__getf2"; 300 Names[RTLIB::OLT_F32] = "__ltsf2"; 301 Names[RTLIB::OLT_F64] = "__ltdf2"; 302 Names[RTLIB::OLT_F128] = "__lttf2"; 303 Names[RTLIB::OLE_F32] = "__lesf2"; 304 Names[RTLIB::OLE_F64] = "__ledf2"; 305 Names[RTLIB::OLE_F128] = "__letf2"; 306 Names[RTLIB::OGT_F32] = "__gtsf2"; 307 Names[RTLIB::OGT_F64] = "__gtdf2"; 308 Names[RTLIB::OGT_F128] = "__gttf2"; 309 Names[RTLIB::UO_F32] = "__unordsf2"; 310 Names[RTLIB::UO_F64] = "__unorddf2"; 311 Names[RTLIB::UO_F128] = "__unordtf2"; 312 Names[RTLIB::O_F32] = "__unordsf2"; 313 Names[RTLIB::O_F64] = "__unorddf2"; 314 Names[RTLIB::O_F128] = "__unordtf2"; 315 Names[RTLIB::MEMCPY] = "memcpy"; 316 Names[RTLIB::MEMMOVE] = "memmove"; 317 Names[RTLIB::MEMSET] = "memset"; 318 Names[RTLIB::UNWIND_RESUME] = "_Unwind_Resume"; 319 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1] = "__sync_val_compare_and_swap_1"; 320 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2] = "__sync_val_compare_and_swap_2"; 321 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4] = "__sync_val_compare_and_swap_4"; 322 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8] = "__sync_val_compare_and_swap_8"; 323 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_16] = "__sync_val_compare_and_swap_16"; 324 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_1] = "__sync_lock_test_and_set_1"; 325 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_2] = "__sync_lock_test_and_set_2"; 326 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_4] = "__sync_lock_test_and_set_4"; 327 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_8] = "__sync_lock_test_and_set_8"; 328 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_16] = "__sync_lock_test_and_set_16"; 329 Names[RTLIB::SYNC_FETCH_AND_ADD_1] = "__sync_fetch_and_add_1"; 330 Names[RTLIB::SYNC_FETCH_AND_ADD_2] = "__sync_fetch_and_add_2"; 331 Names[RTLIB::SYNC_FETCH_AND_ADD_4] = "__sync_fetch_and_add_4"; 332 Names[RTLIB::SYNC_FETCH_AND_ADD_8] = "__sync_fetch_and_add_8"; 333 Names[RTLIB::SYNC_FETCH_AND_ADD_16] = "__sync_fetch_and_add_16"; 334 Names[RTLIB::SYNC_FETCH_AND_SUB_1] = "__sync_fetch_and_sub_1"; 335 Names[RTLIB::SYNC_FETCH_AND_SUB_2] = "__sync_fetch_and_sub_2"; 336 Names[RTLIB::SYNC_FETCH_AND_SUB_4] = "__sync_fetch_and_sub_4"; 337 Names[RTLIB::SYNC_FETCH_AND_SUB_8] = "__sync_fetch_and_sub_8"; 338 Names[RTLIB::SYNC_FETCH_AND_SUB_16] = "__sync_fetch_and_sub_16"; 339 Names[RTLIB::SYNC_FETCH_AND_AND_1] = "__sync_fetch_and_and_1"; 340 Names[RTLIB::SYNC_FETCH_AND_AND_2] = "__sync_fetch_and_and_2"; 341 Names[RTLIB::SYNC_FETCH_AND_AND_4] = "__sync_fetch_and_and_4"; 342 Names[RTLIB::SYNC_FETCH_AND_AND_8] = "__sync_fetch_and_and_8"; 343 Names[RTLIB::SYNC_FETCH_AND_AND_16] = "__sync_fetch_and_and_16"; 344 Names[RTLIB::SYNC_FETCH_AND_OR_1] = "__sync_fetch_and_or_1"; 345 Names[RTLIB::SYNC_FETCH_AND_OR_2] = "__sync_fetch_and_or_2"; 346 Names[RTLIB::SYNC_FETCH_AND_OR_4] = "__sync_fetch_and_or_4"; 347 Names[RTLIB::SYNC_FETCH_AND_OR_8] = "__sync_fetch_and_or_8"; 348 Names[RTLIB::SYNC_FETCH_AND_OR_16] = "__sync_fetch_and_or_16"; 349 Names[RTLIB::SYNC_FETCH_AND_XOR_1] = "__sync_fetch_and_xor_1"; 350 Names[RTLIB::SYNC_FETCH_AND_XOR_2] = "__sync_fetch_and_xor_2"; 351 Names[RTLIB::SYNC_FETCH_AND_XOR_4] = "__sync_fetch_and_xor_4"; 352 Names[RTLIB::SYNC_FETCH_AND_XOR_8] = "__sync_fetch_and_xor_8"; 353 Names[RTLIB::SYNC_FETCH_AND_XOR_16] = "__sync_fetch_and_xor_16"; 354 Names[RTLIB::SYNC_FETCH_AND_NAND_1] = "__sync_fetch_and_nand_1"; 355 Names[RTLIB::SYNC_FETCH_AND_NAND_2] = "__sync_fetch_and_nand_2"; 356 Names[RTLIB::SYNC_FETCH_AND_NAND_4] = "__sync_fetch_and_nand_4"; 357 Names[RTLIB::SYNC_FETCH_AND_NAND_8] = "__sync_fetch_and_nand_8"; 358 Names[RTLIB::SYNC_FETCH_AND_NAND_16] = "__sync_fetch_and_nand_16"; 359 Names[RTLIB::SYNC_FETCH_AND_MAX_1] = "__sync_fetch_and_max_1"; 360 Names[RTLIB::SYNC_FETCH_AND_MAX_2] = "__sync_fetch_and_max_2"; 361 Names[RTLIB::SYNC_FETCH_AND_MAX_4] = "__sync_fetch_and_max_4"; 362 Names[RTLIB::SYNC_FETCH_AND_MAX_8] = "__sync_fetch_and_max_8"; 363 Names[RTLIB::SYNC_FETCH_AND_MAX_16] = "__sync_fetch_and_max_16"; 364 Names[RTLIB::SYNC_FETCH_AND_UMAX_1] = "__sync_fetch_and_umax_1"; 365 Names[RTLIB::SYNC_FETCH_AND_UMAX_2] = "__sync_fetch_and_umax_2"; 366 Names[RTLIB::SYNC_FETCH_AND_UMAX_4] = "__sync_fetch_and_umax_4"; 367 Names[RTLIB::SYNC_FETCH_AND_UMAX_8] = "__sync_fetch_and_umax_8"; 368 Names[RTLIB::SYNC_FETCH_AND_UMAX_16] = "__sync_fetch_and_umax_16"; 369 Names[RTLIB::SYNC_FETCH_AND_MIN_1] = "__sync_fetch_and_min_1"; 370 Names[RTLIB::SYNC_FETCH_AND_MIN_2] = "__sync_fetch_and_min_2"; 371 Names[RTLIB::SYNC_FETCH_AND_MIN_4] = "__sync_fetch_and_min_4"; 372 Names[RTLIB::SYNC_FETCH_AND_MIN_8] = "__sync_fetch_and_min_8"; 373 Names[RTLIB::SYNC_FETCH_AND_MIN_16] = "__sync_fetch_and_min_16"; 374 Names[RTLIB::SYNC_FETCH_AND_UMIN_1] = "__sync_fetch_and_umin_1"; 375 Names[RTLIB::SYNC_FETCH_AND_UMIN_2] = "__sync_fetch_and_umin_2"; 376 Names[RTLIB::SYNC_FETCH_AND_UMIN_4] = "__sync_fetch_and_umin_4"; 377 Names[RTLIB::SYNC_FETCH_AND_UMIN_8] = "__sync_fetch_and_umin_8"; 378 Names[RTLIB::SYNC_FETCH_AND_UMIN_16] = "__sync_fetch_and_umin_16"; 379 380 if (Triple(TM.getTargetTriple()).getEnvironment() == Triple::GNU) { 381 Names[RTLIB::SINCOS_F32] = "sincosf"; 382 Names[RTLIB::SINCOS_F64] = "sincos"; 383 Names[RTLIB::SINCOS_F80] = "sincosl"; 384 Names[RTLIB::SINCOS_F128] = "sincosl"; 385 Names[RTLIB::SINCOS_PPCF128] = "sincosl"; 386 } else { 387 // These are generally not available. 388 Names[RTLIB::SINCOS_F32] = 0; 389 Names[RTLIB::SINCOS_F64] = 0; 390 Names[RTLIB::SINCOS_F80] = 0; 391 Names[RTLIB::SINCOS_F128] = 0; 392 Names[RTLIB::SINCOS_PPCF128] = 0; 393 } 394 395 if (Triple(TM.getTargetTriple()).getOS() != Triple::OpenBSD) { 396 Names[RTLIB::STACKPROTECTOR_CHECK_FAIL] = "__stack_chk_fail"; 397 } else { 398 // These are generally not available. 399 Names[RTLIB::STACKPROTECTOR_CHECK_FAIL] = 0; 400 } 401 } 402 403 /// InitLibcallCallingConvs - Set default libcall CallingConvs. 404 /// 405 static void InitLibcallCallingConvs(CallingConv::ID *CCs) { 406 for (int i = 0; i < RTLIB::UNKNOWN_LIBCALL; ++i) { 407 CCs[i] = CallingConv::C; 408 } 409 } 410 411 /// getFPEXT - Return the FPEXT_*_* value for the given types, or 412 /// UNKNOWN_LIBCALL if there is none. 413 RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) { 414 if (OpVT == MVT::f32) { 415 if (RetVT == MVT::f64) 416 return FPEXT_F32_F64; 417 if (RetVT == MVT::f128) 418 return FPEXT_F32_F128; 419 } else if (OpVT == MVT::f64) { 420 if (RetVT == MVT::f128) 421 return FPEXT_F64_F128; 422 } 423 424 return UNKNOWN_LIBCALL; 425 } 426 427 /// getFPROUND - Return the FPROUND_*_* value for the given types, or 428 /// UNKNOWN_LIBCALL if there is none. 429 RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) { 430 if (RetVT == MVT::f32) { 431 if (OpVT == MVT::f64) 432 return FPROUND_F64_F32; 433 if (OpVT == MVT::f80) 434 return FPROUND_F80_F32; 435 if (OpVT == MVT::f128) 436 return FPROUND_F128_F32; 437 if (OpVT == MVT::ppcf128) 438 return FPROUND_PPCF128_F32; 439 } else if (RetVT == MVT::f64) { 440 if (OpVT == MVT::f80) 441 return FPROUND_F80_F64; 442 if (OpVT == MVT::f128) 443 return FPROUND_F128_F64; 444 if (OpVT == MVT::ppcf128) 445 return FPROUND_PPCF128_F64; 446 } 447 448 return UNKNOWN_LIBCALL; 449 } 450 451 /// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or 452 /// UNKNOWN_LIBCALL if there is none. 453 RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT, EVT RetVT) { 454 if (OpVT == MVT::f32) { 455 if (RetVT == MVT::i8) 456 return FPTOSINT_F32_I8; 457 if (RetVT == MVT::i16) 458 return FPTOSINT_F32_I16; 459 if (RetVT == MVT::i32) 460 return FPTOSINT_F32_I32; 461 if (RetVT == MVT::i64) 462 return FPTOSINT_F32_I64; 463 if (RetVT == MVT::i128) 464 return FPTOSINT_F32_I128; 465 } else if (OpVT == MVT::f64) { 466 if (RetVT == MVT::i8) 467 return FPTOSINT_F64_I8; 468 if (RetVT == MVT::i16) 469 return FPTOSINT_F64_I16; 470 if (RetVT == MVT::i32) 471 return FPTOSINT_F64_I32; 472 if (RetVT == MVT::i64) 473 return FPTOSINT_F64_I64; 474 if (RetVT == MVT::i128) 475 return FPTOSINT_F64_I128; 476 } else if (OpVT == MVT::f80) { 477 if (RetVT == MVT::i32) 478 return FPTOSINT_F80_I32; 479 if (RetVT == MVT::i64) 480 return FPTOSINT_F80_I64; 481 if (RetVT == MVT::i128) 482 return FPTOSINT_F80_I128; 483 } else if (OpVT == MVT::f128) { 484 if (RetVT == MVT::i32) 485 return FPTOSINT_F128_I32; 486 if (RetVT == MVT::i64) 487 return FPTOSINT_F128_I64; 488 if (RetVT == MVT::i128) 489 return FPTOSINT_F128_I128; 490 } else if (OpVT == MVT::ppcf128) { 491 if (RetVT == MVT::i32) 492 return FPTOSINT_PPCF128_I32; 493 if (RetVT == MVT::i64) 494 return FPTOSINT_PPCF128_I64; 495 if (RetVT == MVT::i128) 496 return FPTOSINT_PPCF128_I128; 497 } 498 return UNKNOWN_LIBCALL; 499 } 500 501 /// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or 502 /// UNKNOWN_LIBCALL if there is none. 503 RTLIB::Libcall RTLIB::getFPTOUINT(EVT OpVT, EVT RetVT) { 504 if (OpVT == MVT::f32) { 505 if (RetVT == MVT::i8) 506 return FPTOUINT_F32_I8; 507 if (RetVT == MVT::i16) 508 return FPTOUINT_F32_I16; 509 if (RetVT == MVT::i32) 510 return FPTOUINT_F32_I32; 511 if (RetVT == MVT::i64) 512 return FPTOUINT_F32_I64; 513 if (RetVT == MVT::i128) 514 return FPTOUINT_F32_I128; 515 } else if (OpVT == MVT::f64) { 516 if (RetVT == MVT::i8) 517 return FPTOUINT_F64_I8; 518 if (RetVT == MVT::i16) 519 return FPTOUINT_F64_I16; 520 if (RetVT == MVT::i32) 521 return FPTOUINT_F64_I32; 522 if (RetVT == MVT::i64) 523 return FPTOUINT_F64_I64; 524 if (RetVT == MVT::i128) 525 return FPTOUINT_F64_I128; 526 } else if (OpVT == MVT::f80) { 527 if (RetVT == MVT::i32) 528 return FPTOUINT_F80_I32; 529 if (RetVT == MVT::i64) 530 return FPTOUINT_F80_I64; 531 if (RetVT == MVT::i128) 532 return FPTOUINT_F80_I128; 533 } else if (OpVT == MVT::f128) { 534 if (RetVT == MVT::i32) 535 return FPTOUINT_F128_I32; 536 if (RetVT == MVT::i64) 537 return FPTOUINT_F128_I64; 538 if (RetVT == MVT::i128) 539 return FPTOUINT_F128_I128; 540 } else if (OpVT == MVT::ppcf128) { 541 if (RetVT == MVT::i32) 542 return FPTOUINT_PPCF128_I32; 543 if (RetVT == MVT::i64) 544 return FPTOUINT_PPCF128_I64; 545 if (RetVT == MVT::i128) 546 return FPTOUINT_PPCF128_I128; 547 } 548 return UNKNOWN_LIBCALL; 549 } 550 551 /// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or 552 /// UNKNOWN_LIBCALL if there is none. 553 RTLIB::Libcall RTLIB::getSINTTOFP(EVT OpVT, EVT RetVT) { 554 if (OpVT == MVT::i32) { 555 if (RetVT == MVT::f32) 556 return SINTTOFP_I32_F32; 557 if (RetVT == MVT::f64) 558 return SINTTOFP_I32_F64; 559 if (RetVT == MVT::f80) 560 return SINTTOFP_I32_F80; 561 if (RetVT == MVT::f128) 562 return SINTTOFP_I32_F128; 563 if (RetVT == MVT::ppcf128) 564 return SINTTOFP_I32_PPCF128; 565 } else if (OpVT == MVT::i64) { 566 if (RetVT == MVT::f32) 567 return SINTTOFP_I64_F32; 568 if (RetVT == MVT::f64) 569 return SINTTOFP_I64_F64; 570 if (RetVT == MVT::f80) 571 return SINTTOFP_I64_F80; 572 if (RetVT == MVT::f128) 573 return SINTTOFP_I64_F128; 574 if (RetVT == MVT::ppcf128) 575 return SINTTOFP_I64_PPCF128; 576 } else if (OpVT == MVT::i128) { 577 if (RetVT == MVT::f32) 578 return SINTTOFP_I128_F32; 579 if (RetVT == MVT::f64) 580 return SINTTOFP_I128_F64; 581 if (RetVT == MVT::f80) 582 return SINTTOFP_I128_F80; 583 if (RetVT == MVT::f128) 584 return SINTTOFP_I128_F128; 585 if (RetVT == MVT::ppcf128) 586 return SINTTOFP_I128_PPCF128; 587 } 588 return UNKNOWN_LIBCALL; 589 } 590 591 /// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or 592 /// UNKNOWN_LIBCALL if there is none. 593 RTLIB::Libcall RTLIB::getUINTTOFP(EVT OpVT, EVT RetVT) { 594 if (OpVT == MVT::i32) { 595 if (RetVT == MVT::f32) 596 return UINTTOFP_I32_F32; 597 if (RetVT == MVT::f64) 598 return UINTTOFP_I32_F64; 599 if (RetVT == MVT::f80) 600 return UINTTOFP_I32_F80; 601 if (RetVT == MVT::f128) 602 return UINTTOFP_I32_F128; 603 if (RetVT == MVT::ppcf128) 604 return UINTTOFP_I32_PPCF128; 605 } else if (OpVT == MVT::i64) { 606 if (RetVT == MVT::f32) 607 return UINTTOFP_I64_F32; 608 if (RetVT == MVT::f64) 609 return UINTTOFP_I64_F64; 610 if (RetVT == MVT::f80) 611 return UINTTOFP_I64_F80; 612 if (RetVT == MVT::f128) 613 return UINTTOFP_I64_F128; 614 if (RetVT == MVT::ppcf128) 615 return UINTTOFP_I64_PPCF128; 616 } else if (OpVT == MVT::i128) { 617 if (RetVT == MVT::f32) 618 return UINTTOFP_I128_F32; 619 if (RetVT == MVT::f64) 620 return UINTTOFP_I128_F64; 621 if (RetVT == MVT::f80) 622 return UINTTOFP_I128_F80; 623 if (RetVT == MVT::f128) 624 return UINTTOFP_I128_F128; 625 if (RetVT == MVT::ppcf128) 626 return UINTTOFP_I128_PPCF128; 627 } 628 return UNKNOWN_LIBCALL; 629 } 630 631 /// InitCmpLibcallCCs - Set default comparison libcall CC. 632 /// 633 static void InitCmpLibcallCCs(ISD::CondCode *CCs) { 634 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL); 635 CCs[RTLIB::OEQ_F32] = ISD::SETEQ; 636 CCs[RTLIB::OEQ_F64] = ISD::SETEQ; 637 CCs[RTLIB::OEQ_F128] = ISD::SETEQ; 638 CCs[RTLIB::UNE_F32] = ISD::SETNE; 639 CCs[RTLIB::UNE_F64] = ISD::SETNE; 640 CCs[RTLIB::UNE_F128] = ISD::SETNE; 641 CCs[RTLIB::OGE_F32] = ISD::SETGE; 642 CCs[RTLIB::OGE_F64] = ISD::SETGE; 643 CCs[RTLIB::OGE_F128] = ISD::SETGE; 644 CCs[RTLIB::OLT_F32] = ISD::SETLT; 645 CCs[RTLIB::OLT_F64] = ISD::SETLT; 646 CCs[RTLIB::OLT_F128] = ISD::SETLT; 647 CCs[RTLIB::OLE_F32] = ISD::SETLE; 648 CCs[RTLIB::OLE_F64] = ISD::SETLE; 649 CCs[RTLIB::OLE_F128] = ISD::SETLE; 650 CCs[RTLIB::OGT_F32] = ISD::SETGT; 651 CCs[RTLIB::OGT_F64] = ISD::SETGT; 652 CCs[RTLIB::OGT_F128] = ISD::SETGT; 653 CCs[RTLIB::UO_F32] = ISD::SETNE; 654 CCs[RTLIB::UO_F64] = ISD::SETNE; 655 CCs[RTLIB::UO_F128] = ISD::SETNE; 656 CCs[RTLIB::O_F32] = ISD::SETEQ; 657 CCs[RTLIB::O_F64] = ISD::SETEQ; 658 CCs[RTLIB::O_F128] = ISD::SETEQ; 659 } 660 661 /// NOTE: The constructor takes ownership of TLOF. 662 TargetLoweringBase::TargetLoweringBase(const TargetMachine &tm, 663 const TargetLoweringObjectFile *tlof) 664 : TM(tm), TD(TM.getDataLayout()), TLOF(*tlof) { 665 initActions(); 666 667 // Perform these initializations only once. 668 IsLittleEndian = TD->isLittleEndian(); 669 MaxStoresPerMemset = MaxStoresPerMemcpy = MaxStoresPerMemmove = 8; 670 MaxStoresPerMemsetOptSize = MaxStoresPerMemcpyOptSize 671 = MaxStoresPerMemmoveOptSize = 4; 672 UseUnderscoreSetJmp = false; 673 UseUnderscoreLongJmp = false; 674 SelectIsExpensive = false; 675 IntDivIsCheap = false; 676 Pow2DivIsCheap = false; 677 JumpIsExpensive = false; 678 PredictableSelectIsExpensive = false; 679 StackPointerRegisterToSaveRestore = 0; 680 ExceptionPointerRegister = 0; 681 ExceptionSelectorRegister = 0; 682 BooleanContents = UndefinedBooleanContent; 683 BooleanVectorContents = UndefinedBooleanContent; 684 SchedPreferenceInfo = Sched::ILP; 685 JumpBufSize = 0; 686 JumpBufAlignment = 0; 687 MinFunctionAlignment = 0; 688 PrefFunctionAlignment = 0; 689 PrefLoopAlignment = 0; 690 MinStackArgumentAlignment = 1; 691 InsertFencesForAtomic = false; 692 SupportJumpTables = true; 693 MinimumJumpTableEntries = 4; 694 695 InitLibcallNames(LibcallRoutineNames, TM); 696 InitCmpLibcallCCs(CmpLibcallCCs); 697 InitLibcallCallingConvs(LibcallCallingConvs); 698 } 699 700 TargetLoweringBase::~TargetLoweringBase() { 701 delete &TLOF; 702 } 703 704 void TargetLoweringBase::initActions() { 705 // All operations default to being supported. 706 memset(OpActions, 0, sizeof(OpActions)); 707 memset(LoadExtActions, 0, sizeof(LoadExtActions)); 708 memset(TruncStoreActions, 0, sizeof(TruncStoreActions)); 709 memset(IndexedModeActions, 0, sizeof(IndexedModeActions)); 710 memset(CondCodeActions, 0, sizeof(CondCodeActions)); 711 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*)); 712 memset(TargetDAGCombineArray, 0, array_lengthof(TargetDAGCombineArray)); 713 714 // Set default actions for various operations. 715 for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) { 716 // Default all indexed load / store to expand. 717 for (unsigned IM = (unsigned)ISD::PRE_INC; 718 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) { 719 setIndexedLoadAction(IM, (MVT::SimpleValueType)VT, Expand); 720 setIndexedStoreAction(IM, (MVT::SimpleValueType)VT, Expand); 721 } 722 723 // These operations default to expand. 724 setOperationAction(ISD::FGETSIGN, (MVT::SimpleValueType)VT, Expand); 725 setOperationAction(ISD::CONCAT_VECTORS, (MVT::SimpleValueType)VT, Expand); 726 727 // These library functions default to expand. 728 setOperationAction(ISD::FROUND, (MVT::SimpleValueType)VT, Expand); 729 730 // These operations default to expand for vector types. 731 if (VT >= MVT::FIRST_VECTOR_VALUETYPE && 732 VT <= MVT::LAST_VECTOR_VALUETYPE) 733 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand); 734 } 735 736 // Most targets ignore the @llvm.prefetch intrinsic. 737 setOperationAction(ISD::PREFETCH, MVT::Other, Expand); 738 739 // ConstantFP nodes default to expand. Targets can either change this to 740 // Legal, in which case all fp constants are legal, or use isFPImmLegal() 741 // to optimize expansions for certain constants. 742 setOperationAction(ISD::ConstantFP, MVT::f16, Expand); 743 setOperationAction(ISD::ConstantFP, MVT::f32, Expand); 744 setOperationAction(ISD::ConstantFP, MVT::f64, Expand); 745 setOperationAction(ISD::ConstantFP, MVT::f80, Expand); 746 setOperationAction(ISD::ConstantFP, MVT::f128, Expand); 747 748 // These library functions default to expand. 749 setOperationAction(ISD::FLOG , MVT::f16, Expand); 750 setOperationAction(ISD::FLOG2, MVT::f16, Expand); 751 setOperationAction(ISD::FLOG10, MVT::f16, Expand); 752 setOperationAction(ISD::FEXP , MVT::f16, Expand); 753 setOperationAction(ISD::FEXP2, MVT::f16, Expand); 754 setOperationAction(ISD::FFLOOR, MVT::f16, Expand); 755 setOperationAction(ISD::FNEARBYINT, MVT::f16, Expand); 756 setOperationAction(ISD::FCEIL, MVT::f16, Expand); 757 setOperationAction(ISD::FRINT, MVT::f16, Expand); 758 setOperationAction(ISD::FTRUNC, MVT::f16, Expand); 759 setOperationAction(ISD::FLOG , MVT::f32, Expand); 760 setOperationAction(ISD::FLOG2, MVT::f32, Expand); 761 setOperationAction(ISD::FLOG10, MVT::f32, Expand); 762 setOperationAction(ISD::FEXP , MVT::f32, Expand); 763 setOperationAction(ISD::FEXP2, MVT::f32, Expand); 764 setOperationAction(ISD::FFLOOR, MVT::f32, Expand); 765 setOperationAction(ISD::FNEARBYINT, MVT::f32, Expand); 766 setOperationAction(ISD::FCEIL, MVT::f32, Expand); 767 setOperationAction(ISD::FRINT, MVT::f32, Expand); 768 setOperationAction(ISD::FTRUNC, MVT::f32, Expand); 769 setOperationAction(ISD::FLOG , MVT::f64, Expand); 770 setOperationAction(ISD::FLOG2, MVT::f64, Expand); 771 setOperationAction(ISD::FLOG10, MVT::f64, Expand); 772 setOperationAction(ISD::FEXP , MVT::f64, Expand); 773 setOperationAction(ISD::FEXP2, MVT::f64, Expand); 774 setOperationAction(ISD::FFLOOR, MVT::f64, Expand); 775 setOperationAction(ISD::FNEARBYINT, MVT::f64, Expand); 776 setOperationAction(ISD::FCEIL, MVT::f64, Expand); 777 setOperationAction(ISD::FRINT, MVT::f64, Expand); 778 setOperationAction(ISD::FTRUNC, MVT::f64, Expand); 779 setOperationAction(ISD::FLOG , MVT::f128, Expand); 780 setOperationAction(ISD::FLOG2, MVT::f128, Expand); 781 setOperationAction(ISD::FLOG10, MVT::f128, Expand); 782 setOperationAction(ISD::FEXP , MVT::f128, Expand); 783 setOperationAction(ISD::FEXP2, MVT::f128, Expand); 784 setOperationAction(ISD::FFLOOR, MVT::f128, Expand); 785 setOperationAction(ISD::FNEARBYINT, MVT::f128, Expand); 786 setOperationAction(ISD::FCEIL, MVT::f128, Expand); 787 setOperationAction(ISD::FRINT, MVT::f128, Expand); 788 setOperationAction(ISD::FTRUNC, MVT::f128, Expand); 789 790 // Default ISD::TRAP to expand (which turns it into abort). 791 setOperationAction(ISD::TRAP, MVT::Other, Expand); 792 793 // On most systems, DEBUGTRAP and TRAP have no difference. The "Expand" 794 // here is to inform DAG Legalizer to replace DEBUGTRAP with TRAP. 795 // 796 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Expand); 797 } 798 799 MVT TargetLoweringBase::getPointerTy(uint32_t AS) const { 800 return MVT::getIntegerVT(getPointerSizeInBits(AS)); 801 } 802 803 unsigned TargetLoweringBase::getPointerSizeInBits(uint32_t AS) const { 804 return TD->getPointerSizeInBits(AS); 805 } 806 807 unsigned TargetLoweringBase::getPointerTypeSizeInBits(Type *Ty) const { 808 assert(Ty->isPointerTy()); 809 return getPointerSizeInBits(Ty->getPointerAddressSpace()); 810 } 811 812 MVT TargetLoweringBase::getScalarShiftAmountTy(EVT LHSTy) const { 813 return MVT::getIntegerVT(8*TD->getPointerSize(0)); 814 } 815 816 EVT TargetLoweringBase::getShiftAmountTy(EVT LHSTy) const { 817 assert(LHSTy.isInteger() && "Shift amount is not an integer type!"); 818 if (LHSTy.isVector()) 819 return LHSTy; 820 return getScalarShiftAmountTy(LHSTy); 821 } 822 823 /// canOpTrap - Returns true if the operation can trap for the value type. 824 /// VT must be a legal type. 825 bool TargetLoweringBase::canOpTrap(unsigned Op, EVT VT) const { 826 assert(isTypeLegal(VT)); 827 switch (Op) { 828 default: 829 return false; 830 case ISD::FDIV: 831 case ISD::FREM: 832 case ISD::SDIV: 833 case ISD::UDIV: 834 case ISD::SREM: 835 case ISD::UREM: 836 return true; 837 } 838 } 839 840 841 static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT, 842 unsigned &NumIntermediates, 843 MVT &RegisterVT, 844 TargetLoweringBase *TLI) { 845 // Figure out the right, legal destination reg to copy into. 846 unsigned NumElts = VT.getVectorNumElements(); 847 MVT EltTy = VT.getVectorElementType(); 848 849 unsigned NumVectorRegs = 1; 850 851 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we 852 // could break down into LHS/RHS like LegalizeDAG does. 853 if (!isPowerOf2_32(NumElts)) { 854 NumVectorRegs = NumElts; 855 NumElts = 1; 856 } 857 858 // Divide the input until we get to a supported size. This will always 859 // end with a scalar if the target doesn't support vectors. 860 while (NumElts > 1 && !TLI->isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) { 861 NumElts >>= 1; 862 NumVectorRegs <<= 1; 863 } 864 865 NumIntermediates = NumVectorRegs; 866 867 MVT NewVT = MVT::getVectorVT(EltTy, NumElts); 868 if (!TLI->isTypeLegal(NewVT)) 869 NewVT = EltTy; 870 IntermediateVT = NewVT; 871 872 unsigned NewVTSize = NewVT.getSizeInBits(); 873 874 // Convert sizes such as i33 to i64. 875 if (!isPowerOf2_32(NewVTSize)) 876 NewVTSize = NextPowerOf2(NewVTSize); 877 878 MVT DestVT = TLI->getRegisterType(NewVT); 879 RegisterVT = DestVT; 880 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16. 881 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits()); 882 883 // Otherwise, promotion or legal types use the same number of registers as 884 // the vector decimated to the appropriate level. 885 return NumVectorRegs; 886 } 887 888 /// isLegalRC - Return true if the value types that can be represented by the 889 /// specified register class are all legal. 890 bool TargetLoweringBase::isLegalRC(const TargetRegisterClass *RC) const { 891 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end(); 892 I != E; ++I) { 893 if (isTypeLegal(*I)) 894 return true; 895 } 896 return false; 897 } 898 899 /// Replace/modify any TargetFrameIndex operands with a targte-dependent 900 /// sequence of memory operands that is recognized by PrologEpilogInserter. 901 MachineBasicBlock* 902 TargetLoweringBase::emitPatchPoint(MachineInstr *MI, 903 MachineBasicBlock *MBB) const { 904 const TargetMachine &TM = getTargetMachine(); 905 MachineFunction &MF = *MI->getParent()->getParent(); 906 907 // MI changes inside this loop as we grow operands. 908 for(unsigned OperIdx = 0; OperIdx != MI->getNumOperands(); ++OperIdx) { 909 MachineOperand &MO = MI->getOperand(OperIdx); 910 if (!MO.isFI()) 911 continue; 912 913 // foldMemoryOperand builds a new MI after replacing a single FI operand 914 // with the canonical set of five x86 addressing-mode operands. 915 int FI = MO.getIndex(); 916 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), MI->getDesc()); 917 918 // Copy operands before the frame-index. 919 for (unsigned i = 0; i < OperIdx; ++i) 920 MIB.addOperand(MI->getOperand(i)); 921 // Add frame index operands: direct-mem-ref tag, #FI, offset. 922 MIB.addImm(StackMaps::DirectMemRefOp); 923 MIB.addOperand(MI->getOperand(OperIdx)); 924 MIB.addImm(0); 925 // Copy the operands after the frame index. 926 for (unsigned i = OperIdx + 1; i != MI->getNumOperands(); ++i) 927 MIB.addOperand(MI->getOperand(i)); 928 929 // Inherit previous memory operands. 930 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end()); 931 assert(MIB->mayLoad() && "Folded a stackmap use to a non-load!"); 932 933 // Add a new memory operand for this FI. 934 const MachineFrameInfo &MFI = *MF.getFrameInfo(); 935 assert(MFI.getObjectOffset(FI) != -1); 936 MachineMemOperand *MMO = 937 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FI), 938 MachineMemOperand::MOLoad, 939 TM.getDataLayout()->getPointerSize(), 940 MFI.getObjectAlignment(FI)); 941 MIB->addMemOperand(MF, MMO); 942 943 // Replace the instruction and update the operand index. 944 MBB->insert(MachineBasicBlock::iterator(MI), MIB); 945 OperIdx += (MIB->getNumOperands() - MI->getNumOperands()) - 1; 946 MI->eraseFromParent(); 947 MI = MIB; 948 } 949 return MBB; 950 } 951 952 /// findRepresentativeClass - Return the largest legal super-reg register class 953 /// of the register class for the specified type and its associated "cost". 954 std::pair<const TargetRegisterClass*, uint8_t> 955 TargetLoweringBase::findRepresentativeClass(MVT VT) const { 956 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo(); 957 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy]; 958 if (!RC) 959 return std::make_pair(RC, 0); 960 961 // Compute the set of all super-register classes. 962 BitVector SuperRegRC(TRI->getNumRegClasses()); 963 for (SuperRegClassIterator RCI(RC, TRI); RCI.isValid(); ++RCI) 964 SuperRegRC.setBitsInMask(RCI.getMask()); 965 966 // Find the first legal register class with the largest spill size. 967 const TargetRegisterClass *BestRC = RC; 968 for (int i = SuperRegRC.find_first(); i >= 0; i = SuperRegRC.find_next(i)) { 969 const TargetRegisterClass *SuperRC = TRI->getRegClass(i); 970 // We want the largest possible spill size. 971 if (SuperRC->getSize() <= BestRC->getSize()) 972 continue; 973 if (!isLegalRC(SuperRC)) 974 continue; 975 BestRC = SuperRC; 976 } 977 return std::make_pair(BestRC, 1); 978 } 979 980 /// computeRegisterProperties - Once all of the register classes are added, 981 /// this allows us to compute derived properties we expose. 982 void TargetLoweringBase::computeRegisterProperties() { 983 assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE && 984 "Too many value types for ValueTypeActions to hold!"); 985 986 // Everything defaults to needing one register. 987 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) { 988 NumRegistersForVT[i] = 1; 989 RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i; 990 } 991 // ...except isVoid, which doesn't need any registers. 992 NumRegistersForVT[MVT::isVoid] = 0; 993 994 // Find the largest integer register class. 995 unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE; 996 for (; RegClassForVT[LargestIntReg] == 0; --LargestIntReg) 997 assert(LargestIntReg != MVT::i1 && "No integer registers defined!"); 998 999 // Every integer value type larger than this largest register takes twice as 1000 // many registers to represent as the previous ValueType. 1001 for (unsigned ExpandedReg = LargestIntReg + 1; 1002 ExpandedReg <= MVT::LAST_INTEGER_VALUETYPE; ++ExpandedReg) { 1003 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1]; 1004 RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg; 1005 TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1); 1006 ValueTypeActions.setTypeAction((MVT::SimpleValueType)ExpandedReg, 1007 TypeExpandInteger); 1008 } 1009 1010 // Inspect all of the ValueType's smaller than the largest integer 1011 // register to see which ones need promotion. 1012 unsigned LegalIntReg = LargestIntReg; 1013 for (unsigned IntReg = LargestIntReg - 1; 1014 IntReg >= (unsigned)MVT::i1; --IntReg) { 1015 MVT IVT = (MVT::SimpleValueType)IntReg; 1016 if (isTypeLegal(IVT)) { 1017 LegalIntReg = IntReg; 1018 } else { 1019 RegisterTypeForVT[IntReg] = TransformToType[IntReg] = 1020 (const MVT::SimpleValueType)LegalIntReg; 1021 ValueTypeActions.setTypeAction(IVT, TypePromoteInteger); 1022 } 1023 } 1024 1025 // ppcf128 type is really two f64's. 1026 if (!isTypeLegal(MVT::ppcf128)) { 1027 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64]; 1028 RegisterTypeForVT[MVT::ppcf128] = MVT::f64; 1029 TransformToType[MVT::ppcf128] = MVT::f64; 1030 ValueTypeActions.setTypeAction(MVT::ppcf128, TypeExpandFloat); 1031 } 1032 1033 // Decide how to handle f128. If the target does not have native f128 support, 1034 // expand it to i128 and we will be generating soft float library calls. 1035 if (!isTypeLegal(MVT::f128)) { 1036 NumRegistersForVT[MVT::f128] = NumRegistersForVT[MVT::i128]; 1037 RegisterTypeForVT[MVT::f128] = RegisterTypeForVT[MVT::i128]; 1038 TransformToType[MVT::f128] = MVT::i128; 1039 ValueTypeActions.setTypeAction(MVT::f128, TypeSoftenFloat); 1040 } 1041 1042 // Decide how to handle f64. If the target does not have native f64 support, 1043 // expand it to i64 and we will be generating soft float library calls. 1044 if (!isTypeLegal(MVT::f64)) { 1045 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64]; 1046 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64]; 1047 TransformToType[MVT::f64] = MVT::i64; 1048 ValueTypeActions.setTypeAction(MVT::f64, TypeSoftenFloat); 1049 } 1050 1051 // Decide how to handle f32. If the target does not have native support for 1052 // f32, promote it to f64 if it is legal. Otherwise, expand it to i32. 1053 if (!isTypeLegal(MVT::f32)) { 1054 if (isTypeLegal(MVT::f64)) { 1055 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::f64]; 1056 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::f64]; 1057 TransformToType[MVT::f32] = MVT::f64; 1058 ValueTypeActions.setTypeAction(MVT::f32, TypePromoteInteger); 1059 } else { 1060 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32]; 1061 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32]; 1062 TransformToType[MVT::f32] = MVT::i32; 1063 ValueTypeActions.setTypeAction(MVT::f32, TypeSoftenFloat); 1064 } 1065 } 1066 1067 // Loop over all of the vector value types to see which need transformations. 1068 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE; 1069 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) { 1070 MVT VT = (MVT::SimpleValueType)i; 1071 if (isTypeLegal(VT)) continue; 1072 1073 // Determine if there is a legal wider type. If so, we should promote to 1074 // that wider vector type. 1075 MVT EltVT = VT.getVectorElementType(); 1076 unsigned NElts = VT.getVectorNumElements(); 1077 if (NElts != 1 && !shouldSplitVectorElementType(EltVT)) { 1078 bool IsLegalWiderType = false; 1079 // First try to promote the elements of integer vectors. If no legal 1080 // promotion was found, fallback to the widen-vector method. 1081 for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) { 1082 MVT SVT = (MVT::SimpleValueType)nVT; 1083 // Promote vectors of integers to vectors with the same number 1084 // of elements, with a wider element type. 1085 if (SVT.getVectorElementType().getSizeInBits() > EltVT.getSizeInBits() 1086 && SVT.getVectorNumElements() == NElts && 1087 isTypeLegal(SVT) && SVT.getScalarType().isInteger()) { 1088 TransformToType[i] = SVT; 1089 RegisterTypeForVT[i] = SVT; 1090 NumRegistersForVT[i] = 1; 1091 ValueTypeActions.setTypeAction(VT, TypePromoteInteger); 1092 IsLegalWiderType = true; 1093 break; 1094 } 1095 } 1096 1097 if (IsLegalWiderType) continue; 1098 1099 // Try to widen the vector. 1100 for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) { 1101 MVT SVT = (MVT::SimpleValueType)nVT; 1102 if (SVT.getVectorElementType() == EltVT && 1103 SVT.getVectorNumElements() > NElts && 1104 isTypeLegal(SVT)) { 1105 TransformToType[i] = SVT; 1106 RegisterTypeForVT[i] = SVT; 1107 NumRegistersForVT[i] = 1; 1108 ValueTypeActions.setTypeAction(VT, TypeWidenVector); 1109 IsLegalWiderType = true; 1110 break; 1111 } 1112 } 1113 if (IsLegalWiderType) continue; 1114 } 1115 1116 MVT IntermediateVT; 1117 MVT RegisterVT; 1118 unsigned NumIntermediates; 1119 NumRegistersForVT[i] = 1120 getVectorTypeBreakdownMVT(VT, IntermediateVT, NumIntermediates, 1121 RegisterVT, this); 1122 RegisterTypeForVT[i] = RegisterVT; 1123 1124 MVT NVT = VT.getPow2VectorType(); 1125 if (NVT == VT) { 1126 // Type is already a power of 2. The default action is to split. 1127 TransformToType[i] = MVT::Other; 1128 unsigned NumElts = VT.getVectorNumElements(); 1129 ValueTypeActions.setTypeAction(VT, 1130 NumElts > 1 ? TypeSplitVector : TypeScalarizeVector); 1131 } else { 1132 TransformToType[i] = NVT; 1133 ValueTypeActions.setTypeAction(VT, TypeWidenVector); 1134 } 1135 } 1136 1137 // Determine the 'representative' register class for each value type. 1138 // An representative register class is the largest (meaning one which is 1139 // not a sub-register class / subreg register class) legal register class for 1140 // a group of value types. For example, on i386, i8, i16, and i32 1141 // representative would be GR32; while on x86_64 it's GR64. 1142 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) { 1143 const TargetRegisterClass* RRC; 1144 uint8_t Cost; 1145 tie(RRC, Cost) = findRepresentativeClass((MVT::SimpleValueType)i); 1146 RepRegClassForVT[i] = RRC; 1147 RepRegClassCostForVT[i] = Cost; 1148 } 1149 } 1150 1151 EVT TargetLoweringBase::getSetCCResultType(LLVMContext &, EVT VT) const { 1152 assert(!VT.isVector() && "No default SetCC type for vectors!"); 1153 return getPointerTy(0).SimpleTy; 1154 } 1155 1156 MVT::SimpleValueType TargetLoweringBase::getCmpLibcallReturnType() const { 1157 return MVT::i32; // return the default value 1158 } 1159 1160 /// getVectorTypeBreakdown - Vector types are broken down into some number of 1161 /// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32 1162 /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack. 1163 /// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86. 1164 /// 1165 /// This method returns the number of registers needed, and the VT for each 1166 /// register. It also returns the VT and quantity of the intermediate values 1167 /// before they are promoted/expanded. 1168 /// 1169 unsigned TargetLoweringBase::getVectorTypeBreakdown(LLVMContext &Context, EVT VT, 1170 EVT &IntermediateVT, 1171 unsigned &NumIntermediates, 1172 MVT &RegisterVT) const { 1173 unsigned NumElts = VT.getVectorNumElements(); 1174 1175 // If there is a wider vector type with the same element type as this one, 1176 // or a promoted vector type that has the same number of elements which 1177 // are wider, then we should convert to that legal vector type. 1178 // This handles things like <2 x float> -> <4 x float> and 1179 // <4 x i1> -> <4 x i32>. 1180 LegalizeTypeAction TA = getTypeAction(Context, VT); 1181 if (NumElts != 1 && (TA == TypeWidenVector || TA == TypePromoteInteger)) { 1182 EVT RegisterEVT = getTypeToTransformTo(Context, VT); 1183 if (isTypeLegal(RegisterEVT)) { 1184 IntermediateVT = RegisterEVT; 1185 RegisterVT = RegisterEVT.getSimpleVT(); 1186 NumIntermediates = 1; 1187 return 1; 1188 } 1189 } 1190 1191 // Figure out the right, legal destination reg to copy into. 1192 EVT EltTy = VT.getVectorElementType(); 1193 1194 unsigned NumVectorRegs = 1; 1195 1196 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we 1197 // could break down into LHS/RHS like LegalizeDAG does. 1198 if (!isPowerOf2_32(NumElts)) { 1199 NumVectorRegs = NumElts; 1200 NumElts = 1; 1201 } 1202 1203 // Divide the input until we get to a supported size. This will always 1204 // end with a scalar if the target doesn't support vectors. 1205 while (NumElts > 1 && !isTypeLegal( 1206 EVT::getVectorVT(Context, EltTy, NumElts))) { 1207 NumElts >>= 1; 1208 NumVectorRegs <<= 1; 1209 } 1210 1211 NumIntermediates = NumVectorRegs; 1212 1213 EVT NewVT = EVT::getVectorVT(Context, EltTy, NumElts); 1214 if (!isTypeLegal(NewVT)) 1215 NewVT = EltTy; 1216 IntermediateVT = NewVT; 1217 1218 MVT DestVT = getRegisterType(Context, NewVT); 1219 RegisterVT = DestVT; 1220 unsigned NewVTSize = NewVT.getSizeInBits(); 1221 1222 // Convert sizes such as i33 to i64. 1223 if (!isPowerOf2_32(NewVTSize)) 1224 NewVTSize = NextPowerOf2(NewVTSize); 1225 1226 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16. 1227 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits()); 1228 1229 // Otherwise, promotion or legal types use the same number of registers as 1230 // the vector decimated to the appropriate level. 1231 return NumVectorRegs; 1232 } 1233 1234 /// Get the EVTs and ArgFlags collections that represent the legalized return 1235 /// type of the given function. This does not require a DAG or a return value, 1236 /// and is suitable for use before any DAGs for the function are constructed. 1237 /// TODO: Move this out of TargetLowering.cpp. 1238 void llvm::GetReturnInfo(Type* ReturnType, AttributeSet attr, 1239 SmallVectorImpl<ISD::OutputArg> &Outs, 1240 const TargetLowering &TLI) { 1241 SmallVector<EVT, 4> ValueVTs; 1242 ComputeValueVTs(TLI, ReturnType, ValueVTs); 1243 unsigned NumValues = ValueVTs.size(); 1244 if (NumValues == 0) return; 1245 1246 for (unsigned j = 0, f = NumValues; j != f; ++j) { 1247 EVT VT = ValueVTs[j]; 1248 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 1249 1250 if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::SExt)) 1251 ExtendKind = ISD::SIGN_EXTEND; 1252 else if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::ZExt)) 1253 ExtendKind = ISD::ZERO_EXTEND; 1254 1255 // FIXME: C calling convention requires the return type to be promoted to 1256 // at least 32-bit. But this is not necessary for non-C calling 1257 // conventions. The frontend should mark functions whose return values 1258 // require promoting with signext or zeroext attributes. 1259 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) { 1260 MVT MinVT = TLI.getRegisterType(ReturnType->getContext(), MVT::i32); 1261 if (VT.bitsLT(MinVT)) 1262 VT = MinVT; 1263 } 1264 1265 unsigned NumParts = TLI.getNumRegisters(ReturnType->getContext(), VT); 1266 MVT PartVT = TLI.getRegisterType(ReturnType->getContext(), VT); 1267 1268 // 'inreg' on function refers to return value 1269 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy(); 1270 if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::InReg)) 1271 Flags.setInReg(); 1272 1273 // Propagate extension type if any 1274 if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::SExt)) 1275 Flags.setSExt(); 1276 else if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::ZExt)) 1277 Flags.setZExt(); 1278 1279 for (unsigned i = 0; i < NumParts; ++i) 1280 Outs.push_back(ISD::OutputArg(Flags, PartVT, VT, /*isFixed=*/true, 0, 0)); 1281 } 1282 } 1283 1284 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 1285 /// function arguments in the caller parameter area. This is the actual 1286 /// alignment, not its logarithm. 1287 unsigned TargetLoweringBase::getByValTypeAlignment(Type *Ty) const { 1288 return TD->getCallFrameTypeAlignment(Ty); 1289 } 1290 1291 //===----------------------------------------------------------------------===// 1292 // TargetTransformInfo Helpers 1293 //===----------------------------------------------------------------------===// 1294 1295 int TargetLoweringBase::InstructionOpcodeToISD(unsigned Opcode) const { 1296 enum InstructionOpcodes { 1297 #define HANDLE_INST(NUM, OPCODE, CLASS) OPCODE = NUM, 1298 #define LAST_OTHER_INST(NUM) InstructionOpcodesCount = NUM 1299 #include "llvm/IR/Instruction.def" 1300 }; 1301 switch (static_cast<InstructionOpcodes>(Opcode)) { 1302 case Ret: return 0; 1303 case Br: return 0; 1304 case Switch: return 0; 1305 case IndirectBr: return 0; 1306 case Invoke: return 0; 1307 case Resume: return 0; 1308 case Unreachable: return 0; 1309 case Add: return ISD::ADD; 1310 case FAdd: return ISD::FADD; 1311 case Sub: return ISD::SUB; 1312 case FSub: return ISD::FSUB; 1313 case Mul: return ISD::MUL; 1314 case FMul: return ISD::FMUL; 1315 case UDiv: return ISD::UDIV; 1316 case SDiv: return ISD::UDIV; 1317 case FDiv: return ISD::FDIV; 1318 case URem: return ISD::UREM; 1319 case SRem: return ISD::SREM; 1320 case FRem: return ISD::FREM; 1321 case Shl: return ISD::SHL; 1322 case LShr: return ISD::SRL; 1323 case AShr: return ISD::SRA; 1324 case And: return ISD::AND; 1325 case Or: return ISD::OR; 1326 case Xor: return ISD::XOR; 1327 case Alloca: return 0; 1328 case Load: return ISD::LOAD; 1329 case Store: return ISD::STORE; 1330 case GetElementPtr: return 0; 1331 case Fence: return 0; 1332 case AtomicCmpXchg: return 0; 1333 case AtomicRMW: return 0; 1334 case Trunc: return ISD::TRUNCATE; 1335 case ZExt: return ISD::ZERO_EXTEND; 1336 case SExt: return ISD::SIGN_EXTEND; 1337 case FPToUI: return ISD::FP_TO_UINT; 1338 case FPToSI: return ISD::FP_TO_SINT; 1339 case UIToFP: return ISD::UINT_TO_FP; 1340 case SIToFP: return ISD::SINT_TO_FP; 1341 case FPTrunc: return ISD::FP_ROUND; 1342 case FPExt: return ISD::FP_EXTEND; 1343 case PtrToInt: return ISD::BITCAST; 1344 case IntToPtr: return ISD::BITCAST; 1345 case BitCast: return ISD::BITCAST; 1346 case AddrSpaceCast: return ISD::ADDRSPACECAST; 1347 case ICmp: return ISD::SETCC; 1348 case FCmp: return ISD::SETCC; 1349 case PHI: return 0; 1350 case Call: return 0; 1351 case Select: return ISD::SELECT; 1352 case UserOp1: return 0; 1353 case UserOp2: return 0; 1354 case VAArg: return 0; 1355 case ExtractElement: return ISD::EXTRACT_VECTOR_ELT; 1356 case InsertElement: return ISD::INSERT_VECTOR_ELT; 1357 case ShuffleVector: return ISD::VECTOR_SHUFFLE; 1358 case ExtractValue: return ISD::MERGE_VALUES; 1359 case InsertValue: return ISD::MERGE_VALUES; 1360 case LandingPad: return 0; 1361 } 1362 1363 llvm_unreachable("Unknown instruction type encountered!"); 1364 } 1365 1366 std::pair<unsigned, MVT> 1367 TargetLoweringBase::getTypeLegalizationCost(Type *Ty) const { 1368 LLVMContext &C = Ty->getContext(); 1369 EVT MTy = getValueType(Ty); 1370 1371 unsigned Cost = 1; 1372 // We keep legalizing the type until we find a legal kind. We assume that 1373 // the only operation that costs anything is the split. After splitting 1374 // we need to handle two types. 1375 while (true) { 1376 LegalizeKind LK = getTypeConversion(C, MTy); 1377 1378 if (LK.first == TypeLegal) 1379 return std::make_pair(Cost, MTy.getSimpleVT()); 1380 1381 if (LK.first == TypeSplitVector || LK.first == TypeExpandInteger) 1382 Cost *= 2; 1383 1384 // Keep legalizing the type. 1385 MTy = LK.second; 1386 } 1387 } 1388 1389 //===----------------------------------------------------------------------===// 1390 // Loop Strength Reduction hooks 1391 //===----------------------------------------------------------------------===// 1392 1393 /// isLegalAddressingMode - Return true if the addressing mode represented 1394 /// by AM is legal for this target, for a load/store of the specified type. 1395 bool TargetLoweringBase::isLegalAddressingMode(const AddrMode &AM, 1396 Type *Ty) const { 1397 // The default implementation of this implements a conservative RISCy, r+r and 1398 // r+i addr mode. 1399 1400 // Allows a sign-extended 16-bit immediate field. 1401 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1) 1402 return false; 1403 1404 // No global is ever allowed as a base. 1405 if (AM.BaseGV) 1406 return false; 1407 1408 // Only support r+r, 1409 switch (AM.Scale) { 1410 case 0: // "r+i" or just "i", depending on HasBaseReg. 1411 break; 1412 case 1: 1413 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. 1414 return false; 1415 // Otherwise we have r+r or r+i. 1416 break; 1417 case 2: 1418 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. 1419 return false; 1420 // Allow 2*r as r+r. 1421 break; 1422 } 1423 1424 return true; 1425 } 1426