1 //===-- TargetLoweringBase.cpp - Implement the TargetLoweringBase class ---===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This implements the TargetLoweringBase class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "llvm/Target/TargetLowering.h" 15 #include "llvm/ADT/BitVector.h" 16 #include "llvm/ADT/STLExtras.h" 17 #include "llvm/ADT/StringExtras.h" 18 #include "llvm/ADT/Triple.h" 19 #include "llvm/CodeGen/Analysis.h" 20 #include "llvm/CodeGen/MachineFrameInfo.h" 21 #include "llvm/CodeGen/MachineFunction.h" 22 #include "llvm/CodeGen/MachineInstrBuilder.h" 23 #include "llvm/CodeGen/MachineJumpTableInfo.h" 24 #include "llvm/CodeGen/MachineRegisterInfo.h" 25 #include "llvm/CodeGen/StackMaps.h" 26 #include "llvm/IR/DataLayout.h" 27 #include "llvm/IR/DerivedTypes.h" 28 #include "llvm/IR/GlobalVariable.h" 29 #include "llvm/IR/Mangler.h" 30 #include "llvm/MC/MCAsmInfo.h" 31 #include "llvm/MC/MCContext.h" 32 #include "llvm/MC/MCExpr.h" 33 #include "llvm/Support/BranchProbability.h" 34 #include "llvm/Support/CommandLine.h" 35 #include "llvm/Support/ErrorHandling.h" 36 #include "llvm/Support/MathExtras.h" 37 #include "llvm/Target/TargetLoweringObjectFile.h" 38 #include "llvm/Target/TargetMachine.h" 39 #include "llvm/Target/TargetRegisterInfo.h" 40 #include "llvm/Target/TargetSubtargetInfo.h" 41 #include <cctype> 42 using namespace llvm; 43 44 static cl::opt<bool> JumpIsExpensiveOverride( 45 "jump-is-expensive", cl::init(false), 46 cl::desc("Do not create extra branches to split comparison logic."), 47 cl::Hidden); 48 49 static cl::opt<unsigned> MinimumJumpTableEntries 50 ("min-jump-table-entries", cl::init(4), cl::Hidden, 51 cl::desc("Set minimum number of entries to use a jump table.")); 52 53 static cl::opt<unsigned> MaximumJumpTableSize 54 ("max-jump-table-size", cl::init(0), cl::Hidden, 55 cl::desc("Set maximum size of jump tables; zero for no limit.")); 56 57 /// Minimum jump table density for normal functions. 58 static cl::opt<unsigned> 59 JumpTableDensity("jump-table-density", cl::init(10), cl::Hidden, 60 cl::desc("Minimum density for building a jump table in " 61 "a normal function")); 62 63 /// Minimum jump table density for -Os or -Oz functions. 64 static cl::opt<unsigned> OptsizeJumpTableDensity( 65 "optsize-jump-table-density", cl::init(40), cl::Hidden, 66 cl::desc("Minimum density for building a jump table in " 67 "an optsize function")); 68 69 // Although this default value is arbitrary, it is not random. It is assumed 70 // that a condition that evaluates the same way by a higher percentage than this 71 // is best represented as control flow. Therefore, the default value N should be 72 // set such that the win from N% correct executions is greater than the loss 73 // from (100 - N)% mispredicted executions for the majority of intended targets. 74 static cl::opt<int> MinPercentageForPredictableBranch( 75 "min-predictable-branch", cl::init(99), 76 cl::desc("Minimum percentage (0-100) that a condition must be either true " 77 "or false to assume that the condition is predictable"), 78 cl::Hidden); 79 80 /// InitLibcallNames - Set default libcall names. 81 /// 82 static void InitLibcallNames(const char **Names, const Triple &TT) { 83 Names[RTLIB::SHL_I16] = "__ashlhi3"; 84 Names[RTLIB::SHL_I32] = "__ashlsi3"; 85 Names[RTLIB::SHL_I64] = "__ashldi3"; 86 Names[RTLIB::SHL_I128] = "__ashlti3"; 87 Names[RTLIB::SRL_I16] = "__lshrhi3"; 88 Names[RTLIB::SRL_I32] = "__lshrsi3"; 89 Names[RTLIB::SRL_I64] = "__lshrdi3"; 90 Names[RTLIB::SRL_I128] = "__lshrti3"; 91 Names[RTLIB::SRA_I16] = "__ashrhi3"; 92 Names[RTLIB::SRA_I32] = "__ashrsi3"; 93 Names[RTLIB::SRA_I64] = "__ashrdi3"; 94 Names[RTLIB::SRA_I128] = "__ashrti3"; 95 Names[RTLIB::MUL_I8] = "__mulqi3"; 96 Names[RTLIB::MUL_I16] = "__mulhi3"; 97 Names[RTLIB::MUL_I32] = "__mulsi3"; 98 Names[RTLIB::MUL_I64] = "__muldi3"; 99 Names[RTLIB::MUL_I128] = "__multi3"; 100 Names[RTLIB::MULO_I32] = "__mulosi4"; 101 Names[RTLIB::MULO_I64] = "__mulodi4"; 102 Names[RTLIB::MULO_I128] = "__muloti4"; 103 Names[RTLIB::SDIV_I8] = "__divqi3"; 104 Names[RTLIB::SDIV_I16] = "__divhi3"; 105 Names[RTLIB::SDIV_I32] = "__divsi3"; 106 Names[RTLIB::SDIV_I64] = "__divdi3"; 107 Names[RTLIB::SDIV_I128] = "__divti3"; 108 Names[RTLIB::UDIV_I8] = "__udivqi3"; 109 Names[RTLIB::UDIV_I16] = "__udivhi3"; 110 Names[RTLIB::UDIV_I32] = "__udivsi3"; 111 Names[RTLIB::UDIV_I64] = "__udivdi3"; 112 Names[RTLIB::UDIV_I128] = "__udivti3"; 113 Names[RTLIB::SREM_I8] = "__modqi3"; 114 Names[RTLIB::SREM_I16] = "__modhi3"; 115 Names[RTLIB::SREM_I32] = "__modsi3"; 116 Names[RTLIB::SREM_I64] = "__moddi3"; 117 Names[RTLIB::SREM_I128] = "__modti3"; 118 Names[RTLIB::UREM_I8] = "__umodqi3"; 119 Names[RTLIB::UREM_I16] = "__umodhi3"; 120 Names[RTLIB::UREM_I32] = "__umodsi3"; 121 Names[RTLIB::UREM_I64] = "__umoddi3"; 122 Names[RTLIB::UREM_I128] = "__umodti3"; 123 124 Names[RTLIB::NEG_I32] = "__negsi2"; 125 Names[RTLIB::NEG_I64] = "__negdi2"; 126 Names[RTLIB::ADD_F32] = "__addsf3"; 127 Names[RTLIB::ADD_F64] = "__adddf3"; 128 Names[RTLIB::ADD_F80] = "__addxf3"; 129 Names[RTLIB::ADD_F128] = "__addtf3"; 130 Names[RTLIB::ADD_PPCF128] = "__gcc_qadd"; 131 Names[RTLIB::SUB_F32] = "__subsf3"; 132 Names[RTLIB::SUB_F64] = "__subdf3"; 133 Names[RTLIB::SUB_F80] = "__subxf3"; 134 Names[RTLIB::SUB_F128] = "__subtf3"; 135 Names[RTLIB::SUB_PPCF128] = "__gcc_qsub"; 136 Names[RTLIB::MUL_F32] = "__mulsf3"; 137 Names[RTLIB::MUL_F64] = "__muldf3"; 138 Names[RTLIB::MUL_F80] = "__mulxf3"; 139 Names[RTLIB::MUL_F128] = "__multf3"; 140 Names[RTLIB::MUL_PPCF128] = "__gcc_qmul"; 141 Names[RTLIB::DIV_F32] = "__divsf3"; 142 Names[RTLIB::DIV_F64] = "__divdf3"; 143 Names[RTLIB::DIV_F80] = "__divxf3"; 144 Names[RTLIB::DIV_F128] = "__divtf3"; 145 Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv"; 146 Names[RTLIB::REM_F32] = "fmodf"; 147 Names[RTLIB::REM_F64] = "fmod"; 148 Names[RTLIB::REM_F80] = "fmodl"; 149 Names[RTLIB::REM_F128] = "fmodl"; 150 Names[RTLIB::REM_PPCF128] = "fmodl"; 151 Names[RTLIB::FMA_F32] = "fmaf"; 152 Names[RTLIB::FMA_F64] = "fma"; 153 Names[RTLIB::FMA_F80] = "fmal"; 154 Names[RTLIB::FMA_F128] = "fmal"; 155 Names[RTLIB::FMA_PPCF128] = "fmal"; 156 Names[RTLIB::POWI_F32] = "__powisf2"; 157 Names[RTLIB::POWI_F64] = "__powidf2"; 158 Names[RTLIB::POWI_F80] = "__powixf2"; 159 Names[RTLIB::POWI_F128] = "__powitf2"; 160 Names[RTLIB::POWI_PPCF128] = "__powitf2"; 161 Names[RTLIB::SQRT_F32] = "sqrtf"; 162 Names[RTLIB::SQRT_F64] = "sqrt"; 163 Names[RTLIB::SQRT_F80] = "sqrtl"; 164 Names[RTLIB::SQRT_F128] = "sqrtl"; 165 Names[RTLIB::SQRT_PPCF128] = "sqrtl"; 166 Names[RTLIB::LOG_F32] = "logf"; 167 Names[RTLIB::LOG_F64] = "log"; 168 Names[RTLIB::LOG_F80] = "logl"; 169 Names[RTLIB::LOG_F128] = "logl"; 170 Names[RTLIB::LOG_PPCF128] = "logl"; 171 Names[RTLIB::LOG2_F32] = "log2f"; 172 Names[RTLIB::LOG2_F64] = "log2"; 173 Names[RTLIB::LOG2_F80] = "log2l"; 174 Names[RTLIB::LOG2_F128] = "log2l"; 175 Names[RTLIB::LOG2_PPCF128] = "log2l"; 176 Names[RTLIB::LOG10_F32] = "log10f"; 177 Names[RTLIB::LOG10_F64] = "log10"; 178 Names[RTLIB::LOG10_F80] = "log10l"; 179 Names[RTLIB::LOG10_F128] = "log10l"; 180 Names[RTLIB::LOG10_PPCF128] = "log10l"; 181 Names[RTLIB::EXP_F32] = "expf"; 182 Names[RTLIB::EXP_F64] = "exp"; 183 Names[RTLIB::EXP_F80] = "expl"; 184 Names[RTLIB::EXP_F128] = "expl"; 185 Names[RTLIB::EXP_PPCF128] = "expl"; 186 Names[RTLIB::EXP2_F32] = "exp2f"; 187 Names[RTLIB::EXP2_F64] = "exp2"; 188 Names[RTLIB::EXP2_F80] = "exp2l"; 189 Names[RTLIB::EXP2_F128] = "exp2l"; 190 Names[RTLIB::EXP2_PPCF128] = "exp2l"; 191 Names[RTLIB::SIN_F32] = "sinf"; 192 Names[RTLIB::SIN_F64] = "sin"; 193 Names[RTLIB::SIN_F80] = "sinl"; 194 Names[RTLIB::SIN_F128] = "sinl"; 195 Names[RTLIB::SIN_PPCF128] = "sinl"; 196 Names[RTLIB::COS_F32] = "cosf"; 197 Names[RTLIB::COS_F64] = "cos"; 198 Names[RTLIB::COS_F80] = "cosl"; 199 Names[RTLIB::COS_F128] = "cosl"; 200 Names[RTLIB::COS_PPCF128] = "cosl"; 201 Names[RTLIB::POW_F32] = "powf"; 202 Names[RTLIB::POW_F64] = "pow"; 203 Names[RTLIB::POW_F80] = "powl"; 204 Names[RTLIB::POW_F128] = "powl"; 205 Names[RTLIB::POW_PPCF128] = "powl"; 206 Names[RTLIB::CEIL_F32] = "ceilf"; 207 Names[RTLIB::CEIL_F64] = "ceil"; 208 Names[RTLIB::CEIL_F80] = "ceill"; 209 Names[RTLIB::CEIL_F128] = "ceill"; 210 Names[RTLIB::CEIL_PPCF128] = "ceill"; 211 Names[RTLIB::TRUNC_F32] = "truncf"; 212 Names[RTLIB::TRUNC_F64] = "trunc"; 213 Names[RTLIB::TRUNC_F80] = "truncl"; 214 Names[RTLIB::TRUNC_F128] = "truncl"; 215 Names[RTLIB::TRUNC_PPCF128] = "truncl"; 216 Names[RTLIB::RINT_F32] = "rintf"; 217 Names[RTLIB::RINT_F64] = "rint"; 218 Names[RTLIB::RINT_F80] = "rintl"; 219 Names[RTLIB::RINT_F128] = "rintl"; 220 Names[RTLIB::RINT_PPCF128] = "rintl"; 221 Names[RTLIB::NEARBYINT_F32] = "nearbyintf"; 222 Names[RTLIB::NEARBYINT_F64] = "nearbyint"; 223 Names[RTLIB::NEARBYINT_F80] = "nearbyintl"; 224 Names[RTLIB::NEARBYINT_F128] = "nearbyintl"; 225 Names[RTLIB::NEARBYINT_PPCF128] = "nearbyintl"; 226 Names[RTLIB::ROUND_F32] = "roundf"; 227 Names[RTLIB::ROUND_F64] = "round"; 228 Names[RTLIB::ROUND_F80] = "roundl"; 229 Names[RTLIB::ROUND_F128] = "roundl"; 230 Names[RTLIB::ROUND_PPCF128] = "roundl"; 231 Names[RTLIB::FLOOR_F32] = "floorf"; 232 Names[RTLIB::FLOOR_F64] = "floor"; 233 Names[RTLIB::FLOOR_F80] = "floorl"; 234 Names[RTLIB::FLOOR_F128] = "floorl"; 235 Names[RTLIB::FLOOR_PPCF128] = "floorl"; 236 Names[RTLIB::FMIN_F32] = "fminf"; 237 Names[RTLIB::FMIN_F64] = "fmin"; 238 Names[RTLIB::FMIN_F80] = "fminl"; 239 Names[RTLIB::FMIN_F128] = "fminl"; 240 Names[RTLIB::FMIN_PPCF128] = "fminl"; 241 Names[RTLIB::FMAX_F32] = "fmaxf"; 242 Names[RTLIB::FMAX_F64] = "fmax"; 243 Names[RTLIB::FMAX_F80] = "fmaxl"; 244 Names[RTLIB::FMAX_F128] = "fmaxl"; 245 Names[RTLIB::FMAX_PPCF128] = "fmaxl"; 246 Names[RTLIB::ROUND_F32] = "roundf"; 247 Names[RTLIB::ROUND_F64] = "round"; 248 Names[RTLIB::ROUND_F80] = "roundl"; 249 Names[RTLIB::ROUND_F128] = "roundl"; 250 Names[RTLIB::ROUND_PPCF128] = "roundl"; 251 Names[RTLIB::COPYSIGN_F32] = "copysignf"; 252 Names[RTLIB::COPYSIGN_F64] = "copysign"; 253 Names[RTLIB::COPYSIGN_F80] = "copysignl"; 254 Names[RTLIB::COPYSIGN_F128] = "copysignl"; 255 Names[RTLIB::COPYSIGN_PPCF128] = "copysignl"; 256 Names[RTLIB::FPEXT_F32_PPCF128] = "__gcc_stoq"; 257 Names[RTLIB::FPEXT_F64_PPCF128] = "__gcc_dtoq"; 258 Names[RTLIB::FPEXT_F64_F128] = "__extenddftf2"; 259 Names[RTLIB::FPEXT_F32_F128] = "__extendsftf2"; 260 Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2"; 261 if (TT.isOSDarwin()) { 262 // For f16/f32 conversions, Darwin uses the standard naming scheme, instead 263 // of the gnueabi-style __gnu_*_ieee. 264 // FIXME: What about other targets? 265 Names[RTLIB::FPEXT_F16_F32] = "__extendhfsf2"; 266 Names[RTLIB::FPROUND_F32_F16] = "__truncsfhf2"; 267 } else { 268 Names[RTLIB::FPEXT_F16_F32] = "__gnu_h2f_ieee"; 269 Names[RTLIB::FPROUND_F32_F16] = "__gnu_f2h_ieee"; 270 } 271 Names[RTLIB::FPROUND_F64_F16] = "__truncdfhf2"; 272 Names[RTLIB::FPROUND_F80_F16] = "__truncxfhf2"; 273 Names[RTLIB::FPROUND_F128_F16] = "__trunctfhf2"; 274 Names[RTLIB::FPROUND_PPCF128_F16] = "__trunctfhf2"; 275 Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2"; 276 Names[RTLIB::FPROUND_F80_F32] = "__truncxfsf2"; 277 Names[RTLIB::FPROUND_F128_F32] = "__trunctfsf2"; 278 Names[RTLIB::FPROUND_PPCF128_F32] = "__gcc_qtos"; 279 Names[RTLIB::FPROUND_F80_F64] = "__truncxfdf2"; 280 Names[RTLIB::FPROUND_F128_F64] = "__trunctfdf2"; 281 Names[RTLIB::FPROUND_PPCF128_F64] = "__gcc_qtod"; 282 Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi"; 283 Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi"; 284 Names[RTLIB::FPTOSINT_F32_I128] = "__fixsfti"; 285 Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi"; 286 Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi"; 287 Names[RTLIB::FPTOSINT_F64_I128] = "__fixdfti"; 288 Names[RTLIB::FPTOSINT_F80_I32] = "__fixxfsi"; 289 Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi"; 290 Names[RTLIB::FPTOSINT_F80_I128] = "__fixxfti"; 291 Names[RTLIB::FPTOSINT_F128_I32] = "__fixtfsi"; 292 Names[RTLIB::FPTOSINT_F128_I64] = "__fixtfdi"; 293 Names[RTLIB::FPTOSINT_F128_I128] = "__fixtfti"; 294 Names[RTLIB::FPTOSINT_PPCF128_I32] = "__gcc_qtou"; 295 Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi"; 296 Names[RTLIB::FPTOSINT_PPCF128_I128] = "__fixtfti"; 297 Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi"; 298 Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi"; 299 Names[RTLIB::FPTOUINT_F32_I128] = "__fixunssfti"; 300 Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi"; 301 Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi"; 302 Names[RTLIB::FPTOUINT_F64_I128] = "__fixunsdfti"; 303 Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi"; 304 Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi"; 305 Names[RTLIB::FPTOUINT_F80_I128] = "__fixunsxfti"; 306 Names[RTLIB::FPTOUINT_F128_I32] = "__fixunstfsi"; 307 Names[RTLIB::FPTOUINT_F128_I64] = "__fixunstfdi"; 308 Names[RTLIB::FPTOUINT_F128_I128] = "__fixunstfti"; 309 Names[RTLIB::FPTOUINT_PPCF128_I32] = "__fixunstfsi"; 310 Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi"; 311 Names[RTLIB::FPTOUINT_PPCF128_I128] = "__fixunstfti"; 312 Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf"; 313 Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf"; 314 Names[RTLIB::SINTTOFP_I32_F80] = "__floatsixf"; 315 Names[RTLIB::SINTTOFP_I32_F128] = "__floatsitf"; 316 Names[RTLIB::SINTTOFP_I32_PPCF128] = "__gcc_itoq"; 317 Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf"; 318 Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf"; 319 Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf"; 320 Names[RTLIB::SINTTOFP_I64_F128] = "__floatditf"; 321 Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf"; 322 Names[RTLIB::SINTTOFP_I128_F32] = "__floattisf"; 323 Names[RTLIB::SINTTOFP_I128_F64] = "__floattidf"; 324 Names[RTLIB::SINTTOFP_I128_F80] = "__floattixf"; 325 Names[RTLIB::SINTTOFP_I128_F128] = "__floattitf"; 326 Names[RTLIB::SINTTOFP_I128_PPCF128] = "__floattitf"; 327 Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf"; 328 Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf"; 329 Names[RTLIB::UINTTOFP_I32_F80] = "__floatunsixf"; 330 Names[RTLIB::UINTTOFP_I32_F128] = "__floatunsitf"; 331 Names[RTLIB::UINTTOFP_I32_PPCF128] = "__gcc_utoq"; 332 Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf"; 333 Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf"; 334 Names[RTLIB::UINTTOFP_I64_F80] = "__floatundixf"; 335 Names[RTLIB::UINTTOFP_I64_F128] = "__floatunditf"; 336 Names[RTLIB::UINTTOFP_I64_PPCF128] = "__floatunditf"; 337 Names[RTLIB::UINTTOFP_I128_F32] = "__floatuntisf"; 338 Names[RTLIB::UINTTOFP_I128_F64] = "__floatuntidf"; 339 Names[RTLIB::UINTTOFP_I128_F80] = "__floatuntixf"; 340 Names[RTLIB::UINTTOFP_I128_F128] = "__floatuntitf"; 341 Names[RTLIB::UINTTOFP_I128_PPCF128] = "__floatuntitf"; 342 Names[RTLIB::OEQ_F32] = "__eqsf2"; 343 Names[RTLIB::OEQ_F64] = "__eqdf2"; 344 Names[RTLIB::OEQ_F128] = "__eqtf2"; 345 Names[RTLIB::OEQ_PPCF128] = "__gcc_qeq"; 346 Names[RTLIB::UNE_F32] = "__nesf2"; 347 Names[RTLIB::UNE_F64] = "__nedf2"; 348 Names[RTLIB::UNE_F128] = "__netf2"; 349 Names[RTLIB::UNE_PPCF128] = "__gcc_qne"; 350 Names[RTLIB::OGE_F32] = "__gesf2"; 351 Names[RTLIB::OGE_F64] = "__gedf2"; 352 Names[RTLIB::OGE_F128] = "__getf2"; 353 Names[RTLIB::OGE_PPCF128] = "__gcc_qge"; 354 Names[RTLIB::OLT_F32] = "__ltsf2"; 355 Names[RTLIB::OLT_F64] = "__ltdf2"; 356 Names[RTLIB::OLT_F128] = "__lttf2"; 357 Names[RTLIB::OLT_PPCF128] = "__gcc_qlt"; 358 Names[RTLIB::OLE_F32] = "__lesf2"; 359 Names[RTLIB::OLE_F64] = "__ledf2"; 360 Names[RTLIB::OLE_F128] = "__letf2"; 361 Names[RTLIB::OLE_PPCF128] = "__gcc_qle"; 362 Names[RTLIB::OGT_F32] = "__gtsf2"; 363 Names[RTLIB::OGT_F64] = "__gtdf2"; 364 Names[RTLIB::OGT_F128] = "__gttf2"; 365 Names[RTLIB::OGT_PPCF128] = "__gcc_qgt"; 366 Names[RTLIB::UO_F32] = "__unordsf2"; 367 Names[RTLIB::UO_F64] = "__unorddf2"; 368 Names[RTLIB::UO_F128] = "__unordtf2"; 369 Names[RTLIB::UO_PPCF128] = "__gcc_qunord"; 370 Names[RTLIB::O_F32] = "__unordsf2"; 371 Names[RTLIB::O_F64] = "__unorddf2"; 372 Names[RTLIB::O_F128] = "__unordtf2"; 373 Names[RTLIB::O_PPCF128] = "__gcc_qunord"; 374 Names[RTLIB::MEMCPY] = "memcpy"; 375 Names[RTLIB::MEMMOVE] = "memmove"; 376 Names[RTLIB::MEMSET] = "memset"; 377 Names[RTLIB::MEMCPY_ELEMENT_ATOMIC_1] = "__llvm_memcpy_element_atomic_1"; 378 Names[RTLIB::MEMCPY_ELEMENT_ATOMIC_2] = "__llvm_memcpy_element_atomic_2"; 379 Names[RTLIB::MEMCPY_ELEMENT_ATOMIC_4] = "__llvm_memcpy_element_atomic_4"; 380 Names[RTLIB::MEMCPY_ELEMENT_ATOMIC_8] = "__llvm_memcpy_element_atomic_8"; 381 Names[RTLIB::MEMCPY_ELEMENT_ATOMIC_16] = "__llvm_memcpy_element_atomic_16"; 382 Names[RTLIB::UNWIND_RESUME] = "_Unwind_Resume"; 383 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1] = "__sync_val_compare_and_swap_1"; 384 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2] = "__sync_val_compare_and_swap_2"; 385 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4] = "__sync_val_compare_and_swap_4"; 386 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8] = "__sync_val_compare_and_swap_8"; 387 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_16] = "__sync_val_compare_and_swap_16"; 388 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_1] = "__sync_lock_test_and_set_1"; 389 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_2] = "__sync_lock_test_and_set_2"; 390 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_4] = "__sync_lock_test_and_set_4"; 391 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_8] = "__sync_lock_test_and_set_8"; 392 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_16] = "__sync_lock_test_and_set_16"; 393 Names[RTLIB::SYNC_FETCH_AND_ADD_1] = "__sync_fetch_and_add_1"; 394 Names[RTLIB::SYNC_FETCH_AND_ADD_2] = "__sync_fetch_and_add_2"; 395 Names[RTLIB::SYNC_FETCH_AND_ADD_4] = "__sync_fetch_and_add_4"; 396 Names[RTLIB::SYNC_FETCH_AND_ADD_8] = "__sync_fetch_and_add_8"; 397 Names[RTLIB::SYNC_FETCH_AND_ADD_16] = "__sync_fetch_and_add_16"; 398 Names[RTLIB::SYNC_FETCH_AND_SUB_1] = "__sync_fetch_and_sub_1"; 399 Names[RTLIB::SYNC_FETCH_AND_SUB_2] = "__sync_fetch_and_sub_2"; 400 Names[RTLIB::SYNC_FETCH_AND_SUB_4] = "__sync_fetch_and_sub_4"; 401 Names[RTLIB::SYNC_FETCH_AND_SUB_8] = "__sync_fetch_and_sub_8"; 402 Names[RTLIB::SYNC_FETCH_AND_SUB_16] = "__sync_fetch_and_sub_16"; 403 Names[RTLIB::SYNC_FETCH_AND_AND_1] = "__sync_fetch_and_and_1"; 404 Names[RTLIB::SYNC_FETCH_AND_AND_2] = "__sync_fetch_and_and_2"; 405 Names[RTLIB::SYNC_FETCH_AND_AND_4] = "__sync_fetch_and_and_4"; 406 Names[RTLIB::SYNC_FETCH_AND_AND_8] = "__sync_fetch_and_and_8"; 407 Names[RTLIB::SYNC_FETCH_AND_AND_16] = "__sync_fetch_and_and_16"; 408 Names[RTLIB::SYNC_FETCH_AND_OR_1] = "__sync_fetch_and_or_1"; 409 Names[RTLIB::SYNC_FETCH_AND_OR_2] = "__sync_fetch_and_or_2"; 410 Names[RTLIB::SYNC_FETCH_AND_OR_4] = "__sync_fetch_and_or_4"; 411 Names[RTLIB::SYNC_FETCH_AND_OR_8] = "__sync_fetch_and_or_8"; 412 Names[RTLIB::SYNC_FETCH_AND_OR_16] = "__sync_fetch_and_or_16"; 413 Names[RTLIB::SYNC_FETCH_AND_XOR_1] = "__sync_fetch_and_xor_1"; 414 Names[RTLIB::SYNC_FETCH_AND_XOR_2] = "__sync_fetch_and_xor_2"; 415 Names[RTLIB::SYNC_FETCH_AND_XOR_4] = "__sync_fetch_and_xor_4"; 416 Names[RTLIB::SYNC_FETCH_AND_XOR_8] = "__sync_fetch_and_xor_8"; 417 Names[RTLIB::SYNC_FETCH_AND_XOR_16] = "__sync_fetch_and_xor_16"; 418 Names[RTLIB::SYNC_FETCH_AND_NAND_1] = "__sync_fetch_and_nand_1"; 419 Names[RTLIB::SYNC_FETCH_AND_NAND_2] = "__sync_fetch_and_nand_2"; 420 Names[RTLIB::SYNC_FETCH_AND_NAND_4] = "__sync_fetch_and_nand_4"; 421 Names[RTLIB::SYNC_FETCH_AND_NAND_8] = "__sync_fetch_and_nand_8"; 422 Names[RTLIB::SYNC_FETCH_AND_NAND_16] = "__sync_fetch_and_nand_16"; 423 Names[RTLIB::SYNC_FETCH_AND_MAX_1] = "__sync_fetch_and_max_1"; 424 Names[RTLIB::SYNC_FETCH_AND_MAX_2] = "__sync_fetch_and_max_2"; 425 Names[RTLIB::SYNC_FETCH_AND_MAX_4] = "__sync_fetch_and_max_4"; 426 Names[RTLIB::SYNC_FETCH_AND_MAX_8] = "__sync_fetch_and_max_8"; 427 Names[RTLIB::SYNC_FETCH_AND_MAX_16] = "__sync_fetch_and_max_16"; 428 Names[RTLIB::SYNC_FETCH_AND_UMAX_1] = "__sync_fetch_and_umax_1"; 429 Names[RTLIB::SYNC_FETCH_AND_UMAX_2] = "__sync_fetch_and_umax_2"; 430 Names[RTLIB::SYNC_FETCH_AND_UMAX_4] = "__sync_fetch_and_umax_4"; 431 Names[RTLIB::SYNC_FETCH_AND_UMAX_8] = "__sync_fetch_and_umax_8"; 432 Names[RTLIB::SYNC_FETCH_AND_UMAX_16] = "__sync_fetch_and_umax_16"; 433 Names[RTLIB::SYNC_FETCH_AND_MIN_1] = "__sync_fetch_and_min_1"; 434 Names[RTLIB::SYNC_FETCH_AND_MIN_2] = "__sync_fetch_and_min_2"; 435 Names[RTLIB::SYNC_FETCH_AND_MIN_4] = "__sync_fetch_and_min_4"; 436 Names[RTLIB::SYNC_FETCH_AND_MIN_8] = "__sync_fetch_and_min_8"; 437 Names[RTLIB::SYNC_FETCH_AND_MIN_16] = "__sync_fetch_and_min_16"; 438 Names[RTLIB::SYNC_FETCH_AND_UMIN_1] = "__sync_fetch_and_umin_1"; 439 Names[RTLIB::SYNC_FETCH_AND_UMIN_2] = "__sync_fetch_and_umin_2"; 440 Names[RTLIB::SYNC_FETCH_AND_UMIN_4] = "__sync_fetch_and_umin_4"; 441 Names[RTLIB::SYNC_FETCH_AND_UMIN_8] = "__sync_fetch_and_umin_8"; 442 Names[RTLIB::SYNC_FETCH_AND_UMIN_16] = "__sync_fetch_and_umin_16"; 443 444 Names[RTLIB::ATOMIC_LOAD] = "__atomic_load"; 445 Names[RTLIB::ATOMIC_LOAD_1] = "__atomic_load_1"; 446 Names[RTLIB::ATOMIC_LOAD_2] = "__atomic_load_2"; 447 Names[RTLIB::ATOMIC_LOAD_4] = "__atomic_load_4"; 448 Names[RTLIB::ATOMIC_LOAD_8] = "__atomic_load_8"; 449 Names[RTLIB::ATOMIC_LOAD_16] = "__atomic_load_16"; 450 451 Names[RTLIB::ATOMIC_STORE] = "__atomic_store"; 452 Names[RTLIB::ATOMIC_STORE_1] = "__atomic_store_1"; 453 Names[RTLIB::ATOMIC_STORE_2] = "__atomic_store_2"; 454 Names[RTLIB::ATOMIC_STORE_4] = "__atomic_store_4"; 455 Names[RTLIB::ATOMIC_STORE_8] = "__atomic_store_8"; 456 Names[RTLIB::ATOMIC_STORE_16] = "__atomic_store_16"; 457 458 Names[RTLIB::ATOMIC_EXCHANGE] = "__atomic_exchange"; 459 Names[RTLIB::ATOMIC_EXCHANGE_1] = "__atomic_exchange_1"; 460 Names[RTLIB::ATOMIC_EXCHANGE_2] = "__atomic_exchange_2"; 461 Names[RTLIB::ATOMIC_EXCHANGE_4] = "__atomic_exchange_4"; 462 Names[RTLIB::ATOMIC_EXCHANGE_8] = "__atomic_exchange_8"; 463 Names[RTLIB::ATOMIC_EXCHANGE_16] = "__atomic_exchange_16"; 464 465 Names[RTLIB::ATOMIC_COMPARE_EXCHANGE] = "__atomic_compare_exchange"; 466 Names[RTLIB::ATOMIC_COMPARE_EXCHANGE_1] = "__atomic_compare_exchange_1"; 467 Names[RTLIB::ATOMIC_COMPARE_EXCHANGE_2] = "__atomic_compare_exchange_2"; 468 Names[RTLIB::ATOMIC_COMPARE_EXCHANGE_4] = "__atomic_compare_exchange_4"; 469 Names[RTLIB::ATOMIC_COMPARE_EXCHANGE_8] = "__atomic_compare_exchange_8"; 470 Names[RTLIB::ATOMIC_COMPARE_EXCHANGE_16] = "__atomic_compare_exchange_16"; 471 472 Names[RTLIB::ATOMIC_FETCH_ADD_1] = "__atomic_fetch_add_1"; 473 Names[RTLIB::ATOMIC_FETCH_ADD_2] = "__atomic_fetch_add_2"; 474 Names[RTLIB::ATOMIC_FETCH_ADD_4] = "__atomic_fetch_add_4"; 475 Names[RTLIB::ATOMIC_FETCH_ADD_8] = "__atomic_fetch_add_8"; 476 Names[RTLIB::ATOMIC_FETCH_ADD_16] = "__atomic_fetch_add_16"; 477 Names[RTLIB::ATOMIC_FETCH_SUB_1] = "__atomic_fetch_sub_1"; 478 Names[RTLIB::ATOMIC_FETCH_SUB_2] = "__atomic_fetch_sub_2"; 479 Names[RTLIB::ATOMIC_FETCH_SUB_4] = "__atomic_fetch_sub_4"; 480 Names[RTLIB::ATOMIC_FETCH_SUB_8] = "__atomic_fetch_sub_8"; 481 Names[RTLIB::ATOMIC_FETCH_SUB_16] = "__atomic_fetch_sub_16"; 482 Names[RTLIB::ATOMIC_FETCH_AND_1] = "__atomic_fetch_and_1"; 483 Names[RTLIB::ATOMIC_FETCH_AND_2] = "__atomic_fetch_and_2"; 484 Names[RTLIB::ATOMIC_FETCH_AND_4] = "__atomic_fetch_and_4"; 485 Names[RTLIB::ATOMIC_FETCH_AND_8] = "__atomic_fetch_and_8"; 486 Names[RTLIB::ATOMIC_FETCH_AND_16] = "__atomic_fetch_and_16"; 487 Names[RTLIB::ATOMIC_FETCH_OR_1] = "__atomic_fetch_or_1"; 488 Names[RTLIB::ATOMIC_FETCH_OR_2] = "__atomic_fetch_or_2"; 489 Names[RTLIB::ATOMIC_FETCH_OR_4] = "__atomic_fetch_or_4"; 490 Names[RTLIB::ATOMIC_FETCH_OR_8] = "__atomic_fetch_or_8"; 491 Names[RTLIB::ATOMIC_FETCH_OR_16] = "__atomic_fetch_or_16"; 492 Names[RTLIB::ATOMIC_FETCH_XOR_1] = "__atomic_fetch_xor_1"; 493 Names[RTLIB::ATOMIC_FETCH_XOR_2] = "__atomic_fetch_xor_2"; 494 Names[RTLIB::ATOMIC_FETCH_XOR_4] = "__atomic_fetch_xor_4"; 495 Names[RTLIB::ATOMIC_FETCH_XOR_8] = "__atomic_fetch_xor_8"; 496 Names[RTLIB::ATOMIC_FETCH_XOR_16] = "__atomic_fetch_xor_16"; 497 Names[RTLIB::ATOMIC_FETCH_NAND_1] = "__atomic_fetch_nand_1"; 498 Names[RTLIB::ATOMIC_FETCH_NAND_2] = "__atomic_fetch_nand_2"; 499 Names[RTLIB::ATOMIC_FETCH_NAND_4] = "__atomic_fetch_nand_4"; 500 Names[RTLIB::ATOMIC_FETCH_NAND_8] = "__atomic_fetch_nand_8"; 501 Names[RTLIB::ATOMIC_FETCH_NAND_16] = "__atomic_fetch_nand_16"; 502 503 if (TT.isGNUEnvironment()) { 504 Names[RTLIB::SINCOS_F32] = "sincosf"; 505 Names[RTLIB::SINCOS_F64] = "sincos"; 506 Names[RTLIB::SINCOS_F80] = "sincosl"; 507 Names[RTLIB::SINCOS_F128] = "sincosl"; 508 Names[RTLIB::SINCOS_PPCF128] = "sincosl"; 509 } 510 511 if (!TT.isOSOpenBSD()) { 512 Names[RTLIB::STACKPROTECTOR_CHECK_FAIL] = "__stack_chk_fail"; 513 } 514 515 Names[RTLIB::DEOPTIMIZE] = "__llvm_deoptimize"; 516 } 517 518 /// Set default libcall CallingConvs. 519 static void InitLibcallCallingConvs(CallingConv::ID *CCs) { 520 for (int LC = 0; LC < RTLIB::UNKNOWN_LIBCALL; ++LC) 521 CCs[LC] = CallingConv::C; 522 } 523 524 /// getFPEXT - Return the FPEXT_*_* value for the given types, or 525 /// UNKNOWN_LIBCALL if there is none. 526 RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) { 527 if (OpVT == MVT::f16) { 528 if (RetVT == MVT::f32) 529 return FPEXT_F16_F32; 530 } else if (OpVT == MVT::f32) { 531 if (RetVT == MVT::f64) 532 return FPEXT_F32_F64; 533 if (RetVT == MVT::f128) 534 return FPEXT_F32_F128; 535 if (RetVT == MVT::ppcf128) 536 return FPEXT_F32_PPCF128; 537 } else if (OpVT == MVT::f64) { 538 if (RetVT == MVT::f128) 539 return FPEXT_F64_F128; 540 else if (RetVT == MVT::ppcf128) 541 return FPEXT_F64_PPCF128; 542 } 543 544 return UNKNOWN_LIBCALL; 545 } 546 547 /// getFPROUND - Return the FPROUND_*_* value for the given types, or 548 /// UNKNOWN_LIBCALL if there is none. 549 RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) { 550 if (RetVT == MVT::f16) { 551 if (OpVT == MVT::f32) 552 return FPROUND_F32_F16; 553 if (OpVT == MVT::f64) 554 return FPROUND_F64_F16; 555 if (OpVT == MVT::f80) 556 return FPROUND_F80_F16; 557 if (OpVT == MVT::f128) 558 return FPROUND_F128_F16; 559 if (OpVT == MVT::ppcf128) 560 return FPROUND_PPCF128_F16; 561 } else if (RetVT == MVT::f32) { 562 if (OpVT == MVT::f64) 563 return FPROUND_F64_F32; 564 if (OpVT == MVT::f80) 565 return FPROUND_F80_F32; 566 if (OpVT == MVT::f128) 567 return FPROUND_F128_F32; 568 if (OpVT == MVT::ppcf128) 569 return FPROUND_PPCF128_F32; 570 } else if (RetVT == MVT::f64) { 571 if (OpVT == MVT::f80) 572 return FPROUND_F80_F64; 573 if (OpVT == MVT::f128) 574 return FPROUND_F128_F64; 575 if (OpVT == MVT::ppcf128) 576 return FPROUND_PPCF128_F64; 577 } 578 579 return UNKNOWN_LIBCALL; 580 } 581 582 /// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or 583 /// UNKNOWN_LIBCALL if there is none. 584 RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT, EVT RetVT) { 585 if (OpVT == MVT::f32) { 586 if (RetVT == MVT::i32) 587 return FPTOSINT_F32_I32; 588 if (RetVT == MVT::i64) 589 return FPTOSINT_F32_I64; 590 if (RetVT == MVT::i128) 591 return FPTOSINT_F32_I128; 592 } else if (OpVT == MVT::f64) { 593 if (RetVT == MVT::i32) 594 return FPTOSINT_F64_I32; 595 if (RetVT == MVT::i64) 596 return FPTOSINT_F64_I64; 597 if (RetVT == MVT::i128) 598 return FPTOSINT_F64_I128; 599 } else if (OpVT == MVT::f80) { 600 if (RetVT == MVT::i32) 601 return FPTOSINT_F80_I32; 602 if (RetVT == MVT::i64) 603 return FPTOSINT_F80_I64; 604 if (RetVT == MVT::i128) 605 return FPTOSINT_F80_I128; 606 } else if (OpVT == MVT::f128) { 607 if (RetVT == MVT::i32) 608 return FPTOSINT_F128_I32; 609 if (RetVT == MVT::i64) 610 return FPTOSINT_F128_I64; 611 if (RetVT == MVT::i128) 612 return FPTOSINT_F128_I128; 613 } else if (OpVT == MVT::ppcf128) { 614 if (RetVT == MVT::i32) 615 return FPTOSINT_PPCF128_I32; 616 if (RetVT == MVT::i64) 617 return FPTOSINT_PPCF128_I64; 618 if (RetVT == MVT::i128) 619 return FPTOSINT_PPCF128_I128; 620 } 621 return UNKNOWN_LIBCALL; 622 } 623 624 /// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or 625 /// UNKNOWN_LIBCALL if there is none. 626 RTLIB::Libcall RTLIB::getFPTOUINT(EVT OpVT, EVT RetVT) { 627 if (OpVT == MVT::f32) { 628 if (RetVT == MVT::i32) 629 return FPTOUINT_F32_I32; 630 if (RetVT == MVT::i64) 631 return FPTOUINT_F32_I64; 632 if (RetVT == MVT::i128) 633 return FPTOUINT_F32_I128; 634 } else if (OpVT == MVT::f64) { 635 if (RetVT == MVT::i32) 636 return FPTOUINT_F64_I32; 637 if (RetVT == MVT::i64) 638 return FPTOUINT_F64_I64; 639 if (RetVT == MVT::i128) 640 return FPTOUINT_F64_I128; 641 } else if (OpVT == MVT::f80) { 642 if (RetVT == MVT::i32) 643 return FPTOUINT_F80_I32; 644 if (RetVT == MVT::i64) 645 return FPTOUINT_F80_I64; 646 if (RetVT == MVT::i128) 647 return FPTOUINT_F80_I128; 648 } else if (OpVT == MVT::f128) { 649 if (RetVT == MVT::i32) 650 return FPTOUINT_F128_I32; 651 if (RetVT == MVT::i64) 652 return FPTOUINT_F128_I64; 653 if (RetVT == MVT::i128) 654 return FPTOUINT_F128_I128; 655 } else if (OpVT == MVT::ppcf128) { 656 if (RetVT == MVT::i32) 657 return FPTOUINT_PPCF128_I32; 658 if (RetVT == MVT::i64) 659 return FPTOUINT_PPCF128_I64; 660 if (RetVT == MVT::i128) 661 return FPTOUINT_PPCF128_I128; 662 } 663 return UNKNOWN_LIBCALL; 664 } 665 666 /// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or 667 /// UNKNOWN_LIBCALL if there is none. 668 RTLIB::Libcall RTLIB::getSINTTOFP(EVT OpVT, EVT RetVT) { 669 if (OpVT == MVT::i32) { 670 if (RetVT == MVT::f32) 671 return SINTTOFP_I32_F32; 672 if (RetVT == MVT::f64) 673 return SINTTOFP_I32_F64; 674 if (RetVT == MVT::f80) 675 return SINTTOFP_I32_F80; 676 if (RetVT == MVT::f128) 677 return SINTTOFP_I32_F128; 678 if (RetVT == MVT::ppcf128) 679 return SINTTOFP_I32_PPCF128; 680 } else if (OpVT == MVT::i64) { 681 if (RetVT == MVT::f32) 682 return SINTTOFP_I64_F32; 683 if (RetVT == MVT::f64) 684 return SINTTOFP_I64_F64; 685 if (RetVT == MVT::f80) 686 return SINTTOFP_I64_F80; 687 if (RetVT == MVT::f128) 688 return SINTTOFP_I64_F128; 689 if (RetVT == MVT::ppcf128) 690 return SINTTOFP_I64_PPCF128; 691 } else if (OpVT == MVT::i128) { 692 if (RetVT == MVT::f32) 693 return SINTTOFP_I128_F32; 694 if (RetVT == MVT::f64) 695 return SINTTOFP_I128_F64; 696 if (RetVT == MVT::f80) 697 return SINTTOFP_I128_F80; 698 if (RetVT == MVT::f128) 699 return SINTTOFP_I128_F128; 700 if (RetVT == MVT::ppcf128) 701 return SINTTOFP_I128_PPCF128; 702 } 703 return UNKNOWN_LIBCALL; 704 } 705 706 /// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or 707 /// UNKNOWN_LIBCALL if there is none. 708 RTLIB::Libcall RTLIB::getUINTTOFP(EVT OpVT, EVT RetVT) { 709 if (OpVT == MVT::i32) { 710 if (RetVT == MVT::f32) 711 return UINTTOFP_I32_F32; 712 if (RetVT == MVT::f64) 713 return UINTTOFP_I32_F64; 714 if (RetVT == MVT::f80) 715 return UINTTOFP_I32_F80; 716 if (RetVT == MVT::f128) 717 return UINTTOFP_I32_F128; 718 if (RetVT == MVT::ppcf128) 719 return UINTTOFP_I32_PPCF128; 720 } else if (OpVT == MVT::i64) { 721 if (RetVT == MVT::f32) 722 return UINTTOFP_I64_F32; 723 if (RetVT == MVT::f64) 724 return UINTTOFP_I64_F64; 725 if (RetVT == MVT::f80) 726 return UINTTOFP_I64_F80; 727 if (RetVT == MVT::f128) 728 return UINTTOFP_I64_F128; 729 if (RetVT == MVT::ppcf128) 730 return UINTTOFP_I64_PPCF128; 731 } else if (OpVT == MVT::i128) { 732 if (RetVT == MVT::f32) 733 return UINTTOFP_I128_F32; 734 if (RetVT == MVT::f64) 735 return UINTTOFP_I128_F64; 736 if (RetVT == MVT::f80) 737 return UINTTOFP_I128_F80; 738 if (RetVT == MVT::f128) 739 return UINTTOFP_I128_F128; 740 if (RetVT == MVT::ppcf128) 741 return UINTTOFP_I128_PPCF128; 742 } 743 return UNKNOWN_LIBCALL; 744 } 745 746 RTLIB::Libcall RTLIB::getSYNC(unsigned Opc, MVT VT) { 747 #define OP_TO_LIBCALL(Name, Enum) \ 748 case Name: \ 749 switch (VT.SimpleTy) { \ 750 default: \ 751 return UNKNOWN_LIBCALL; \ 752 case MVT::i8: \ 753 return Enum##_1; \ 754 case MVT::i16: \ 755 return Enum##_2; \ 756 case MVT::i32: \ 757 return Enum##_4; \ 758 case MVT::i64: \ 759 return Enum##_8; \ 760 case MVT::i128: \ 761 return Enum##_16; \ 762 } 763 764 switch (Opc) { 765 OP_TO_LIBCALL(ISD::ATOMIC_SWAP, SYNC_LOCK_TEST_AND_SET) 766 OP_TO_LIBCALL(ISD::ATOMIC_CMP_SWAP, SYNC_VAL_COMPARE_AND_SWAP) 767 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_ADD, SYNC_FETCH_AND_ADD) 768 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_SUB, SYNC_FETCH_AND_SUB) 769 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_AND, SYNC_FETCH_AND_AND) 770 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_OR, SYNC_FETCH_AND_OR) 771 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_XOR, SYNC_FETCH_AND_XOR) 772 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_NAND, SYNC_FETCH_AND_NAND) 773 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_MAX, SYNC_FETCH_AND_MAX) 774 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_UMAX, SYNC_FETCH_AND_UMAX) 775 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_MIN, SYNC_FETCH_AND_MIN) 776 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_UMIN, SYNC_FETCH_AND_UMIN) 777 } 778 779 #undef OP_TO_LIBCALL 780 781 return UNKNOWN_LIBCALL; 782 } 783 784 RTLIB::Libcall RTLIB::getMEMCPY_ELEMENT_ATOMIC(uint64_t ElementSize) { 785 switch (ElementSize) { 786 case 1: 787 return MEMCPY_ELEMENT_ATOMIC_1; 788 case 2: 789 return MEMCPY_ELEMENT_ATOMIC_2; 790 case 4: 791 return MEMCPY_ELEMENT_ATOMIC_4; 792 case 8: 793 return MEMCPY_ELEMENT_ATOMIC_8; 794 case 16: 795 return MEMCPY_ELEMENT_ATOMIC_16; 796 default: 797 return UNKNOWN_LIBCALL; 798 } 799 800 } 801 802 /// InitCmpLibcallCCs - Set default comparison libcall CC. 803 /// 804 static void InitCmpLibcallCCs(ISD::CondCode *CCs) { 805 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL); 806 CCs[RTLIB::OEQ_F32] = ISD::SETEQ; 807 CCs[RTLIB::OEQ_F64] = ISD::SETEQ; 808 CCs[RTLIB::OEQ_F128] = ISD::SETEQ; 809 CCs[RTLIB::OEQ_PPCF128] = ISD::SETEQ; 810 CCs[RTLIB::UNE_F32] = ISD::SETNE; 811 CCs[RTLIB::UNE_F64] = ISD::SETNE; 812 CCs[RTLIB::UNE_F128] = ISD::SETNE; 813 CCs[RTLIB::UNE_PPCF128] = ISD::SETNE; 814 CCs[RTLIB::OGE_F32] = ISD::SETGE; 815 CCs[RTLIB::OGE_F64] = ISD::SETGE; 816 CCs[RTLIB::OGE_F128] = ISD::SETGE; 817 CCs[RTLIB::OGE_PPCF128] = ISD::SETGE; 818 CCs[RTLIB::OLT_F32] = ISD::SETLT; 819 CCs[RTLIB::OLT_F64] = ISD::SETLT; 820 CCs[RTLIB::OLT_F128] = ISD::SETLT; 821 CCs[RTLIB::OLT_PPCF128] = ISD::SETLT; 822 CCs[RTLIB::OLE_F32] = ISD::SETLE; 823 CCs[RTLIB::OLE_F64] = ISD::SETLE; 824 CCs[RTLIB::OLE_F128] = ISD::SETLE; 825 CCs[RTLIB::OLE_PPCF128] = ISD::SETLE; 826 CCs[RTLIB::OGT_F32] = ISD::SETGT; 827 CCs[RTLIB::OGT_F64] = ISD::SETGT; 828 CCs[RTLIB::OGT_F128] = ISD::SETGT; 829 CCs[RTLIB::OGT_PPCF128] = ISD::SETGT; 830 CCs[RTLIB::UO_F32] = ISD::SETNE; 831 CCs[RTLIB::UO_F64] = ISD::SETNE; 832 CCs[RTLIB::UO_F128] = ISD::SETNE; 833 CCs[RTLIB::UO_PPCF128] = ISD::SETNE; 834 CCs[RTLIB::O_F32] = ISD::SETEQ; 835 CCs[RTLIB::O_F64] = ISD::SETEQ; 836 CCs[RTLIB::O_F128] = ISD::SETEQ; 837 CCs[RTLIB::O_PPCF128] = ISD::SETEQ; 838 } 839 840 /// NOTE: The TargetMachine owns TLOF. 841 TargetLoweringBase::TargetLoweringBase(const TargetMachine &tm) : TM(tm) { 842 initActions(); 843 844 // Perform these initializations only once. 845 MaxStoresPerMemset = MaxStoresPerMemcpy = MaxStoresPerMemmove = 8; 846 MaxStoresPerMemsetOptSize = MaxStoresPerMemcpyOptSize 847 = MaxStoresPerMemmoveOptSize = 4; 848 UseUnderscoreSetJmp = false; 849 UseUnderscoreLongJmp = false; 850 HasMultipleConditionRegisters = false; 851 HasExtractBitsInsn = false; 852 JumpIsExpensive = JumpIsExpensiveOverride; 853 PredictableSelectIsExpensive = false; 854 EnableExtLdPromotion = false; 855 HasFloatingPointExceptions = true; 856 StackPointerRegisterToSaveRestore = 0; 857 BooleanContents = UndefinedBooleanContent; 858 BooleanFloatContents = UndefinedBooleanContent; 859 BooleanVectorContents = UndefinedBooleanContent; 860 SchedPreferenceInfo = Sched::ILP; 861 JumpBufSize = 0; 862 JumpBufAlignment = 0; 863 MinFunctionAlignment = 0; 864 PrefFunctionAlignment = 0; 865 PrefLoopAlignment = 0; 866 GatherAllAliasesMaxDepth = 18; 867 MinStackArgumentAlignment = 1; 868 // TODO: the default will be switched to 0 in the next commit, along 869 // with the Target-specific changes necessary. 870 MaxAtomicSizeInBitsSupported = 1024; 871 872 MinCmpXchgSizeInBits = 0; 873 874 std::fill(std::begin(LibcallRoutineNames), std::end(LibcallRoutineNames), nullptr); 875 876 InitLibcallNames(LibcallRoutineNames, TM.getTargetTriple()); 877 InitCmpLibcallCCs(CmpLibcallCCs); 878 InitLibcallCallingConvs(LibcallCallingConvs); 879 } 880 881 void TargetLoweringBase::initActions() { 882 // All operations default to being supported. 883 memset(OpActions, 0, sizeof(OpActions)); 884 memset(LoadExtActions, 0, sizeof(LoadExtActions)); 885 memset(TruncStoreActions, 0, sizeof(TruncStoreActions)); 886 memset(IndexedModeActions, 0, sizeof(IndexedModeActions)); 887 memset(CondCodeActions, 0, sizeof(CondCodeActions)); 888 std::fill(std::begin(RegClassForVT), std::end(RegClassForVT), nullptr); 889 std::fill(std::begin(TargetDAGCombineArray), 890 std::end(TargetDAGCombineArray), 0); 891 892 // Set default actions for various operations. 893 for (MVT VT : MVT::all_valuetypes()) { 894 // Default all indexed load / store to expand. 895 for (unsigned IM = (unsigned)ISD::PRE_INC; 896 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) { 897 setIndexedLoadAction(IM, VT, Expand); 898 setIndexedStoreAction(IM, VT, Expand); 899 } 900 901 // Most backends expect to see the node which just returns the value loaded. 902 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Expand); 903 904 // These operations default to expand. 905 setOperationAction(ISD::FGETSIGN, VT, Expand); 906 setOperationAction(ISD::CONCAT_VECTORS, VT, Expand); 907 setOperationAction(ISD::FMINNUM, VT, Expand); 908 setOperationAction(ISD::FMAXNUM, VT, Expand); 909 setOperationAction(ISD::FMINNAN, VT, Expand); 910 setOperationAction(ISD::FMAXNAN, VT, Expand); 911 setOperationAction(ISD::FMAD, VT, Expand); 912 setOperationAction(ISD::SMIN, VT, Expand); 913 setOperationAction(ISD::SMAX, VT, Expand); 914 setOperationAction(ISD::UMIN, VT, Expand); 915 setOperationAction(ISD::UMAX, VT, Expand); 916 setOperationAction(ISD::ABS, VT, Expand); 917 918 // Overflow operations default to expand 919 setOperationAction(ISD::SADDO, VT, Expand); 920 setOperationAction(ISD::SSUBO, VT, Expand); 921 setOperationAction(ISD::UADDO, VT, Expand); 922 setOperationAction(ISD::USUBO, VT, Expand); 923 setOperationAction(ISD::SMULO, VT, Expand); 924 setOperationAction(ISD::UMULO, VT, Expand); 925 926 // ADDCARRY operations default to expand 927 setOperationAction(ISD::ADDCARRY, VT, Expand); 928 setOperationAction(ISD::SUBCARRY, VT, Expand); 929 930 // These default to Expand so they will be expanded to CTLZ/CTTZ by default. 931 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand); 932 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand); 933 934 setOperationAction(ISD::BITREVERSE, VT, Expand); 935 936 // These library functions default to expand. 937 setOperationAction(ISD::FROUND, VT, Expand); 938 939 // These operations default to expand for vector types. 940 if (VT.isVector()) { 941 setOperationAction(ISD::FCOPYSIGN, VT, Expand); 942 setOperationAction(ISD::ANY_EXTEND_VECTOR_INREG, VT, Expand); 943 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, VT, Expand); 944 setOperationAction(ISD::ZERO_EXTEND_VECTOR_INREG, VT, Expand); 945 } 946 947 // For most targets @llvm.get.dynamic.area.offset just returns 0. 948 setOperationAction(ISD::GET_DYNAMIC_AREA_OFFSET, VT, Expand); 949 } 950 951 // Most targets ignore the @llvm.prefetch intrinsic. 952 setOperationAction(ISD::PREFETCH, MVT::Other, Expand); 953 954 // Most targets also ignore the @llvm.readcyclecounter intrinsic. 955 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Expand); 956 957 // ConstantFP nodes default to expand. Targets can either change this to 958 // Legal, in which case all fp constants are legal, or use isFPImmLegal() 959 // to optimize expansions for certain constants. 960 setOperationAction(ISD::ConstantFP, MVT::f16, Expand); 961 setOperationAction(ISD::ConstantFP, MVT::f32, Expand); 962 setOperationAction(ISD::ConstantFP, MVT::f64, Expand); 963 setOperationAction(ISD::ConstantFP, MVT::f80, Expand); 964 setOperationAction(ISD::ConstantFP, MVT::f128, Expand); 965 966 // These library functions default to expand. 967 for (MVT VT : {MVT::f32, MVT::f64, MVT::f128}) { 968 setOperationAction(ISD::FLOG , VT, Expand); 969 setOperationAction(ISD::FLOG2, VT, Expand); 970 setOperationAction(ISD::FLOG10, VT, Expand); 971 setOperationAction(ISD::FEXP , VT, Expand); 972 setOperationAction(ISD::FEXP2, VT, Expand); 973 setOperationAction(ISD::FFLOOR, VT, Expand); 974 setOperationAction(ISD::FNEARBYINT, VT, Expand); 975 setOperationAction(ISD::FCEIL, VT, Expand); 976 setOperationAction(ISD::FRINT, VT, Expand); 977 setOperationAction(ISD::FTRUNC, VT, Expand); 978 setOperationAction(ISD::FROUND, VT, Expand); 979 } 980 981 // Default ISD::TRAP to expand (which turns it into abort). 982 setOperationAction(ISD::TRAP, MVT::Other, Expand); 983 984 // On most systems, DEBUGTRAP and TRAP have no difference. The "Expand" 985 // here is to inform DAG Legalizer to replace DEBUGTRAP with TRAP. 986 // 987 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Expand); 988 } 989 990 MVT TargetLoweringBase::getScalarShiftAmountTy(const DataLayout &DL, 991 EVT) const { 992 return MVT::getIntegerVT(8 * DL.getPointerSize(0)); 993 } 994 995 EVT TargetLoweringBase::getShiftAmountTy(EVT LHSTy, 996 const DataLayout &DL) const { 997 assert(LHSTy.isInteger() && "Shift amount is not an integer type!"); 998 if (LHSTy.isVector()) 999 return LHSTy; 1000 return getScalarShiftAmountTy(DL, LHSTy); 1001 } 1002 1003 bool TargetLoweringBase::canOpTrap(unsigned Op, EVT VT) const { 1004 assert(isTypeLegal(VT)); 1005 switch (Op) { 1006 default: 1007 return false; 1008 case ISD::SDIV: 1009 case ISD::UDIV: 1010 case ISD::SREM: 1011 case ISD::UREM: 1012 return true; 1013 } 1014 } 1015 1016 void TargetLoweringBase::setJumpIsExpensive(bool isExpensive) { 1017 // If the command-line option was specified, ignore this request. 1018 if (!JumpIsExpensiveOverride.getNumOccurrences()) 1019 JumpIsExpensive = isExpensive; 1020 } 1021 1022 TargetLoweringBase::LegalizeKind 1023 TargetLoweringBase::getTypeConversion(LLVMContext &Context, EVT VT) const { 1024 // If this is a simple type, use the ComputeRegisterProp mechanism. 1025 if (VT.isSimple()) { 1026 MVT SVT = VT.getSimpleVT(); 1027 assert((unsigned)SVT.SimpleTy < array_lengthof(TransformToType)); 1028 MVT NVT = TransformToType[SVT.SimpleTy]; 1029 LegalizeTypeAction LA = ValueTypeActions.getTypeAction(SVT); 1030 1031 assert((LA == TypeLegal || LA == TypeSoftenFloat || 1032 ValueTypeActions.getTypeAction(NVT) != TypePromoteInteger) && 1033 "Promote may not follow Expand or Promote"); 1034 1035 if (LA == TypeSplitVector) 1036 return LegalizeKind(LA, 1037 EVT::getVectorVT(Context, SVT.getVectorElementType(), 1038 SVT.getVectorNumElements() / 2)); 1039 if (LA == TypeScalarizeVector) 1040 return LegalizeKind(LA, SVT.getVectorElementType()); 1041 return LegalizeKind(LA, NVT); 1042 } 1043 1044 // Handle Extended Scalar Types. 1045 if (!VT.isVector()) { 1046 assert(VT.isInteger() && "Float types must be simple"); 1047 unsigned BitSize = VT.getSizeInBits(); 1048 // First promote to a power-of-two size, then expand if necessary. 1049 if (BitSize < 8 || !isPowerOf2_32(BitSize)) { 1050 EVT NVT = VT.getRoundIntegerType(Context); 1051 assert(NVT != VT && "Unable to round integer VT"); 1052 LegalizeKind NextStep = getTypeConversion(Context, NVT); 1053 // Avoid multi-step promotion. 1054 if (NextStep.first == TypePromoteInteger) 1055 return NextStep; 1056 // Return rounded integer type. 1057 return LegalizeKind(TypePromoteInteger, NVT); 1058 } 1059 1060 return LegalizeKind(TypeExpandInteger, 1061 EVT::getIntegerVT(Context, VT.getSizeInBits() / 2)); 1062 } 1063 1064 // Handle vector types. 1065 unsigned NumElts = VT.getVectorNumElements(); 1066 EVT EltVT = VT.getVectorElementType(); 1067 1068 // Vectors with only one element are always scalarized. 1069 if (NumElts == 1) 1070 return LegalizeKind(TypeScalarizeVector, EltVT); 1071 1072 // Try to widen vector elements until the element type is a power of two and 1073 // promote it to a legal type later on, for example: 1074 // <3 x i8> -> <4 x i8> -> <4 x i32> 1075 if (EltVT.isInteger()) { 1076 // Vectors with a number of elements that is not a power of two are always 1077 // widened, for example <3 x i8> -> <4 x i8>. 1078 if (!VT.isPow2VectorType()) { 1079 NumElts = (unsigned)NextPowerOf2(NumElts); 1080 EVT NVT = EVT::getVectorVT(Context, EltVT, NumElts); 1081 return LegalizeKind(TypeWidenVector, NVT); 1082 } 1083 1084 // Examine the element type. 1085 LegalizeKind LK = getTypeConversion(Context, EltVT); 1086 1087 // If type is to be expanded, split the vector. 1088 // <4 x i140> -> <2 x i140> 1089 if (LK.first == TypeExpandInteger) 1090 return LegalizeKind(TypeSplitVector, 1091 EVT::getVectorVT(Context, EltVT, NumElts / 2)); 1092 1093 // Promote the integer element types until a legal vector type is found 1094 // or until the element integer type is too big. If a legal type was not 1095 // found, fallback to the usual mechanism of widening/splitting the 1096 // vector. 1097 EVT OldEltVT = EltVT; 1098 while (1) { 1099 // Increase the bitwidth of the element to the next pow-of-two 1100 // (which is greater than 8 bits). 1101 EltVT = EVT::getIntegerVT(Context, 1 + EltVT.getSizeInBits()) 1102 .getRoundIntegerType(Context); 1103 1104 // Stop trying when getting a non-simple element type. 1105 // Note that vector elements may be greater than legal vector element 1106 // types. Example: X86 XMM registers hold 64bit element on 32bit 1107 // systems. 1108 if (!EltVT.isSimple()) 1109 break; 1110 1111 // Build a new vector type and check if it is legal. 1112 MVT NVT = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts); 1113 // Found a legal promoted vector type. 1114 if (NVT != MVT() && ValueTypeActions.getTypeAction(NVT) == TypeLegal) 1115 return LegalizeKind(TypePromoteInteger, 1116 EVT::getVectorVT(Context, EltVT, NumElts)); 1117 } 1118 1119 // Reset the type to the unexpanded type if we did not find a legal vector 1120 // type with a promoted vector element type. 1121 EltVT = OldEltVT; 1122 } 1123 1124 // Try to widen the vector until a legal type is found. 1125 // If there is no wider legal type, split the vector. 1126 while (1) { 1127 // Round up to the next power of 2. 1128 NumElts = (unsigned)NextPowerOf2(NumElts); 1129 1130 // If there is no simple vector type with this many elements then there 1131 // cannot be a larger legal vector type. Note that this assumes that 1132 // there are no skipped intermediate vector types in the simple types. 1133 if (!EltVT.isSimple()) 1134 break; 1135 MVT LargerVector = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts); 1136 if (LargerVector == MVT()) 1137 break; 1138 1139 // If this type is legal then widen the vector. 1140 if (ValueTypeActions.getTypeAction(LargerVector) == TypeLegal) 1141 return LegalizeKind(TypeWidenVector, LargerVector); 1142 } 1143 1144 // Widen odd vectors to next power of two. 1145 if (!VT.isPow2VectorType()) { 1146 EVT NVT = VT.getPow2VectorType(Context); 1147 return LegalizeKind(TypeWidenVector, NVT); 1148 } 1149 1150 // Vectors with illegal element types are expanded. 1151 EVT NVT = EVT::getVectorVT(Context, EltVT, VT.getVectorNumElements() / 2); 1152 return LegalizeKind(TypeSplitVector, NVT); 1153 } 1154 1155 static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT, 1156 unsigned &NumIntermediates, 1157 MVT &RegisterVT, 1158 TargetLoweringBase *TLI) { 1159 // Figure out the right, legal destination reg to copy into. 1160 unsigned NumElts = VT.getVectorNumElements(); 1161 MVT EltTy = VT.getVectorElementType(); 1162 1163 unsigned NumVectorRegs = 1; 1164 1165 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we 1166 // could break down into LHS/RHS like LegalizeDAG does. 1167 if (!isPowerOf2_32(NumElts)) { 1168 NumVectorRegs = NumElts; 1169 NumElts = 1; 1170 } 1171 1172 // Divide the input until we get to a supported size. This will always 1173 // end with a scalar if the target doesn't support vectors. 1174 while (NumElts > 1 && !TLI->isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) { 1175 NumElts >>= 1; 1176 NumVectorRegs <<= 1; 1177 } 1178 1179 NumIntermediates = NumVectorRegs; 1180 1181 MVT NewVT = MVT::getVectorVT(EltTy, NumElts); 1182 if (!TLI->isTypeLegal(NewVT)) 1183 NewVT = EltTy; 1184 IntermediateVT = NewVT; 1185 1186 unsigned NewVTSize = NewVT.getSizeInBits(); 1187 1188 // Convert sizes such as i33 to i64. 1189 if (!isPowerOf2_32(NewVTSize)) 1190 NewVTSize = NextPowerOf2(NewVTSize); 1191 1192 MVT DestVT = TLI->getRegisterType(NewVT); 1193 RegisterVT = DestVT; 1194 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16. 1195 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits()); 1196 1197 // Otherwise, promotion or legal types use the same number of registers as 1198 // the vector decimated to the appropriate level. 1199 return NumVectorRegs; 1200 } 1201 1202 /// isLegalRC - Return true if the value types that can be represented by the 1203 /// specified register class are all legal. 1204 bool TargetLoweringBase::isLegalRC(const TargetRegisterInfo &TRI, 1205 const TargetRegisterClass &RC) const { 1206 for (auto I = TRI.legalclasstypes_begin(RC); *I != MVT::Other; ++I) 1207 if (isTypeLegal(*I)) 1208 return true; 1209 return false; 1210 } 1211 1212 /// Replace/modify any TargetFrameIndex operands with a targte-dependent 1213 /// sequence of memory operands that is recognized by PrologEpilogInserter. 1214 MachineBasicBlock * 1215 TargetLoweringBase::emitPatchPoint(MachineInstr &InitialMI, 1216 MachineBasicBlock *MBB) const { 1217 MachineInstr *MI = &InitialMI; 1218 MachineFunction &MF = *MI->getParent()->getParent(); 1219 MachineFrameInfo &MFI = MF.getFrameInfo(); 1220 1221 // We're handling multiple types of operands here: 1222 // PATCHPOINT MetaArgs - live-in, read only, direct 1223 // STATEPOINT Deopt Spill - live-through, read only, indirect 1224 // STATEPOINT Deopt Alloca - live-through, read only, direct 1225 // (We're currently conservative and mark the deopt slots read/write in 1226 // practice.) 1227 // STATEPOINT GC Spill - live-through, read/write, indirect 1228 // STATEPOINT GC Alloca - live-through, read/write, direct 1229 // The live-in vs live-through is handled already (the live through ones are 1230 // all stack slots), but we need to handle the different type of stackmap 1231 // operands and memory effects here. 1232 1233 // MI changes inside this loop as we grow operands. 1234 for(unsigned OperIdx = 0; OperIdx != MI->getNumOperands(); ++OperIdx) { 1235 MachineOperand &MO = MI->getOperand(OperIdx); 1236 if (!MO.isFI()) 1237 continue; 1238 1239 // foldMemoryOperand builds a new MI after replacing a single FI operand 1240 // with the canonical set of five x86 addressing-mode operands. 1241 int FI = MO.getIndex(); 1242 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), MI->getDesc()); 1243 1244 // Copy operands before the frame-index. 1245 for (unsigned i = 0; i < OperIdx; ++i) 1246 MIB.add(MI->getOperand(i)); 1247 // Add frame index operands recognized by stackmaps.cpp 1248 if (MFI.isStatepointSpillSlotObjectIndex(FI)) { 1249 // indirect-mem-ref tag, size, #FI, offset. 1250 // Used for spills inserted by StatepointLowering. This codepath is not 1251 // used for patchpoints/stackmaps at all, for these spilling is done via 1252 // foldMemoryOperand callback only. 1253 assert(MI->getOpcode() == TargetOpcode::STATEPOINT && "sanity"); 1254 MIB.addImm(StackMaps::IndirectMemRefOp); 1255 MIB.addImm(MFI.getObjectSize(FI)); 1256 MIB.add(MI->getOperand(OperIdx)); 1257 MIB.addImm(0); 1258 } else { 1259 // direct-mem-ref tag, #FI, offset. 1260 // Used by patchpoint, and direct alloca arguments to statepoints 1261 MIB.addImm(StackMaps::DirectMemRefOp); 1262 MIB.add(MI->getOperand(OperIdx)); 1263 MIB.addImm(0); 1264 } 1265 // Copy the operands after the frame index. 1266 for (unsigned i = OperIdx + 1; i != MI->getNumOperands(); ++i) 1267 MIB.add(MI->getOperand(i)); 1268 1269 // Inherit previous memory operands. 1270 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end()); 1271 assert(MIB->mayLoad() && "Folded a stackmap use to a non-load!"); 1272 1273 // Add a new memory operand for this FI. 1274 assert(MFI.getObjectOffset(FI) != -1); 1275 1276 auto Flags = MachineMemOperand::MOLoad; 1277 if (MI->getOpcode() == TargetOpcode::STATEPOINT) { 1278 Flags |= MachineMemOperand::MOStore; 1279 Flags |= MachineMemOperand::MOVolatile; 1280 } 1281 MachineMemOperand *MMO = MF.getMachineMemOperand( 1282 MachinePointerInfo::getFixedStack(MF, FI), Flags, 1283 MF.getDataLayout().getPointerSize(), MFI.getObjectAlignment(FI)); 1284 MIB->addMemOperand(MF, MMO); 1285 1286 // Replace the instruction and update the operand index. 1287 MBB->insert(MachineBasicBlock::iterator(MI), MIB); 1288 OperIdx += (MIB->getNumOperands() - MI->getNumOperands()) - 1; 1289 MI->eraseFromParent(); 1290 MI = MIB; 1291 } 1292 return MBB; 1293 } 1294 1295 /// findRepresentativeClass - Return the largest legal super-reg register class 1296 /// of the register class for the specified type and its associated "cost". 1297 // This function is in TargetLowering because it uses RegClassForVT which would 1298 // need to be moved to TargetRegisterInfo and would necessitate moving 1299 // isTypeLegal over as well - a massive change that would just require 1300 // TargetLowering having a TargetRegisterInfo class member that it would use. 1301 std::pair<const TargetRegisterClass *, uint8_t> 1302 TargetLoweringBase::findRepresentativeClass(const TargetRegisterInfo *TRI, 1303 MVT VT) const { 1304 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy]; 1305 if (!RC) 1306 return std::make_pair(RC, 0); 1307 1308 // Compute the set of all super-register classes. 1309 BitVector SuperRegRC(TRI->getNumRegClasses()); 1310 for (SuperRegClassIterator RCI(RC, TRI); RCI.isValid(); ++RCI) 1311 SuperRegRC.setBitsInMask(RCI.getMask()); 1312 1313 // Find the first legal register class with the largest spill size. 1314 const TargetRegisterClass *BestRC = RC; 1315 for (int i = SuperRegRC.find_first(); i >= 0; i = SuperRegRC.find_next(i)) { 1316 const TargetRegisterClass *SuperRC = TRI->getRegClass(i); 1317 // We want the largest possible spill size. 1318 if (TRI->getSpillSize(*SuperRC) <= TRI->getSpillSize(*BestRC)) 1319 continue; 1320 if (!isLegalRC(*TRI, *SuperRC)) 1321 continue; 1322 BestRC = SuperRC; 1323 } 1324 return std::make_pair(BestRC, 1); 1325 } 1326 1327 /// computeRegisterProperties - Once all of the register classes are added, 1328 /// this allows us to compute derived properties we expose. 1329 void TargetLoweringBase::computeRegisterProperties( 1330 const TargetRegisterInfo *TRI) { 1331 static_assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE, 1332 "Too many value types for ValueTypeActions to hold!"); 1333 1334 // Everything defaults to needing one register. 1335 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) { 1336 NumRegistersForVT[i] = 1; 1337 RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i; 1338 } 1339 // ...except isVoid, which doesn't need any registers. 1340 NumRegistersForVT[MVT::isVoid] = 0; 1341 1342 // Find the largest integer register class. 1343 unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE; 1344 for (; RegClassForVT[LargestIntReg] == nullptr; --LargestIntReg) 1345 assert(LargestIntReg != MVT::i1 && "No integer registers defined!"); 1346 1347 // Every integer value type larger than this largest register takes twice as 1348 // many registers to represent as the previous ValueType. 1349 for (unsigned ExpandedReg = LargestIntReg + 1; 1350 ExpandedReg <= MVT::LAST_INTEGER_VALUETYPE; ++ExpandedReg) { 1351 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1]; 1352 RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg; 1353 TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1); 1354 ValueTypeActions.setTypeAction((MVT::SimpleValueType)ExpandedReg, 1355 TypeExpandInteger); 1356 } 1357 1358 // Inspect all of the ValueType's smaller than the largest integer 1359 // register to see which ones need promotion. 1360 unsigned LegalIntReg = LargestIntReg; 1361 for (unsigned IntReg = LargestIntReg - 1; 1362 IntReg >= (unsigned)MVT::i1; --IntReg) { 1363 MVT IVT = (MVT::SimpleValueType)IntReg; 1364 if (isTypeLegal(IVT)) { 1365 LegalIntReg = IntReg; 1366 } else { 1367 RegisterTypeForVT[IntReg] = TransformToType[IntReg] = 1368 (const MVT::SimpleValueType)LegalIntReg; 1369 ValueTypeActions.setTypeAction(IVT, TypePromoteInteger); 1370 } 1371 } 1372 1373 // ppcf128 type is really two f64's. 1374 if (!isTypeLegal(MVT::ppcf128)) { 1375 if (isTypeLegal(MVT::f64)) { 1376 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64]; 1377 RegisterTypeForVT[MVT::ppcf128] = MVT::f64; 1378 TransformToType[MVT::ppcf128] = MVT::f64; 1379 ValueTypeActions.setTypeAction(MVT::ppcf128, TypeExpandFloat); 1380 } else { 1381 NumRegistersForVT[MVT::ppcf128] = NumRegistersForVT[MVT::i128]; 1382 RegisterTypeForVT[MVT::ppcf128] = RegisterTypeForVT[MVT::i128]; 1383 TransformToType[MVT::ppcf128] = MVT::i128; 1384 ValueTypeActions.setTypeAction(MVT::ppcf128, TypeSoftenFloat); 1385 } 1386 } 1387 1388 // Decide how to handle f128. If the target does not have native f128 support, 1389 // expand it to i128 and we will be generating soft float library calls. 1390 if (!isTypeLegal(MVT::f128)) { 1391 NumRegistersForVT[MVT::f128] = NumRegistersForVT[MVT::i128]; 1392 RegisterTypeForVT[MVT::f128] = RegisterTypeForVT[MVT::i128]; 1393 TransformToType[MVT::f128] = MVT::i128; 1394 ValueTypeActions.setTypeAction(MVT::f128, TypeSoftenFloat); 1395 } 1396 1397 // Decide how to handle f64. If the target does not have native f64 support, 1398 // expand it to i64 and we will be generating soft float library calls. 1399 if (!isTypeLegal(MVT::f64)) { 1400 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64]; 1401 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64]; 1402 TransformToType[MVT::f64] = MVT::i64; 1403 ValueTypeActions.setTypeAction(MVT::f64, TypeSoftenFloat); 1404 } 1405 1406 // Decide how to handle f32. If the target does not have native f32 support, 1407 // expand it to i32 and we will be generating soft float library calls. 1408 if (!isTypeLegal(MVT::f32)) { 1409 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32]; 1410 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32]; 1411 TransformToType[MVT::f32] = MVT::i32; 1412 ValueTypeActions.setTypeAction(MVT::f32, TypeSoftenFloat); 1413 } 1414 1415 // Decide how to handle f16. If the target does not have native f16 support, 1416 // promote it to f32, because there are no f16 library calls (except for 1417 // conversions). 1418 if (!isTypeLegal(MVT::f16)) { 1419 NumRegistersForVT[MVT::f16] = NumRegistersForVT[MVT::f32]; 1420 RegisterTypeForVT[MVT::f16] = RegisterTypeForVT[MVT::f32]; 1421 TransformToType[MVT::f16] = MVT::f32; 1422 ValueTypeActions.setTypeAction(MVT::f16, TypePromoteFloat); 1423 } 1424 1425 // Loop over all of the vector value types to see which need transformations. 1426 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE; 1427 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) { 1428 MVT VT = (MVT::SimpleValueType) i; 1429 if (isTypeLegal(VT)) 1430 continue; 1431 1432 MVT EltVT = VT.getVectorElementType(); 1433 unsigned NElts = VT.getVectorNumElements(); 1434 bool IsLegalWiderType = false; 1435 LegalizeTypeAction PreferredAction = getPreferredVectorAction(VT); 1436 switch (PreferredAction) { 1437 case TypePromoteInteger: { 1438 // Try to promote the elements of integer vectors. If no legal 1439 // promotion was found, fall through to the widen-vector method. 1440 for (unsigned nVT = i + 1; nVT <= MVT::LAST_INTEGER_VECTOR_VALUETYPE; ++nVT) { 1441 MVT SVT = (MVT::SimpleValueType) nVT; 1442 // Promote vectors of integers to vectors with the same number 1443 // of elements, with a wider element type. 1444 if (SVT.getScalarSizeInBits() > EltVT.getSizeInBits() && 1445 SVT.getVectorNumElements() == NElts && isTypeLegal(SVT)) { 1446 TransformToType[i] = SVT; 1447 RegisterTypeForVT[i] = SVT; 1448 NumRegistersForVT[i] = 1; 1449 ValueTypeActions.setTypeAction(VT, TypePromoteInteger); 1450 IsLegalWiderType = true; 1451 break; 1452 } 1453 } 1454 if (IsLegalWiderType) 1455 break; 1456 } 1457 case TypeWidenVector: { 1458 // Try to widen the vector. 1459 for (unsigned nVT = i + 1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) { 1460 MVT SVT = (MVT::SimpleValueType) nVT; 1461 if (SVT.getVectorElementType() == EltVT 1462 && SVT.getVectorNumElements() > NElts && isTypeLegal(SVT)) { 1463 TransformToType[i] = SVT; 1464 RegisterTypeForVT[i] = SVT; 1465 NumRegistersForVT[i] = 1; 1466 ValueTypeActions.setTypeAction(VT, TypeWidenVector); 1467 IsLegalWiderType = true; 1468 break; 1469 } 1470 } 1471 if (IsLegalWiderType) 1472 break; 1473 } 1474 case TypeSplitVector: 1475 case TypeScalarizeVector: { 1476 MVT IntermediateVT; 1477 MVT RegisterVT; 1478 unsigned NumIntermediates; 1479 NumRegistersForVT[i] = getVectorTypeBreakdownMVT(VT, IntermediateVT, 1480 NumIntermediates, RegisterVT, this); 1481 RegisterTypeForVT[i] = RegisterVT; 1482 1483 MVT NVT = VT.getPow2VectorType(); 1484 if (NVT == VT) { 1485 // Type is already a power of 2. The default action is to split. 1486 TransformToType[i] = MVT::Other; 1487 if (PreferredAction == TypeScalarizeVector) 1488 ValueTypeActions.setTypeAction(VT, TypeScalarizeVector); 1489 else if (PreferredAction == TypeSplitVector) 1490 ValueTypeActions.setTypeAction(VT, TypeSplitVector); 1491 else 1492 // Set type action according to the number of elements. 1493 ValueTypeActions.setTypeAction(VT, NElts == 1 ? TypeScalarizeVector 1494 : TypeSplitVector); 1495 } else { 1496 TransformToType[i] = NVT; 1497 ValueTypeActions.setTypeAction(VT, TypeWidenVector); 1498 } 1499 break; 1500 } 1501 default: 1502 llvm_unreachable("Unknown vector legalization action!"); 1503 } 1504 } 1505 1506 // Determine the 'representative' register class for each value type. 1507 // An representative register class is the largest (meaning one which is 1508 // not a sub-register class / subreg register class) legal register class for 1509 // a group of value types. For example, on i386, i8, i16, and i32 1510 // representative would be GR32; while on x86_64 it's GR64. 1511 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) { 1512 const TargetRegisterClass* RRC; 1513 uint8_t Cost; 1514 std::tie(RRC, Cost) = findRepresentativeClass(TRI, (MVT::SimpleValueType)i); 1515 RepRegClassForVT[i] = RRC; 1516 RepRegClassCostForVT[i] = Cost; 1517 } 1518 } 1519 1520 EVT TargetLoweringBase::getSetCCResultType(const DataLayout &DL, LLVMContext &, 1521 EVT VT) const { 1522 assert(!VT.isVector() && "No default SetCC type for vectors!"); 1523 return getPointerTy(DL).SimpleTy; 1524 } 1525 1526 MVT::SimpleValueType TargetLoweringBase::getCmpLibcallReturnType() const { 1527 return MVT::i32; // return the default value 1528 } 1529 1530 /// getVectorTypeBreakdown - Vector types are broken down into some number of 1531 /// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32 1532 /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack. 1533 /// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86. 1534 /// 1535 /// This method returns the number of registers needed, and the VT for each 1536 /// register. It also returns the VT and quantity of the intermediate values 1537 /// before they are promoted/expanded. 1538 /// 1539 unsigned TargetLoweringBase::getVectorTypeBreakdown(LLVMContext &Context, EVT VT, 1540 EVT &IntermediateVT, 1541 unsigned &NumIntermediates, 1542 MVT &RegisterVT) const { 1543 unsigned NumElts = VT.getVectorNumElements(); 1544 1545 // If there is a wider vector type with the same element type as this one, 1546 // or a promoted vector type that has the same number of elements which 1547 // are wider, then we should convert to that legal vector type. 1548 // This handles things like <2 x float> -> <4 x float> and 1549 // <4 x i1> -> <4 x i32>. 1550 LegalizeTypeAction TA = getTypeAction(Context, VT); 1551 if (NumElts != 1 && (TA == TypeWidenVector || TA == TypePromoteInteger)) { 1552 EVT RegisterEVT = getTypeToTransformTo(Context, VT); 1553 if (isTypeLegal(RegisterEVT)) { 1554 IntermediateVT = RegisterEVT; 1555 RegisterVT = RegisterEVT.getSimpleVT(); 1556 NumIntermediates = 1; 1557 return 1; 1558 } 1559 } 1560 1561 // Figure out the right, legal destination reg to copy into. 1562 EVT EltTy = VT.getVectorElementType(); 1563 1564 unsigned NumVectorRegs = 1; 1565 1566 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we 1567 // could break down into LHS/RHS like LegalizeDAG does. 1568 if (!isPowerOf2_32(NumElts)) { 1569 NumVectorRegs = NumElts; 1570 NumElts = 1; 1571 } 1572 1573 // Divide the input until we get to a supported size. This will always 1574 // end with a scalar if the target doesn't support vectors. 1575 while (NumElts > 1 && !isTypeLegal( 1576 EVT::getVectorVT(Context, EltTy, NumElts))) { 1577 NumElts >>= 1; 1578 NumVectorRegs <<= 1; 1579 } 1580 1581 NumIntermediates = NumVectorRegs; 1582 1583 EVT NewVT = EVT::getVectorVT(Context, EltTy, NumElts); 1584 if (!isTypeLegal(NewVT)) 1585 NewVT = EltTy; 1586 IntermediateVT = NewVT; 1587 1588 MVT DestVT = getRegisterType(Context, NewVT); 1589 RegisterVT = DestVT; 1590 unsigned NewVTSize = NewVT.getSizeInBits(); 1591 1592 // Convert sizes such as i33 to i64. 1593 if (!isPowerOf2_32(NewVTSize)) 1594 NewVTSize = NextPowerOf2(NewVTSize); 1595 1596 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16. 1597 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits()); 1598 1599 // Otherwise, promotion or legal types use the same number of registers as 1600 // the vector decimated to the appropriate level. 1601 return NumVectorRegs; 1602 } 1603 1604 /// Get the EVTs and ArgFlags collections that represent the legalized return 1605 /// type of the given function. This does not require a DAG or a return value, 1606 /// and is suitable for use before any DAGs for the function are constructed. 1607 /// TODO: Move this out of TargetLowering.cpp. 1608 void llvm::GetReturnInfo(Type *ReturnType, AttributeList attr, 1609 SmallVectorImpl<ISD::OutputArg> &Outs, 1610 const TargetLowering &TLI, const DataLayout &DL) { 1611 SmallVector<EVT, 4> ValueVTs; 1612 ComputeValueVTs(TLI, DL, ReturnType, ValueVTs); 1613 unsigned NumValues = ValueVTs.size(); 1614 if (NumValues == 0) return; 1615 1616 for (unsigned j = 0, f = NumValues; j != f; ++j) { 1617 EVT VT = ValueVTs[j]; 1618 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 1619 1620 if (attr.hasAttribute(AttributeList::ReturnIndex, Attribute::SExt)) 1621 ExtendKind = ISD::SIGN_EXTEND; 1622 else if (attr.hasAttribute(AttributeList::ReturnIndex, Attribute::ZExt)) 1623 ExtendKind = ISD::ZERO_EXTEND; 1624 1625 // FIXME: C calling convention requires the return type to be promoted to 1626 // at least 32-bit. But this is not necessary for non-C calling 1627 // conventions. The frontend should mark functions whose return values 1628 // require promoting with signext or zeroext attributes. 1629 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) { 1630 MVT MinVT = TLI.getRegisterType(ReturnType->getContext(), MVT::i32); 1631 if (VT.bitsLT(MinVT)) 1632 VT = MinVT; 1633 } 1634 1635 unsigned NumParts = TLI.getNumRegisters(ReturnType->getContext(), VT); 1636 MVT PartVT = TLI.getRegisterType(ReturnType->getContext(), VT); 1637 1638 // 'inreg' on function refers to return value 1639 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy(); 1640 if (attr.hasAttribute(AttributeList::ReturnIndex, Attribute::InReg)) 1641 Flags.setInReg(); 1642 1643 // Propagate extension type if any 1644 if (attr.hasAttribute(AttributeList::ReturnIndex, Attribute::SExt)) 1645 Flags.setSExt(); 1646 else if (attr.hasAttribute(AttributeList::ReturnIndex, Attribute::ZExt)) 1647 Flags.setZExt(); 1648 1649 for (unsigned i = 0; i < NumParts; ++i) 1650 Outs.push_back(ISD::OutputArg(Flags, PartVT, VT, /*isFixed=*/true, 0, 0)); 1651 } 1652 } 1653 1654 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 1655 /// function arguments in the caller parameter area. This is the actual 1656 /// alignment, not its logarithm. 1657 unsigned TargetLoweringBase::getByValTypeAlignment(Type *Ty, 1658 const DataLayout &DL) const { 1659 return DL.getABITypeAlignment(Ty); 1660 } 1661 1662 bool TargetLoweringBase::allowsMemoryAccess(LLVMContext &Context, 1663 const DataLayout &DL, EVT VT, 1664 unsigned AddrSpace, 1665 unsigned Alignment, 1666 bool *Fast) const { 1667 // Check if the specified alignment is sufficient based on the data layout. 1668 // TODO: While using the data layout works in practice, a better solution 1669 // would be to implement this check directly (make this a virtual function). 1670 // For example, the ABI alignment may change based on software platform while 1671 // this function should only be affected by hardware implementation. 1672 Type *Ty = VT.getTypeForEVT(Context); 1673 if (Alignment >= DL.getABITypeAlignment(Ty)) { 1674 // Assume that an access that meets the ABI-specified alignment is fast. 1675 if (Fast != nullptr) 1676 *Fast = true; 1677 return true; 1678 } 1679 1680 // This is a misaligned access. 1681 return allowsMisalignedMemoryAccesses(VT, AddrSpace, Alignment, Fast); 1682 } 1683 1684 BranchProbability TargetLoweringBase::getPredictableBranchThreshold() const { 1685 return BranchProbability(MinPercentageForPredictableBranch, 100); 1686 } 1687 1688 //===----------------------------------------------------------------------===// 1689 // TargetTransformInfo Helpers 1690 //===----------------------------------------------------------------------===// 1691 1692 int TargetLoweringBase::InstructionOpcodeToISD(unsigned Opcode) const { 1693 enum InstructionOpcodes { 1694 #define HANDLE_INST(NUM, OPCODE, CLASS) OPCODE = NUM, 1695 #define LAST_OTHER_INST(NUM) InstructionOpcodesCount = NUM 1696 #include "llvm/IR/Instruction.def" 1697 }; 1698 switch (static_cast<InstructionOpcodes>(Opcode)) { 1699 case Ret: return 0; 1700 case Br: return 0; 1701 case Switch: return 0; 1702 case IndirectBr: return 0; 1703 case Invoke: return 0; 1704 case Resume: return 0; 1705 case Unreachable: return 0; 1706 case CleanupRet: return 0; 1707 case CatchRet: return 0; 1708 case CatchPad: return 0; 1709 case CatchSwitch: return 0; 1710 case CleanupPad: return 0; 1711 case Add: return ISD::ADD; 1712 case FAdd: return ISD::FADD; 1713 case Sub: return ISD::SUB; 1714 case FSub: return ISD::FSUB; 1715 case Mul: return ISD::MUL; 1716 case FMul: return ISD::FMUL; 1717 case UDiv: return ISD::UDIV; 1718 case SDiv: return ISD::SDIV; 1719 case FDiv: return ISD::FDIV; 1720 case URem: return ISD::UREM; 1721 case SRem: return ISD::SREM; 1722 case FRem: return ISD::FREM; 1723 case Shl: return ISD::SHL; 1724 case LShr: return ISD::SRL; 1725 case AShr: return ISD::SRA; 1726 case And: return ISD::AND; 1727 case Or: return ISD::OR; 1728 case Xor: return ISD::XOR; 1729 case Alloca: return 0; 1730 case Load: return ISD::LOAD; 1731 case Store: return ISD::STORE; 1732 case GetElementPtr: return 0; 1733 case Fence: return 0; 1734 case AtomicCmpXchg: return 0; 1735 case AtomicRMW: return 0; 1736 case Trunc: return ISD::TRUNCATE; 1737 case ZExt: return ISD::ZERO_EXTEND; 1738 case SExt: return ISD::SIGN_EXTEND; 1739 case FPToUI: return ISD::FP_TO_UINT; 1740 case FPToSI: return ISD::FP_TO_SINT; 1741 case UIToFP: return ISD::UINT_TO_FP; 1742 case SIToFP: return ISD::SINT_TO_FP; 1743 case FPTrunc: return ISD::FP_ROUND; 1744 case FPExt: return ISD::FP_EXTEND; 1745 case PtrToInt: return ISD::BITCAST; 1746 case IntToPtr: return ISD::BITCAST; 1747 case BitCast: return ISD::BITCAST; 1748 case AddrSpaceCast: return ISD::ADDRSPACECAST; 1749 case ICmp: return ISD::SETCC; 1750 case FCmp: return ISD::SETCC; 1751 case PHI: return 0; 1752 case Call: return 0; 1753 case Select: return ISD::SELECT; 1754 case UserOp1: return 0; 1755 case UserOp2: return 0; 1756 case VAArg: return 0; 1757 case ExtractElement: return ISD::EXTRACT_VECTOR_ELT; 1758 case InsertElement: return ISD::INSERT_VECTOR_ELT; 1759 case ShuffleVector: return ISD::VECTOR_SHUFFLE; 1760 case ExtractValue: return ISD::MERGE_VALUES; 1761 case InsertValue: return ISD::MERGE_VALUES; 1762 case LandingPad: return 0; 1763 } 1764 1765 llvm_unreachable("Unknown instruction type encountered!"); 1766 } 1767 1768 std::pair<int, MVT> 1769 TargetLoweringBase::getTypeLegalizationCost(const DataLayout &DL, 1770 Type *Ty) const { 1771 LLVMContext &C = Ty->getContext(); 1772 EVT MTy = getValueType(DL, Ty); 1773 1774 int Cost = 1; 1775 // We keep legalizing the type until we find a legal kind. We assume that 1776 // the only operation that costs anything is the split. After splitting 1777 // we need to handle two types. 1778 while (true) { 1779 LegalizeKind LK = getTypeConversion(C, MTy); 1780 1781 if (LK.first == TypeLegal) 1782 return std::make_pair(Cost, MTy.getSimpleVT()); 1783 1784 if (LK.first == TypeSplitVector || LK.first == TypeExpandInteger) 1785 Cost *= 2; 1786 1787 // Do not loop with f128 type. 1788 if (MTy == LK.second) 1789 return std::make_pair(Cost, MTy.getSimpleVT()); 1790 1791 // Keep legalizing the type. 1792 MTy = LK.second; 1793 } 1794 } 1795 1796 Value *TargetLoweringBase::getDefaultSafeStackPointerLocation(IRBuilder<> &IRB, 1797 bool UseTLS) const { 1798 // compiler-rt provides a variable with a magic name. Targets that do not 1799 // link with compiler-rt may also provide such a variable. 1800 Module *M = IRB.GetInsertBlock()->getParent()->getParent(); 1801 const char *UnsafeStackPtrVar = "__safestack_unsafe_stack_ptr"; 1802 auto UnsafeStackPtr = 1803 dyn_cast_or_null<GlobalVariable>(M->getNamedValue(UnsafeStackPtrVar)); 1804 1805 Type *StackPtrTy = Type::getInt8PtrTy(M->getContext()); 1806 1807 if (!UnsafeStackPtr) { 1808 auto TLSModel = UseTLS ? 1809 GlobalValue::InitialExecTLSModel : 1810 GlobalValue::NotThreadLocal; 1811 // The global variable is not defined yet, define it ourselves. 1812 // We use the initial-exec TLS model because we do not support the 1813 // variable living anywhere other than in the main executable. 1814 UnsafeStackPtr = new GlobalVariable( 1815 *M, StackPtrTy, false, GlobalValue::ExternalLinkage, nullptr, 1816 UnsafeStackPtrVar, nullptr, TLSModel); 1817 } else { 1818 // The variable exists, check its type and attributes. 1819 if (UnsafeStackPtr->getValueType() != StackPtrTy) 1820 report_fatal_error(Twine(UnsafeStackPtrVar) + " must have void* type"); 1821 if (UseTLS != UnsafeStackPtr->isThreadLocal()) 1822 report_fatal_error(Twine(UnsafeStackPtrVar) + " must " + 1823 (UseTLS ? "" : "not ") + "be thread-local"); 1824 } 1825 return UnsafeStackPtr; 1826 } 1827 1828 Value *TargetLoweringBase::getSafeStackPointerLocation(IRBuilder<> &IRB) const { 1829 if (!TM.getTargetTriple().isAndroid()) 1830 return getDefaultSafeStackPointerLocation(IRB, true); 1831 1832 // Android provides a libc function to retrieve the address of the current 1833 // thread's unsafe stack pointer. 1834 Module *M = IRB.GetInsertBlock()->getParent()->getParent(); 1835 Type *StackPtrTy = Type::getInt8PtrTy(M->getContext()); 1836 Value *Fn = M->getOrInsertFunction("__safestack_pointer_address", 1837 StackPtrTy->getPointerTo(0)); 1838 return IRB.CreateCall(Fn); 1839 } 1840 1841 //===----------------------------------------------------------------------===// 1842 // Loop Strength Reduction hooks 1843 //===----------------------------------------------------------------------===// 1844 1845 /// isLegalAddressingMode - Return true if the addressing mode represented 1846 /// by AM is legal for this target, for a load/store of the specified type. 1847 bool TargetLoweringBase::isLegalAddressingMode(const DataLayout &DL, 1848 const AddrMode &AM, Type *Ty, 1849 unsigned AS) const { 1850 // The default implementation of this implements a conservative RISCy, r+r and 1851 // r+i addr mode. 1852 1853 // Allows a sign-extended 16-bit immediate field. 1854 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1) 1855 return false; 1856 1857 // No global is ever allowed as a base. 1858 if (AM.BaseGV) 1859 return false; 1860 1861 // Only support r+r, 1862 switch (AM.Scale) { 1863 case 0: // "r+i" or just "i", depending on HasBaseReg. 1864 break; 1865 case 1: 1866 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. 1867 return false; 1868 // Otherwise we have r+r or r+i. 1869 break; 1870 case 2: 1871 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. 1872 return false; 1873 // Allow 2*r as r+r. 1874 break; 1875 default: // Don't allow n * r 1876 return false; 1877 } 1878 1879 return true; 1880 } 1881 1882 //===----------------------------------------------------------------------===// 1883 // Stack Protector 1884 //===----------------------------------------------------------------------===// 1885 1886 // For OpenBSD return its special guard variable. Otherwise return nullptr, 1887 // so that SelectionDAG handle SSP. 1888 Value *TargetLoweringBase::getIRStackGuard(IRBuilder<> &IRB) const { 1889 if (getTargetMachine().getTargetTriple().isOSOpenBSD()) { 1890 Module &M = *IRB.GetInsertBlock()->getParent()->getParent(); 1891 PointerType *PtrTy = Type::getInt8PtrTy(M.getContext()); 1892 return M.getOrInsertGlobal("__guard_local", PtrTy); 1893 } 1894 return nullptr; 1895 } 1896 1897 // Currently only support "standard" __stack_chk_guard. 1898 // TODO: add LOAD_STACK_GUARD support. 1899 void TargetLoweringBase::insertSSPDeclarations(Module &M) const { 1900 M.getOrInsertGlobal("__stack_chk_guard", Type::getInt8PtrTy(M.getContext())); 1901 } 1902 1903 // Currently only support "standard" __stack_chk_guard. 1904 // TODO: add LOAD_STACK_GUARD support. 1905 Value *TargetLoweringBase::getSDagStackGuard(const Module &M) const { 1906 return M.getGlobalVariable("__stack_chk_guard", true); 1907 } 1908 1909 Value *TargetLoweringBase::getSSPStackGuardCheck(const Module &M) const { 1910 return nullptr; 1911 } 1912 1913 unsigned TargetLoweringBase::getMinimumJumpTableEntries() const { 1914 return MinimumJumpTableEntries; 1915 } 1916 1917 void TargetLoweringBase::setMinimumJumpTableEntries(unsigned Val) { 1918 MinimumJumpTableEntries = Val; 1919 } 1920 1921 unsigned TargetLoweringBase::getMinimumJumpTableDensity(bool OptForSize) const { 1922 return OptForSize ? OptsizeJumpTableDensity : JumpTableDensity; 1923 } 1924 1925 unsigned TargetLoweringBase::getMaximumJumpTableSize() const { 1926 return MaximumJumpTableSize; 1927 } 1928 1929 void TargetLoweringBase::setMaximumJumpTableSize(unsigned Val) { 1930 MaximumJumpTableSize = Val; 1931 } 1932 1933 //===----------------------------------------------------------------------===// 1934 // Reciprocal Estimates 1935 //===----------------------------------------------------------------------===// 1936 1937 /// Get the reciprocal estimate attribute string for a function that will 1938 /// override the target defaults. 1939 static StringRef getRecipEstimateForFunc(MachineFunction &MF) { 1940 const Function *F = MF.getFunction(); 1941 return F->getFnAttribute("reciprocal-estimates").getValueAsString(); 1942 } 1943 1944 /// Construct a string for the given reciprocal operation of the given type. 1945 /// This string should match the corresponding option to the front-end's 1946 /// "-mrecip" flag assuming those strings have been passed through in an 1947 /// attribute string. For example, "vec-divf" for a division of a vXf32. 1948 static std::string getReciprocalOpName(bool IsSqrt, EVT VT) { 1949 std::string Name = VT.isVector() ? "vec-" : ""; 1950 1951 Name += IsSqrt ? "sqrt" : "div"; 1952 1953 // TODO: Handle "half" or other float types? 1954 if (VT.getScalarType() == MVT::f64) { 1955 Name += "d"; 1956 } else { 1957 assert(VT.getScalarType() == MVT::f32 && 1958 "Unexpected FP type for reciprocal estimate"); 1959 Name += "f"; 1960 } 1961 1962 return Name; 1963 } 1964 1965 /// Return the character position and value (a single numeric character) of a 1966 /// customized refinement operation in the input string if it exists. Return 1967 /// false if there is no customized refinement step count. 1968 static bool parseRefinementStep(StringRef In, size_t &Position, 1969 uint8_t &Value) { 1970 const char RefStepToken = ':'; 1971 Position = In.find(RefStepToken); 1972 if (Position == StringRef::npos) 1973 return false; 1974 1975 StringRef RefStepString = In.substr(Position + 1); 1976 // Allow exactly one numeric character for the additional refinement 1977 // step parameter. 1978 if (RefStepString.size() == 1) { 1979 char RefStepChar = RefStepString[0]; 1980 if (RefStepChar >= '0' && RefStepChar <= '9') { 1981 Value = RefStepChar - '0'; 1982 return true; 1983 } 1984 } 1985 report_fatal_error("Invalid refinement step for -recip."); 1986 } 1987 1988 /// For the input attribute string, return one of the ReciprocalEstimate enum 1989 /// status values (enabled, disabled, or not specified) for this operation on 1990 /// the specified data type. 1991 static int getOpEnabled(bool IsSqrt, EVT VT, StringRef Override) { 1992 if (Override.empty()) 1993 return TargetLoweringBase::ReciprocalEstimate::Unspecified; 1994 1995 SmallVector<StringRef, 4> OverrideVector; 1996 SplitString(Override, OverrideVector, ","); 1997 unsigned NumArgs = OverrideVector.size(); 1998 1999 // Check if "all", "none", or "default" was specified. 2000 if (NumArgs == 1) { 2001 // Look for an optional setting of the number of refinement steps needed 2002 // for this type of reciprocal operation. 2003 size_t RefPos; 2004 uint8_t RefSteps; 2005 if (parseRefinementStep(Override, RefPos, RefSteps)) { 2006 // Split the string for further processing. 2007 Override = Override.substr(0, RefPos); 2008 } 2009 2010 // All reciprocal types are enabled. 2011 if (Override == "all") 2012 return TargetLoweringBase::ReciprocalEstimate::Enabled; 2013 2014 // All reciprocal types are disabled. 2015 if (Override == "none") 2016 return TargetLoweringBase::ReciprocalEstimate::Disabled; 2017 2018 // Target defaults for enablement are used. 2019 if (Override == "default") 2020 return TargetLoweringBase::ReciprocalEstimate::Unspecified; 2021 } 2022 2023 // The attribute string may omit the size suffix ('f'/'d'). 2024 std::string VTName = getReciprocalOpName(IsSqrt, VT); 2025 std::string VTNameNoSize = VTName; 2026 VTNameNoSize.pop_back(); 2027 static const char DisabledPrefix = '!'; 2028 2029 for (StringRef RecipType : OverrideVector) { 2030 size_t RefPos; 2031 uint8_t RefSteps; 2032 if (parseRefinementStep(RecipType, RefPos, RefSteps)) 2033 RecipType = RecipType.substr(0, RefPos); 2034 2035 // Ignore the disablement token for string matching. 2036 bool IsDisabled = RecipType[0] == DisabledPrefix; 2037 if (IsDisabled) 2038 RecipType = RecipType.substr(1); 2039 2040 if (RecipType.equals(VTName) || RecipType.equals(VTNameNoSize)) 2041 return IsDisabled ? TargetLoweringBase::ReciprocalEstimate::Disabled 2042 : TargetLoweringBase::ReciprocalEstimate::Enabled; 2043 } 2044 2045 return TargetLoweringBase::ReciprocalEstimate::Unspecified; 2046 } 2047 2048 /// For the input attribute string, return the customized refinement step count 2049 /// for this operation on the specified data type. If the step count does not 2050 /// exist, return the ReciprocalEstimate enum value for unspecified. 2051 static int getOpRefinementSteps(bool IsSqrt, EVT VT, StringRef Override) { 2052 if (Override.empty()) 2053 return TargetLoweringBase::ReciprocalEstimate::Unspecified; 2054 2055 SmallVector<StringRef, 4> OverrideVector; 2056 SplitString(Override, OverrideVector, ","); 2057 unsigned NumArgs = OverrideVector.size(); 2058 2059 // Check if "all", "default", or "none" was specified. 2060 if (NumArgs == 1) { 2061 // Look for an optional setting of the number of refinement steps needed 2062 // for this type of reciprocal operation. 2063 size_t RefPos; 2064 uint8_t RefSteps; 2065 if (!parseRefinementStep(Override, RefPos, RefSteps)) 2066 return TargetLoweringBase::ReciprocalEstimate::Unspecified; 2067 2068 // Split the string for further processing. 2069 Override = Override.substr(0, RefPos); 2070 assert(Override != "none" && 2071 "Disabled reciprocals, but specifed refinement steps?"); 2072 2073 // If this is a general override, return the specified number of steps. 2074 if (Override == "all" || Override == "default") 2075 return RefSteps; 2076 } 2077 2078 // The attribute string may omit the size suffix ('f'/'d'). 2079 std::string VTName = getReciprocalOpName(IsSqrt, VT); 2080 std::string VTNameNoSize = VTName; 2081 VTNameNoSize.pop_back(); 2082 2083 for (StringRef RecipType : OverrideVector) { 2084 size_t RefPos; 2085 uint8_t RefSteps; 2086 if (!parseRefinementStep(RecipType, RefPos, RefSteps)) 2087 continue; 2088 2089 RecipType = RecipType.substr(0, RefPos); 2090 if (RecipType.equals(VTName) || RecipType.equals(VTNameNoSize)) 2091 return RefSteps; 2092 } 2093 2094 return TargetLoweringBase::ReciprocalEstimate::Unspecified; 2095 } 2096 2097 int TargetLoweringBase::getRecipEstimateSqrtEnabled(EVT VT, 2098 MachineFunction &MF) const { 2099 return getOpEnabled(true, VT, getRecipEstimateForFunc(MF)); 2100 } 2101 2102 int TargetLoweringBase::getRecipEstimateDivEnabled(EVT VT, 2103 MachineFunction &MF) const { 2104 return getOpEnabled(false, VT, getRecipEstimateForFunc(MF)); 2105 } 2106 2107 int TargetLoweringBase::getSqrtRefinementSteps(EVT VT, 2108 MachineFunction &MF) const { 2109 return getOpRefinementSteps(true, VT, getRecipEstimateForFunc(MF)); 2110 } 2111 2112 int TargetLoweringBase::getDivRefinementSteps(EVT VT, 2113 MachineFunction &MF) const { 2114 return getOpRefinementSteps(false, VT, getRecipEstimateForFunc(MF)); 2115 } 2116 2117 void TargetLoweringBase::finalizeLowering(MachineFunction &MF) const { 2118 MF.getRegInfo().freezeReservedRegs(MF); 2119 } 2120