1 //===- TargetLoweringBase.cpp - Implement the TargetLoweringBase class ----===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This implements the TargetLoweringBase class. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "llvm/ADT/BitVector.h" 14 #include "llvm/ADT/STLExtras.h" 15 #include "llvm/ADT/SmallVector.h" 16 #include "llvm/ADT/StringExtras.h" 17 #include "llvm/ADT/StringRef.h" 18 #include "llvm/ADT/Triple.h" 19 #include "llvm/ADT/Twine.h" 20 #include "llvm/Analysis/Loads.h" 21 #include "llvm/Analysis/TargetTransformInfo.h" 22 #include "llvm/CodeGen/Analysis.h" 23 #include "llvm/CodeGen/ISDOpcodes.h" 24 #include "llvm/CodeGen/MachineBasicBlock.h" 25 #include "llvm/CodeGen/MachineFrameInfo.h" 26 #include "llvm/CodeGen/MachineFunction.h" 27 #include "llvm/CodeGen/MachineInstr.h" 28 #include "llvm/CodeGen/MachineInstrBuilder.h" 29 #include "llvm/CodeGen/MachineMemOperand.h" 30 #include "llvm/CodeGen/MachineOperand.h" 31 #include "llvm/CodeGen/MachineRegisterInfo.h" 32 #include "llvm/CodeGen/RuntimeLibcalls.h" 33 #include "llvm/CodeGen/StackMaps.h" 34 #include "llvm/CodeGen/TargetLowering.h" 35 #include "llvm/CodeGen/TargetOpcodes.h" 36 #include "llvm/CodeGen/TargetRegisterInfo.h" 37 #include "llvm/CodeGen/ValueTypes.h" 38 #include "llvm/IR/Attributes.h" 39 #include "llvm/IR/CallingConv.h" 40 #include "llvm/IR/DataLayout.h" 41 #include "llvm/IR/DerivedTypes.h" 42 #include "llvm/IR/Function.h" 43 #include "llvm/IR/GlobalValue.h" 44 #include "llvm/IR/GlobalVariable.h" 45 #include "llvm/IR/IRBuilder.h" 46 #include "llvm/IR/Module.h" 47 #include "llvm/IR/Type.h" 48 #include "llvm/Support/BranchProbability.h" 49 #include "llvm/Support/Casting.h" 50 #include "llvm/Support/CommandLine.h" 51 #include "llvm/Support/Compiler.h" 52 #include "llvm/Support/ErrorHandling.h" 53 #include "llvm/Support/MachineValueType.h" 54 #include "llvm/Support/MathExtras.h" 55 #include "llvm/Target/TargetMachine.h" 56 #include "llvm/Transforms/Utils/SizeOpts.h" 57 #include <algorithm> 58 #include <cassert> 59 #include <cstddef> 60 #include <cstdint> 61 #include <cstring> 62 #include <iterator> 63 #include <string> 64 #include <tuple> 65 #include <utility> 66 67 using namespace llvm; 68 69 static cl::opt<bool> JumpIsExpensiveOverride( 70 "jump-is-expensive", cl::init(false), 71 cl::desc("Do not create extra branches to split comparison logic."), 72 cl::Hidden); 73 74 static cl::opt<unsigned> MinimumJumpTableEntries 75 ("min-jump-table-entries", cl::init(4), cl::Hidden, 76 cl::desc("Set minimum number of entries to use a jump table.")); 77 78 static cl::opt<unsigned> MaximumJumpTableSize 79 ("max-jump-table-size", cl::init(UINT_MAX), cl::Hidden, 80 cl::desc("Set maximum size of jump tables.")); 81 82 /// Minimum jump table density for normal functions. 83 static cl::opt<unsigned> 84 JumpTableDensity("jump-table-density", cl::init(10), cl::Hidden, 85 cl::desc("Minimum density for building a jump table in " 86 "a normal function")); 87 88 /// Minimum jump table density for -Os or -Oz functions. 89 static cl::opt<unsigned> OptsizeJumpTableDensity( 90 "optsize-jump-table-density", cl::init(40), cl::Hidden, 91 cl::desc("Minimum density for building a jump table in " 92 "an optsize function")); 93 94 // FIXME: This option is only to test if the strict fp operation processed 95 // correctly by preventing mutating strict fp operation to normal fp operation 96 // during development. When the backend supports strict float operation, this 97 // option will be meaningless. 98 static cl::opt<bool> DisableStrictNodeMutation("disable-strictnode-mutation", 99 cl::desc("Don't mutate strict-float node to a legalize node"), 100 cl::init(false), cl::Hidden); 101 102 static bool darwinHasSinCos(const Triple &TT) { 103 assert(TT.isOSDarwin() && "should be called with darwin triple"); 104 // Don't bother with 32 bit x86. 105 if (TT.getArch() == Triple::x86) 106 return false; 107 // Macos < 10.9 has no sincos_stret. 108 if (TT.isMacOSX()) 109 return !TT.isMacOSXVersionLT(10, 9) && TT.isArch64Bit(); 110 // iOS < 7.0 has no sincos_stret. 111 if (TT.isiOS()) 112 return !TT.isOSVersionLT(7, 0); 113 // Any other darwin such as WatchOS/TvOS is new enough. 114 return true; 115 } 116 117 // Although this default value is arbitrary, it is not random. It is assumed 118 // that a condition that evaluates the same way by a higher percentage than this 119 // is best represented as control flow. Therefore, the default value N should be 120 // set such that the win from N% correct executions is greater than the loss 121 // from (100 - N)% mispredicted executions for the majority of intended targets. 122 static cl::opt<int> MinPercentageForPredictableBranch( 123 "min-predictable-branch", cl::init(99), 124 cl::desc("Minimum percentage (0-100) that a condition must be either true " 125 "or false to assume that the condition is predictable"), 126 cl::Hidden); 127 128 void TargetLoweringBase::InitLibcalls(const Triple &TT) { 129 #define HANDLE_LIBCALL(code, name) \ 130 setLibcallName(RTLIB::code, name); 131 #include "llvm/IR/RuntimeLibcalls.def" 132 #undef HANDLE_LIBCALL 133 // Initialize calling conventions to their default. 134 for (int LC = 0; LC < RTLIB::UNKNOWN_LIBCALL; ++LC) 135 setLibcallCallingConv((RTLIB::Libcall)LC, CallingConv::C); 136 137 // For IEEE quad-precision libcall names, PPC uses "kf" instead of "tf". 138 if (TT.getArch() == Triple::ppc || TT.isPPC64()) { 139 setLibcallName(RTLIB::ADD_F128, "__addkf3"); 140 setLibcallName(RTLIB::SUB_F128, "__subkf3"); 141 setLibcallName(RTLIB::MUL_F128, "__mulkf3"); 142 setLibcallName(RTLIB::DIV_F128, "__divkf3"); 143 setLibcallName(RTLIB::FPEXT_F32_F128, "__extendsfkf2"); 144 setLibcallName(RTLIB::FPEXT_F64_F128, "__extenddfkf2"); 145 setLibcallName(RTLIB::FPROUND_F128_F32, "__trunckfsf2"); 146 setLibcallName(RTLIB::FPROUND_F128_F64, "__trunckfdf2"); 147 setLibcallName(RTLIB::FPTOSINT_F128_I32, "__fixkfsi"); 148 setLibcallName(RTLIB::FPTOSINT_F128_I64, "__fixkfdi"); 149 setLibcallName(RTLIB::FPTOUINT_F128_I32, "__fixunskfsi"); 150 setLibcallName(RTLIB::FPTOUINT_F128_I64, "__fixunskfdi"); 151 setLibcallName(RTLIB::SINTTOFP_I32_F128, "__floatsikf"); 152 setLibcallName(RTLIB::SINTTOFP_I64_F128, "__floatdikf"); 153 setLibcallName(RTLIB::UINTTOFP_I32_F128, "__floatunsikf"); 154 setLibcallName(RTLIB::UINTTOFP_I64_F128, "__floatundikf"); 155 setLibcallName(RTLIB::OEQ_F128, "__eqkf2"); 156 setLibcallName(RTLIB::UNE_F128, "__nekf2"); 157 setLibcallName(RTLIB::OGE_F128, "__gekf2"); 158 setLibcallName(RTLIB::OLT_F128, "__ltkf2"); 159 setLibcallName(RTLIB::OLE_F128, "__lekf2"); 160 setLibcallName(RTLIB::OGT_F128, "__gtkf2"); 161 setLibcallName(RTLIB::UO_F128, "__unordkf2"); 162 } 163 164 // A few names are different on particular architectures or environments. 165 if (TT.isOSDarwin()) { 166 // For f16/f32 conversions, Darwin uses the standard naming scheme, instead 167 // of the gnueabi-style __gnu_*_ieee. 168 // FIXME: What about other targets? 169 setLibcallName(RTLIB::FPEXT_F16_F32, "__extendhfsf2"); 170 setLibcallName(RTLIB::FPROUND_F32_F16, "__truncsfhf2"); 171 172 // Some darwins have an optimized __bzero/bzero function. 173 switch (TT.getArch()) { 174 case Triple::x86: 175 case Triple::x86_64: 176 if (TT.isMacOSX() && !TT.isMacOSXVersionLT(10, 6)) 177 setLibcallName(RTLIB::BZERO, "__bzero"); 178 break; 179 case Triple::aarch64: 180 case Triple::aarch64_32: 181 setLibcallName(RTLIB::BZERO, "bzero"); 182 break; 183 default: 184 break; 185 } 186 187 if (darwinHasSinCos(TT)) { 188 setLibcallName(RTLIB::SINCOS_STRET_F32, "__sincosf_stret"); 189 setLibcallName(RTLIB::SINCOS_STRET_F64, "__sincos_stret"); 190 if (TT.isWatchABI()) { 191 setLibcallCallingConv(RTLIB::SINCOS_STRET_F32, 192 CallingConv::ARM_AAPCS_VFP); 193 setLibcallCallingConv(RTLIB::SINCOS_STRET_F64, 194 CallingConv::ARM_AAPCS_VFP); 195 } 196 } 197 } else { 198 setLibcallName(RTLIB::FPEXT_F16_F32, "__gnu_h2f_ieee"); 199 setLibcallName(RTLIB::FPROUND_F32_F16, "__gnu_f2h_ieee"); 200 } 201 202 if (TT.isGNUEnvironment() || TT.isOSFuchsia() || 203 (TT.isAndroid() && !TT.isAndroidVersionLT(9))) { 204 setLibcallName(RTLIB::SINCOS_F32, "sincosf"); 205 setLibcallName(RTLIB::SINCOS_F64, "sincos"); 206 setLibcallName(RTLIB::SINCOS_F80, "sincosl"); 207 setLibcallName(RTLIB::SINCOS_F128, "sincosl"); 208 setLibcallName(RTLIB::SINCOS_PPCF128, "sincosl"); 209 } 210 211 if (TT.isPS4CPU()) { 212 setLibcallName(RTLIB::SINCOS_F32, "sincosf"); 213 setLibcallName(RTLIB::SINCOS_F64, "sincos"); 214 } 215 216 if (TT.isOSOpenBSD()) { 217 setLibcallName(RTLIB::STACKPROTECTOR_CHECK_FAIL, nullptr); 218 } 219 } 220 221 /// getFPEXT - Return the FPEXT_*_* value for the given types, or 222 /// UNKNOWN_LIBCALL if there is none. 223 RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) { 224 if (OpVT == MVT::f16) { 225 if (RetVT == MVT::f32) 226 return FPEXT_F16_F32; 227 } else if (OpVT == MVT::f32) { 228 if (RetVT == MVT::f64) 229 return FPEXT_F32_F64; 230 if (RetVT == MVT::f128) 231 return FPEXT_F32_F128; 232 if (RetVT == MVT::ppcf128) 233 return FPEXT_F32_PPCF128; 234 } else if (OpVT == MVT::f64) { 235 if (RetVT == MVT::f128) 236 return FPEXT_F64_F128; 237 else if (RetVT == MVT::ppcf128) 238 return FPEXT_F64_PPCF128; 239 } else if (OpVT == MVT::f80) { 240 if (RetVT == MVT::f128) 241 return FPEXT_F80_F128; 242 } 243 244 return UNKNOWN_LIBCALL; 245 } 246 247 /// getFPROUND - Return the FPROUND_*_* value for the given types, or 248 /// UNKNOWN_LIBCALL if there is none. 249 RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) { 250 if (RetVT == MVT::f16) { 251 if (OpVT == MVT::f32) 252 return FPROUND_F32_F16; 253 if (OpVT == MVT::f64) 254 return FPROUND_F64_F16; 255 if (OpVT == MVT::f80) 256 return FPROUND_F80_F16; 257 if (OpVT == MVT::f128) 258 return FPROUND_F128_F16; 259 if (OpVT == MVT::ppcf128) 260 return FPROUND_PPCF128_F16; 261 } else if (RetVT == MVT::f32) { 262 if (OpVT == MVT::f64) 263 return FPROUND_F64_F32; 264 if (OpVT == MVT::f80) 265 return FPROUND_F80_F32; 266 if (OpVT == MVT::f128) 267 return FPROUND_F128_F32; 268 if (OpVT == MVT::ppcf128) 269 return FPROUND_PPCF128_F32; 270 } else if (RetVT == MVT::f64) { 271 if (OpVT == MVT::f80) 272 return FPROUND_F80_F64; 273 if (OpVT == MVT::f128) 274 return FPROUND_F128_F64; 275 if (OpVT == MVT::ppcf128) 276 return FPROUND_PPCF128_F64; 277 } else if (RetVT == MVT::f80) { 278 if (OpVT == MVT::f128) 279 return FPROUND_F128_F80; 280 } 281 282 return UNKNOWN_LIBCALL; 283 } 284 285 /// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or 286 /// UNKNOWN_LIBCALL if there is none. 287 RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT, EVT RetVT) { 288 if (OpVT == MVT::f32) { 289 if (RetVT == MVT::i32) 290 return FPTOSINT_F32_I32; 291 if (RetVT == MVT::i64) 292 return FPTOSINT_F32_I64; 293 if (RetVT == MVT::i128) 294 return FPTOSINT_F32_I128; 295 } else if (OpVT == MVT::f64) { 296 if (RetVT == MVT::i32) 297 return FPTOSINT_F64_I32; 298 if (RetVT == MVT::i64) 299 return FPTOSINT_F64_I64; 300 if (RetVT == MVT::i128) 301 return FPTOSINT_F64_I128; 302 } else if (OpVT == MVT::f80) { 303 if (RetVT == MVT::i32) 304 return FPTOSINT_F80_I32; 305 if (RetVT == MVT::i64) 306 return FPTOSINT_F80_I64; 307 if (RetVT == MVT::i128) 308 return FPTOSINT_F80_I128; 309 } else if (OpVT == MVT::f128) { 310 if (RetVT == MVT::i32) 311 return FPTOSINT_F128_I32; 312 if (RetVT == MVT::i64) 313 return FPTOSINT_F128_I64; 314 if (RetVT == MVT::i128) 315 return FPTOSINT_F128_I128; 316 } else if (OpVT == MVT::ppcf128) { 317 if (RetVT == MVT::i32) 318 return FPTOSINT_PPCF128_I32; 319 if (RetVT == MVT::i64) 320 return FPTOSINT_PPCF128_I64; 321 if (RetVT == MVT::i128) 322 return FPTOSINT_PPCF128_I128; 323 } 324 return UNKNOWN_LIBCALL; 325 } 326 327 /// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or 328 /// UNKNOWN_LIBCALL if there is none. 329 RTLIB::Libcall RTLIB::getFPTOUINT(EVT OpVT, EVT RetVT) { 330 if (OpVT == MVT::f32) { 331 if (RetVT == MVT::i32) 332 return FPTOUINT_F32_I32; 333 if (RetVT == MVT::i64) 334 return FPTOUINT_F32_I64; 335 if (RetVT == MVT::i128) 336 return FPTOUINT_F32_I128; 337 } else if (OpVT == MVT::f64) { 338 if (RetVT == MVT::i32) 339 return FPTOUINT_F64_I32; 340 if (RetVT == MVT::i64) 341 return FPTOUINT_F64_I64; 342 if (RetVT == MVT::i128) 343 return FPTOUINT_F64_I128; 344 } else if (OpVT == MVT::f80) { 345 if (RetVT == MVT::i32) 346 return FPTOUINT_F80_I32; 347 if (RetVT == MVT::i64) 348 return FPTOUINT_F80_I64; 349 if (RetVT == MVT::i128) 350 return FPTOUINT_F80_I128; 351 } else if (OpVT == MVT::f128) { 352 if (RetVT == MVT::i32) 353 return FPTOUINT_F128_I32; 354 if (RetVT == MVT::i64) 355 return FPTOUINT_F128_I64; 356 if (RetVT == MVT::i128) 357 return FPTOUINT_F128_I128; 358 } else if (OpVT == MVT::ppcf128) { 359 if (RetVT == MVT::i32) 360 return FPTOUINT_PPCF128_I32; 361 if (RetVT == MVT::i64) 362 return FPTOUINT_PPCF128_I64; 363 if (RetVT == MVT::i128) 364 return FPTOUINT_PPCF128_I128; 365 } 366 return UNKNOWN_LIBCALL; 367 } 368 369 /// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or 370 /// UNKNOWN_LIBCALL if there is none. 371 RTLIB::Libcall RTLIB::getSINTTOFP(EVT OpVT, EVT RetVT) { 372 if (OpVT == MVT::i32) { 373 if (RetVT == MVT::f32) 374 return SINTTOFP_I32_F32; 375 if (RetVT == MVT::f64) 376 return SINTTOFP_I32_F64; 377 if (RetVT == MVT::f80) 378 return SINTTOFP_I32_F80; 379 if (RetVT == MVT::f128) 380 return SINTTOFP_I32_F128; 381 if (RetVT == MVT::ppcf128) 382 return SINTTOFP_I32_PPCF128; 383 } else if (OpVT == MVT::i64) { 384 if (RetVT == MVT::f32) 385 return SINTTOFP_I64_F32; 386 if (RetVT == MVT::f64) 387 return SINTTOFP_I64_F64; 388 if (RetVT == MVT::f80) 389 return SINTTOFP_I64_F80; 390 if (RetVT == MVT::f128) 391 return SINTTOFP_I64_F128; 392 if (RetVT == MVT::ppcf128) 393 return SINTTOFP_I64_PPCF128; 394 } else if (OpVT == MVT::i128) { 395 if (RetVT == MVT::f32) 396 return SINTTOFP_I128_F32; 397 if (RetVT == MVT::f64) 398 return SINTTOFP_I128_F64; 399 if (RetVT == MVT::f80) 400 return SINTTOFP_I128_F80; 401 if (RetVT == MVT::f128) 402 return SINTTOFP_I128_F128; 403 if (RetVT == MVT::ppcf128) 404 return SINTTOFP_I128_PPCF128; 405 } 406 return UNKNOWN_LIBCALL; 407 } 408 409 /// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or 410 /// UNKNOWN_LIBCALL if there is none. 411 RTLIB::Libcall RTLIB::getUINTTOFP(EVT OpVT, EVT RetVT) { 412 if (OpVT == MVT::i32) { 413 if (RetVT == MVT::f32) 414 return UINTTOFP_I32_F32; 415 if (RetVT == MVT::f64) 416 return UINTTOFP_I32_F64; 417 if (RetVT == MVT::f80) 418 return UINTTOFP_I32_F80; 419 if (RetVT == MVT::f128) 420 return UINTTOFP_I32_F128; 421 if (RetVT == MVT::ppcf128) 422 return UINTTOFP_I32_PPCF128; 423 } else if (OpVT == MVT::i64) { 424 if (RetVT == MVT::f32) 425 return UINTTOFP_I64_F32; 426 if (RetVT == MVT::f64) 427 return UINTTOFP_I64_F64; 428 if (RetVT == MVT::f80) 429 return UINTTOFP_I64_F80; 430 if (RetVT == MVT::f128) 431 return UINTTOFP_I64_F128; 432 if (RetVT == MVT::ppcf128) 433 return UINTTOFP_I64_PPCF128; 434 } else if (OpVT == MVT::i128) { 435 if (RetVT == MVT::f32) 436 return UINTTOFP_I128_F32; 437 if (RetVT == MVT::f64) 438 return UINTTOFP_I128_F64; 439 if (RetVT == MVT::f80) 440 return UINTTOFP_I128_F80; 441 if (RetVT == MVT::f128) 442 return UINTTOFP_I128_F128; 443 if (RetVT == MVT::ppcf128) 444 return UINTTOFP_I128_PPCF128; 445 } 446 return UNKNOWN_LIBCALL; 447 } 448 449 RTLIB::Libcall RTLIB::getSYNC(unsigned Opc, MVT VT) { 450 #define OP_TO_LIBCALL(Name, Enum) \ 451 case Name: \ 452 switch (VT.SimpleTy) { \ 453 default: \ 454 return UNKNOWN_LIBCALL; \ 455 case MVT::i8: \ 456 return Enum##_1; \ 457 case MVT::i16: \ 458 return Enum##_2; \ 459 case MVT::i32: \ 460 return Enum##_4; \ 461 case MVT::i64: \ 462 return Enum##_8; \ 463 case MVT::i128: \ 464 return Enum##_16; \ 465 } 466 467 switch (Opc) { 468 OP_TO_LIBCALL(ISD::ATOMIC_SWAP, SYNC_LOCK_TEST_AND_SET) 469 OP_TO_LIBCALL(ISD::ATOMIC_CMP_SWAP, SYNC_VAL_COMPARE_AND_SWAP) 470 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_ADD, SYNC_FETCH_AND_ADD) 471 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_SUB, SYNC_FETCH_AND_SUB) 472 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_AND, SYNC_FETCH_AND_AND) 473 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_OR, SYNC_FETCH_AND_OR) 474 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_XOR, SYNC_FETCH_AND_XOR) 475 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_NAND, SYNC_FETCH_AND_NAND) 476 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_MAX, SYNC_FETCH_AND_MAX) 477 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_UMAX, SYNC_FETCH_AND_UMAX) 478 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_MIN, SYNC_FETCH_AND_MIN) 479 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_UMIN, SYNC_FETCH_AND_UMIN) 480 } 481 482 #undef OP_TO_LIBCALL 483 484 return UNKNOWN_LIBCALL; 485 } 486 487 RTLIB::Libcall RTLIB::getMEMCPY_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize) { 488 switch (ElementSize) { 489 case 1: 490 return MEMCPY_ELEMENT_UNORDERED_ATOMIC_1; 491 case 2: 492 return MEMCPY_ELEMENT_UNORDERED_ATOMIC_2; 493 case 4: 494 return MEMCPY_ELEMENT_UNORDERED_ATOMIC_4; 495 case 8: 496 return MEMCPY_ELEMENT_UNORDERED_ATOMIC_8; 497 case 16: 498 return MEMCPY_ELEMENT_UNORDERED_ATOMIC_16; 499 default: 500 return UNKNOWN_LIBCALL; 501 } 502 } 503 504 RTLIB::Libcall RTLIB::getMEMMOVE_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize) { 505 switch (ElementSize) { 506 case 1: 507 return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_1; 508 case 2: 509 return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_2; 510 case 4: 511 return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_4; 512 case 8: 513 return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_8; 514 case 16: 515 return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_16; 516 default: 517 return UNKNOWN_LIBCALL; 518 } 519 } 520 521 RTLIB::Libcall RTLIB::getMEMSET_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize) { 522 switch (ElementSize) { 523 case 1: 524 return MEMSET_ELEMENT_UNORDERED_ATOMIC_1; 525 case 2: 526 return MEMSET_ELEMENT_UNORDERED_ATOMIC_2; 527 case 4: 528 return MEMSET_ELEMENT_UNORDERED_ATOMIC_4; 529 case 8: 530 return MEMSET_ELEMENT_UNORDERED_ATOMIC_8; 531 case 16: 532 return MEMSET_ELEMENT_UNORDERED_ATOMIC_16; 533 default: 534 return UNKNOWN_LIBCALL; 535 } 536 } 537 538 /// InitCmpLibcallCCs - Set default comparison libcall CC. 539 static void InitCmpLibcallCCs(ISD::CondCode *CCs) { 540 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL); 541 CCs[RTLIB::OEQ_F32] = ISD::SETEQ; 542 CCs[RTLIB::OEQ_F64] = ISD::SETEQ; 543 CCs[RTLIB::OEQ_F128] = ISD::SETEQ; 544 CCs[RTLIB::OEQ_PPCF128] = ISD::SETEQ; 545 CCs[RTLIB::UNE_F32] = ISD::SETNE; 546 CCs[RTLIB::UNE_F64] = ISD::SETNE; 547 CCs[RTLIB::UNE_F128] = ISD::SETNE; 548 CCs[RTLIB::UNE_PPCF128] = ISD::SETNE; 549 CCs[RTLIB::OGE_F32] = ISD::SETGE; 550 CCs[RTLIB::OGE_F64] = ISD::SETGE; 551 CCs[RTLIB::OGE_F128] = ISD::SETGE; 552 CCs[RTLIB::OGE_PPCF128] = ISD::SETGE; 553 CCs[RTLIB::OLT_F32] = ISD::SETLT; 554 CCs[RTLIB::OLT_F64] = ISD::SETLT; 555 CCs[RTLIB::OLT_F128] = ISD::SETLT; 556 CCs[RTLIB::OLT_PPCF128] = ISD::SETLT; 557 CCs[RTLIB::OLE_F32] = ISD::SETLE; 558 CCs[RTLIB::OLE_F64] = ISD::SETLE; 559 CCs[RTLIB::OLE_F128] = ISD::SETLE; 560 CCs[RTLIB::OLE_PPCF128] = ISD::SETLE; 561 CCs[RTLIB::OGT_F32] = ISD::SETGT; 562 CCs[RTLIB::OGT_F64] = ISD::SETGT; 563 CCs[RTLIB::OGT_F128] = ISD::SETGT; 564 CCs[RTLIB::OGT_PPCF128] = ISD::SETGT; 565 CCs[RTLIB::UO_F32] = ISD::SETNE; 566 CCs[RTLIB::UO_F64] = ISD::SETNE; 567 CCs[RTLIB::UO_F128] = ISD::SETNE; 568 CCs[RTLIB::UO_PPCF128] = ISD::SETNE; 569 } 570 571 /// NOTE: The TargetMachine owns TLOF. 572 TargetLoweringBase::TargetLoweringBase(const TargetMachine &tm) : TM(tm) { 573 initActions(); 574 575 // Perform these initializations only once. 576 MaxStoresPerMemset = MaxStoresPerMemcpy = MaxStoresPerMemmove = 577 MaxLoadsPerMemcmp = 8; 578 MaxGluedStoresPerMemcpy = 0; 579 MaxStoresPerMemsetOptSize = MaxStoresPerMemcpyOptSize = 580 MaxStoresPerMemmoveOptSize = MaxLoadsPerMemcmpOptSize = 4; 581 HasMultipleConditionRegisters = false; 582 HasExtractBitsInsn = false; 583 JumpIsExpensive = JumpIsExpensiveOverride; 584 PredictableSelectIsExpensive = false; 585 EnableExtLdPromotion = false; 586 StackPointerRegisterToSaveRestore = 0; 587 BooleanContents = UndefinedBooleanContent; 588 BooleanFloatContents = UndefinedBooleanContent; 589 BooleanVectorContents = UndefinedBooleanContent; 590 SchedPreferenceInfo = Sched::ILP; 591 GatherAllAliasesMaxDepth = 18; 592 IsStrictFPEnabled = DisableStrictNodeMutation; 593 // TODO: the default will be switched to 0 in the next commit, along 594 // with the Target-specific changes necessary. 595 MaxAtomicSizeInBitsSupported = 1024; 596 597 MinCmpXchgSizeInBits = 0; 598 SupportsUnalignedAtomics = false; 599 600 std::fill(std::begin(LibcallRoutineNames), std::end(LibcallRoutineNames), nullptr); 601 602 InitLibcalls(TM.getTargetTriple()); 603 InitCmpLibcallCCs(CmpLibcallCCs); 604 } 605 606 void TargetLoweringBase::initActions() { 607 // All operations default to being supported. 608 memset(OpActions, 0, sizeof(OpActions)); 609 memset(LoadExtActions, 0, sizeof(LoadExtActions)); 610 memset(TruncStoreActions, 0, sizeof(TruncStoreActions)); 611 memset(IndexedModeActions, 0, sizeof(IndexedModeActions)); 612 memset(CondCodeActions, 0, sizeof(CondCodeActions)); 613 std::fill(std::begin(RegClassForVT), std::end(RegClassForVT), nullptr); 614 std::fill(std::begin(TargetDAGCombineArray), 615 std::end(TargetDAGCombineArray), 0); 616 617 for (MVT VT : MVT::fp_valuetypes()) { 618 MVT IntVT = MVT::getIntegerVT(VT.getFixedSizeInBits()); 619 if (IntVT.isValid()) { 620 setOperationAction(ISD::ATOMIC_SWAP, VT, Promote); 621 AddPromotedToType(ISD::ATOMIC_SWAP, VT, IntVT); 622 } 623 } 624 625 // Set default actions for various operations. 626 for (MVT VT : MVT::all_valuetypes()) { 627 // Default all indexed load / store to expand. 628 for (unsigned IM = (unsigned)ISD::PRE_INC; 629 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) { 630 setIndexedLoadAction(IM, VT, Expand); 631 setIndexedStoreAction(IM, VT, Expand); 632 setIndexedMaskedLoadAction(IM, VT, Expand); 633 setIndexedMaskedStoreAction(IM, VT, Expand); 634 } 635 636 // Most backends expect to see the node which just returns the value loaded. 637 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Expand); 638 639 // These operations default to expand. 640 setOperationAction(ISD::FGETSIGN, VT, Expand); 641 setOperationAction(ISD::CONCAT_VECTORS, VT, Expand); 642 setOperationAction(ISD::FMINNUM, VT, Expand); 643 setOperationAction(ISD::FMAXNUM, VT, Expand); 644 setOperationAction(ISD::FMINNUM_IEEE, VT, Expand); 645 setOperationAction(ISD::FMAXNUM_IEEE, VT, Expand); 646 setOperationAction(ISD::FMINIMUM, VT, Expand); 647 setOperationAction(ISD::FMAXIMUM, VT, Expand); 648 setOperationAction(ISD::FMAD, VT, Expand); 649 setOperationAction(ISD::SMIN, VT, Expand); 650 setOperationAction(ISD::SMAX, VT, Expand); 651 setOperationAction(ISD::UMIN, VT, Expand); 652 setOperationAction(ISD::UMAX, VT, Expand); 653 setOperationAction(ISD::ABS, VT, Expand); 654 setOperationAction(ISD::FSHL, VT, Expand); 655 setOperationAction(ISD::FSHR, VT, Expand); 656 setOperationAction(ISD::SADDSAT, VT, Expand); 657 setOperationAction(ISD::UADDSAT, VT, Expand); 658 setOperationAction(ISD::SSUBSAT, VT, Expand); 659 setOperationAction(ISD::USUBSAT, VT, Expand); 660 setOperationAction(ISD::SSHLSAT, VT, Expand); 661 setOperationAction(ISD::USHLSAT, VT, Expand); 662 setOperationAction(ISD::SMULFIX, VT, Expand); 663 setOperationAction(ISD::SMULFIXSAT, VT, Expand); 664 setOperationAction(ISD::UMULFIX, VT, Expand); 665 setOperationAction(ISD::UMULFIXSAT, VT, Expand); 666 setOperationAction(ISD::SDIVFIX, VT, Expand); 667 setOperationAction(ISD::SDIVFIXSAT, VT, Expand); 668 setOperationAction(ISD::UDIVFIX, VT, Expand); 669 setOperationAction(ISD::UDIVFIXSAT, VT, Expand); 670 671 // Overflow operations default to expand 672 setOperationAction(ISD::SADDO, VT, Expand); 673 setOperationAction(ISD::SSUBO, VT, Expand); 674 setOperationAction(ISD::UADDO, VT, Expand); 675 setOperationAction(ISD::USUBO, VT, Expand); 676 setOperationAction(ISD::SMULO, VT, Expand); 677 setOperationAction(ISD::UMULO, VT, Expand); 678 679 // ADDCARRY operations default to expand 680 setOperationAction(ISD::ADDCARRY, VT, Expand); 681 setOperationAction(ISD::SUBCARRY, VT, Expand); 682 setOperationAction(ISD::SETCCCARRY, VT, Expand); 683 setOperationAction(ISD::SADDO_CARRY, VT, Expand); 684 setOperationAction(ISD::SSUBO_CARRY, VT, Expand); 685 686 // ADDC/ADDE/SUBC/SUBE default to expand. 687 setOperationAction(ISD::ADDC, VT, Expand); 688 setOperationAction(ISD::ADDE, VT, Expand); 689 setOperationAction(ISD::SUBC, VT, Expand); 690 setOperationAction(ISD::SUBE, VT, Expand); 691 692 // These default to Expand so they will be expanded to CTLZ/CTTZ by default. 693 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand); 694 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand); 695 696 setOperationAction(ISD::BITREVERSE, VT, Expand); 697 setOperationAction(ISD::PARITY, VT, Expand); 698 699 // These library functions default to expand. 700 setOperationAction(ISD::FROUND, VT, Expand); 701 setOperationAction(ISD::FROUNDEVEN, VT, Expand); 702 setOperationAction(ISD::FPOWI, VT, Expand); 703 704 // These operations default to expand for vector types. 705 if (VT.isVector()) { 706 setOperationAction(ISD::FCOPYSIGN, VT, Expand); 707 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand); 708 setOperationAction(ISD::ANY_EXTEND_VECTOR_INREG, VT, Expand); 709 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, VT, Expand); 710 setOperationAction(ISD::ZERO_EXTEND_VECTOR_INREG, VT, Expand); 711 setOperationAction(ISD::SPLAT_VECTOR, VT, Expand); 712 } 713 714 // Constrained floating-point operations default to expand. 715 #define DAG_INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC, DAGN) \ 716 setOperationAction(ISD::STRICT_##DAGN, VT, Expand); 717 #include "llvm/IR/ConstrainedOps.def" 718 719 // For most targets @llvm.get.dynamic.area.offset just returns 0. 720 setOperationAction(ISD::GET_DYNAMIC_AREA_OFFSET, VT, Expand); 721 722 // Vector reduction default to expand. 723 setOperationAction(ISD::VECREDUCE_FADD, VT, Expand); 724 setOperationAction(ISD::VECREDUCE_FMUL, VT, Expand); 725 setOperationAction(ISD::VECREDUCE_ADD, VT, Expand); 726 setOperationAction(ISD::VECREDUCE_MUL, VT, Expand); 727 setOperationAction(ISD::VECREDUCE_AND, VT, Expand); 728 setOperationAction(ISD::VECREDUCE_OR, VT, Expand); 729 setOperationAction(ISD::VECREDUCE_XOR, VT, Expand); 730 setOperationAction(ISD::VECREDUCE_SMAX, VT, Expand); 731 setOperationAction(ISD::VECREDUCE_SMIN, VT, Expand); 732 setOperationAction(ISD::VECREDUCE_UMAX, VT, Expand); 733 setOperationAction(ISD::VECREDUCE_UMIN, VT, Expand); 734 setOperationAction(ISD::VECREDUCE_FMAX, VT, Expand); 735 setOperationAction(ISD::VECREDUCE_FMIN, VT, Expand); 736 } 737 738 // Most targets ignore the @llvm.prefetch intrinsic. 739 setOperationAction(ISD::PREFETCH, MVT::Other, Expand); 740 741 // Most targets also ignore the @llvm.readcyclecounter intrinsic. 742 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Expand); 743 744 // ConstantFP nodes default to expand. Targets can either change this to 745 // Legal, in which case all fp constants are legal, or use isFPImmLegal() 746 // to optimize expansions for certain constants. 747 setOperationAction(ISD::ConstantFP, MVT::f16, Expand); 748 setOperationAction(ISD::ConstantFP, MVT::f32, Expand); 749 setOperationAction(ISD::ConstantFP, MVT::f64, Expand); 750 setOperationAction(ISD::ConstantFP, MVT::f80, Expand); 751 setOperationAction(ISD::ConstantFP, MVT::f128, Expand); 752 753 // These library functions default to expand. 754 for (MVT VT : {MVT::f32, MVT::f64, MVT::f128}) { 755 setOperationAction(ISD::FCBRT, VT, Expand); 756 setOperationAction(ISD::FLOG , VT, Expand); 757 setOperationAction(ISD::FLOG2, VT, Expand); 758 setOperationAction(ISD::FLOG10, VT, Expand); 759 setOperationAction(ISD::FEXP , VT, Expand); 760 setOperationAction(ISD::FEXP2, VT, Expand); 761 setOperationAction(ISD::FFLOOR, VT, Expand); 762 setOperationAction(ISD::FNEARBYINT, VT, Expand); 763 setOperationAction(ISD::FCEIL, VT, Expand); 764 setOperationAction(ISD::FRINT, VT, Expand); 765 setOperationAction(ISD::FTRUNC, VT, Expand); 766 setOperationAction(ISD::FROUND, VT, Expand); 767 setOperationAction(ISD::FROUNDEVEN, VT, Expand); 768 setOperationAction(ISD::LROUND, VT, Expand); 769 setOperationAction(ISD::LLROUND, VT, Expand); 770 setOperationAction(ISD::LRINT, VT, Expand); 771 setOperationAction(ISD::LLRINT, VT, Expand); 772 } 773 774 // Default ISD::TRAP to expand (which turns it into abort). 775 setOperationAction(ISD::TRAP, MVT::Other, Expand); 776 777 // On most systems, DEBUGTRAP and TRAP have no difference. The "Expand" 778 // here is to inform DAG Legalizer to replace DEBUGTRAP with TRAP. 779 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Expand); 780 } 781 782 MVT TargetLoweringBase::getScalarShiftAmountTy(const DataLayout &DL, 783 EVT) const { 784 return MVT::getIntegerVT(DL.getPointerSizeInBits(0)); 785 } 786 787 EVT TargetLoweringBase::getShiftAmountTy(EVT LHSTy, const DataLayout &DL, 788 bool LegalTypes) const { 789 assert(LHSTy.isInteger() && "Shift amount is not an integer type!"); 790 if (LHSTy.isVector()) 791 return LHSTy; 792 return LegalTypes ? getScalarShiftAmountTy(DL, LHSTy) 793 : getPointerTy(DL); 794 } 795 796 bool TargetLoweringBase::canOpTrap(unsigned Op, EVT VT) const { 797 assert(isTypeLegal(VT)); 798 switch (Op) { 799 default: 800 return false; 801 case ISD::SDIV: 802 case ISD::UDIV: 803 case ISD::SREM: 804 case ISD::UREM: 805 return true; 806 } 807 } 808 809 bool TargetLoweringBase::isFreeAddrSpaceCast(unsigned SrcAS, 810 unsigned DestAS) const { 811 return TM.isNoopAddrSpaceCast(SrcAS, DestAS); 812 } 813 814 void TargetLoweringBase::setJumpIsExpensive(bool isExpensive) { 815 // If the command-line option was specified, ignore this request. 816 if (!JumpIsExpensiveOverride.getNumOccurrences()) 817 JumpIsExpensive = isExpensive; 818 } 819 820 TargetLoweringBase::LegalizeKind 821 TargetLoweringBase::getTypeConversion(LLVMContext &Context, EVT VT) const { 822 // If this is a simple type, use the ComputeRegisterProp mechanism. 823 if (VT.isSimple()) { 824 MVT SVT = VT.getSimpleVT(); 825 assert((unsigned)SVT.SimpleTy < array_lengthof(TransformToType)); 826 MVT NVT = TransformToType[SVT.SimpleTy]; 827 LegalizeTypeAction LA = ValueTypeActions.getTypeAction(SVT); 828 829 assert((LA == TypeLegal || LA == TypeSoftenFloat || 830 LA == TypeSoftPromoteHalf || 831 (NVT.isVector() || 832 ValueTypeActions.getTypeAction(NVT) != TypePromoteInteger)) && 833 "Promote may not follow Expand or Promote"); 834 835 if (LA == TypeSplitVector) 836 return LegalizeKind(LA, EVT(SVT).getHalfNumVectorElementsVT(Context)); 837 if (LA == TypeScalarizeVector) 838 return LegalizeKind(LA, SVT.getVectorElementType()); 839 return LegalizeKind(LA, NVT); 840 } 841 842 // Handle Extended Scalar Types. 843 if (!VT.isVector()) { 844 assert(VT.isInteger() && "Float types must be simple"); 845 unsigned BitSize = VT.getSizeInBits(); 846 // First promote to a power-of-two size, then expand if necessary. 847 if (BitSize < 8 || !isPowerOf2_32(BitSize)) { 848 EVT NVT = VT.getRoundIntegerType(Context); 849 assert(NVT != VT && "Unable to round integer VT"); 850 LegalizeKind NextStep = getTypeConversion(Context, NVT); 851 // Avoid multi-step promotion. 852 if (NextStep.first == TypePromoteInteger) 853 return NextStep; 854 // Return rounded integer type. 855 return LegalizeKind(TypePromoteInteger, NVT); 856 } 857 858 return LegalizeKind(TypeExpandInteger, 859 EVT::getIntegerVT(Context, VT.getSizeInBits() / 2)); 860 } 861 862 // Handle vector types. 863 ElementCount NumElts = VT.getVectorElementCount(); 864 EVT EltVT = VT.getVectorElementType(); 865 866 // Vectors with only one element are always scalarized. 867 if (NumElts.isScalar()) 868 return LegalizeKind(TypeScalarizeVector, EltVT); 869 870 if (VT.getVectorElementCount() == ElementCount::getScalable(1)) 871 report_fatal_error("Cannot legalize this vector"); 872 873 // Try to widen vector elements until the element type is a power of two and 874 // promote it to a legal type later on, for example: 875 // <3 x i8> -> <4 x i8> -> <4 x i32> 876 if (EltVT.isInteger()) { 877 // Vectors with a number of elements that is not a power of two are always 878 // widened, for example <3 x i8> -> <4 x i8>. 879 if (!VT.isPow2VectorType()) { 880 NumElts = NumElts.coefficientNextPowerOf2(); 881 EVT NVT = EVT::getVectorVT(Context, EltVT, NumElts); 882 return LegalizeKind(TypeWidenVector, NVT); 883 } 884 885 // Examine the element type. 886 LegalizeKind LK = getTypeConversion(Context, EltVT); 887 888 // If type is to be expanded, split the vector. 889 // <4 x i140> -> <2 x i140> 890 if (LK.first == TypeExpandInteger) 891 return LegalizeKind(TypeSplitVector, 892 VT.getHalfNumVectorElementsVT(Context)); 893 894 // Promote the integer element types until a legal vector type is found 895 // or until the element integer type is too big. If a legal type was not 896 // found, fallback to the usual mechanism of widening/splitting the 897 // vector. 898 EVT OldEltVT = EltVT; 899 while (true) { 900 // Increase the bitwidth of the element to the next pow-of-two 901 // (which is greater than 8 bits). 902 EltVT = EVT::getIntegerVT(Context, 1 + EltVT.getSizeInBits()) 903 .getRoundIntegerType(Context); 904 905 // Stop trying when getting a non-simple element type. 906 // Note that vector elements may be greater than legal vector element 907 // types. Example: X86 XMM registers hold 64bit element on 32bit 908 // systems. 909 if (!EltVT.isSimple()) 910 break; 911 912 // Build a new vector type and check if it is legal. 913 MVT NVT = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts); 914 // Found a legal promoted vector type. 915 if (NVT != MVT() && ValueTypeActions.getTypeAction(NVT) == TypeLegal) 916 return LegalizeKind(TypePromoteInteger, 917 EVT::getVectorVT(Context, EltVT, NumElts)); 918 } 919 920 // Reset the type to the unexpanded type if we did not find a legal vector 921 // type with a promoted vector element type. 922 EltVT = OldEltVT; 923 } 924 925 // Try to widen the vector until a legal type is found. 926 // If there is no wider legal type, split the vector. 927 while (true) { 928 // Round up to the next power of 2. 929 NumElts = NumElts.coefficientNextPowerOf2(); 930 931 // If there is no simple vector type with this many elements then there 932 // cannot be a larger legal vector type. Note that this assumes that 933 // there are no skipped intermediate vector types in the simple types. 934 if (!EltVT.isSimple()) 935 break; 936 MVT LargerVector = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts); 937 if (LargerVector == MVT()) 938 break; 939 940 // If this type is legal then widen the vector. 941 if (ValueTypeActions.getTypeAction(LargerVector) == TypeLegal) 942 return LegalizeKind(TypeWidenVector, LargerVector); 943 } 944 945 // Widen odd vectors to next power of two. 946 if (!VT.isPow2VectorType()) { 947 EVT NVT = VT.getPow2VectorType(Context); 948 return LegalizeKind(TypeWidenVector, NVT); 949 } 950 951 // Vectors with illegal element types are expanded. 952 EVT NVT = EVT::getVectorVT(Context, EltVT, 953 VT.getVectorElementCount().divideCoefficientBy(2)); 954 return LegalizeKind(TypeSplitVector, NVT); 955 } 956 957 static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT, 958 unsigned &NumIntermediates, 959 MVT &RegisterVT, 960 TargetLoweringBase *TLI) { 961 // Figure out the right, legal destination reg to copy into. 962 ElementCount EC = VT.getVectorElementCount(); 963 MVT EltTy = VT.getVectorElementType(); 964 965 unsigned NumVectorRegs = 1; 966 967 // Scalable vectors cannot be scalarized, so splitting or widening is 968 // required. 969 if (VT.isScalableVector() && !isPowerOf2_32(EC.getKnownMinValue())) 970 llvm_unreachable( 971 "Splitting or widening of non-power-of-2 MVTs is not implemented."); 972 973 // FIXME: We don't support non-power-of-2-sized vectors for now. 974 // Ideally we could break down into LHS/RHS like LegalizeDAG does. 975 if (!isPowerOf2_32(EC.getKnownMinValue())) { 976 // Split EC to unit size (scalable property is preserved). 977 NumVectorRegs = EC.getKnownMinValue(); 978 EC = ElementCount::getFixed(1); 979 } 980 981 // Divide the input until we get to a supported size. This will 982 // always end up with an EC that represent a scalar or a scalable 983 // scalar. 984 while (EC.getKnownMinValue() > 1 && 985 !TLI->isTypeLegal(MVT::getVectorVT(EltTy, EC))) { 986 EC = EC.divideCoefficientBy(2); 987 NumVectorRegs <<= 1; 988 } 989 990 NumIntermediates = NumVectorRegs; 991 992 MVT NewVT = MVT::getVectorVT(EltTy, EC); 993 if (!TLI->isTypeLegal(NewVT)) 994 NewVT = EltTy; 995 IntermediateVT = NewVT; 996 997 unsigned LaneSizeInBits = NewVT.getScalarSizeInBits(); 998 999 // Convert sizes such as i33 to i64. 1000 if (!isPowerOf2_32(LaneSizeInBits)) 1001 LaneSizeInBits = NextPowerOf2(LaneSizeInBits); 1002 1003 MVT DestVT = TLI->getRegisterType(NewVT); 1004 RegisterVT = DestVT; 1005 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16. 1006 return NumVectorRegs * (LaneSizeInBits / DestVT.getScalarSizeInBits()); 1007 1008 // Otherwise, promotion or legal types use the same number of registers as 1009 // the vector decimated to the appropriate level. 1010 return NumVectorRegs; 1011 } 1012 1013 /// isLegalRC - Return true if the value types that can be represented by the 1014 /// specified register class are all legal. 1015 bool TargetLoweringBase::isLegalRC(const TargetRegisterInfo &TRI, 1016 const TargetRegisterClass &RC) const { 1017 for (auto I = TRI.legalclasstypes_begin(RC); *I != MVT::Other; ++I) 1018 if (isTypeLegal(*I)) 1019 return true; 1020 return false; 1021 } 1022 1023 /// Replace/modify any TargetFrameIndex operands with a targte-dependent 1024 /// sequence of memory operands that is recognized by PrologEpilogInserter. 1025 MachineBasicBlock * 1026 TargetLoweringBase::emitPatchPoint(MachineInstr &InitialMI, 1027 MachineBasicBlock *MBB) const { 1028 MachineInstr *MI = &InitialMI; 1029 MachineFunction &MF = *MI->getMF(); 1030 MachineFrameInfo &MFI = MF.getFrameInfo(); 1031 1032 // We're handling multiple types of operands here: 1033 // PATCHPOINT MetaArgs - live-in, read only, direct 1034 // STATEPOINT Deopt Spill - live-through, read only, indirect 1035 // STATEPOINT Deopt Alloca - live-through, read only, direct 1036 // (We're currently conservative and mark the deopt slots read/write in 1037 // practice.) 1038 // STATEPOINT GC Spill - live-through, read/write, indirect 1039 // STATEPOINT GC Alloca - live-through, read/write, direct 1040 // The live-in vs live-through is handled already (the live through ones are 1041 // all stack slots), but we need to handle the different type of stackmap 1042 // operands and memory effects here. 1043 1044 if (!llvm::any_of(MI->operands(), 1045 [](MachineOperand &Operand) { return Operand.isFI(); })) 1046 return MBB; 1047 1048 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), MI->getDesc()); 1049 1050 // Inherit previous memory operands. 1051 MIB.cloneMemRefs(*MI); 1052 1053 for (unsigned i = 0; i < MI->getNumOperands(); ++i) { 1054 MachineOperand &MO = MI->getOperand(i); 1055 if (!MO.isFI()) { 1056 // Index of Def operand this Use it tied to. 1057 // Since Defs are coming before Uses, if Use is tied, then 1058 // index of Def must be smaller that index of that Use. 1059 // Also, Defs preserve their position in new MI. 1060 unsigned TiedTo = i; 1061 if (MO.isReg() && MO.isTied()) 1062 TiedTo = MI->findTiedOperandIdx(i); 1063 MIB.add(MO); 1064 if (TiedTo < i) 1065 MIB->tieOperands(TiedTo, MIB->getNumOperands() - 1); 1066 continue; 1067 } 1068 1069 // foldMemoryOperand builds a new MI after replacing a single FI operand 1070 // with the canonical set of five x86 addressing-mode operands. 1071 int FI = MO.getIndex(); 1072 1073 // Add frame index operands recognized by stackmaps.cpp 1074 if (MFI.isStatepointSpillSlotObjectIndex(FI)) { 1075 // indirect-mem-ref tag, size, #FI, offset. 1076 // Used for spills inserted by StatepointLowering. This codepath is not 1077 // used for patchpoints/stackmaps at all, for these spilling is done via 1078 // foldMemoryOperand callback only. 1079 assert(MI->getOpcode() == TargetOpcode::STATEPOINT && "sanity"); 1080 MIB.addImm(StackMaps::IndirectMemRefOp); 1081 MIB.addImm(MFI.getObjectSize(FI)); 1082 MIB.add(MO); 1083 MIB.addImm(0); 1084 } else { 1085 // direct-mem-ref tag, #FI, offset. 1086 // Used by patchpoint, and direct alloca arguments to statepoints 1087 MIB.addImm(StackMaps::DirectMemRefOp); 1088 MIB.add(MO); 1089 MIB.addImm(0); 1090 } 1091 1092 assert(MIB->mayLoad() && "Folded a stackmap use to a non-load!"); 1093 1094 // Add a new memory operand for this FI. 1095 assert(MFI.getObjectOffset(FI) != -1); 1096 1097 // Note: STATEPOINT MMOs are added during SelectionDAG. STACKMAP, and 1098 // PATCHPOINT should be updated to do the same. (TODO) 1099 if (MI->getOpcode() != TargetOpcode::STATEPOINT) { 1100 auto Flags = MachineMemOperand::MOLoad; 1101 MachineMemOperand *MMO = MF.getMachineMemOperand( 1102 MachinePointerInfo::getFixedStack(MF, FI), Flags, 1103 MF.getDataLayout().getPointerSize(), MFI.getObjectAlign(FI)); 1104 MIB->addMemOperand(MF, MMO); 1105 } 1106 } 1107 MBB->insert(MachineBasicBlock::iterator(MI), MIB); 1108 MI->eraseFromParent(); 1109 return MBB; 1110 } 1111 1112 MachineBasicBlock * 1113 TargetLoweringBase::emitXRayCustomEvent(MachineInstr &MI, 1114 MachineBasicBlock *MBB) const { 1115 assert(MI.getOpcode() == TargetOpcode::PATCHABLE_EVENT_CALL && 1116 "Called emitXRayCustomEvent on the wrong MI!"); 1117 auto &MF = *MI.getMF(); 1118 auto MIB = BuildMI(MF, MI.getDebugLoc(), MI.getDesc()); 1119 for (unsigned OpIdx = 0; OpIdx != MI.getNumOperands(); ++OpIdx) 1120 MIB.add(MI.getOperand(OpIdx)); 1121 1122 MBB->insert(MachineBasicBlock::iterator(MI), MIB); 1123 MI.eraseFromParent(); 1124 return MBB; 1125 } 1126 1127 MachineBasicBlock * 1128 TargetLoweringBase::emitXRayTypedEvent(MachineInstr &MI, 1129 MachineBasicBlock *MBB) const { 1130 assert(MI.getOpcode() == TargetOpcode::PATCHABLE_TYPED_EVENT_CALL && 1131 "Called emitXRayTypedEvent on the wrong MI!"); 1132 auto &MF = *MI.getMF(); 1133 auto MIB = BuildMI(MF, MI.getDebugLoc(), MI.getDesc()); 1134 for (unsigned OpIdx = 0; OpIdx != MI.getNumOperands(); ++OpIdx) 1135 MIB.add(MI.getOperand(OpIdx)); 1136 1137 MBB->insert(MachineBasicBlock::iterator(MI), MIB); 1138 MI.eraseFromParent(); 1139 return MBB; 1140 } 1141 1142 /// findRepresentativeClass - Return the largest legal super-reg register class 1143 /// of the register class for the specified type and its associated "cost". 1144 // This function is in TargetLowering because it uses RegClassForVT which would 1145 // need to be moved to TargetRegisterInfo and would necessitate moving 1146 // isTypeLegal over as well - a massive change that would just require 1147 // TargetLowering having a TargetRegisterInfo class member that it would use. 1148 std::pair<const TargetRegisterClass *, uint8_t> 1149 TargetLoweringBase::findRepresentativeClass(const TargetRegisterInfo *TRI, 1150 MVT VT) const { 1151 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy]; 1152 if (!RC) 1153 return std::make_pair(RC, 0); 1154 1155 // Compute the set of all super-register classes. 1156 BitVector SuperRegRC(TRI->getNumRegClasses()); 1157 for (SuperRegClassIterator RCI(RC, TRI); RCI.isValid(); ++RCI) 1158 SuperRegRC.setBitsInMask(RCI.getMask()); 1159 1160 // Find the first legal register class with the largest spill size. 1161 const TargetRegisterClass *BestRC = RC; 1162 for (unsigned i : SuperRegRC.set_bits()) { 1163 const TargetRegisterClass *SuperRC = TRI->getRegClass(i); 1164 // We want the largest possible spill size. 1165 if (TRI->getSpillSize(*SuperRC) <= TRI->getSpillSize(*BestRC)) 1166 continue; 1167 if (!isLegalRC(*TRI, *SuperRC)) 1168 continue; 1169 BestRC = SuperRC; 1170 } 1171 return std::make_pair(BestRC, 1); 1172 } 1173 1174 /// computeRegisterProperties - Once all of the register classes are added, 1175 /// this allows us to compute derived properties we expose. 1176 void TargetLoweringBase::computeRegisterProperties( 1177 const TargetRegisterInfo *TRI) { 1178 static_assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE, 1179 "Too many value types for ValueTypeActions to hold!"); 1180 1181 // Everything defaults to needing one register. 1182 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) { 1183 NumRegistersForVT[i] = 1; 1184 RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i; 1185 } 1186 // ...except isVoid, which doesn't need any registers. 1187 NumRegistersForVT[MVT::isVoid] = 0; 1188 1189 // Find the largest integer register class. 1190 unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE; 1191 for (; RegClassForVT[LargestIntReg] == nullptr; --LargestIntReg) 1192 assert(LargestIntReg != MVT::i1 && "No integer registers defined!"); 1193 1194 // Every integer value type larger than this largest register takes twice as 1195 // many registers to represent as the previous ValueType. 1196 for (unsigned ExpandedReg = LargestIntReg + 1; 1197 ExpandedReg <= MVT::LAST_INTEGER_VALUETYPE; ++ExpandedReg) { 1198 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1]; 1199 RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg; 1200 TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1); 1201 ValueTypeActions.setTypeAction((MVT::SimpleValueType)ExpandedReg, 1202 TypeExpandInteger); 1203 } 1204 1205 // Inspect all of the ValueType's smaller than the largest integer 1206 // register to see which ones need promotion. 1207 unsigned LegalIntReg = LargestIntReg; 1208 for (unsigned IntReg = LargestIntReg - 1; 1209 IntReg >= (unsigned)MVT::i1; --IntReg) { 1210 MVT IVT = (MVT::SimpleValueType)IntReg; 1211 if (isTypeLegal(IVT)) { 1212 LegalIntReg = IntReg; 1213 } else { 1214 RegisterTypeForVT[IntReg] = TransformToType[IntReg] = 1215 (MVT::SimpleValueType)LegalIntReg; 1216 ValueTypeActions.setTypeAction(IVT, TypePromoteInteger); 1217 } 1218 } 1219 1220 // ppcf128 type is really two f64's. 1221 if (!isTypeLegal(MVT::ppcf128)) { 1222 if (isTypeLegal(MVT::f64)) { 1223 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64]; 1224 RegisterTypeForVT[MVT::ppcf128] = MVT::f64; 1225 TransformToType[MVT::ppcf128] = MVT::f64; 1226 ValueTypeActions.setTypeAction(MVT::ppcf128, TypeExpandFloat); 1227 } else { 1228 NumRegistersForVT[MVT::ppcf128] = NumRegistersForVT[MVT::i128]; 1229 RegisterTypeForVT[MVT::ppcf128] = RegisterTypeForVT[MVT::i128]; 1230 TransformToType[MVT::ppcf128] = MVT::i128; 1231 ValueTypeActions.setTypeAction(MVT::ppcf128, TypeSoftenFloat); 1232 } 1233 } 1234 1235 // Decide how to handle f128. If the target does not have native f128 support, 1236 // expand it to i128 and we will be generating soft float library calls. 1237 if (!isTypeLegal(MVT::f128)) { 1238 NumRegistersForVT[MVT::f128] = NumRegistersForVT[MVT::i128]; 1239 RegisterTypeForVT[MVT::f128] = RegisterTypeForVT[MVT::i128]; 1240 TransformToType[MVT::f128] = MVT::i128; 1241 ValueTypeActions.setTypeAction(MVT::f128, TypeSoftenFloat); 1242 } 1243 1244 // Decide how to handle f64. If the target does not have native f64 support, 1245 // expand it to i64 and we will be generating soft float library calls. 1246 if (!isTypeLegal(MVT::f64)) { 1247 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64]; 1248 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64]; 1249 TransformToType[MVT::f64] = MVT::i64; 1250 ValueTypeActions.setTypeAction(MVT::f64, TypeSoftenFloat); 1251 } 1252 1253 // Decide how to handle f32. If the target does not have native f32 support, 1254 // expand it to i32 and we will be generating soft float library calls. 1255 if (!isTypeLegal(MVT::f32)) { 1256 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32]; 1257 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32]; 1258 TransformToType[MVT::f32] = MVT::i32; 1259 ValueTypeActions.setTypeAction(MVT::f32, TypeSoftenFloat); 1260 } 1261 1262 // Decide how to handle f16. If the target does not have native f16 support, 1263 // promote it to f32, because there are no f16 library calls (except for 1264 // conversions). 1265 if (!isTypeLegal(MVT::f16)) { 1266 // Allow targets to control how we legalize half. 1267 if (softPromoteHalfType()) { 1268 NumRegistersForVT[MVT::f16] = NumRegistersForVT[MVT::i16]; 1269 RegisterTypeForVT[MVT::f16] = RegisterTypeForVT[MVT::i16]; 1270 TransformToType[MVT::f16] = MVT::f32; 1271 ValueTypeActions.setTypeAction(MVT::f16, TypeSoftPromoteHalf); 1272 } else { 1273 NumRegistersForVT[MVT::f16] = NumRegistersForVT[MVT::f32]; 1274 RegisterTypeForVT[MVT::f16] = RegisterTypeForVT[MVT::f32]; 1275 TransformToType[MVT::f16] = MVT::f32; 1276 ValueTypeActions.setTypeAction(MVT::f16, TypePromoteFloat); 1277 } 1278 } 1279 1280 // Loop over all of the vector value types to see which need transformations. 1281 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE; 1282 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) { 1283 MVT VT = (MVT::SimpleValueType) i; 1284 if (isTypeLegal(VT)) 1285 continue; 1286 1287 MVT EltVT = VT.getVectorElementType(); 1288 ElementCount EC = VT.getVectorElementCount(); 1289 bool IsLegalWiderType = false; 1290 bool IsScalable = VT.isScalableVector(); 1291 LegalizeTypeAction PreferredAction = getPreferredVectorAction(VT); 1292 switch (PreferredAction) { 1293 case TypePromoteInteger: { 1294 MVT::SimpleValueType EndVT = IsScalable ? 1295 MVT::LAST_INTEGER_SCALABLE_VECTOR_VALUETYPE : 1296 MVT::LAST_INTEGER_FIXEDLEN_VECTOR_VALUETYPE; 1297 // Try to promote the elements of integer vectors. If no legal 1298 // promotion was found, fall through to the widen-vector method. 1299 for (unsigned nVT = i + 1; 1300 (MVT::SimpleValueType)nVT <= EndVT; ++nVT) { 1301 MVT SVT = (MVT::SimpleValueType) nVT; 1302 // Promote vectors of integers to vectors with the same number 1303 // of elements, with a wider element type. 1304 if (SVT.getScalarSizeInBits() > EltVT.getFixedSizeInBits() && 1305 SVT.getVectorElementCount() == EC && isTypeLegal(SVT)) { 1306 TransformToType[i] = SVT; 1307 RegisterTypeForVT[i] = SVT; 1308 NumRegistersForVT[i] = 1; 1309 ValueTypeActions.setTypeAction(VT, TypePromoteInteger); 1310 IsLegalWiderType = true; 1311 break; 1312 } 1313 } 1314 if (IsLegalWiderType) 1315 break; 1316 LLVM_FALLTHROUGH; 1317 } 1318 1319 case TypeWidenVector: 1320 if (isPowerOf2_32(EC.getKnownMinValue())) { 1321 // Try to widen the vector. 1322 for (unsigned nVT = i + 1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) { 1323 MVT SVT = (MVT::SimpleValueType) nVT; 1324 if (SVT.getVectorElementType() == EltVT && 1325 SVT.isScalableVector() == IsScalable && 1326 SVT.getVectorElementCount().getKnownMinValue() > 1327 EC.getKnownMinValue() && 1328 isTypeLegal(SVT)) { 1329 TransformToType[i] = SVT; 1330 RegisterTypeForVT[i] = SVT; 1331 NumRegistersForVT[i] = 1; 1332 ValueTypeActions.setTypeAction(VT, TypeWidenVector); 1333 IsLegalWiderType = true; 1334 break; 1335 } 1336 } 1337 if (IsLegalWiderType) 1338 break; 1339 } else { 1340 // Only widen to the next power of 2 to keep consistency with EVT. 1341 MVT NVT = VT.getPow2VectorType(); 1342 if (isTypeLegal(NVT)) { 1343 TransformToType[i] = NVT; 1344 ValueTypeActions.setTypeAction(VT, TypeWidenVector); 1345 RegisterTypeForVT[i] = NVT; 1346 NumRegistersForVT[i] = 1; 1347 break; 1348 } 1349 } 1350 LLVM_FALLTHROUGH; 1351 1352 case TypeSplitVector: 1353 case TypeScalarizeVector: { 1354 MVT IntermediateVT; 1355 MVT RegisterVT; 1356 unsigned NumIntermediates; 1357 unsigned NumRegisters = getVectorTypeBreakdownMVT(VT, IntermediateVT, 1358 NumIntermediates, RegisterVT, this); 1359 NumRegistersForVT[i] = NumRegisters; 1360 assert(NumRegistersForVT[i] == NumRegisters && 1361 "NumRegistersForVT size cannot represent NumRegisters!"); 1362 RegisterTypeForVT[i] = RegisterVT; 1363 1364 MVT NVT = VT.getPow2VectorType(); 1365 if (NVT == VT) { 1366 // Type is already a power of 2. The default action is to split. 1367 TransformToType[i] = MVT::Other; 1368 if (PreferredAction == TypeScalarizeVector) 1369 ValueTypeActions.setTypeAction(VT, TypeScalarizeVector); 1370 else if (PreferredAction == TypeSplitVector) 1371 ValueTypeActions.setTypeAction(VT, TypeSplitVector); 1372 else if (EC.getKnownMinValue() > 1) 1373 ValueTypeActions.setTypeAction(VT, TypeSplitVector); 1374 else 1375 ValueTypeActions.setTypeAction(VT, EC.isScalable() 1376 ? TypeScalarizeScalableVector 1377 : TypeScalarizeVector); 1378 } else { 1379 TransformToType[i] = NVT; 1380 ValueTypeActions.setTypeAction(VT, TypeWidenVector); 1381 } 1382 break; 1383 } 1384 default: 1385 llvm_unreachable("Unknown vector legalization action!"); 1386 } 1387 } 1388 1389 // Determine the 'representative' register class for each value type. 1390 // An representative register class is the largest (meaning one which is 1391 // not a sub-register class / subreg register class) legal register class for 1392 // a group of value types. For example, on i386, i8, i16, and i32 1393 // representative would be GR32; while on x86_64 it's GR64. 1394 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) { 1395 const TargetRegisterClass* RRC; 1396 uint8_t Cost; 1397 std::tie(RRC, Cost) = findRepresentativeClass(TRI, (MVT::SimpleValueType)i); 1398 RepRegClassForVT[i] = RRC; 1399 RepRegClassCostForVT[i] = Cost; 1400 } 1401 } 1402 1403 EVT TargetLoweringBase::getSetCCResultType(const DataLayout &DL, LLVMContext &, 1404 EVT VT) const { 1405 assert(!VT.isVector() && "No default SetCC type for vectors!"); 1406 return getPointerTy(DL).SimpleTy; 1407 } 1408 1409 MVT::SimpleValueType TargetLoweringBase::getCmpLibcallReturnType() const { 1410 return MVT::i32; // return the default value 1411 } 1412 1413 /// getVectorTypeBreakdown - Vector types are broken down into some number of 1414 /// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32 1415 /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack. 1416 /// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86. 1417 /// 1418 /// This method returns the number of registers needed, and the VT for each 1419 /// register. It also returns the VT and quantity of the intermediate values 1420 /// before they are promoted/expanded. 1421 unsigned TargetLoweringBase::getVectorTypeBreakdown(LLVMContext &Context, EVT VT, 1422 EVT &IntermediateVT, 1423 unsigned &NumIntermediates, 1424 MVT &RegisterVT) const { 1425 ElementCount EltCnt = VT.getVectorElementCount(); 1426 1427 // If there is a wider vector type with the same element type as this one, 1428 // or a promoted vector type that has the same number of elements which 1429 // are wider, then we should convert to that legal vector type. 1430 // This handles things like <2 x float> -> <4 x float> and 1431 // <4 x i1> -> <4 x i32>. 1432 LegalizeTypeAction TA = getTypeAction(Context, VT); 1433 if (EltCnt.getKnownMinValue() != 1 && 1434 (TA == TypeWidenVector || TA == TypePromoteInteger)) { 1435 EVT RegisterEVT = getTypeToTransformTo(Context, VT); 1436 if (isTypeLegal(RegisterEVT)) { 1437 IntermediateVT = RegisterEVT; 1438 RegisterVT = RegisterEVT.getSimpleVT(); 1439 NumIntermediates = 1; 1440 return 1; 1441 } 1442 } 1443 1444 // Figure out the right, legal destination reg to copy into. 1445 EVT EltTy = VT.getVectorElementType(); 1446 1447 unsigned NumVectorRegs = 1; 1448 1449 // Scalable vectors cannot be scalarized, so handle the legalisation of the 1450 // types like done elsewhere in SelectionDAG. 1451 if (VT.isScalableVector() && !isPowerOf2_32(EltCnt.getKnownMinValue())) { 1452 LegalizeKind LK; 1453 EVT PartVT = VT; 1454 do { 1455 // Iterate until we've found a legal (part) type to hold VT. 1456 LK = getTypeConversion(Context, PartVT); 1457 PartVT = LK.second; 1458 } while (LK.first != TypeLegal); 1459 1460 NumIntermediates = VT.getVectorElementCount().getKnownMinValue() / 1461 PartVT.getVectorElementCount().getKnownMinValue(); 1462 1463 // FIXME: This code needs to be extended to handle more complex vector 1464 // breakdowns, like nxv7i64 -> nxv8i64 -> 4 x nxv2i64. Currently the only 1465 // supported cases are vectors that are broken down into equal parts 1466 // such as nxv6i64 -> 3 x nxv2i64. 1467 assert((PartVT.getVectorElementCount() * NumIntermediates) == 1468 VT.getVectorElementCount() && 1469 "Expected an integer multiple of PartVT"); 1470 IntermediateVT = PartVT; 1471 RegisterVT = getRegisterType(Context, IntermediateVT); 1472 return NumIntermediates; 1473 } 1474 1475 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally 1476 // we could break down into LHS/RHS like LegalizeDAG does. 1477 if (!isPowerOf2_32(EltCnt.getKnownMinValue())) { 1478 NumVectorRegs = EltCnt.getKnownMinValue(); 1479 EltCnt = ElementCount::getFixed(1); 1480 } 1481 1482 // Divide the input until we get to a supported size. This will always 1483 // end with a scalar if the target doesn't support vectors. 1484 while (EltCnt.getKnownMinValue() > 1 && 1485 !isTypeLegal(EVT::getVectorVT(Context, EltTy, EltCnt))) { 1486 EltCnt = EltCnt.divideCoefficientBy(2); 1487 NumVectorRegs <<= 1; 1488 } 1489 1490 NumIntermediates = NumVectorRegs; 1491 1492 EVT NewVT = EVT::getVectorVT(Context, EltTy, EltCnt); 1493 if (!isTypeLegal(NewVT)) 1494 NewVT = EltTy; 1495 IntermediateVT = NewVT; 1496 1497 MVT DestVT = getRegisterType(Context, NewVT); 1498 RegisterVT = DestVT; 1499 1500 if (EVT(DestVT).bitsLT(NewVT)) { // Value is expanded, e.g. i64 -> i16. 1501 TypeSize NewVTSize = NewVT.getSizeInBits(); 1502 // Convert sizes such as i33 to i64. 1503 if (!isPowerOf2_32(NewVTSize.getKnownMinSize())) 1504 NewVTSize = NewVTSize.coefficientNextPowerOf2(); 1505 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits()); 1506 } 1507 1508 // Otherwise, promotion or legal types use the same number of registers as 1509 // the vector decimated to the appropriate level. 1510 return NumVectorRegs; 1511 } 1512 1513 bool TargetLoweringBase::isSuitableForJumpTable(const SwitchInst *SI, 1514 uint64_t NumCases, 1515 uint64_t Range, 1516 ProfileSummaryInfo *PSI, 1517 BlockFrequencyInfo *BFI) const { 1518 // FIXME: This function check the maximum table size and density, but the 1519 // minimum size is not checked. It would be nice if the minimum size is 1520 // also combined within this function. Currently, the minimum size check is 1521 // performed in findJumpTable() in SelectionDAGBuiler and 1522 // getEstimatedNumberOfCaseClusters() in BasicTTIImpl. 1523 const bool OptForSize = 1524 SI->getParent()->getParent()->hasOptSize() || 1525 llvm::shouldOptimizeForSize(SI->getParent(), PSI, BFI); 1526 const unsigned MinDensity = getMinimumJumpTableDensity(OptForSize); 1527 const unsigned MaxJumpTableSize = getMaximumJumpTableSize(); 1528 1529 // Check whether the number of cases is small enough and 1530 // the range is dense enough for a jump table. 1531 return (OptForSize || Range <= MaxJumpTableSize) && 1532 (NumCases * 100 >= Range * MinDensity); 1533 } 1534 1535 /// Get the EVTs and ArgFlags collections that represent the legalized return 1536 /// type of the given function. This does not require a DAG or a return value, 1537 /// and is suitable for use before any DAGs for the function are constructed. 1538 /// TODO: Move this out of TargetLowering.cpp. 1539 void llvm::GetReturnInfo(CallingConv::ID CC, Type *ReturnType, 1540 AttributeList attr, 1541 SmallVectorImpl<ISD::OutputArg> &Outs, 1542 const TargetLowering &TLI, const DataLayout &DL) { 1543 SmallVector<EVT, 4> ValueVTs; 1544 ComputeValueVTs(TLI, DL, ReturnType, ValueVTs); 1545 unsigned NumValues = ValueVTs.size(); 1546 if (NumValues == 0) return; 1547 1548 for (unsigned j = 0, f = NumValues; j != f; ++j) { 1549 EVT VT = ValueVTs[j]; 1550 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 1551 1552 if (attr.hasAttribute(AttributeList::ReturnIndex, Attribute::SExt)) 1553 ExtendKind = ISD::SIGN_EXTEND; 1554 else if (attr.hasAttribute(AttributeList::ReturnIndex, Attribute::ZExt)) 1555 ExtendKind = ISD::ZERO_EXTEND; 1556 1557 // FIXME: C calling convention requires the return type to be promoted to 1558 // at least 32-bit. But this is not necessary for non-C calling 1559 // conventions. The frontend should mark functions whose return values 1560 // require promoting with signext or zeroext attributes. 1561 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) { 1562 MVT MinVT = TLI.getRegisterType(ReturnType->getContext(), MVT::i32); 1563 if (VT.bitsLT(MinVT)) 1564 VT = MinVT; 1565 } 1566 1567 unsigned NumParts = 1568 TLI.getNumRegistersForCallingConv(ReturnType->getContext(), CC, VT); 1569 MVT PartVT = 1570 TLI.getRegisterTypeForCallingConv(ReturnType->getContext(), CC, VT); 1571 1572 // 'inreg' on function refers to return value 1573 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy(); 1574 if (attr.hasAttribute(AttributeList::ReturnIndex, Attribute::InReg)) 1575 Flags.setInReg(); 1576 1577 // Propagate extension type if any 1578 if (attr.hasAttribute(AttributeList::ReturnIndex, Attribute::SExt)) 1579 Flags.setSExt(); 1580 else if (attr.hasAttribute(AttributeList::ReturnIndex, Attribute::ZExt)) 1581 Flags.setZExt(); 1582 1583 for (unsigned i = 0; i < NumParts; ++i) 1584 Outs.push_back(ISD::OutputArg(Flags, PartVT, VT, /*isfixed=*/true, 0, 0)); 1585 } 1586 } 1587 1588 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 1589 /// function arguments in the caller parameter area. This is the actual 1590 /// alignment, not its logarithm. 1591 unsigned TargetLoweringBase::getByValTypeAlignment(Type *Ty, 1592 const DataLayout &DL) const { 1593 return DL.getABITypeAlign(Ty).value(); 1594 } 1595 1596 bool TargetLoweringBase::allowsMemoryAccessForAlignment( 1597 LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace, 1598 Align Alignment, MachineMemOperand::Flags Flags, bool *Fast) const { 1599 // Check if the specified alignment is sufficient based on the data layout. 1600 // TODO: While using the data layout works in practice, a better solution 1601 // would be to implement this check directly (make this a virtual function). 1602 // For example, the ABI alignment may change based on software platform while 1603 // this function should only be affected by hardware implementation. 1604 Type *Ty = VT.getTypeForEVT(Context); 1605 if (Alignment >= DL.getABITypeAlign(Ty)) { 1606 // Assume that an access that meets the ABI-specified alignment is fast. 1607 if (Fast != nullptr) 1608 *Fast = true; 1609 return true; 1610 } 1611 1612 // This is a misaligned access. 1613 return allowsMisalignedMemoryAccesses(VT, AddrSpace, Alignment.value(), Flags, 1614 Fast); 1615 } 1616 1617 bool TargetLoweringBase::allowsMemoryAccessForAlignment( 1618 LLVMContext &Context, const DataLayout &DL, EVT VT, 1619 const MachineMemOperand &MMO, bool *Fast) const { 1620 return allowsMemoryAccessForAlignment(Context, DL, VT, MMO.getAddrSpace(), 1621 MMO.getAlign(), MMO.getFlags(), Fast); 1622 } 1623 1624 bool TargetLoweringBase::allowsMemoryAccess(LLVMContext &Context, 1625 const DataLayout &DL, EVT VT, 1626 unsigned AddrSpace, Align Alignment, 1627 MachineMemOperand::Flags Flags, 1628 bool *Fast) const { 1629 return allowsMemoryAccessForAlignment(Context, DL, VT, AddrSpace, Alignment, 1630 Flags, Fast); 1631 } 1632 1633 bool TargetLoweringBase::allowsMemoryAccess(LLVMContext &Context, 1634 const DataLayout &DL, EVT VT, 1635 const MachineMemOperand &MMO, 1636 bool *Fast) const { 1637 return allowsMemoryAccess(Context, DL, VT, MMO.getAddrSpace(), MMO.getAlign(), 1638 MMO.getFlags(), Fast); 1639 } 1640 1641 BranchProbability TargetLoweringBase::getPredictableBranchThreshold() const { 1642 return BranchProbability(MinPercentageForPredictableBranch, 100); 1643 } 1644 1645 //===----------------------------------------------------------------------===// 1646 // TargetTransformInfo Helpers 1647 //===----------------------------------------------------------------------===// 1648 1649 int TargetLoweringBase::InstructionOpcodeToISD(unsigned Opcode) const { 1650 enum InstructionOpcodes { 1651 #define HANDLE_INST(NUM, OPCODE, CLASS) OPCODE = NUM, 1652 #define LAST_OTHER_INST(NUM) InstructionOpcodesCount = NUM 1653 #include "llvm/IR/Instruction.def" 1654 }; 1655 switch (static_cast<InstructionOpcodes>(Opcode)) { 1656 case Ret: return 0; 1657 case Br: return 0; 1658 case Switch: return 0; 1659 case IndirectBr: return 0; 1660 case Invoke: return 0; 1661 case CallBr: return 0; 1662 case Resume: return 0; 1663 case Unreachable: return 0; 1664 case CleanupRet: return 0; 1665 case CatchRet: return 0; 1666 case CatchPad: return 0; 1667 case CatchSwitch: return 0; 1668 case CleanupPad: return 0; 1669 case FNeg: return ISD::FNEG; 1670 case Add: return ISD::ADD; 1671 case FAdd: return ISD::FADD; 1672 case Sub: return ISD::SUB; 1673 case FSub: return ISD::FSUB; 1674 case Mul: return ISD::MUL; 1675 case FMul: return ISD::FMUL; 1676 case UDiv: return ISD::UDIV; 1677 case SDiv: return ISD::SDIV; 1678 case FDiv: return ISD::FDIV; 1679 case URem: return ISD::UREM; 1680 case SRem: return ISD::SREM; 1681 case FRem: return ISD::FREM; 1682 case Shl: return ISD::SHL; 1683 case LShr: return ISD::SRL; 1684 case AShr: return ISD::SRA; 1685 case And: return ISD::AND; 1686 case Or: return ISD::OR; 1687 case Xor: return ISD::XOR; 1688 case Alloca: return 0; 1689 case Load: return ISD::LOAD; 1690 case Store: return ISD::STORE; 1691 case GetElementPtr: return 0; 1692 case Fence: return 0; 1693 case AtomicCmpXchg: return 0; 1694 case AtomicRMW: return 0; 1695 case Trunc: return ISD::TRUNCATE; 1696 case ZExt: return ISD::ZERO_EXTEND; 1697 case SExt: return ISD::SIGN_EXTEND; 1698 case FPToUI: return ISD::FP_TO_UINT; 1699 case FPToSI: return ISD::FP_TO_SINT; 1700 case UIToFP: return ISD::UINT_TO_FP; 1701 case SIToFP: return ISD::SINT_TO_FP; 1702 case FPTrunc: return ISD::FP_ROUND; 1703 case FPExt: return ISD::FP_EXTEND; 1704 case PtrToInt: return ISD::BITCAST; 1705 case IntToPtr: return ISD::BITCAST; 1706 case BitCast: return ISD::BITCAST; 1707 case AddrSpaceCast: return ISD::ADDRSPACECAST; 1708 case ICmp: return ISD::SETCC; 1709 case FCmp: return ISD::SETCC; 1710 case PHI: return 0; 1711 case Call: return 0; 1712 case Select: return ISD::SELECT; 1713 case UserOp1: return 0; 1714 case UserOp2: return 0; 1715 case VAArg: return 0; 1716 case ExtractElement: return ISD::EXTRACT_VECTOR_ELT; 1717 case InsertElement: return ISD::INSERT_VECTOR_ELT; 1718 case ShuffleVector: return ISD::VECTOR_SHUFFLE; 1719 case ExtractValue: return ISD::MERGE_VALUES; 1720 case InsertValue: return ISD::MERGE_VALUES; 1721 case LandingPad: return 0; 1722 case Freeze: return ISD::FREEZE; 1723 } 1724 1725 llvm_unreachable("Unknown instruction type encountered!"); 1726 } 1727 1728 std::pair<int, MVT> 1729 TargetLoweringBase::getTypeLegalizationCost(const DataLayout &DL, 1730 Type *Ty) const { 1731 LLVMContext &C = Ty->getContext(); 1732 EVT MTy = getValueType(DL, Ty); 1733 1734 int Cost = 1; 1735 // We keep legalizing the type until we find a legal kind. We assume that 1736 // the only operation that costs anything is the split. After splitting 1737 // we need to handle two types. 1738 while (true) { 1739 LegalizeKind LK = getTypeConversion(C, MTy); 1740 1741 if (LK.first == TypeLegal) 1742 return std::make_pair(Cost, MTy.getSimpleVT()); 1743 1744 if (LK.first == TypeSplitVector || LK.first == TypeExpandInteger) 1745 Cost *= 2; 1746 1747 // Do not loop with f128 type. 1748 if (MTy == LK.second) 1749 return std::make_pair(Cost, MTy.getSimpleVT()); 1750 1751 // Keep legalizing the type. 1752 MTy = LK.second; 1753 } 1754 } 1755 1756 Value *TargetLoweringBase::getDefaultSafeStackPointerLocation(IRBuilder<> &IRB, 1757 bool UseTLS) const { 1758 // compiler-rt provides a variable with a magic name. Targets that do not 1759 // link with compiler-rt may also provide such a variable. 1760 Module *M = IRB.GetInsertBlock()->getParent()->getParent(); 1761 const char *UnsafeStackPtrVar = "__safestack_unsafe_stack_ptr"; 1762 auto UnsafeStackPtr = 1763 dyn_cast_or_null<GlobalVariable>(M->getNamedValue(UnsafeStackPtrVar)); 1764 1765 Type *StackPtrTy = Type::getInt8PtrTy(M->getContext()); 1766 1767 if (!UnsafeStackPtr) { 1768 auto TLSModel = UseTLS ? 1769 GlobalValue::InitialExecTLSModel : 1770 GlobalValue::NotThreadLocal; 1771 // The global variable is not defined yet, define it ourselves. 1772 // We use the initial-exec TLS model because we do not support the 1773 // variable living anywhere other than in the main executable. 1774 UnsafeStackPtr = new GlobalVariable( 1775 *M, StackPtrTy, false, GlobalValue::ExternalLinkage, nullptr, 1776 UnsafeStackPtrVar, nullptr, TLSModel); 1777 } else { 1778 // The variable exists, check its type and attributes. 1779 if (UnsafeStackPtr->getValueType() != StackPtrTy) 1780 report_fatal_error(Twine(UnsafeStackPtrVar) + " must have void* type"); 1781 if (UseTLS != UnsafeStackPtr->isThreadLocal()) 1782 report_fatal_error(Twine(UnsafeStackPtrVar) + " must " + 1783 (UseTLS ? "" : "not ") + "be thread-local"); 1784 } 1785 return UnsafeStackPtr; 1786 } 1787 1788 Value *TargetLoweringBase::getSafeStackPointerLocation(IRBuilder<> &IRB) const { 1789 if (!TM.getTargetTriple().isAndroid()) 1790 return getDefaultSafeStackPointerLocation(IRB, true); 1791 1792 // Android provides a libc function to retrieve the address of the current 1793 // thread's unsafe stack pointer. 1794 Module *M = IRB.GetInsertBlock()->getParent()->getParent(); 1795 Type *StackPtrTy = Type::getInt8PtrTy(M->getContext()); 1796 FunctionCallee Fn = M->getOrInsertFunction("__safestack_pointer_address", 1797 StackPtrTy->getPointerTo(0)); 1798 return IRB.CreateCall(Fn); 1799 } 1800 1801 //===----------------------------------------------------------------------===// 1802 // Loop Strength Reduction hooks 1803 //===----------------------------------------------------------------------===// 1804 1805 /// isLegalAddressingMode - Return true if the addressing mode represented 1806 /// by AM is legal for this target, for a load/store of the specified type. 1807 bool TargetLoweringBase::isLegalAddressingMode(const DataLayout &DL, 1808 const AddrMode &AM, Type *Ty, 1809 unsigned AS, Instruction *I) const { 1810 // The default implementation of this implements a conservative RISCy, r+r and 1811 // r+i addr mode. 1812 1813 // Allows a sign-extended 16-bit immediate field. 1814 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1) 1815 return false; 1816 1817 // No global is ever allowed as a base. 1818 if (AM.BaseGV) 1819 return false; 1820 1821 // Only support r+r, 1822 switch (AM.Scale) { 1823 case 0: // "r+i" or just "i", depending on HasBaseReg. 1824 break; 1825 case 1: 1826 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. 1827 return false; 1828 // Otherwise we have r+r or r+i. 1829 break; 1830 case 2: 1831 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. 1832 return false; 1833 // Allow 2*r as r+r. 1834 break; 1835 default: // Don't allow n * r 1836 return false; 1837 } 1838 1839 return true; 1840 } 1841 1842 //===----------------------------------------------------------------------===// 1843 // Stack Protector 1844 //===----------------------------------------------------------------------===// 1845 1846 // For OpenBSD return its special guard variable. Otherwise return nullptr, 1847 // so that SelectionDAG handle SSP. 1848 Value *TargetLoweringBase::getIRStackGuard(IRBuilder<> &IRB) const { 1849 if (getTargetMachine().getTargetTriple().isOSOpenBSD()) { 1850 Module &M = *IRB.GetInsertBlock()->getParent()->getParent(); 1851 PointerType *PtrTy = Type::getInt8PtrTy(M.getContext()); 1852 Constant *C = M.getOrInsertGlobal("__guard_local", PtrTy); 1853 if (GlobalVariable *G = dyn_cast_or_null<GlobalVariable>(C)) 1854 G->setVisibility(GlobalValue::HiddenVisibility); 1855 return C; 1856 } 1857 return nullptr; 1858 } 1859 1860 // Currently only support "standard" __stack_chk_guard. 1861 // TODO: add LOAD_STACK_GUARD support. 1862 void TargetLoweringBase::insertSSPDeclarations(Module &M) const { 1863 if (!M.getNamedValue("__stack_chk_guard")) 1864 new GlobalVariable(M, Type::getInt8PtrTy(M.getContext()), false, 1865 GlobalVariable::ExternalLinkage, 1866 nullptr, "__stack_chk_guard"); 1867 } 1868 1869 // Currently only support "standard" __stack_chk_guard. 1870 // TODO: add LOAD_STACK_GUARD support. 1871 Value *TargetLoweringBase::getSDagStackGuard(const Module &M) const { 1872 return M.getNamedValue("__stack_chk_guard"); 1873 } 1874 1875 Function *TargetLoweringBase::getSSPStackGuardCheck(const Module &M) const { 1876 return nullptr; 1877 } 1878 1879 unsigned TargetLoweringBase::getMinimumJumpTableEntries() const { 1880 return MinimumJumpTableEntries; 1881 } 1882 1883 void TargetLoweringBase::setMinimumJumpTableEntries(unsigned Val) { 1884 MinimumJumpTableEntries = Val; 1885 } 1886 1887 unsigned TargetLoweringBase::getMinimumJumpTableDensity(bool OptForSize) const { 1888 return OptForSize ? OptsizeJumpTableDensity : JumpTableDensity; 1889 } 1890 1891 unsigned TargetLoweringBase::getMaximumJumpTableSize() const { 1892 return MaximumJumpTableSize; 1893 } 1894 1895 void TargetLoweringBase::setMaximumJumpTableSize(unsigned Val) { 1896 MaximumJumpTableSize = Val; 1897 } 1898 1899 bool TargetLoweringBase::isJumpTableRelative() const { 1900 return getTargetMachine().isPositionIndependent(); 1901 } 1902 1903 //===----------------------------------------------------------------------===// 1904 // Reciprocal Estimates 1905 //===----------------------------------------------------------------------===// 1906 1907 /// Get the reciprocal estimate attribute string for a function that will 1908 /// override the target defaults. 1909 static StringRef getRecipEstimateForFunc(MachineFunction &MF) { 1910 const Function &F = MF.getFunction(); 1911 return F.getFnAttribute("reciprocal-estimates").getValueAsString(); 1912 } 1913 1914 /// Construct a string for the given reciprocal operation of the given type. 1915 /// This string should match the corresponding option to the front-end's 1916 /// "-mrecip" flag assuming those strings have been passed through in an 1917 /// attribute string. For example, "vec-divf" for a division of a vXf32. 1918 static std::string getReciprocalOpName(bool IsSqrt, EVT VT) { 1919 std::string Name = VT.isVector() ? "vec-" : ""; 1920 1921 Name += IsSqrt ? "sqrt" : "div"; 1922 1923 // TODO: Handle "half" or other float types? 1924 if (VT.getScalarType() == MVT::f64) { 1925 Name += "d"; 1926 } else { 1927 assert(VT.getScalarType() == MVT::f32 && 1928 "Unexpected FP type for reciprocal estimate"); 1929 Name += "f"; 1930 } 1931 1932 return Name; 1933 } 1934 1935 /// Return the character position and value (a single numeric character) of a 1936 /// customized refinement operation in the input string if it exists. Return 1937 /// false if there is no customized refinement step count. 1938 static bool parseRefinementStep(StringRef In, size_t &Position, 1939 uint8_t &Value) { 1940 const char RefStepToken = ':'; 1941 Position = In.find(RefStepToken); 1942 if (Position == StringRef::npos) 1943 return false; 1944 1945 StringRef RefStepString = In.substr(Position + 1); 1946 // Allow exactly one numeric character for the additional refinement 1947 // step parameter. 1948 if (RefStepString.size() == 1) { 1949 char RefStepChar = RefStepString[0]; 1950 if (RefStepChar >= '0' && RefStepChar <= '9') { 1951 Value = RefStepChar - '0'; 1952 return true; 1953 } 1954 } 1955 report_fatal_error("Invalid refinement step for -recip."); 1956 } 1957 1958 /// For the input attribute string, return one of the ReciprocalEstimate enum 1959 /// status values (enabled, disabled, or not specified) for this operation on 1960 /// the specified data type. 1961 static int getOpEnabled(bool IsSqrt, EVT VT, StringRef Override) { 1962 if (Override.empty()) 1963 return TargetLoweringBase::ReciprocalEstimate::Unspecified; 1964 1965 SmallVector<StringRef, 4> OverrideVector; 1966 Override.split(OverrideVector, ','); 1967 unsigned NumArgs = OverrideVector.size(); 1968 1969 // Check if "all", "none", or "default" was specified. 1970 if (NumArgs == 1) { 1971 // Look for an optional setting of the number of refinement steps needed 1972 // for this type of reciprocal operation. 1973 size_t RefPos; 1974 uint8_t RefSteps; 1975 if (parseRefinementStep(Override, RefPos, RefSteps)) { 1976 // Split the string for further processing. 1977 Override = Override.substr(0, RefPos); 1978 } 1979 1980 // All reciprocal types are enabled. 1981 if (Override == "all") 1982 return TargetLoweringBase::ReciprocalEstimate::Enabled; 1983 1984 // All reciprocal types are disabled. 1985 if (Override == "none") 1986 return TargetLoweringBase::ReciprocalEstimate::Disabled; 1987 1988 // Target defaults for enablement are used. 1989 if (Override == "default") 1990 return TargetLoweringBase::ReciprocalEstimate::Unspecified; 1991 } 1992 1993 // The attribute string may omit the size suffix ('f'/'d'). 1994 std::string VTName = getReciprocalOpName(IsSqrt, VT); 1995 std::string VTNameNoSize = VTName; 1996 VTNameNoSize.pop_back(); 1997 static const char DisabledPrefix = '!'; 1998 1999 for (StringRef RecipType : OverrideVector) { 2000 size_t RefPos; 2001 uint8_t RefSteps; 2002 if (parseRefinementStep(RecipType, RefPos, RefSteps)) 2003 RecipType = RecipType.substr(0, RefPos); 2004 2005 // Ignore the disablement token for string matching. 2006 bool IsDisabled = RecipType[0] == DisabledPrefix; 2007 if (IsDisabled) 2008 RecipType = RecipType.substr(1); 2009 2010 if (RecipType.equals(VTName) || RecipType.equals(VTNameNoSize)) 2011 return IsDisabled ? TargetLoweringBase::ReciprocalEstimate::Disabled 2012 : TargetLoweringBase::ReciprocalEstimate::Enabled; 2013 } 2014 2015 return TargetLoweringBase::ReciprocalEstimate::Unspecified; 2016 } 2017 2018 /// For the input attribute string, return the customized refinement step count 2019 /// for this operation on the specified data type. If the step count does not 2020 /// exist, return the ReciprocalEstimate enum value for unspecified. 2021 static int getOpRefinementSteps(bool IsSqrt, EVT VT, StringRef Override) { 2022 if (Override.empty()) 2023 return TargetLoweringBase::ReciprocalEstimate::Unspecified; 2024 2025 SmallVector<StringRef, 4> OverrideVector; 2026 Override.split(OverrideVector, ','); 2027 unsigned NumArgs = OverrideVector.size(); 2028 2029 // Check if "all", "default", or "none" was specified. 2030 if (NumArgs == 1) { 2031 // Look for an optional setting of the number of refinement steps needed 2032 // for this type of reciprocal operation. 2033 size_t RefPos; 2034 uint8_t RefSteps; 2035 if (!parseRefinementStep(Override, RefPos, RefSteps)) 2036 return TargetLoweringBase::ReciprocalEstimate::Unspecified; 2037 2038 // Split the string for further processing. 2039 Override = Override.substr(0, RefPos); 2040 assert(Override != "none" && 2041 "Disabled reciprocals, but specifed refinement steps?"); 2042 2043 // If this is a general override, return the specified number of steps. 2044 if (Override == "all" || Override == "default") 2045 return RefSteps; 2046 } 2047 2048 // The attribute string may omit the size suffix ('f'/'d'). 2049 std::string VTName = getReciprocalOpName(IsSqrt, VT); 2050 std::string VTNameNoSize = VTName; 2051 VTNameNoSize.pop_back(); 2052 2053 for (StringRef RecipType : OverrideVector) { 2054 size_t RefPos; 2055 uint8_t RefSteps; 2056 if (!parseRefinementStep(RecipType, RefPos, RefSteps)) 2057 continue; 2058 2059 RecipType = RecipType.substr(0, RefPos); 2060 if (RecipType.equals(VTName) || RecipType.equals(VTNameNoSize)) 2061 return RefSteps; 2062 } 2063 2064 return TargetLoweringBase::ReciprocalEstimate::Unspecified; 2065 } 2066 2067 int TargetLoweringBase::getRecipEstimateSqrtEnabled(EVT VT, 2068 MachineFunction &MF) const { 2069 return getOpEnabled(true, VT, getRecipEstimateForFunc(MF)); 2070 } 2071 2072 int TargetLoweringBase::getRecipEstimateDivEnabled(EVT VT, 2073 MachineFunction &MF) const { 2074 return getOpEnabled(false, VT, getRecipEstimateForFunc(MF)); 2075 } 2076 2077 int TargetLoweringBase::getSqrtRefinementSteps(EVT VT, 2078 MachineFunction &MF) const { 2079 return getOpRefinementSteps(true, VT, getRecipEstimateForFunc(MF)); 2080 } 2081 2082 int TargetLoweringBase::getDivRefinementSteps(EVT VT, 2083 MachineFunction &MF) const { 2084 return getOpRefinementSteps(false, VT, getRecipEstimateForFunc(MF)); 2085 } 2086 2087 void TargetLoweringBase::finalizeLowering(MachineFunction &MF) const { 2088 MF.getRegInfo().freezeReservedRegs(MF); 2089 } 2090 2091 MachineMemOperand::Flags 2092 TargetLoweringBase::getLoadMemOperandFlags(const LoadInst &LI, 2093 const DataLayout &DL) const { 2094 MachineMemOperand::Flags Flags = MachineMemOperand::MOLoad; 2095 if (LI.isVolatile()) 2096 Flags |= MachineMemOperand::MOVolatile; 2097 2098 if (LI.hasMetadata(LLVMContext::MD_nontemporal)) 2099 Flags |= MachineMemOperand::MONonTemporal; 2100 2101 if (LI.hasMetadata(LLVMContext::MD_invariant_load)) 2102 Flags |= MachineMemOperand::MOInvariant; 2103 2104 if (isDereferenceablePointer(LI.getPointerOperand(), LI.getType(), DL)) 2105 Flags |= MachineMemOperand::MODereferenceable; 2106 2107 Flags |= getTargetMMOFlags(LI); 2108 return Flags; 2109 } 2110 2111 MachineMemOperand::Flags 2112 TargetLoweringBase::getStoreMemOperandFlags(const StoreInst &SI, 2113 const DataLayout &DL) const { 2114 MachineMemOperand::Flags Flags = MachineMemOperand::MOStore; 2115 2116 if (SI.isVolatile()) 2117 Flags |= MachineMemOperand::MOVolatile; 2118 2119 if (SI.hasMetadata(LLVMContext::MD_nontemporal)) 2120 Flags |= MachineMemOperand::MONonTemporal; 2121 2122 // FIXME: Not preserving dereferenceable 2123 Flags |= getTargetMMOFlags(SI); 2124 return Flags; 2125 } 2126 2127 MachineMemOperand::Flags 2128 TargetLoweringBase::getAtomicMemOperandFlags(const Instruction &AI, 2129 const DataLayout &DL) const { 2130 auto Flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore; 2131 2132 if (const AtomicRMWInst *RMW = dyn_cast<AtomicRMWInst>(&AI)) { 2133 if (RMW->isVolatile()) 2134 Flags |= MachineMemOperand::MOVolatile; 2135 } else if (const AtomicCmpXchgInst *CmpX = dyn_cast<AtomicCmpXchgInst>(&AI)) { 2136 if (CmpX->isVolatile()) 2137 Flags |= MachineMemOperand::MOVolatile; 2138 } else 2139 llvm_unreachable("not an atomic instruction"); 2140 2141 // FIXME: Not preserving dereferenceable 2142 Flags |= getTargetMMOFlags(AI); 2143 return Flags; 2144 } 2145 2146 //===----------------------------------------------------------------------===// 2147 // GlobalISel Hooks 2148 //===----------------------------------------------------------------------===// 2149 2150 bool TargetLoweringBase::shouldLocalize(const MachineInstr &MI, 2151 const TargetTransformInfo *TTI) const { 2152 auto &MF = *MI.getMF(); 2153 auto &MRI = MF.getRegInfo(); 2154 // Assuming a spill and reload of a value has a cost of 1 instruction each, 2155 // this helper function computes the maximum number of uses we should consider 2156 // for remat. E.g. on arm64 global addresses take 2 insts to materialize. We 2157 // break even in terms of code size when the original MI has 2 users vs 2158 // choosing to potentially spill. Any more than 2 users we we have a net code 2159 // size increase. This doesn't take into account register pressure though. 2160 auto maxUses = [](unsigned RematCost) { 2161 // A cost of 1 means remats are basically free. 2162 if (RematCost == 1) 2163 return UINT_MAX; 2164 if (RematCost == 2) 2165 return 2U; 2166 2167 // Remat is too expensive, only sink if there's one user. 2168 if (RematCost > 2) 2169 return 1U; 2170 llvm_unreachable("Unexpected remat cost"); 2171 }; 2172 2173 // Helper to walk through uses and terminate if we've reached a limit. Saves 2174 // us spending time traversing uses if all we want to know is if it's >= min. 2175 auto isUsesAtMost = [&](unsigned Reg, unsigned MaxUses) { 2176 unsigned NumUses = 0; 2177 auto UI = MRI.use_instr_nodbg_begin(Reg), UE = MRI.use_instr_nodbg_end(); 2178 for (; UI != UE && NumUses < MaxUses; ++UI) { 2179 NumUses++; 2180 } 2181 // If we haven't reached the end yet then there are more than MaxUses users. 2182 return UI == UE; 2183 }; 2184 2185 switch (MI.getOpcode()) { 2186 default: 2187 return false; 2188 // Constants-like instructions should be close to their users. 2189 // We don't want long live-ranges for them. 2190 case TargetOpcode::G_CONSTANT: 2191 case TargetOpcode::G_FCONSTANT: 2192 case TargetOpcode::G_FRAME_INDEX: 2193 case TargetOpcode::G_INTTOPTR: 2194 return true; 2195 case TargetOpcode::G_GLOBAL_VALUE: { 2196 unsigned RematCost = TTI->getGISelRematGlobalCost(); 2197 Register Reg = MI.getOperand(0).getReg(); 2198 unsigned MaxUses = maxUses(RematCost); 2199 if (MaxUses == UINT_MAX) 2200 return true; // Remats are "free" so always localize. 2201 bool B = isUsesAtMost(Reg, MaxUses); 2202 return B; 2203 } 2204 } 2205 } 2206