1 //===- InstrEmitter.h - Emit MachineInstrs for the SelectionDAG -*- C++ -*--==// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This declares the Emit routines for the SelectionDAG class, which creates 10 // MachineInstrs based on the decisions of the SelectionDAG instruction 11 // selection. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #ifndef LLVM_LIB_CODEGEN_SELECTIONDAG_INSTREMITTER_H 16 #define LLVM_LIB_CODEGEN_SELECTIONDAG_INSTREMITTER_H 17 18 #include "llvm/ADT/DenseMap.h" 19 #include "llvm/CodeGen/MachineBasicBlock.h" 20 #include "llvm/CodeGen/SelectionDAGNodes.h" 21 22 namespace llvm { 23 24 class MachineInstrBuilder; 25 class MCInstrDesc; 26 class SDDbgLabel; 27 class SDDbgValue; 28 class TargetLowering; 29 30 class LLVM_LIBRARY_VISIBILITY InstrEmitter { 31 MachineFunction *MF; 32 MachineRegisterInfo *MRI; 33 const TargetInstrInfo *TII; 34 const TargetRegisterInfo *TRI; 35 const TargetLowering *TLI; 36 37 MachineBasicBlock *MBB; 38 MachineBasicBlock::iterator InsertPos; 39 40 /// Should we try to produce DBG_INSTR_REF instructions? 41 bool EmitDebugInstrRefs; 42 43 /// EmitCopyFromReg - Generate machine code for an CopyFromReg node or an 44 /// implicit physical register output. 45 void EmitCopyFromReg(SDNode *Node, unsigned ResNo, 46 bool IsClone, bool IsCloned, 47 Register SrcReg, 48 DenseMap<SDValue, Register> &VRBaseMap); 49 50 void CreateVirtualRegisters(SDNode *Node, 51 MachineInstrBuilder &MIB, 52 const MCInstrDesc &II, 53 bool IsClone, bool IsCloned, 54 DenseMap<SDValue, Register> &VRBaseMap); 55 56 /// getVR - Return the virtual register corresponding to the specified result 57 /// of the specified node. 58 Register getVR(SDValue Op, 59 DenseMap<SDValue, Register> &VRBaseMap); 60 61 /// AddRegisterOperand - Add the specified register as an operand to the 62 /// specified machine instr. Insert register copies if the register is 63 /// not in the required register class. 64 void AddRegisterOperand(MachineInstrBuilder &MIB, 65 SDValue Op, 66 unsigned IIOpNum, 67 const MCInstrDesc *II, 68 DenseMap<SDValue, Register> &VRBaseMap, 69 bool IsDebug, bool IsClone, bool IsCloned); 70 71 /// AddOperand - Add the specified operand to the specified machine instr. II 72 /// specifies the instruction information for the node, and IIOpNum is the 73 /// operand number (in the II) that we are adding. IIOpNum and II are used for 74 /// assertions only. 75 void AddOperand(MachineInstrBuilder &MIB, 76 SDValue Op, 77 unsigned IIOpNum, 78 const MCInstrDesc *II, 79 DenseMap<SDValue, Register> &VRBaseMap, 80 bool IsDebug, bool IsClone, bool IsCloned); 81 82 /// ConstrainForSubReg - Try to constrain VReg to a register class that 83 /// supports SubIdx sub-registers. Emit a copy if that isn't possible. 84 /// Return the virtual register to use. 85 Register ConstrainForSubReg(Register VReg, unsigned SubIdx, MVT VT, 86 bool isDivergent, const DebugLoc &DL); 87 88 /// EmitSubregNode - Generate machine code for subreg nodes. 89 /// 90 void EmitSubregNode(SDNode *Node, DenseMap<SDValue, Register> &VRBaseMap, 91 bool IsClone, bool IsCloned); 92 93 /// EmitCopyToRegClassNode - Generate machine code for COPY_TO_REGCLASS nodes. 94 /// COPY_TO_REGCLASS is just a normal copy, except that the destination 95 /// register is constrained to be in a particular register class. 96 /// 97 void EmitCopyToRegClassNode(SDNode *Node, 98 DenseMap<SDValue, Register> &VRBaseMap); 99 100 /// EmitRegSequence - Generate machine code for REG_SEQUENCE nodes. 101 /// 102 void EmitRegSequence(SDNode *Node, DenseMap<SDValue, Register> &VRBaseMap, 103 bool IsClone, bool IsCloned); 104 public: 105 /// CountResults - The results of target nodes have register or immediate 106 /// operands first, then an optional chain, and optional flag operands 107 /// (which do not go into the machine instrs.) 108 static unsigned CountResults(SDNode *Node); 109 110 /// EmitDbgValue - Generate machine instruction for a dbg_value node. 111 /// 112 MachineInstr *EmitDbgValue(SDDbgValue *SD, 113 DenseMap<SDValue, Register> &VRBaseMap); 114 115 /// Attempt to emit a dbg_value as a DBG_INSTR_REF. May fail and return 116 /// nullptr, in which case we fall back to plain EmitDbgValue. 117 MachineInstr *EmitDbgInstrRef(SDDbgValue *SD, 118 DenseMap<SDValue, Register> &VRBaseMap); 119 120 /// Generate machine instruction for a dbg_label node. 121 MachineInstr *EmitDbgLabel(SDDbgLabel *SD); 122 123 /// EmitNode - Generate machine code for a node and needed dependencies. 124 /// 125 void EmitNode(SDNode *Node, bool IsClone, bool IsCloned, 126 DenseMap<SDValue, Register> &VRBaseMap) { 127 if (Node->isMachineOpcode()) 128 EmitMachineNode(Node, IsClone, IsCloned, VRBaseMap); 129 else 130 EmitSpecialNode(Node, IsClone, IsCloned, VRBaseMap); 131 } 132 133 /// getBlock - Return the current basic block. 134 MachineBasicBlock *getBlock() { return MBB; } 135 136 /// getInsertPos - Return the current insertion position. 137 MachineBasicBlock::iterator getInsertPos() { return InsertPos; } 138 139 /// InstrEmitter - Construct an InstrEmitter and set it to start inserting 140 /// at the given position in the given block. 141 InstrEmitter(const TargetMachine &TM, MachineBasicBlock *mbb, 142 MachineBasicBlock::iterator insertpos); 143 144 private: 145 void EmitMachineNode(SDNode *Node, bool IsClone, bool IsCloned, 146 DenseMap<SDValue, Register> &VRBaseMap); 147 void EmitSpecialNode(SDNode *Node, bool IsClone, bool IsCloned, 148 DenseMap<SDValue, Register> &VRBaseMap); 149 }; 150 151 } 152 153 #endif 154