1 //===- RegisterUsageInfo.cpp - Register Usage Information Storage ---------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 ///
10 /// This pass is required to take advantage of the interprocedural register
11 /// allocation infrastructure.
12 ///
13 //===----------------------------------------------------------------------===//
14 
15 #include "llvm/CodeGen/RegisterUsageInfo.h"
16 #include "llvm/ADT/SmallVector.h"
17 #include "llvm/CodeGen/MachineOperand.h"
18 #include "llvm/CodeGen/TargetRegisterInfo.h"
19 #include "llvm/CodeGen/TargetSubtargetInfo.h"
20 #include "llvm/IR/Function.h"
21 #include "llvm/IR/Module.h"
22 #include "llvm/Pass.h"
23 #include "llvm/Support/CommandLine.h"
24 #include "llvm/Support/raw_ostream.h"
25 #include "llvm/Target/TargetMachine.h"
26 #include <algorithm>
27 #include <cassert>
28 #include <cstdint>
29 #include <utility>
30 #include <vector>
31 
32 using namespace llvm;
33 
34 static cl::opt<bool> DumpRegUsage(
35     "print-regusage", cl::init(false), cl::Hidden,
36     cl::desc("print register usage details collected for analysis."));
37 
38 INITIALIZE_PASS(PhysicalRegisterUsageInfo, "reg-usage-info",
39                 "Register Usage Information Storage", false, true)
40 
41 char PhysicalRegisterUsageInfo::ID = 0;
42 
43 void PhysicalRegisterUsageInfo::setTargetMachine(const LLVMTargetMachine &TM) {
44   this->TM = &TM;
45 }
46 
47 bool PhysicalRegisterUsageInfo::doInitialization(Module &M) {
48   RegMasks.grow(M.size());
49   return false;
50 }
51 
52 bool PhysicalRegisterUsageInfo::doFinalization(Module &M) {
53   if (DumpRegUsage)
54     print(errs());
55 
56   RegMasks.shrink_and_clear();
57   return false;
58 }
59 
60 void PhysicalRegisterUsageInfo::storeUpdateRegUsageInfo(
61     const Function &FP, ArrayRef<uint32_t> RegMask) {
62   RegMasks[&FP] = RegMask;
63 }
64 
65 ArrayRef<uint32_t>
66 PhysicalRegisterUsageInfo::getRegUsageInfo(const Function &FP) {
67   auto It = RegMasks.find(&FP);
68   if (It != RegMasks.end())
69     return makeArrayRef<uint32_t>(It->second);
70   return ArrayRef<uint32_t>();
71 }
72 
73 void PhysicalRegisterUsageInfo::print(raw_ostream &OS, const Module *M) const {
74   using FuncPtrRegMaskPair = std::pair<const Function *, std::vector<uint32_t>>;
75 
76   SmallVector<const FuncPtrRegMaskPair *, 64> FPRMPairVector;
77 
78   // Create a vector of pointer to RegMasks entries
79   for (const auto &RegMask : RegMasks)
80     FPRMPairVector.push_back(&RegMask);
81 
82   // sort the vector to print analysis in alphabatic order of function name.
83   llvm::sort(
84       FPRMPairVector,
85       [](const FuncPtrRegMaskPair *A, const FuncPtrRegMaskPair *B) -> bool {
86         return A->first->getName() < B->first->getName();
87       });
88 
89   for (const FuncPtrRegMaskPair *FPRMPair : FPRMPairVector) {
90     OS << FPRMPair->first->getName() << " "
91        << "Clobbered Registers: ";
92     const TargetRegisterInfo *TRI
93         = TM->getSubtarget<TargetSubtargetInfo>(*(FPRMPair->first))
94           .getRegisterInfo();
95 
96     for (unsigned PReg = 1, PRegE = TRI->getNumRegs(); PReg < PRegE; ++PReg) {
97       if (MachineOperand::clobbersPhysReg(&(FPRMPair->second[0]), PReg))
98         OS << printReg(PReg, TRI) << " ";
99     }
100     OS << "\n";
101   }
102 }
103