1 //===- RegisterClassInfo.cpp - Dynamic Register Class Info ----------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the RegisterClassInfo class which provides dynamic
11 // information about target register classes. Callee-saved vs. caller-saved and
12 // reserved registers depend on calling conventions and other dynamic
13 // information, so some things cannot be determined statically.
14 //
15 //===----------------------------------------------------------------------===//
16 
17 #include "llvm/ADT/ArrayRef.h"
18 #include "llvm/ADT/BitVector.h"
19 #include "llvm/ADT/SmallVector.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
22 #include "llvm/CodeGen/RegisterClassInfo.h"
23 #include "llvm/MC/MCRegisterInfo.h"
24 #include "llvm/Support/CommandLine.h"
25 #include "llvm/Support/Debug.h"
26 #include "llvm/Support/raw_ostream.h"
27 #include "llvm/Target/TargetRegisterInfo.h"
28 #include "llvm/Target/TargetSubtargetInfo.h"
29 #include <algorithm>
30 #include <cassert>
31 #include <cstdint>
32 
33 using namespace llvm;
34 
35 #define DEBUG_TYPE "regalloc"
36 
37 static cl::opt<unsigned>
38 StressRA("stress-regalloc", cl::Hidden, cl::init(0), cl::value_desc("N"),
39          cl::desc("Limit all regclasses to N registers"));
40 
41 RegisterClassInfo::RegisterClassInfo() = default;
42 
43 void RegisterClassInfo::runOnMachineFunction(const MachineFunction &mf) {
44   bool Update = false;
45   MF = &mf;
46 
47   // Allocate new array the first time we see a new target.
48   if (MF->getSubtarget().getRegisterInfo() != TRI) {
49     TRI = MF->getSubtarget().getRegisterInfo();
50     RegClass.reset(new RCInfo[TRI->getNumRegClasses()]);
51     unsigned NumPSets = TRI->getNumRegPressureSets();
52     PSetLimits.reset(new unsigned[NumPSets]);
53     std::fill(&PSetLimits[0], &PSetLimits[NumPSets], 0);
54     Update = true;
55   }
56 
57   // Does this MF have different CSRs?
58   assert(TRI && "no register info set");
59   const MCPhysReg *CSR = TRI->getCalleeSavedRegs(MF);
60   if (Update || CSR != CalleeSaved) {
61     // Build a CSRNum map. Every CSR alias gets an entry pointing to the last
62     // overlapping CSR.
63     CSRNum.clear();
64     CSRNum.resize(TRI->getNumRegs(), 0);
65     for (unsigned N = 0; unsigned Reg = CSR[N]; ++N)
66       for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
67         CSRNum[*AI] = N + 1; // 0 means no CSR, 1 means CalleeSaved[0], ...
68     Update = true;
69   }
70   CalleeSaved = CSR;
71 
72   // Different reserved registers?
73   const BitVector &RR = MF->getRegInfo().getReservedRegs();
74   if (Reserved.size() != RR.size() || RR != Reserved) {
75     Update = true;
76     Reserved = RR;
77   }
78 
79   // Invalidate cached information from previous function.
80   if (Update)
81     ++Tag;
82 }
83 
84 /// compute - Compute the preferred allocation order for RC with reserved
85 /// registers filtered out. Volatile registers come first followed by CSR
86 /// aliases ordered according to the CSR order specified by the target.
87 void RegisterClassInfo::compute(const TargetRegisterClass *RC) const {
88   assert(RC && "no register class given");
89   RCInfo &RCI = RegClass[RC->getID()];
90 
91   // Raw register count, including all reserved regs.
92   unsigned NumRegs = RC->getNumRegs();
93 
94   if (!RCI.Order)
95     RCI.Order.reset(new MCPhysReg[NumRegs]);
96 
97   unsigned N = 0;
98   SmallVector<MCPhysReg, 16> CSRAlias;
99   unsigned MinCost = 0xff;
100   unsigned LastCost = ~0u;
101   unsigned LastCostChange = 0;
102 
103   // FIXME: Once targets reserve registers instead of removing them from the
104   // allocation order, we can simply use begin/end here.
105   ArrayRef<MCPhysReg> RawOrder = RC->getRawAllocationOrder(*MF);
106   for (unsigned i = 0; i != RawOrder.size(); ++i) {
107     unsigned PhysReg = RawOrder[i];
108     // Remove reserved registers from the allocation order.
109     if (Reserved.test(PhysReg))
110       continue;
111     unsigned Cost = TRI->getCostPerUse(PhysReg);
112     MinCost = std::min(MinCost, Cost);
113 
114     if (CSRNum[PhysReg])
115       // PhysReg aliases a CSR, save it for later.
116       CSRAlias.push_back(PhysReg);
117     else {
118       if (Cost != LastCost)
119         LastCostChange = N;
120       RCI.Order[N++] = PhysReg;
121       LastCost = Cost;
122     }
123   }
124   RCI.NumRegs = N + CSRAlias.size();
125   assert(RCI.NumRegs <= NumRegs && "Allocation order larger than regclass");
126 
127   // CSR aliases go after the volatile registers, preserve the target's order.
128   for (unsigned i = 0, e = CSRAlias.size(); i != e; ++i) {
129     unsigned PhysReg = CSRAlias[i];
130     unsigned Cost = TRI->getCostPerUse(PhysReg);
131     if (Cost != LastCost)
132       LastCostChange = N;
133     RCI.Order[N++] = PhysReg;
134     LastCost = Cost;
135   }
136 
137   // Register allocator stress test.  Clip register class to N registers.
138   if (StressRA && RCI.NumRegs > StressRA)
139     RCI.NumRegs = StressRA;
140 
141   // Check if RC is a proper sub-class.
142   if (const TargetRegisterClass *Super =
143           TRI->getLargestLegalSuperClass(RC, *MF))
144     if (Super != RC && getNumAllocatableRegs(Super) > RCI.NumRegs)
145       RCI.ProperSubClass = true;
146 
147   RCI.MinCost = uint8_t(MinCost);
148   RCI.LastCostChange = LastCostChange;
149 
150   DEBUG({
151     dbgs() << "AllocationOrder(" << TRI->getRegClassName(RC) << ") = [";
152     for (unsigned I = 0; I != RCI.NumRegs; ++I)
153       dbgs() << ' ' << PrintReg(RCI.Order[I], TRI);
154     dbgs() << (RCI.ProperSubClass ? " ] (sub-class)\n" : " ]\n");
155   });
156 
157   // RCI is now up-to-date.
158   RCI.Tag = Tag;
159 }
160 
161 /// This is not accurate because two overlapping register sets may have some
162 /// nonoverlapping reserved registers. However, computing the allocation order
163 /// for all register classes would be too expensive.
164 unsigned RegisterClassInfo::computePSetLimit(unsigned Idx) const {
165   const TargetRegisterClass *RC = nullptr;
166   unsigned NumRCUnits = 0;
167   for (const TargetRegisterClass *C : TRI->regclasses()) {
168     const int *PSetID = TRI->getRegClassPressureSets(C);
169     for (; *PSetID != -1; ++PSetID) {
170       if ((unsigned)*PSetID == Idx)
171         break;
172     }
173     if (*PSetID == -1)
174       continue;
175 
176     // Found a register class that counts against this pressure set.
177     // For efficiency, only compute the set order for the largest set.
178     unsigned NUnits = TRI->getRegClassWeight(C).WeightLimit;
179     if (!RC || NUnits > NumRCUnits) {
180       RC = C;
181       NumRCUnits = NUnits;
182     }
183   }
184   compute(RC);
185   unsigned NReserved = RC->getNumRegs() - getNumAllocatableRegs(RC);
186   return TRI->getRegPressureSetLimit(*MF, Idx) -
187          TRI->getRegClassWeight(RC).RegWeight * NReserved;
188 }
189