1 //===-- RegisterClassInfo.cpp - Dynamic Register Class Info ---------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the RegisterClassInfo class which provides dynamic
11 // information about target register classes. Callee saved and reserved
12 // registers depends on calling conventions and other dynamic information, so
13 // some things cannot be determined statically.
14 //
15 //===----------------------------------------------------------------------===//
16 
17 #define DEBUG_TYPE "regalloc"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/RegisterClassInfo.h"
20 #include "llvm/Target/TargetMachine.h"
21 #include "llvm/Support/CommandLine.h"
22 #include "llvm/Support/Debug.h"
23 #include "llvm/Support/raw_ostream.h"
24 
25 using namespace llvm;
26 
27 static cl::opt<unsigned>
28 StressRA("stress-regalloc", cl::Hidden, cl::init(0), cl::value_desc("N"),
29          cl::desc("Limit all regclasses to N registers"));
30 
31 RegisterClassInfo::RegisterClassInfo() : Tag(0), MF(0), TRI(0), CalleeSaved(0)
32 {}
33 
34 void RegisterClassInfo::runOnMachineFunction(const MachineFunction &mf) {
35   bool Update = false;
36   MF = &mf;
37 
38   // Allocate new array the first time we see a new target.
39   if (MF->getTarget().getRegisterInfo() != TRI) {
40     TRI = MF->getTarget().getRegisterInfo();
41     RegClass.reset(new RCInfo[TRI->getNumRegClasses()]);
42     Update = true;
43   }
44 
45   // Does this MF have different CSRs?
46   const uint16_t *CSR = TRI->getCalleeSavedRegs(MF);
47   if (Update || CSR != CalleeSaved) {
48     // Build a CSRNum map. Every CSR alias gets an entry pointing to the last
49     // overlapping CSR.
50     CSRNum.clear();
51     CSRNum.resize(TRI->getNumRegs(), 0);
52     for (unsigned N = 0; unsigned Reg = CSR[N]; ++N)
53       for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
54         CSRNum[*AI] = N + 1; // 0 means no CSR, 1 means CalleeSaved[0], ...
55     Update = true;
56   }
57   CalleeSaved = CSR;
58 
59   // Different reserved registers?
60   BitVector RR = TRI->getReservedRegs(*MF);
61   if (RR != Reserved)
62     Update = true;
63   Reserved = RR;
64 
65   // Invalidate cached information from previous function.
66   if (Update)
67     ++Tag;
68 }
69 
70 /// compute - Compute the preferred allocation order for RC with reserved
71 /// registers filtered out. Volatile registers come first followed by CSR
72 /// aliases ordered according to the CSR order specified by the target.
73 void RegisterClassInfo::compute(const TargetRegisterClass *RC) const {
74   RCInfo &RCI = RegClass[RC->getID()];
75 
76   // Raw register count, including all reserved regs.
77   unsigned NumRegs = RC->getNumRegs();
78 
79   if (!RCI.Order)
80     RCI.Order.reset(new unsigned[NumRegs]);
81 
82   unsigned N = 0;
83   SmallVector<unsigned, 16> CSRAlias;
84 
85   // FIXME: Once targets reserve registers instead of removing them from the
86   // allocation order, we can simply use begin/end here.
87   ArrayRef<uint16_t> RawOrder = RC->getRawAllocationOrder(*MF);
88   for (unsigned i = 0; i != RawOrder.size(); ++i) {
89     unsigned PhysReg = RawOrder[i];
90     // Remove reserved registers from the allocation order.
91     if (Reserved.test(PhysReg))
92       continue;
93     if (CSRNum[PhysReg])
94       // PhysReg aliases a CSR, save it for later.
95       CSRAlias.push_back(PhysReg);
96     else
97       RCI.Order[N++] = PhysReg;
98   }
99   RCI.NumRegs = N + CSRAlias.size();
100   assert (RCI.NumRegs <= NumRegs && "Allocation order larger than regclass");
101 
102   // CSR aliases go after the volatile registers, preserve the target's order.
103   std::copy(CSRAlias.begin(), CSRAlias.end(), &RCI.Order[N]);
104 
105   // Register allocator stress test.  Clip register class to N registers.
106   if (StressRA && RCI.NumRegs > StressRA)
107     RCI.NumRegs = StressRA;
108 
109   // Check if RC is a proper sub-class.
110   if (const TargetRegisterClass *Super = TRI->getLargestLegalSuperClass(RC))
111     if (Super != RC && getNumAllocatableRegs(Super) > RCI.NumRegs)
112       RCI.ProperSubClass = true;
113 
114   DEBUG({
115     dbgs() << "AllocationOrder(" << RC->getName() << ") = [";
116     for (unsigned I = 0; I != RCI.NumRegs; ++I)
117       dbgs() << ' ' << PrintReg(RCI.Order[I], TRI);
118     dbgs() << (RCI.ProperSubClass ? " ] (sub-class)\n" : " ]\n");
119   });
120 
121   // RCI is now up-to-date.
122   RCI.Tag = Tag;
123 }
124 
125