1 //===-- RegisterClassInfo.cpp - Dynamic Register Class Info ---------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the RegisterClassInfo class which provides dynamic
11 // information about target register classes. Callee saved and reserved
12 // registers depends on calling conventions and other dynamic information, so
13 // some things cannot be determined statically.
14 //
15 //===----------------------------------------------------------------------===//
16 
17 #include "RegisterClassInfo.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/Target/TargetMachine.h"
20 
21 using namespace llvm;
22 
23 RegisterClassInfo::RegisterClassInfo() : Tag(0), MF(0), TRI(0), CalleeSaved(0)
24 {}
25 
26 void RegisterClassInfo::runOnMachineFunction(const MachineFunction &mf) {
27   bool Update = false;
28   MF = &mf;
29 
30   // Allocate new array the first time we see a new target.
31   if (MF->getTarget().getRegisterInfo() != TRI) {
32     TRI = MF->getTarget().getRegisterInfo();
33     RegClass.reset(new RCInfo[TRI->getNumRegClasses()]);
34     Update = true;
35   }
36 
37   // Does this MF have different CSRs?
38   const unsigned *CSR = TRI->getCalleeSavedRegs(MF);
39   if (Update || CSR != CalleeSaved) {
40     // Build a CSRNum map. Every CSR alias gets an entry pointing to the last
41     // overlapping CSR.
42     CSRNum.clear();
43     CSRNum.resize(TRI->getNumRegs(), 0);
44     for (unsigned N = 0; unsigned Reg = CSR[N]; ++N)
45       for (const unsigned *AS = TRI->getOverlaps(Reg);
46            unsigned Alias = *AS; ++AS)
47         CSRNum[Alias] = N + 1; // 0 means no CSR, 1 means CalleeSaved[0], ...
48     Update = true;
49   }
50   CalleeSaved = CSR;
51 
52   // Different reserved registers?
53   BitVector RR = TRI->getReservedRegs(*MF);
54   if (RR != Reserved)
55     Update = true;
56   Reserved = RR;
57 
58   // Invalidate cached information from previous function.
59   if (Update)
60     ++Tag;
61 }
62 
63 /// compute - Compute the preferred allocation order for RC with reserved
64 /// registers filtered out. Volatile registers come first followed by CSR
65 /// aliases ordered according to the CSR order specified by the target.
66 void RegisterClassInfo::compute(const TargetRegisterClass *RC) const {
67   RCInfo &RCI = RegClass[RC->getID()];
68 
69   // Raw register count, including all reserved regs.
70   unsigned NumRegs = RC->getNumRegs();
71 
72   if (!RCI.Order)
73     RCI.Order.reset(new unsigned[NumRegs]);
74 
75   unsigned N = 0;
76   SmallVector<std::pair<unsigned, unsigned>, 8> CSRAlias;
77 
78   // FIXME: Once targets reserve registers instead of removing them from the
79   // allocation order, we can simply use begin/end here.
80   TargetRegisterClass::iterator AOB = RC->allocation_order_begin(*MF);
81   TargetRegisterClass::iterator AOE = RC->allocation_order_end(*MF);
82 
83   for (TargetRegisterClass::iterator I = AOB; I != AOE; ++I) {
84     unsigned PhysReg = *I;
85     // Remove reserved registers from the allocation order.
86     if (Reserved.test(PhysReg))
87       continue;
88     if (unsigned CSR = CSRNum[PhysReg])
89       // PhysReg aliases a CSR, save it for later.
90       CSRAlias.push_back(std::make_pair(CSR, PhysReg));
91     else
92       RCI.Order[N++] = PhysReg;
93   }
94   RCI.NumRegs = N + CSRAlias.size();
95   assert (RCI.NumRegs <= NumRegs && "Allocation order larger than regclass");
96 
97   // Sort CSR aliases acording to the CSR ordering.
98   if (CSRAlias.size() >= 2)
99     array_pod_sort(CSRAlias.begin(), CSRAlias.end());
100 
101   for (unsigned i = 0, e = CSRAlias.size(); i != e; ++i)
102       RCI.Order[N++] = CSRAlias[i].second;
103 
104   // RCI is now up-to-date.
105   RCI.Tag = Tag;
106 }
107 
108