1 //===-- RegUsageInfoCollector.cpp - Register Usage Information Collector --===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 ///
10 /// This pass is required to take advantage of the interprocedural register
11 /// allocation infrastructure.
12 ///
13 /// This pass is simple MachineFunction pass which collects register usage
14 /// details by iterating through each physical registers and checking
15 /// MRI::isPhysRegUsed() then creates a RegMask based on this details.
16 /// The pass then stores this RegMask in PhysicalRegisterUsageInfo.cpp
17 ///
18 //===----------------------------------------------------------------------===//
19 
20 #include "llvm/ADT/Statistic.h"
21 #include "llvm/CodeGen/MachineBasicBlock.h"
22 #include "llvm/CodeGen/MachineFunctionPass.h"
23 #include "llvm/CodeGen/MachineInstr.h"
24 #include "llvm/CodeGen/MachineOperand.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/Passes.h"
27 #include "llvm/CodeGen/RegisterUsageInfo.h"
28 #include "llvm/Support/Debug.h"
29 #include "llvm/Support/raw_ostream.h"
30 #include "llvm/CodeGen/TargetFrameLowering.h"
31 
32 using namespace llvm;
33 
34 #define DEBUG_TYPE "ip-regalloc"
35 
36 STATISTIC(NumCSROpt,
37           "Number of functions optimized for callee saved registers");
38 
39 namespace llvm {
40 void initializeRegUsageInfoCollectorPass(PassRegistry &);
41 }
42 
43 namespace {
44 class RegUsageInfoCollector : public MachineFunctionPass {
45 public:
46   RegUsageInfoCollector() : MachineFunctionPass(ID) {
47     PassRegistry &Registry = *PassRegistry::getPassRegistry();
48     initializeRegUsageInfoCollectorPass(Registry);
49   }
50 
51   StringRef getPassName() const override {
52     return "Register Usage Information Collector Pass";
53   }
54 
55   void getAnalysisUsage(AnalysisUsage &AU) const override;
56 
57   bool runOnMachineFunction(MachineFunction &MF) override;
58 
59   static char ID;
60 };
61 } // end of anonymous namespace
62 
63 char RegUsageInfoCollector::ID = 0;
64 
65 INITIALIZE_PASS_BEGIN(RegUsageInfoCollector, "RegUsageInfoCollector",
66                       "Register Usage Information Collector", false, false)
67 INITIALIZE_PASS_DEPENDENCY(PhysicalRegisterUsageInfo)
68 INITIALIZE_PASS_END(RegUsageInfoCollector, "RegUsageInfoCollector",
69                     "Register Usage Information Collector", false, false)
70 
71 FunctionPass *llvm::createRegUsageInfoCollector() {
72   return new RegUsageInfoCollector();
73 }
74 
75 void RegUsageInfoCollector::getAnalysisUsage(AnalysisUsage &AU) const {
76   AU.addRequired<PhysicalRegisterUsageInfo>();
77   AU.setPreservesAll();
78   MachineFunctionPass::getAnalysisUsage(AU);
79 }
80 
81 bool RegUsageInfoCollector::runOnMachineFunction(MachineFunction &MF) {
82   MachineRegisterInfo *MRI = &MF.getRegInfo();
83   const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
84   const TargetMachine &TM = MF.getTarget();
85 
86   LLVM_DEBUG(dbgs() << " -------------------- " << getPassName()
87                     << " -------------------- \n");
88   LLVM_DEBUG(dbgs() << "Function Name : " << MF.getName() << "\n");
89 
90   std::vector<uint32_t> RegMask;
91 
92   // Compute the size of the bit vector to represent all the registers.
93   // The bit vector is broken into 32-bit chunks, thus takes the ceil of
94   // the number of registers divided by 32 for the size.
95   unsigned RegMaskSize = (TRI->getNumRegs() + 31) / 32;
96   RegMask.resize(RegMaskSize, 0xFFFFFFFF);
97 
98   const Function &F = MF.getFunction();
99 
100   PhysicalRegisterUsageInfo *PRUI = &getAnalysis<PhysicalRegisterUsageInfo>();
101 
102   PRUI->setTargetMachine(&TM);
103 
104   LLVM_DEBUG(dbgs() << "Clobbered Registers: ");
105 
106   const BitVector &UsedPhysRegsMask = MRI->getUsedPhysRegsMask();
107   auto SetRegAsDefined = [&RegMask] (unsigned Reg) {
108     RegMask[Reg / 32] &= ~(1u << Reg % 32);
109   };
110   // Scan all the physical registers. When a register is defined in the current
111   // function set it and all the aliasing registers as defined in the regmask.
112   for (unsigned PReg = 1, PRegE = TRI->getNumRegs(); PReg < PRegE; ++PReg) {
113     // If a register is defined by an instruction mark it as defined together
114     // with all it's aliases.
115     if (!MRI->def_empty(PReg)) {
116       for (MCRegAliasIterator AI(PReg, TRI, true); AI.isValid(); ++AI)
117         SetRegAsDefined(*AI);
118       continue;
119     }
120     // If a register is in the UsedPhysRegsMask set then mark it as defined.
121     // All clobbered aliases will also be in the set, so we can skip setting
122     // as defined all the aliases here.
123     if (UsedPhysRegsMask.test(PReg))
124       SetRegAsDefined(PReg);
125   }
126 
127   if (!TargetFrameLowering::isSafeForNoCSROpt(F)) {
128     const uint32_t *CallPreservedMask =
129         TRI->getCallPreservedMask(MF, F.getCallingConv());
130     if (CallPreservedMask) {
131       // Set callee saved register as preserved.
132       for (unsigned i = 0; i < RegMaskSize; ++i)
133         RegMask[i] = RegMask[i] | CallPreservedMask[i];
134     }
135   } else {
136     ++NumCSROpt;
137     LLVM_DEBUG(dbgs() << MF.getName()
138                       << " function optimized for not having CSR.\n");
139   }
140 
141   for (unsigned PReg = 1, PRegE = TRI->getNumRegs(); PReg < PRegE; ++PReg)
142     if (MachineOperand::clobbersPhysReg(&(RegMask[0]), PReg))
143       LLVM_DEBUG(dbgs() << printReg(PReg, TRI) << " ");
144 
145   LLVM_DEBUG(dbgs() << " \n----------------------------------------\n");
146 
147   PRUI->storeUpdateRegUsageInfo(&F, std::move(RegMask));
148 
149   return false;
150 }
151