1 //===-- RegUsageInfoCollector.cpp - Register Usage Information Collector --===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 ///
9 /// This pass is required to take advantage of the interprocedural register
10 /// allocation infrastructure.
11 ///
12 /// This pass is simple MachineFunction pass which collects register usage
13 /// details by iterating through each physical registers and checking
14 /// MRI::isPhysRegUsed() then creates a RegMask based on this details.
15 /// The pass then stores this RegMask in PhysicalRegisterUsageInfo.cpp
16 ///
17 //===----------------------------------------------------------------------===//
18 
19 #include "llvm/ADT/Statistic.h"
20 #include "llvm/CodeGen/MachineBasicBlock.h"
21 #include "llvm/CodeGen/MachineFunctionPass.h"
22 #include "llvm/CodeGen/MachineInstr.h"
23 #include "llvm/CodeGen/MachineOperand.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/Passes.h"
26 #include "llvm/CodeGen/RegisterUsageInfo.h"
27 #include "llvm/Support/Debug.h"
28 #include "llvm/Support/raw_ostream.h"
29 #include "llvm/CodeGen/TargetFrameLowering.h"
30 
31 using namespace llvm;
32 
33 #define DEBUG_TYPE "ip-regalloc"
34 
35 STATISTIC(NumCSROpt,
36           "Number of functions optimized for callee saved registers");
37 
38 namespace {
39 
40 class RegUsageInfoCollector : public MachineFunctionPass {
41 public:
42   RegUsageInfoCollector() : MachineFunctionPass(ID) {
43     PassRegistry &Registry = *PassRegistry::getPassRegistry();
44     initializeRegUsageInfoCollectorPass(Registry);
45   }
46 
47   StringRef getPassName() const override {
48     return "Register Usage Information Collector Pass";
49   }
50 
51   void getAnalysisUsage(AnalysisUsage &AU) const override {
52     AU.addRequired<PhysicalRegisterUsageInfo>();
53     AU.setPreservesAll();
54     MachineFunctionPass::getAnalysisUsage(AU);
55   }
56 
57   bool runOnMachineFunction(MachineFunction &MF) override;
58 
59   // Call determineCalleeSaves and then also set the bits for subregs and
60   // fully saved superregs.
61   static void computeCalleeSavedRegs(BitVector &SavedRegs, MachineFunction &MF);
62 
63   static char ID;
64 };
65 
66 } // end of anonymous namespace
67 
68 char RegUsageInfoCollector::ID = 0;
69 
70 INITIALIZE_PASS_BEGIN(RegUsageInfoCollector, "RegUsageInfoCollector",
71                       "Register Usage Information Collector", false, false)
72 INITIALIZE_PASS_DEPENDENCY(PhysicalRegisterUsageInfo)
73 INITIALIZE_PASS_END(RegUsageInfoCollector, "RegUsageInfoCollector",
74                     "Register Usage Information Collector", false, false)
75 
76 FunctionPass *llvm::createRegUsageInfoCollector() {
77   return new RegUsageInfoCollector();
78 }
79 
80 bool RegUsageInfoCollector::runOnMachineFunction(MachineFunction &MF) {
81   MachineRegisterInfo *MRI = &MF.getRegInfo();
82   const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
83   const LLVMTargetMachine &TM = MF.getTarget();
84 
85   LLVM_DEBUG(dbgs() << " -------------------- " << getPassName()
86                     << " -------------------- \n");
87   LLVM_DEBUG(dbgs() << "Function Name : " << MF.getName() << "\n");
88 
89   std::vector<uint32_t> RegMask;
90 
91   // Compute the size of the bit vector to represent all the registers.
92   // The bit vector is broken into 32-bit chunks, thus takes the ceil of
93   // the number of registers divided by 32 for the size.
94   unsigned RegMaskSize = MachineOperand::getRegMaskSize(TRI->getNumRegs());
95   RegMask.resize(RegMaskSize, ~((uint32_t)0));
96 
97   const Function &F = MF.getFunction();
98 
99   PhysicalRegisterUsageInfo &PRUI = getAnalysis<PhysicalRegisterUsageInfo>();
100   PRUI.setTargetMachine(TM);
101 
102   LLVM_DEBUG(dbgs() << "Clobbered Registers: ");
103 
104   BitVector SavedRegs;
105   computeCalleeSavedRegs(SavedRegs, MF);
106 
107   const BitVector &UsedPhysRegsMask = MRI->getUsedPhysRegsMask();
108   auto SetRegAsDefined = [&RegMask] (unsigned Reg) {
109     RegMask[Reg / 32] &= ~(1u << Reg % 32);
110   };
111   // Scan all the physical registers. When a register is defined in the current
112   // function set it and all the aliasing registers as defined in the regmask.
113   for (unsigned PReg = 1, PRegE = TRI->getNumRegs(); PReg < PRegE; ++PReg) {
114     // Don't count registers that are saved and restored.
115     if (SavedRegs.test(PReg))
116       continue;
117     // If a register is defined by an instruction mark it as defined together
118     // with all it's unsaved aliases.
119     if (!MRI->def_empty(PReg)) {
120       for (MCRegAliasIterator AI(PReg, TRI, true); AI.isValid(); ++AI)
121         if (!SavedRegs.test(*AI))
122           SetRegAsDefined(*AI);
123       continue;
124     }
125     // If a register is in the UsedPhysRegsMask set then mark it as defined.
126     // All clobbered aliases will also be in the set, so we can skip setting
127     // as defined all the aliases here.
128     if (UsedPhysRegsMask.test(PReg))
129       SetRegAsDefined(PReg);
130   }
131 
132   if (TargetFrameLowering::isSafeForNoCSROpt(F)) {
133     ++NumCSROpt;
134     LLVM_DEBUG(dbgs() << MF.getName()
135                       << " function optimized for not having CSR.\n");
136   }
137 
138   for (unsigned PReg = 1, PRegE = TRI->getNumRegs(); PReg < PRegE; ++PReg)
139     if (MachineOperand::clobbersPhysReg(&(RegMask[0]), PReg))
140       LLVM_DEBUG(dbgs() << printReg(PReg, TRI) << " ");
141 
142   LLVM_DEBUG(dbgs() << " \n----------------------------------------\n");
143 
144   PRUI.storeUpdateRegUsageInfo(F, RegMask);
145 
146   return false;
147 }
148 
149 void RegUsageInfoCollector::
150 computeCalleeSavedRegs(BitVector &SavedRegs, MachineFunction &MF) {
151   const TargetFrameLowering &TFI = *MF.getSubtarget().getFrameLowering();
152   const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
153 
154   // Target will return the set of registers that it saves/restores as needed.
155   SavedRegs.clear();
156   TFI.determineCalleeSaves(MF, SavedRegs);
157 
158   // Insert subregs.
159   const MCPhysReg *CSRegs = TRI.getCalleeSavedRegs(&MF);
160   for (unsigned i = 0; CSRegs[i]; ++i) {
161     unsigned Reg = CSRegs[i];
162     if (SavedRegs.test(Reg))
163       for (MCSubRegIterator SR(Reg, &TRI, false); SR.isValid(); ++SR)
164         SavedRegs.set(*SR);
165   }
166 
167   // Insert any register fully saved via subregisters.
168   for (const TargetRegisterClass *RC : TRI.regclasses()) {
169     if (!RC->CoveredBySubRegs)
170        continue;
171 
172     for (unsigned PReg = 1, PRegE = TRI.getNumRegs(); PReg < PRegE; ++PReg) {
173       if (SavedRegs.test(PReg))
174         continue;
175 
176       // Check if PReg is fully covered by its subregs.
177       if (!RC->contains(PReg))
178         continue;
179 
180       // Add PReg to SavedRegs if all subregs are saved.
181       bool AllSubRegsSaved = true;
182       for (MCSubRegIterator SR(PReg, &TRI, false); SR.isValid(); ++SR)
183         if (!SavedRegs.test(*SR)) {
184           AllSubRegsSaved = false;
185           break;
186         }
187       if (AllSubRegsSaved)
188         SavedRegs.set(PReg);
189     }
190   }
191 }
192