1 //===-- RegAllocBase.cpp - Register Allocator Base Class ------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the RegAllocBase class which provides common functionality
11 // for LiveIntervalUnion-based register allocators.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "RegAllocBase.h"
16 #include "Spiller.h"
17 #include "llvm/ADT/Statistic.h"
18 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
19 #include "llvm/CodeGen/LiveRangeEdit.h"
20 #include "llvm/CodeGen/LiveRegMatrix.h"
21 #include "llvm/CodeGen/MachineInstr.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/CodeGen/VirtRegMap.h"
24 #include "llvm/Target/TargetRegisterInfo.h"
25 #ifndef NDEBUG
26 #include "llvm/ADT/SparseBitVector.h"
27 #endif
28 #include "llvm/Support/CommandLine.h"
29 #include "llvm/Support/Debug.h"
30 #include "llvm/Support/ErrorHandling.h"
31 #include "llvm/Support/raw_ostream.h"
32 #include "llvm/Support/Timer.h"
33 
34 using namespace llvm;
35 
36 #define DEBUG_TYPE "regalloc"
37 
38 STATISTIC(NumNewQueued    , "Number of new live ranges queued");
39 
40 // Temporary verification option until we can put verification inside
41 // MachineVerifier.
42 static cl::opt<bool, true>
43 VerifyRegAlloc("verify-regalloc", cl::location(RegAllocBase::VerifyEnabled),
44                cl::desc("Verify during register allocation"));
45 
46 const char RegAllocBase::TimerGroupName[] = "Register Allocation";
47 bool RegAllocBase::VerifyEnabled = false;
48 
49 //===----------------------------------------------------------------------===//
50 //                         RegAllocBase Implementation
51 //===----------------------------------------------------------------------===//
52 
53 // Pin the vtable to this file.
54 void RegAllocBase::anchor() {}
55 
56 void RegAllocBase::init(VirtRegMap &vrm,
57                         LiveIntervals &lis,
58                         LiveRegMatrix &mat) {
59   TRI = &vrm.getTargetRegInfo();
60   MRI = &vrm.getRegInfo();
61   VRM = &vrm;
62   LIS = &lis;
63   Matrix = &mat;
64   MRI->freezeReservedRegs(vrm.getMachineFunction());
65   RegClassInfo.runOnMachineFunction(vrm.getMachineFunction());
66 }
67 
68 // Visit all the live registers. If they are already assigned to a physical
69 // register, unify them with the corresponding LiveIntervalUnion, otherwise push
70 // them on the priority queue for later assignment.
71 void RegAllocBase::seedLiveRegs() {
72   NamedRegionTimer T("Seed Live Regs", TimerGroupName, TimePassesIsEnabled);
73   for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
74     unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
75     if (MRI->reg_nodbg_empty(Reg))
76       continue;
77     enqueue(&LIS->getInterval(Reg));
78   }
79 }
80 
81 // Top-level driver to manage the queue of unassigned VirtRegs and call the
82 // selectOrSplit implementation.
83 void RegAllocBase::allocatePhysRegs() {
84   seedLiveRegs();
85 
86   // Continue assigning vregs one at a time to available physical registers.
87   while (LiveInterval *VirtReg = dequeue()) {
88     assert(!VRM->hasPhys(VirtReg->reg) && "Register already assigned");
89 
90     // Unused registers can appear when the spiller coalesces snippets.
91     if (MRI->reg_nodbg_empty(VirtReg->reg)) {
92       DEBUG(dbgs() << "Dropping unused " << *VirtReg << '\n');
93       LIS->removeInterval(VirtReg->reg);
94       continue;
95     }
96 
97     // Invalidate all interference queries, live ranges could have changed.
98     Matrix->invalidateVirtRegs();
99 
100     // selectOrSplit requests the allocator to return an available physical
101     // register if possible and populate a list of new live intervals that
102     // result from splitting.
103     DEBUG(dbgs() << "\nselectOrSplit "
104           << MRI->getRegClass(VirtReg->reg)->getName()
105           << ':' << *VirtReg << " w=" << VirtReg->weight << '\n');
106     typedef SmallVector<unsigned, 4> VirtRegVec;
107     VirtRegVec SplitVRegs;
108     unsigned AvailablePhysReg = selectOrSplit(*VirtReg, SplitVRegs);
109 
110     if (AvailablePhysReg == ~0u) {
111       // selectOrSplit failed to find a register!
112       // Probably caused by an inline asm.
113       MachineInstr *MI = nullptr;
114       for (MachineRegisterInfo::reg_instr_iterator
115            I = MRI->reg_instr_begin(VirtReg->reg), E = MRI->reg_instr_end();
116            I != E; ) {
117         MachineInstr *TmpMI = &*(I++);
118         if (TmpMI->isInlineAsm()) {
119           MI = TmpMI;
120           break;
121         }
122       }
123       if (MI)
124         MI->emitError("inline assembly requires more registers than available");
125       else
126         report_fatal_error("ran out of registers during register allocation");
127       // Keep going after reporting the error.
128       VRM->assignVirt2Phys(VirtReg->reg,
129                  RegClassInfo.getOrder(MRI->getRegClass(VirtReg->reg)).front());
130       continue;
131     }
132 
133     if (AvailablePhysReg)
134       Matrix->assign(*VirtReg, AvailablePhysReg);
135 
136     for (VirtRegVec::iterator I = SplitVRegs.begin(), E = SplitVRegs.end();
137          I != E; ++I) {
138       LiveInterval *SplitVirtReg = &LIS->getInterval(*I);
139       assert(!VRM->hasPhys(SplitVirtReg->reg) && "Register already assigned");
140       if (MRI->reg_nodbg_empty(SplitVirtReg->reg)) {
141         DEBUG(dbgs() << "not queueing unused  " << *SplitVirtReg << '\n');
142         LIS->removeInterval(SplitVirtReg->reg);
143         continue;
144       }
145       DEBUG(dbgs() << "queuing new interval: " << *SplitVirtReg << "\n");
146       assert(TargetRegisterInfo::isVirtualRegister(SplitVirtReg->reg) &&
147              "expect split value in virtual register");
148       enqueue(SplitVirtReg);
149       ++NumNewQueued;
150     }
151   }
152 }
153