1 //===-- RegAllocBase.cpp - Register Allocator Base Class ------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the RegAllocBase class which provides common functionality
11 // for LiveIntervalUnion-based register allocators.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "RegAllocBase.h"
16 #include "Spiller.h"
17 #include "llvm/ADT/Statistic.h"
18 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
19 #include "llvm/CodeGen/LiveRangeEdit.h"
20 #include "llvm/CodeGen/LiveRegMatrix.h"
21 #include "llvm/CodeGen/MachineInstr.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/CodeGen/VirtRegMap.h"
24 #include "llvm/Target/TargetRegisterInfo.h"
25 #include "llvm/Support/CommandLine.h"
26 #include "llvm/Support/Debug.h"
27 #include "llvm/Support/raw_ostream.h"
28 #include "llvm/Support/ErrorHandling.h"
29 #include "llvm/Support/raw_ostream.h"
30 #include "llvm/Support/Timer.h"
31 
32 using namespace llvm;
33 
34 #define DEBUG_TYPE "regalloc"
35 
36 STATISTIC(NumNewQueued    , "Number of new live ranges queued");
37 
38 // Temporary verification option until we can put verification inside
39 // MachineVerifier.
40 static cl::opt<bool, true>
41 VerifyRegAlloc("verify-regalloc", cl::location(RegAllocBase::VerifyEnabled),
42                cl::desc("Verify during register allocation"));
43 
44 const char RegAllocBase::TimerGroupName[] = "regalloc";
45 const char RegAllocBase::TimerGroupDescription[] = "Register Allocation";
46 bool RegAllocBase::VerifyEnabled = false;
47 
48 //===----------------------------------------------------------------------===//
49 //                         RegAllocBase Implementation
50 //===----------------------------------------------------------------------===//
51 
52 // Pin the vtable to this file.
53 void RegAllocBase::anchor() {}
54 
55 void RegAllocBase::init(VirtRegMap &vrm,
56                         LiveIntervals &lis,
57                         LiveRegMatrix &mat) {
58   TRI = &vrm.getTargetRegInfo();
59   MRI = &vrm.getRegInfo();
60   VRM = &vrm;
61   LIS = &lis;
62   Matrix = &mat;
63   MRI->freezeReservedRegs(vrm.getMachineFunction());
64   RegClassInfo.runOnMachineFunction(vrm.getMachineFunction());
65 }
66 
67 // Visit all the live registers. If they are already assigned to a physical
68 // register, unify them with the corresponding LiveIntervalUnion, otherwise push
69 // them on the priority queue for later assignment.
70 void RegAllocBase::seedLiveRegs() {
71   NamedRegionTimer T("seed", "Seed Live Regs", TimerGroupName,
72                      TimerGroupDescription, TimePassesIsEnabled);
73   for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
74     unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
75     if (MRI->reg_nodbg_empty(Reg))
76       continue;
77     enqueue(&LIS->getInterval(Reg));
78   }
79 }
80 
81 // Top-level driver to manage the queue of unassigned VirtRegs and call the
82 // selectOrSplit implementation.
83 void RegAllocBase::allocatePhysRegs() {
84   seedLiveRegs();
85 
86   // Continue assigning vregs one at a time to available physical registers.
87   while (LiveInterval *VirtReg = dequeue()) {
88     assert(!VRM->hasPhys(VirtReg->reg) && "Register already assigned");
89 
90     // Unused registers can appear when the spiller coalesces snippets.
91     if (MRI->reg_nodbg_empty(VirtReg->reg)) {
92       DEBUG(dbgs() << "Dropping unused " << *VirtReg << '\n');
93       aboutToRemoveInterval(*VirtReg);
94       LIS->removeInterval(VirtReg->reg);
95       continue;
96     }
97 
98     // Invalidate all interference queries, live ranges could have changed.
99     Matrix->invalidateVirtRegs();
100 
101     // selectOrSplit requests the allocator to return an available physical
102     // register if possible and populate a list of new live intervals that
103     // result from splitting.
104     DEBUG(dbgs() << "\nselectOrSplit "
105           << TRI->getRegClassName(MRI->getRegClass(VirtReg->reg))
106           << ':' << *VirtReg << " w=" << VirtReg->weight << '\n');
107     typedef SmallVector<unsigned, 4> VirtRegVec;
108     VirtRegVec SplitVRegs;
109     unsigned AvailablePhysReg = selectOrSplit(*VirtReg, SplitVRegs);
110 
111     if (AvailablePhysReg == ~0u) {
112       // selectOrSplit failed to find a register!
113       // Probably caused by an inline asm.
114       MachineInstr *MI = nullptr;
115       for (MachineRegisterInfo::reg_instr_iterator
116            I = MRI->reg_instr_begin(VirtReg->reg), E = MRI->reg_instr_end();
117            I != E; ) {
118         MachineInstr *TmpMI = &*(I++);
119         if (TmpMI->isInlineAsm()) {
120           MI = TmpMI;
121           break;
122         }
123       }
124       if (MI)
125         MI->emitError("inline assembly requires more registers than available");
126       else
127         report_fatal_error("ran out of registers during register allocation");
128       // Keep going after reporting the error.
129       VRM->assignVirt2Phys(VirtReg->reg,
130                  RegClassInfo.getOrder(MRI->getRegClass(VirtReg->reg)).front());
131       continue;
132     }
133 
134     if (AvailablePhysReg)
135       Matrix->assign(*VirtReg, AvailablePhysReg);
136 
137     for (VirtRegVec::iterator I = SplitVRegs.begin(), E = SplitVRegs.end();
138          I != E; ++I) {
139       LiveInterval *SplitVirtReg = &LIS->getInterval(*I);
140       assert(!VRM->hasPhys(SplitVirtReg->reg) && "Register already assigned");
141       if (MRI->reg_nodbg_empty(SplitVirtReg->reg)) {
142         DEBUG(dbgs() << "not queueing unused  " << *SplitVirtReg << '\n');
143         aboutToRemoveInterval(*SplitVirtReg);
144         LIS->removeInterval(SplitVirtReg->reg);
145         continue;
146       }
147       DEBUG(dbgs() << "queuing new interval: " << *SplitVirtReg << "\n");
148       assert(!SplitVirtReg->empty() && "expecting non-empty interval");
149       assert(TargetRegisterInfo::isVirtualRegister(SplitVirtReg->reg) &&
150              "expect split value in virtual register");
151       enqueue(SplitVirtReg);
152       ++NumNewQueued;
153     }
154   }
155 }
156 
157 void RegAllocBase::postOptimization() {
158   spiller().postOptimization();
159   for (auto DeadInst : DeadRemats) {
160     LIS->RemoveMachineInstrFromMaps(*DeadInst);
161     DeadInst->eraseFromParent();
162   }
163   DeadRemats.clear();
164 }
165