1 //===- RegAllocBase.cpp - Register Allocator Base Class -------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the RegAllocBase class which provides common functionality
10 // for LiveIntervalUnion-based register allocators.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "RegAllocBase.h"
15 #include "Spiller.h"
16 #include "llvm/ADT/SmallVector.h"
17 #include "llvm/ADT/Statistic.h"
18 #include "llvm/CodeGen/LiveInterval.h"
19 #include "llvm/CodeGen/LiveIntervals.h"
20 #include "llvm/CodeGen/LiveRegMatrix.h"
21 #include "llvm/CodeGen/MachineInstr.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/CodeGen/TargetRegisterInfo.h"
24 #include "llvm/CodeGen/VirtRegMap.h"
25 #include "llvm/Pass.h"
26 #include "llvm/Support/CommandLine.h"
27 #include "llvm/Support/Debug.h"
28 #include "llvm/Support/ErrorHandling.h"
29 #include "llvm/Support/Timer.h"
30 #include "llvm/Support/raw_ostream.h"
31 #include <cassert>
32 
33 using namespace llvm;
34 
35 #define DEBUG_TYPE "regalloc"
36 
37 STATISTIC(NumNewQueued    , "Number of new live ranges queued");
38 
39 // Temporary verification option until we can put verification inside
40 // MachineVerifier.
41 static cl::opt<bool, true>
42     VerifyRegAlloc("verify-regalloc", cl::location(RegAllocBase::VerifyEnabled),
43                    cl::Hidden, cl::desc("Verify during register allocation"));
44 
45 const char RegAllocBase::TimerGroupName[] = "regalloc";
46 const char RegAllocBase::TimerGroupDescription[] = "Register Allocation";
47 bool RegAllocBase::VerifyEnabled = false;
48 
49 //===----------------------------------------------------------------------===//
50 //                         RegAllocBase Implementation
51 //===----------------------------------------------------------------------===//
52 
53 // Pin the vtable to this file.
54 void RegAllocBase::anchor() {}
55 
56 void RegAllocBase::init(VirtRegMap &vrm,
57                         LiveIntervals &lis,
58                         LiveRegMatrix &mat) {
59   TRI = &vrm.getTargetRegInfo();
60   MRI = &vrm.getRegInfo();
61   VRM = &vrm;
62   LIS = &lis;
63   Matrix = &mat;
64   MRI->freezeReservedRegs(vrm.getMachineFunction());
65   RegClassInfo.runOnMachineFunction(vrm.getMachineFunction());
66 }
67 
68 // Visit all the live registers. If they are already assigned to a physical
69 // register, unify them with the corresponding LiveIntervalUnion, otherwise push
70 // them on the priority queue for later assignment.
71 void RegAllocBase::seedLiveRegs() {
72   NamedRegionTimer T("seed", "Seed Live Regs", TimerGroupName,
73                      TimerGroupDescription, TimePassesIsEnabled);
74   for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
75     unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
76     if (MRI->reg_nodbg_empty(Reg))
77       continue;
78     enqueue(&LIS->getInterval(Reg));
79   }
80 }
81 
82 // Top-level driver to manage the queue of unassigned VirtRegs and call the
83 // selectOrSplit implementation.
84 void RegAllocBase::allocatePhysRegs() {
85   seedLiveRegs();
86 
87   // Continue assigning vregs one at a time to available physical registers.
88   while (LiveInterval *VirtReg = dequeue()) {
89     assert(!VRM->hasPhys(VirtReg->reg) && "Register already assigned");
90 
91     // Unused registers can appear when the spiller coalesces snippets.
92     if (MRI->reg_nodbg_empty(VirtReg->reg)) {
93       LLVM_DEBUG(dbgs() << "Dropping unused " << *VirtReg << '\n');
94       aboutToRemoveInterval(*VirtReg);
95       LIS->removeInterval(VirtReg->reg);
96       continue;
97     }
98 
99     // Invalidate all interference queries, live ranges could have changed.
100     Matrix->invalidateVirtRegs();
101 
102     // selectOrSplit requests the allocator to return an available physical
103     // register if possible and populate a list of new live intervals that
104     // result from splitting.
105     LLVM_DEBUG(dbgs() << "\nselectOrSplit "
106                       << TRI->getRegClassName(MRI->getRegClass(VirtReg->reg))
107                       << ':' << *VirtReg << " w=" << VirtReg->weight << '\n');
108 
109     using VirtRegVec = SmallVector<unsigned, 4>;
110 
111     VirtRegVec SplitVRegs;
112     unsigned AvailablePhysReg = selectOrSplit(*VirtReg, SplitVRegs);
113 
114     if (AvailablePhysReg == ~0u) {
115       // selectOrSplit failed to find a register!
116       // Probably caused by an inline asm.
117       MachineInstr *MI = nullptr;
118       for (MachineRegisterInfo::reg_instr_iterator
119            I = MRI->reg_instr_begin(VirtReg->reg), E = MRI->reg_instr_end();
120            I != E; ) {
121         MachineInstr *TmpMI = &*(I++);
122         if (TmpMI->isInlineAsm()) {
123           MI = TmpMI;
124           break;
125         }
126       }
127       if (MI)
128         MI->emitError("inline assembly requires more registers than available");
129       else
130         report_fatal_error("ran out of registers during register allocation");
131       // Keep going after reporting the error.
132       VRM->assignVirt2Phys(VirtReg->reg,
133                  RegClassInfo.getOrder(MRI->getRegClass(VirtReg->reg)).front());
134       continue;
135     }
136 
137     if (AvailablePhysReg)
138       Matrix->assign(*VirtReg, AvailablePhysReg);
139 
140     for (unsigned Reg : SplitVRegs) {
141       assert(LIS->hasInterval(Reg));
142 
143       LiveInterval *SplitVirtReg = &LIS->getInterval(Reg);
144       assert(!VRM->hasPhys(SplitVirtReg->reg) && "Register already assigned");
145       if (MRI->reg_nodbg_empty(SplitVirtReg->reg)) {
146         assert(SplitVirtReg->empty() && "Non-empty but used interval");
147         LLVM_DEBUG(dbgs() << "not queueing unused  " << *SplitVirtReg << '\n');
148         aboutToRemoveInterval(*SplitVirtReg);
149         LIS->removeInterval(SplitVirtReg->reg);
150         continue;
151       }
152       LLVM_DEBUG(dbgs() << "queuing new interval: " << *SplitVirtReg << "\n");
153       assert(TargetRegisterInfo::isVirtualRegister(SplitVirtReg->reg) &&
154              "expect split value in virtual register");
155       enqueue(SplitVirtReg);
156       ++NumNewQueued;
157     }
158   }
159 }
160 
161 void RegAllocBase::postOptimization() {
162   spiller().postOptimization();
163   for (auto DeadInst : DeadRemats) {
164     LIS->RemoveMachineInstrFromMaps(*DeadInst);
165     DeadInst->eraseFromParent();
166   }
167   DeadRemats.clear();
168 }
169