1 //===-- RegAllocBase.cpp - Register Allocator Base Class ------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the RegAllocBase class which provides common functionality
11 // for LiveIntervalUnion-based register allocators.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "RegAllocBase.h"
16 #include "Spiller.h"
17 #include "llvm/ADT/Statistic.h"
18 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
19 #include "llvm/CodeGen/LiveRangeEdit.h"
20 #include "llvm/CodeGen/LiveRegMatrix.h"
21 #include "llvm/CodeGen/MachineInstr.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/CodeGen/VirtRegMap.h"
24 #include "llvm/Support/CommandLine.h"
25 #include "llvm/Support/Debug.h"
26 #include "llvm/Support/ErrorHandling.h"
27 #include "llvm/Support/Timer.h"
28 #include "llvm/Support/raw_ostream.h"
29 #include "llvm/Target/TargetRegisterInfo.h"
30 
31 using namespace llvm;
32 
33 #define DEBUG_TYPE "regalloc"
34 
35 STATISTIC(NumNewQueued    , "Number of new live ranges queued");
36 
37 // Temporary verification option until we can put verification inside
38 // MachineVerifier.
39 static cl::opt<bool, true>
40 VerifyRegAlloc("verify-regalloc", cl::location(RegAllocBase::VerifyEnabled),
41                cl::desc("Verify during register allocation"));
42 
43 const char RegAllocBase::TimerGroupName[] = "regalloc";
44 const char RegAllocBase::TimerGroupDescription[] = "Register Allocation";
45 bool RegAllocBase::VerifyEnabled = false;
46 
47 //===----------------------------------------------------------------------===//
48 //                         RegAllocBase Implementation
49 //===----------------------------------------------------------------------===//
50 
51 // Pin the vtable to this file.
52 void RegAllocBase::anchor() {}
53 
54 void RegAllocBase::init(VirtRegMap &vrm,
55                         LiveIntervals &lis,
56                         LiveRegMatrix &mat) {
57   TRI = &vrm.getTargetRegInfo();
58   MRI = &vrm.getRegInfo();
59   VRM = &vrm;
60   LIS = &lis;
61   Matrix = &mat;
62   MRI->freezeReservedRegs(vrm.getMachineFunction());
63   RegClassInfo.runOnMachineFunction(vrm.getMachineFunction());
64 }
65 
66 // Visit all the live registers. If they are already assigned to a physical
67 // register, unify them with the corresponding LiveIntervalUnion, otherwise push
68 // them on the priority queue for later assignment.
69 void RegAllocBase::seedLiveRegs() {
70   NamedRegionTimer T("seed", "Seed Live Regs", TimerGroupName,
71                      TimerGroupDescription, TimePassesIsEnabled);
72   for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
73     unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
74     if (MRI->reg_nodbg_empty(Reg))
75       continue;
76     enqueue(&LIS->getInterval(Reg));
77   }
78 }
79 
80 // Top-level driver to manage the queue of unassigned VirtRegs and call the
81 // selectOrSplit implementation.
82 void RegAllocBase::allocatePhysRegs() {
83   seedLiveRegs();
84 
85   // Continue assigning vregs one at a time to available physical registers.
86   while (LiveInterval *VirtReg = dequeue()) {
87     assert(!VRM->hasPhys(VirtReg->reg) && "Register already assigned");
88 
89     // Unused registers can appear when the spiller coalesces snippets.
90     if (MRI->reg_nodbg_empty(VirtReg->reg)) {
91       DEBUG(dbgs() << "Dropping unused " << *VirtReg << '\n');
92       aboutToRemoveInterval(*VirtReg);
93       LIS->removeInterval(VirtReg->reg);
94       continue;
95     }
96 
97     // Invalidate all interference queries, live ranges could have changed.
98     Matrix->invalidateVirtRegs();
99 
100     // selectOrSplit requests the allocator to return an available physical
101     // register if possible and populate a list of new live intervals that
102     // result from splitting.
103     DEBUG(dbgs() << "\nselectOrSplit "
104           << TRI->getRegClassName(MRI->getRegClass(VirtReg->reg))
105           << ':' << *VirtReg << " w=" << VirtReg->weight << '\n');
106     typedef SmallVector<unsigned, 4> VirtRegVec;
107     VirtRegVec SplitVRegs;
108     unsigned AvailablePhysReg = selectOrSplit(*VirtReg, SplitVRegs);
109 
110     if (AvailablePhysReg == ~0u) {
111       // selectOrSplit failed to find a register!
112       // Probably caused by an inline asm.
113       MachineInstr *MI = nullptr;
114       for (MachineRegisterInfo::reg_instr_iterator
115            I = MRI->reg_instr_begin(VirtReg->reg), E = MRI->reg_instr_end();
116            I != E; ) {
117         MachineInstr *TmpMI = &*(I++);
118         if (TmpMI->isInlineAsm()) {
119           MI = TmpMI;
120           break;
121         }
122       }
123       if (MI)
124         MI->emitError("inline assembly requires more registers than available");
125       else
126         report_fatal_error("ran out of registers during register allocation");
127       // Keep going after reporting the error.
128       VRM->assignVirt2Phys(VirtReg->reg,
129                  RegClassInfo.getOrder(MRI->getRegClass(VirtReg->reg)).front());
130       continue;
131     }
132 
133     if (AvailablePhysReg)
134       Matrix->assign(*VirtReg, AvailablePhysReg);
135 
136     for (unsigned Reg : SplitVRegs) {
137       assert(LIS->hasInterval(Reg));
138 
139       LiveInterval *SplitVirtReg = &LIS->getInterval(Reg);
140       assert(!VRM->hasPhys(SplitVirtReg->reg) && "Register already assigned");
141       if (MRI->reg_nodbg_empty(SplitVirtReg->reg)) {
142         assert(SplitVirtReg->empty() && "Non-empty but used interval");
143         DEBUG(dbgs() << "not queueing unused  " << *SplitVirtReg << '\n');
144         aboutToRemoveInterval(*SplitVirtReg);
145         LIS->removeInterval(SplitVirtReg->reg);
146         continue;
147       }
148       DEBUG(dbgs() << "queuing new interval: " << *SplitVirtReg << "\n");
149       assert(TargetRegisterInfo::isVirtualRegister(SplitVirtReg->reg) &&
150              "expect split value in virtual register");
151       enqueue(SplitVirtReg);
152       ++NumNewQueued;
153     }
154   }
155 }
156 
157 void RegAllocBase::postOptimization() {
158   spiller().postOptimization();
159   for (auto DeadInst : DeadRemats) {
160     LIS->RemoveMachineInstrFromMaps(*DeadInst);
161     DeadInst->eraseFromParent();
162   }
163   DeadRemats.clear();
164 }
165